CN105489651A - 半导体器件及其制造方法 - Google Patents
半导体器件及其制造方法 Download PDFInfo
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- CN105489651A CN105489651A CN201410484165.0A CN201410484165A CN105489651A CN 105489651 A CN105489651 A CN 105489651A CN 201410484165 A CN201410484165 A CN 201410484165A CN 105489651 A CN105489651 A CN 105489651A
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Classifications
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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- H—ELECTRICITY
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
一种半导体器件,包括:多个鳍片结构,在衬底上沿第一方向延伸;栅极堆叠结构,在衬底上沿第二方向延伸,跨越多个鳍片结构,其中栅极堆叠结构包括栅极导电层和栅极绝缘层,栅极导电层由掺杂多晶半导体构成;沟道区,多个鳍片结构中位于栅极堆叠结构下方;源漏区,在多个鳍片结构上、位于栅极堆叠结构沿第一方向两侧。依照本发明的半导体器件及其制造方法,对大面积多晶半导体栅极执行掺杂之后再刻蚀形成栅极线条,能有效提高对于掺杂多晶半导体栅极调节阈值电压的精度,以低成本抑制短沟道效应。
Description
技术领域
本发明涉及一种半导体器件及其制造方法,特别是涉及一种掺杂多晶硅先栅工艺的FinFET及其制造方法。
背景技术
在当前的亚20nm技术中,三维多栅器件(FinFET或Tri-gate)是主要的器件结构,这种结构增强了栅极控制能力、抑制了漏电与短沟道效应。
例如,双栅SOI结构的MOSFET与传统的单栅体Si或者SOIMOSFET相比,能够抑制短沟道效应(SCE)以及漏致感应势垒降低(DIBL)效应,具有更低的结电容,能够实现沟道轻掺杂,可以通过设置金属栅极的功函数来调节阈值电压,能够得到约2倍的驱动电流,降低了对于有效栅氧厚度(EOT)的要求。而三栅器件与双栅器件相比,栅极包围了沟道区顶面以及两个侧面,栅极控制能力更强。进一步地,全环绕纳米线多栅器件更具有优势。
通常,一种FinFET结构以及制造方法包括:在体Si或者SOI衬底中刻蚀形成多个平行的沿第一方向延伸的鳍片和沟槽;在沟槽中填充绝缘材料,回刻以露出部分鳍片,形成浅沟槽隔离(STI);在鳍片顶部以及侧壁沉积通常为氧化硅的较薄(例如仅1~5nm)假栅极绝缘层,在假栅极绝缘层上沉积通常为多晶硅、非晶硅的假栅极层以及氮化硅的假栅极盖层;刻蚀假栅极层和假栅极绝缘层,形成沿第二方向延伸的假栅极堆叠,其中第二方向优选地垂直于第一方向;以假栅极堆叠为掩模,对鳍片进行倾斜的浅掺杂注入形成轻掺杂漏结构(LDD)特别是源漏延伸(SDE)结构以抑制漏致感应势垒降低效应;在假栅极堆叠的沿第一方向的两侧沉积并刻蚀形成栅极侧墙;在栅极侧墙两侧外延生长晶格常数相近材料形成高应力的源漏区(由于栅极侧墙、假栅极堆叠顶部等为绝缘介电质材质,无法在其上外延生长半导体材料),优选采用SiGe、SiC等高于Si应力的材料以提高载流子迁移率;优选地,在源漏区上形成接触刻蚀停止层(CESL);在晶片上沉积层间介质层(ILD);刻蚀去除假栅极堆叠,在ILD中留下栅极沟槽;在栅极沟槽中沉积高k材料(HK)的栅极绝缘层以及金属/金属合金/金属氮化物(MG)的栅极导电层,并优选包括氮化物材质的栅极盖层以保护金属栅极。进一步地,利用掩模刻蚀ILD形成源漏接触孔,暴露源漏区;可选地,为了降低源漏接触电阻,在源漏接触孔中形成金属硅化物。填充金属/金属氮化物形成接触塞,通常优选填充率较高的金属W、Ti。由于CESL、栅极侧墙的存在,填充的金属W、Ti会自动对准源漏区,最终形成接触塞。
然而,上述金属栅极和高k材料构成的栅极堆叠结构,虽然能够有效提高栅极控制能力,例如有效抑制短沟道效应并且精确调节阈值电压,但是随着FinFET器件特征尺寸(沟道区长度,通常稍大于或者等于金属栅极堆叠沿第一方向的长度/宽度)持续缩减至例如10nm乃至8nm以下,如何有效提高金属材料填充后栅工艺形成的栅极沟槽成为难题,工艺复杂性使得制造成本高居难下。而另一方面,传统的应用于平面大尺寸MOSFET的多晶硅栅极结构难以应用于后栅工艺的FinFET,因为对于短沟道、短栅长器件而言难以精确控制窄栅极内部的掺杂剂分布均匀,如此形成的多晶硅栅极面临短沟道效应控制困难、阈值电压调节难以精确等等技术挑战。
发明内容
由上所述,本发明的目的在于克服上述技术困难,提出一种新的FinFET结构及其制造方法,能有效提高对于掺杂多晶半导体栅极调节阈值电压的精度,以低成本抑制短沟道效应。
为此,本发明提供了一种半导体器件,包括:多个鳍片结构,在衬底上沿第一方向延伸;栅极堆叠结构,在衬底上沿第二方向延伸,跨越多个鳍片结构,其中栅极堆叠结构包括栅极导电层和栅极绝缘层,栅极导电层由掺杂多晶半导体构成;沟道区,多个鳍片结构中位于栅极堆叠结构下方;源漏区,在多个鳍片结构上、位于栅极堆叠结构沿第一方向两侧。
其中,掺杂多晶半导体选自多晶Si、多晶SiGe、多晶Si:C、多晶Si:H、多晶Ge、多晶SiGeC、多晶GeSn、多晶SiSn、多晶InP、多晶GaN、多晶InSb、多晶碳化半导体的任意一种或其组合。
其中,栅极绝缘层仅位于栅极导电层下方。
其中,源漏区包括在多个鳍片结构中的源漏延伸区、以及在源漏延伸区上方的抬升源漏区。
其中,多个鳍片结构中部和/或底部具有穿通阻挡层。
本发明还提供了一种半导体器件制造方法,包括:在衬底上形成沿第一方向延伸的多个鳍片;在鳍片上形成沿第二方向延伸的绝缘层和掺杂多晶半导体层;沿第二方向依次刻蚀掺杂多晶半导体层和绝缘层,分别形成栅极导电层和栅极绝缘层;在栅极堆叠结构沿第一方向的两侧形成栅极侧墙和源漏区。
其中,形成栅极堆叠结构之前进一步包括,执行离子注入,在鳍片中部和/或底部形成穿通阻挡层。
其中,形成掺杂多晶半导体层的步骤具体包括:在鳍片上沉积绝缘层和多晶半导体层,随后对多晶半导体层执行离子注入掺杂;或者,在鳍片上原位沉积掺杂而形成掺杂多晶半导体层。
其中,掺杂多晶半导体选自多晶Si、多晶SiGe、多晶Si:C、多晶Si:H、多晶Ge、多晶SiGeC、多晶GeSn、多晶SiSn、多晶InP、多晶GaN、多晶InSb、多晶碳化半导体的任意一种或其组合。
其中,形成源漏区的步骤具体包括:在栅极堆叠结构两侧形成第一栅极侧墙;以第一栅极侧墙为掩模对鳍片执行轻掺杂离子注入,形成源漏延伸区;在第一栅极侧墙两侧的源漏延伸区上外延生长抬升源漏区;在第一栅极侧墙两侧形成第二栅极侧墙;以第二栅极侧墙为掩模对抬升源漏区执行重掺杂离子注入。
其中,沉积多晶半导体层之后、执行离子注入掺杂之前,进一步包括对多晶半导体层执行平坦化工艺;或者,在形成掺杂多晶半导体层之后、刻蚀掺杂多晶半导体层之前,进一步包括对掺杂多晶半导体层执行平坦化工艺。
依照本发明的半导体器件及其制造方法,对大面积多晶半导体栅极执行掺杂之后再刻蚀形成栅极线条,能有效提高对于掺杂多晶半导体栅极调节阈值电压的精度,以低成本抑制短沟道效应。
附图说明
以下参照附图来详细说明本发明的技术方案,其中:
图1至图12为依照本发明的FinFET制造方法各步骤的示意图;以及
图13为依照本发明的FinFET器件结构透视图。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果,公开了有效提高多晶半导体栅极阈值电压控制精度的三维多栅FinFET及其制造方法。需要指出的是,类似的附图标记表示类似的结构,本申请中所用的术语“第一”、“第二”、“上”、“下”等等可用于修饰各种器件结构或制造工序。这些修饰除非特别说明并非暗示所修饰器件结构或制造工序的空间、次序或层级关系。
值得注意的是,以下各个附图中上部部分为器件沿图13中第一方向(鳍片延伸方向,源漏延伸方向,也即Y-Y’轴线)的剖视图,中间部分为器件沿第二方向(栅极堆叠延伸方向,垂直于第一方向,也即X-X’轴线)的栅极堆叠中线的剖视图,下部部分为器件沿平行于第二方向且位于栅极堆叠之外(第一方向上具有一定距离)位置处(也即X1-X1’轴线)获得的剖视图。
如图1所示,在衬底1上形成沿第一方向延伸的多个鳍片结构1F以及鳍片结构之间的沟槽1G,其中第一方向为未来器件沟道区延伸方向(图13中的Y-Y’轴线)。提供衬底1,衬底1依照器件用途需要而合理选择,可包括单晶体硅(Si)、单晶体锗(Ge)、应变硅(StrainedSi)、锗硅(SiGe),或是化合物半导体材料,例如氮化镓(GaN)、砷化镓(GaAs)、磷化铟(InP)、锑化铟(InSb),以及碳基半导体例如石墨烯、SiC、碳纳管等等。出于与CMOS工艺兼容的考虑,衬底1优选地为体Si。任选的,在衬底1上形成硬掩模层2,例如通过LPCVD、PECVD、溅射等工艺形成的氮化硅、氮氧化硅层2。在硬掩模层2上涂覆光刻胶并曝光显影形成光刻胶图形(未示出),以光刻胶图形为掩模,刻蚀硬掩模层2形成硬掩模图形,并且进一步以硬掩模图形2为掩模刻蚀衬底1,在衬底1中形成多个沿第一方向平行分布的沟槽1G以及沟槽1G之间剩余的衬底1材料所构成的鳍片1F。刻蚀优选各向异性的刻蚀,例如等离子体干法刻蚀、反应离子刻蚀(RIE)或者四甲基氢氧化铵(TMAH)湿法腐蚀,使得沟槽1G的深宽比优选地大于5:1。鳍片1F沿第二方向的宽度例如仅为5~50nm并优选10~20nm。
如图2所示,在鳍片结构1F和衬底1上形成隔离介质层3。例如,在鳍片1F之间的沟槽1G中通过PECVD、HDPCVD、RTO(快速热氧化)、旋涂、FlowCVD等工艺沉积填充材质例如为氧化硅、氮氧化硅、氢氧化硅、有机物等的绝缘隔离介质层3。如图2所示,由于鳍片结构1F的存在,沉积的层3在鳍片结构1F顶部具有凸起。优选地,采用CMP、回刻(etch-back)等平坦化工艺处理层3,直至暴露硬掩模层2。
如图3所示,在鳍片1F中和/或底部形成穿通阻挡层(PTSL)4。在图2所示结构平坦化露出硬掩模层2之后,执行离子注入,可以包括N、C、F、P、Cl、As、B、In、Sb、Ga、Si、Ge等及其组合。随后执行退火,例如在500~1200摄氏度下热处理1ms~10min,使得注入的元素与鳍片1F反应,形成高掺杂的(掺杂上述材料的Si)或者绝缘材料的(例如掺杂有上述元素的氧化硅)的穿通阻挡层4。在本发明一个实施例中,控制注入能量和剂量,仅在鳍片1F中形成了沟道穿通阻挡层4A,如图3所示,以抑制沟道区通过STI侧面的泄漏。然而,在本发明另一优选实施例中,控制注入能量和剂量,使得穿通阻挡层4还分布在鳍片1F底部与衬底1界面处作为STI穿通阻挡层4B,以有效隔绝鳍片1F中沟道区、源漏区与相邻鳍片有源区之间的泄漏电流。层4B材质可以与层4A材质相同,也可以包含上述元素中的不同组分(但至少包含氧)。层4B可以与层4A同时一次性注入形成(不同元素注入深度不同),也可以先后两次不同深度、剂量的注入,例如可以先深距离注入形成层4B,后浅距离注入形成层4A,反之亦然。此外,除了上述高掺杂的穿通阻挡层之外,也可以注入大量的氧(O)以形成氧化硅基的绝缘层以作为穿通阻挡层(该氧化硅层内也可以进一步掺杂上述杂质)。值得注意的是,沟道穿通阻挡层4A距离鳍片1F顶部(或底部)的高度可以任意设定,在本发明一个实施例中优选为鳍片1F自身高度的1/3~1/2。STI穿通阻挡层4B和沟道穿通阻挡层4A厚度例如是5~30nm。层4A的宽度(沿第一和/或第二方向)依照整个器件有源区宽度而设定,层4A的宽度则与鳍片1F相同,也即层4B的宽度明显大于层4A的宽度。
如图4所示,选择性刻蚀隔离层3,再次形成沟槽1G,暴露出鳍片1F一部分。可以采用光刻胶图形或者其他硬掩模图形,选择各向异性的刻蚀方法,例如等离子体干法刻蚀、RIE,刻蚀隔离层3,使得剩余的隔离层3构成了浅沟槽隔离(STI)3。优选地,沟槽1G的深度,也即STI3顶部距离鳍片1F顶部的距离,大于等于沟道穿通阻挡层4A顶部距离鳍片1F顶部的距离,以便完全抑制沟道区之间的穿通。随后,湿法腐蚀去除了硬掩模2。
如图5所示,在整个晶片上、也即在鳍片1F、STI3上形成绝缘层5A、以及多晶半导体材料层5B。例如通过PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、溅射等常规工艺,在整个器件结构上形成决烟草5A以及多晶半导体层5B。绝缘层5A的材质可以是氧化物、氮化物、氮氧化物或者其他高k材料,例如为氧化硅、氮化硅、氮氧化硅、高K材料。其中,高k材料包括但不限于包括选自HfO2、HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOx的铪基材料(其中,各材料依照多元金属组分配比以及化学价不同,氧原子含量x可合理调整,例如可为1~6且不限于整数),或是包括选自ZrO2、La2O3、LaAlO3、TiO2、Y2O3的稀土基高K介质材料,或是包括Al2O3,以其上述材料的复合层。多晶半导体层5B的材质包括多晶Si、多晶SiGe、多晶Si:C、多晶Si:H、多晶Ge、多晶SiGeC、多晶GeSn、多晶SiSn、多晶InP、多晶GaN、多晶InSb、多晶碳化半导体等。可以选择工艺参数,例如提高沉积温度(例如850~1300摄氏度)使得一次形成上述材料的多晶半导体层;也可以先在较低温度下(例如600~800摄氏度)下先形成上述材料的非晶、微晶半导体层,然后采用激光退火、RTA退火等修复工艺使得半导体层中的晶粒重新组合形成多晶半导体层。
如图6所示,对多晶半导体层5B进行掺杂,形成掺杂多晶半导体层5B’。在本发明一个优选实施例中,可以采用离子注入,依据不同的器件类型对多晶半导体栅极掺入不同的掺杂剂以调节所需的阈值电压,例如针对pFinFET注入B、In、Mg、Be、Al、Ga、Sn等,针对nFinFET注入P、As、N、Sb、Bi、S、Se、Te等。随后,优选地对整个器件执行退火(例如退火温度600~800摄氏度,退火时间1s~3min),激活杂质并且促使其在整个多晶半导体层5B中均匀分布,而形成了掺杂多晶半导体层5B’。在此过程中,相对于先形成栅极线条然后再掺杂的工艺,本发明的器件及其制造方法利用大面积注入然后激活退火,避免了因为离子注入方向的不均匀分布或者等离子点火喷射系统的偶然波动给小尺寸栅极线条带来的掺杂浓度局部巨大跃变,也通过大面积、长距离的扩散提高了掺杂层5B’内掺杂剂分布的均匀性,有助于精确控制器件的阈值电压,在晶片的不同区域内均可以获得稳定、均一化的电学特性。
值得注意的是,虽然图5、图6显示了先沉积然后再注入掺杂的一个优选实施例,但是实际上图5、图6的进程可以合并为在沉积腔室内间歇或者交替通入掺杂剂原料气(例如上述掺杂剂的氟化物或氢化物等等)而执行原位沉积,随后一并执行激活退火而促使掺杂剂均匀分布。
在以上沉积过程中,由于受到衬底上鳍片的影响,多晶半导体层的顶部是凹凸不平的(未示出),这将影响离子注入的精度,例如由于顶部突起而在局部吸收了较多的杂质,而突起根部区域则可能相对于邻近区域具有较少的杂质,如此在后期形成器件时会出现杂质分布的周期性变化。因此,依照本发明一个优选实施例,在沉积多晶半导体层之后、执行离子注入掺杂之前,进一步包括对多晶半导体层执行平坦化工艺;或者,在形成掺杂多晶半导体层之后、刻蚀掺杂多晶半导体层之前,进一步包括对掺杂多晶半导体层执行平坦化工艺。
如图7所示,对掺杂多晶半导体层5B’、绝缘层5A执行图形化工艺,形成沿第二方向分布的栅极堆叠5。例如在整个器件上涂覆光刻胶(未示出),利用含有沿第二方向(优选垂至于鳍片1F延伸的第一方向)分布线条的掩模或者刻线板对光刻胶曝光、显影而形成多个沿第二方向延伸分布的光刻胶图形,随后以光刻胶图形为掩模依次刻蚀掺杂多晶半导体层5B’、绝缘层5A,直至暴露鳍片结构1F顶部以及STI3的顶部。刻蚀工艺优选各向异性的刻蚀工艺,例如等离子干法刻蚀、RIE等,刻蚀气体可以为针对硅基材质(如多晶硅、氧化硅、氮化硅等)的碳氟基刻蚀气体,也可以为针对非硅基材质(例如多晶SiGe、多晶Ge、其他高k材料)的卤素刻蚀气体(例如Cl2、Br2、HBr、HCl等)。留下的掺杂多晶半导体层5B’构成了多晶材料的栅极导电层5G,而留下的绝缘层5A构成了栅极绝缘层5GOX。如前所述,因为利用大面积掺杂并激活退火,使得掺杂剂在栅极5G中分布均匀,最终使得器件阈值电压控制精确。如图7上部以及中部所示,栅极堆叠5(5G/5GOX)仅分布在沿X-X’轴线的一定宽度范围内,在一定距离之外的X1-X1’轴线处没有分布。
如图8所示,在栅极堆叠5沿第一方向的两侧形成第一栅极侧墙6A。在整个器件上通过LPCVD、PECVD、HDPCVD、UHVCVD、MOCVD、MBE、ALD、蒸发、(磁控)溅射等工艺形成绝缘材料层6,其材质例如氮化硅、氮氧化硅、氧化硅、含碳氧化硅、非晶碳、类金刚石无定形碳(DLC)等及其组合。在本发明一个实施例中,优选氮化硅。随后,采用各向异性刻蚀工艺,刻蚀绝缘材料层6,仅在栅极堆叠结构5沿第一方向的两侧留下第一栅极侧墙6A。值得注意的是,虽然图8所示第一栅极侧墙6A为三角形,但是在本发明另一优选实施例中,侧墙6A优选具有L型,也即具有水平的第一部分以及垂直的第二部分,以便与栅极堆叠5保持良好的共形,从而利于减薄栅极侧墙6A的厚度,以进一步缩减器件尺寸、提高器件均匀度。在本发明一个优选实施例中,层6A的厚度例如仅1~5nm、优选2~4nm、并最佳为3nm。
随后,如图9所示,以第一栅极侧墙6A为掩模,对包含器件的晶片执行轻掺杂离子注入,在栅极堆叠5和栅极侧墙6A沿第一方向的两侧鳍片1F中形成了轻掺杂源漏(LDD)或者源漏延伸区(SDE)结构1LS/1LD,两者之间的鳍片1F构成了沟道区1C。其中,垂直倾角β(注入方向与垂直方向所夹的锐角角度)可以例如0~45±0.5度)。可以通过以垂直方向为轴线,180度旋转晶片衬底1或者旋转离子注入腔室中喷嘴而实现在栅极堆叠结构5沿第一方向两侧形成对称的LDD/SDE结构。此外,依照本发明的优选实施例,可以调整垂直倾角β以调整LDD/SDE结构的纵向(沿垂直方向)结深,从而控制源漏区与鳍片1F之间底部界面特性。
如图10所示,在栅极侧墙6A沿第一方向两侧的LDD源漏区1LS/1LD上外延生长抬升源漏区1HS和1HD。例如通过PECVD、MOCVD、MBE、ALD、热分解、蒸发、溅射等工艺,在栅极堆叠结构5/栅极侧墙6A沿第一方向的两侧上方外延生长抬升漏区1HD和提升源区1HS。其中,抬升源漏区1HS/1HD材质优选与衬底1、鳍片1F不同,例如具有更高应力的SiGe、Si:C、Si:H、SiSn、GeSn、SiGe:C等及其组合。在此过程中,可以执行原位掺杂或者离子注入掺杂以调整源漏区的掺杂类型和/或浓度。如图10下部所示,由于外延生长在各个晶面生长速度不一致,最后外延形成的抬升源漏区往往具有菱形、钻石形等剖面。
随后,如图11所示,在第一栅极侧墙6A上进一步形成第二栅极侧墙6B,其材质工艺类似于第一栅极侧墙。此后,以第二栅极侧墙6B为掩模,进行第二次离子注入,执行源漏重掺杂(纵向结深浅),使得提升源漏1HD/1HS具有高于源漏1S/1D、轻掺杂源漏的杂质浓度。随后,退火以激活掺杂的杂质。与此同时,该退火还进一步减缓了LDD/SDE的注入对于鳍片结构顶部的损伤以及减少外延层中的缺陷,有利于以精简的工艺提高器件的可靠性。
如图12所示,在整个器件上形成接触刻蚀停止层(CESL)7A以及层间介质层(ILD)7B。优选地,先在器件上通过PECVD、HDPCVD、溅射等工艺形成氮化硅的接触刻蚀停止层7A(可以省略)。随后,通过旋涂、喷涂、丝网印刷、CVD、PVD等工艺形成氧化硅、低k材料的ILD7B,其中低k材料包括但不限于有机低k材料(例如含芳基或者多元环的有机聚合物)、无机低k材料(例如无定形碳氮薄膜、多晶硼氮薄膜、氟硅玻璃、BSG、PSG、BPSG)、多孔低k材料(例如二硅三氧烷(SSQ)基多孔低k材料、多孔二氧化硅、多孔SiOCH、掺C二氧化硅、掺F多孔无定形碳、多孔金刚石、多孔有机聚合物)。
之后可以采用常规工艺完成器件互连。例如,依次刻蚀ILD7B、接触刻蚀停止层7A,直至暴露源漏区1HS/1HD,形成接触孔。刻蚀方法优选各向异性的干法刻蚀,例如等离子干法刻蚀或者RIE。优选地,在接触孔暴露的源漏区上形成金属硅化物(未示出)以降低接触电阻。例如,在接触孔中蒸发、溅射、MOCVD、MBE、ALD形成金属层(未示出),其材质例如Ni、Pt、Co、Ti、W等金属以及金属合金。在250~1000摄氏度下退火1ms~10min,使得金属或金属合金与源漏区中所含的Si元素反应形成金属硅化物,以降低接触电阻。随后在接触孔中填充接触金属层,例如通过MOCVD、MBE、ALD、蒸发、溅射等工艺,形成了接触金属层,其材料优选延展性较好、填充率较高并且相对低成本的材料,例如包括W、Ti、Pt、Ta、Mo、Cu、Al、Ag、Au等金属、这些金属的合金、以及这些金属的相应氮化物。随后,采用CMP、回刻等工艺平坦化接触金属层,直至暴露CESL层7A。
最后形成的器件结构如图12所示,包括:多个鳍片结构1F,在衬底1上沿第一方向延伸分布,多个鳍片结构1F之间存在多个浅沟槽隔离(STI)3;栅极堆叠结构包括栅极导电层5G以及栅极绝缘层5GOX,跨越每个鳍片结构,沿第二方向延伸分布,栅极堆叠结构5下方的鳍片结构构成沟道区1C;源漏区,形成在栅极堆叠沿第一方向两侧的鳍片结构之上;其中,栅极导电层5G由掺杂多晶半导体构成,栅极绝缘层5GOX仅分布在栅极导电层5G下方。其他的器件结构和材料、参数等已经参照附图1至附图12描述在制造过程中,在此不再赘述。
依照本发明的半导体器件及其制造方法,对大面积多晶半导体栅极执行掺杂之后再刻蚀形成栅极线条,能有效提高对于掺杂多晶半导体栅极调节阈值电压的精度,以低成本抑制短沟道效应。
尽管已参照一个或多个示例性实施例说明本发明,本领域技术人员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和等价方式。此外,由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此,本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例,而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。
Claims (11)
1.一种半导体器件,包括:
多个鳍片结构,在衬底上沿第一方向延伸;
栅极堆叠结构,在衬底上沿第二方向延伸,跨越多个鳍片结构,其中栅极堆叠结构包括栅极导电层和栅极绝缘层,栅极导电层由掺杂多晶半导体构成;
沟道区,多个鳍片结构中位于栅极堆叠结构下方;
源漏区,在多个鳍片结构上、位于栅极堆叠结构沿第一方向两侧。
2.如权利要求1的半导体器件,其中,掺杂多晶半导体选自多晶Si、多晶SiGe、多晶Si:C、多晶Si:H、多晶Ge、多晶SiGeC、多晶GeSn、多晶SiSn、多晶InP、多晶GaN、多晶InSb、多晶碳化半导体的任意一种或其组合。
3.如权利要求1的半导体器件,其中,栅极绝缘层仅位于栅极导电层下方。
4.如权利要求1的半导体器件,其中,源漏区包括在多个鳍片结构中的源漏延伸区、以及在源漏延伸区上方的抬升源漏区。
5.如权利要求1的半导体器件,其中,多个鳍片结构中部和/或底部具有穿通阻挡层。
6.一种半导体器件制造方法,包括:
在衬底上形成沿第一方向延伸的多个鳍片;
在鳍片上形成沿第二方向延伸的绝缘层和掺杂多晶半导体层;
沿第二方向依次刻蚀掺杂多晶半导体层和绝缘层,分别形成栅极导电层和栅极绝缘层;
在栅极堆叠结构沿第一方向的两侧形成栅极侧墙和源漏区。
7.如权利要求6的半导体器件制造方法,其中,形成栅极堆叠结构之前进一步包括,执行离子注入,在鳍片中部和/或底部形成穿通阻挡层。
8.如权利要求6的半导体器件制造方法,其中,形成掺杂多晶半导体层的步骤具体包括:在鳍片上沉积绝缘层和多晶半导体层,随后对多晶半导体层执行离子注入掺杂;或者,在鳍片上原位沉积掺杂而形成掺杂多晶半导体层。
9.如权利要求8的半导体器件制造方法,其中,沉积多晶半导体层之后、执行离子注入掺杂之前,进一步包括对多晶半导体层执行平坦化工艺;或者,在形成掺杂多晶半导体层之后、刻蚀掺杂多晶半导体层之前,进一步包括对掺杂多晶半导体层执行平坦化工艺。
10.如权利要求6的半导体器件制造方法,其中,掺杂多晶半导体选自多晶Si、多晶SiGe、多晶Si:C、多晶Si:H、多晶Ge、多晶SiGeC、多晶GeSn、多晶SiSn、多晶InP、多晶GaN、多晶InSb、多晶碳化半导体的任意一种或其组合。
11.如权利要求6的半导体器件制造方法,其中,形成源漏区的步骤具体包括:在栅极堆叠结构两侧形成第一栅极侧墙;以第一栅极侧墙为掩模对鳍片执行轻掺杂离子注入,形成源漏延伸区;在第一栅极侧墙两侧的源漏延伸区上外延生长抬升源漏区;在第一栅极侧墙两侧形成第二栅极侧墙;以第二栅极侧墙为掩模对抬升源漏区执行重掺杂离子注入。
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CN109891692B (zh) * | 2016-09-28 | 2021-09-10 | 菲尼萨公司 | 注入物再生长vcsel和具有不同vcsel类型的异构组合的vcsel阵列 |
CN111418070A (zh) * | 2017-09-29 | 2020-07-14 | 思睿逻辑国际半导体有限公司 | 双栅极金属氧化物半导体场效应晶体管 |
CN111418070B (zh) * | 2017-09-29 | 2021-10-15 | 思睿逻辑国际半导体有限公司 | 双栅极金属氧化物半导体场效应晶体管 |
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