WO2020191571A1 - Registre à décalage et son procédé d'attaque, circuit d'attaque de grille et dispositif d'affichage - Google Patents

Registre à décalage et son procédé d'attaque, circuit d'attaque de grille et dispositif d'affichage Download PDF

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Publication number
WO2020191571A1
WO2020191571A1 PCT/CN2019/079477 CN2019079477W WO2020191571A1 WO 2020191571 A1 WO2020191571 A1 WO 2020191571A1 CN 2019079477 W CN2019079477 W CN 2019079477W WO 2020191571 A1 WO2020191571 A1 WO 2020191571A1
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WIPO (PCT)
Prior art keywords
node
coupled
blanking
transistor
terminal
Prior art date
Application number
PCT/CN2019/079477
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English (en)
Chinese (zh)
Inventor
袁志东
李永谦
徐海侠
袁粲
Original Assignee
京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥鑫晟光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/649,519 priority Critical patent/US11232763B2/en
Priority to CN201980000383.3A priority patent/CN110114817B/zh
Priority to PCT/CN2019/079477 priority patent/WO2020191571A1/fr
Publication of WO2020191571A1 publication Critical patent/WO2020191571A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to the field of display technology, in particular to a shift register and a driving method thereof, a gate driving circuit, an array substrate, and a display device.
  • the gate driver on array (Gate Driver on Array, GOA for short) technology fabricates a gate driver circuit on an array substrate to realize the function of scanning pixels row by row.
  • the gate driving circuit may include a plurality of cascaded shift registers. The scan signal is output from the output terminal of the shift register to drive the pixels, and the cascade signal can be output at the same time to drive the next stage shift register.
  • organic light-emitting diode Organic Light-Emitting Diode, OLED for short
  • OLED Organic Light-Emitting Diode
  • the OLED display device uses the current provided by the driving transistor to drive the light-emitting device to emit light. Therefore, in order to meet the requirements for the uniformity of the light emission of the display panel, it is necessary to improve the uniformity of the electrical characteristics of the driving transistors.
  • an internal compensation method or an external compensation method can be used to improve the consistency of the electrical characteristics of the driving transistor.
  • the embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit, an array substrate, and a display device.
  • a shift register including a compensation selection circuit, a storage circuit, a blanking input circuit, and a shift register circuit.
  • the compensation selection circuit is coupled to the compensation selection control signal terminal, the input terminal and the first node, and is configured to provide the input signal from the input terminal to the first node according to the compensation selection control signal from the compensation selection control signal terminal.
  • the storage circuit is coupled to the blanking control signal terminal and the first node, and is configured to store and maintain the voltage difference between the blanking control signal terminal and the first node.
  • the blanking input circuit is coupled to the first node, the blanking input signal terminal, and the second node, and is configured to provide a blanking input signal from the blanking input signal terminal to the second node according to the voltage of the first node.
  • the shift register circuit is coupled to the second node, the clock signal terminal, the input terminal and the output terminal, and is configured to provide a compensation drive signal through the output terminal according to the voltage of the second node and the clock signal from the clock signal terminal during the blanking period During the display period, according to the input signal and the clock signal, the scan drive signal is provided through the output terminal.
  • the compensation selection circuit includes a first transistor.
  • the control electrode of the first transistor is coupled to the compensation selection control signal terminal, the first electrode of the first transistor is coupled to the input terminal, and the second electrode of the first transistor is coupled to the first node.
  • the storage circuit includes a first capacitor.
  • the first electrode of the first capacitor is coupled to the blanking control signal terminal, and the second electrode of the first capacitor is coupled to the first node.
  • the blanking input circuit includes a second transistor.
  • the control electrode of the second transistor is coupled to the first node, the first electrode of the second transistor is coupled to the blanking input signal terminal, and the second electrode of the second transistor is coupled to the second node.
  • the blanking input signal terminal is coupled to the blanking control signal terminal.
  • the shift register circuit includes a display input circuit, an output circuit, a pull-down circuit, a pull-down control circuit, a display reset circuit, and a blanking reset circuit.
  • the display input circuit is coupled to the input terminal and the second node, and is configured to provide an input signal to the second node.
  • the output circuit is coupled to the second node, the clock signal terminal and the output terminal, and is configured to output the scan driving signal according to the voltage and clock signal of the second node during the display period, and according to the voltage and the voltage of the second node during the blanking period
  • the clock signal outputs the compensation driving signal.
  • the pull-down circuit is coupled to the second node, the third node, the first voltage terminal and the output terminal, and is configured to control the voltages of the second node and the output terminal according to the voltage of the third node.
  • the pull-down control circuit is coupled to the second node and the third node, and is configured to control the voltage of the third node according to the voltage of the second node.
  • the display reset circuit is coupled to the display reset signal terminal, the second node and the first voltage terminal, and is configured to reset the second node based on the display reset signal from the display reset signal terminal.
  • the blanking reset circuit is coupled to the blanking reset signal terminal, the second node and the first voltage terminal, and is configured to reset the second node based on the blanking reset signal from the blanking reset signal terminal.
  • the display input circuit includes a third transistor.
  • the control electrode and the first electrode of the third transistor are coupled to the input terminal, and the second electrode of the third transistor is coupled to the second node.
  • the output circuit includes a fourth transistor and a second capacitor.
  • the control electrode of the fourth transistor is coupled to the second node, the first electrode of the fourth transistor is coupled to the clock signal terminal, and the second electrode of the fourth transistor is coupled to the output terminal.
  • the first pole of the second capacitor is coupled to the second node, and the second pole of the second capacitor is coupled to the output terminal.
  • the pull-down circuit includes a fifth transistor and a sixth transistor.
  • the control electrode of the fifth transistor is coupled to the third node, the first electrode of the fifth transistor is coupled to the second node, and the second electrode of the fifth transistor is coupled to the first voltage terminal.
  • the control electrode of the sixth transistor is coupled to the third node, the first electrode of the sixth transistor is coupled to the output terminal, and the second electrode of the sixth transistor is coupled to the first voltage terminal.
  • the pull-down control circuit includes an inverter.
  • the first pole of the inverter is coupled to the second node, and the second pole of the inverter is coupled to the third node.
  • the display reset circuit includes a seventh transistor.
  • the control electrode of the seventh transistor is coupled to the display reset signal terminal, the first electrode of the seventh transistor is coupled to the second node, and the second electrode of the seventh transistor is coupled to the first voltage terminal.
  • the blanking reset circuit includes an eighth transistor.
  • the control electrode of the eighth transistor is coupled to the blanking reset signal terminal, the first electrode of the eighth transistor is coupled to the second node, and the second electrode of the eighth transistor is coupled to the first voltage terminal.
  • the gate driving circuit includes a plurality of cascaded shift registers as in any one of the first aspect of the present disclosure.
  • the output terminal of the Nth stage shift register is coupled to the input terminal of the N+1th stage shift register, where N is a positive integer.
  • the gate driving circuit further includes a compensation selection control signal line, a blanking control signal line, a blanking input signal line, and a first clock signal line.
  • the compensation selection control signal line is coupled to the compensation selection control signal terminal of each shift register to provide a compensation selection control signal.
  • the blanking control signal line is coupled to the blanking control signal end of each shift register to provide a blanking control signal.
  • the blanking input signal line is coupled to the blanking input signal end of each shift register to provide a blanking input signal.
  • the first clock signal line is coupled to the clock signal terminal of the 2N-1 stage shift register to provide a clock signal.
  • the second clock signal line is coupled to the clock signal end of the 2N-stage shift register to provide a clock signal.
  • N is a positive integer.
  • the gate driving circuit further includes a compensation selection control signal line, a blanking control signal line, a first clock signal line, and a second clock signal line.
  • the compensation selection control signal line is coupled to the compensation selection control signal terminal of each shift register to provide a compensation selection control signal.
  • the blanking control signal line is coupled to the blanking control signal terminal of each shift register to provide a blanking control signal, and is coupled to the blanking input signal terminal of each shift register to provide a blanking input signal.
  • the first clock signal line is coupled to the clock signal terminal of the 2N-1 stage shift register to provide a clock signal.
  • the second clock signal line is coupled to the clock signal terminal of the 2N-stage shift register to provide a clock signal.
  • N is a positive integer.
  • the gate driving circuit further includes a blanking reset signal line.
  • the blanking reset signal line is coupled to the blanking reset signal end of each shift register to provide a blanking reset signal.
  • the output terminal of the N+1th stage shift register is coupled to the display reset signal terminal of the Nth stage shift register, where N is a positive integer.
  • an array substrate includes the gate driving circuit according to any one of the second aspects of the present disclosure.
  • a display panel includes the array substrate as described in the third aspect of the present disclosure.
  • a method for driving the shift register according to any one of the first aspects of the present disclosure.
  • the method includes: during the display period, according to the compensation selection control signal, the input signal is provided to the first node; the voltage difference between the blanking control signal terminal and the first node is stored and maintained; during the blanking period, according to the first node The voltage of one node provides the blanking input signal to the second node; and according to the voltage of the second node and the clock signal, a compensation driving signal is output.
  • the method further includes: during the display period, providing an input signal to the second node; and outputting a scan driving signal according to the voltage and the clock signal of the second node.
  • Fig. 1 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 2 shows an exemplary circuit diagram of a shift register according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure
  • FIG. 4 shows a timing diagram of each signal in the working process of the gate driving circuit shown in FIG. 3;
  • FIG. 5 shows a schematic flowchart of a method for driving a shift register according to an embodiment of the present disclosure.
  • internal compensation or external compensation can be used to improve the consistency of the electrical characteristics of the drive transistor.
  • external compensation can also be achieved by providing a sensing transistor.
  • the gate drive circuit needs to provide a scanning drive signal during the display period of one frame to display the pixels, and the gate drive circuit needs to provide a compensation drive signal during the blanking period of one frame to sense the pixel current , So as to perform external compensation.
  • the blanking period refers to a stage during which the display panel is not displaying, and "one frame", “every frame” or "a certain frame” includes the display period and the blanking period that are performed sequentially.
  • the gate drive circuit outputs a compensation drive signal to the pixels row by row. For example, during the blanking period of the first frame, output the compensation drive signal of the first row of pixels, and output the compensation drive signal of the second row of pixels during the blanking period of the second frame, and so on, to complete the line-by-line sequential compensation of the display panel .
  • the shift register provided by the embodiments of the present disclosure can realize random compensation of one row of pixels, thereby avoiding linear patterns on the display panel.
  • the embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit, an array substrate, and a display device.
  • the embodiments and examples of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • Fig. 1 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure.
  • the shift register 10 may include a compensation selection circuit 100, a storage circuit 200, a blanking input circuit 300, and a shift register circuit 400. It will be described in detail below with reference to the drawings.
  • the compensation selection circuit 100 may be coupled to the compensation selection control signal terminal OE, the input terminal and the first node K, and according to the compensation selection control signal OE from the compensation selection control signal terminal, the input from the input terminal
  • the signal STU is provided to the first node K.
  • the compensation selection circuit 100 may be coupled to the compensation selection control signal terminal to receive the compensation selection control signal OE.
  • the compensation selection circuit 100 is coupled to the input terminal to receive the input signal STU.
  • the compensation selection circuit may provide the received input signal STU to the first node K according to the received compensation selection control signal OE.
  • the storage circuit 200 may be coupled to the blanking control signal terminal and the first node K, and may store and maintain the voltage difference between the blanking control signal terminal and the first node K. In an embodiment, the storage circuit 200 is coupled between the blanking control signal terminal and the first node K to store and maintain the voltage difference between the blanking control signal CLKS and the voltage of the first node K.
  • the blanking input circuit 300 can be coupled to the first node K, the blanking input signal terminal, and the second node L (also called the pull-up node), and according to the voltage of the first node K, the blanking input signal terminal
  • the hidden input signal BSTU is provided to the second node L.
  • the blanking input circuit 300 may be coupled to the blanking input signal terminal to receive the blanking input signal BSTU.
  • the blanking input circuit 300 may provide the received blanking input signal BSTU to the second node L according to the voltage of the first node K.
  • the blanking input signal terminal may be coupled to a voltage source to receive the voltage signal as the blanking input signal BSTU.
  • the shift register circuit 400 may be coupled to the second node L, the clock signal terminal, the input terminal, and the output terminal OUTPUT, and in the blanking period according to the voltage of the second node L and the clock signal CLK from the clock signal terminal, through the output terminal OUTPUT Provide compensation drive signal.
  • the shift register circuit 400 may be coupled to the clock signal terminal to receive the clock signal CLK. During the blanking period, the shift register circuit 400 outputs the received clock signal CLK through the output terminal OUTPUT according to the voltage of the second node L as a compensation driving signal.
  • the shift register circuit 400 may provide a scan driving signal through the output terminal OUTPUT according to the input signal STU and the clock signal CLK during the display period.
  • the shift register circuit 400 may also be coupled to the input terminal to receive the input signal STU.
  • the shift register circuit 400 outputs the clock signal CLK through the output terminal OUTPUT according to the received input signal STU as a scan driving signal.
  • the scan driving signal of the N+1th stage shift register can be used to control the shift of the N+2th and Nth stage shift registers, and can be used to drive the display.
  • the corresponding row of pixels in the panel is displayed.
  • the compensation driving signal of the N-th stage shift register is used to sense the driving current of the corresponding row of pixels, thereby performing compensation based on the sensed driving current.
  • N is a positive integer.
  • the shift register circuit 400 may include a display input circuit 410, an output circuit 420, a pull-down circuit 430, a pull-down control circuit 440, a display reset circuit 450, and a blanking reset circuit 460. It will be described in detail below with reference to the drawings.
  • the display input circuit 410 may be coupled to the input terminal and the second node L, and may provide the input signal STU to the second node L.
  • the display input circuit 420 is coupled to the input terminal to receive input The signal STU provides the received input signal STU to the second node L.
  • the output circuit 420 may be coupled to the second node, the clock signal terminal, and the output terminal OUTPUT, and may output a scan driving signal according to the voltage of the second node L and the clock signal CLK during the display period, and according to the blanking period
  • the voltage of the second node L and the clock signal CLK output a compensation driving signal.
  • the output circuit 420 may be coupled to the clock signal terminal to receive the clock signal CLK.
  • the output circuit 420 outputs the received clock signal CLK through the output terminal OUTPUT according to the voltage of the second node L as a scan driving signal.
  • the output circuit 420 outputs the received clock signal CLK through the output terminal OUTPUT according to the voltage of the second node L as a compensation driving signal.
  • each output circuit is coupled with a corresponding clock signal.
  • Each output circuit can output a corresponding driving signal according to the voltage of the second node L and the corresponding clock signal.
  • the pull-down circuit 430 may be coupled to the second node L, the third node M (also referred to as the pull-down node), the first voltage terminal, and the output terminal OUTPUT, and may control the third node M according to the voltage of the third node M.
  • the pull-down circuit may be coupled to the first voltage terminal to receive the first voltage VGL.
  • the first voltage terminal can provide a low-level signal, that is, the first voltage VGL is a low-level signal.
  • the pull-down circuit 430 is also coupled to the output terminal OUTPUT to control the voltages of the second node L and the output terminal OUTPUT according to the received first voltage VGL under the voltage control of the third node M.
  • the pull-down control circuit 440 may be coupled to the second node L and the third node, and may control the voltage of the third node M according to the voltage of the second node L.
  • the display reset circuit 450 may be coupled to the display reset signal terminal, the second node L, and the first voltage terminal, and may reset the second node L according to the display reset signal STD from the display reset signal terminal.
  • the display reset circuit 450 may be coupled to the display reset signal terminal to receive the display reset signal STD.
  • the display reset circuit 450 may be coupled to the first voltage terminal to receive the first voltage VGL.
  • the display reset circuit 450 may provide the received first voltage VGL to the second node L under the control of the received display reset signal STD, thereby pulling down the voltage of the second node L and resetting the second node L.
  • the blanking reset circuit 460 may be coupled to the blanking reset signal terminal, the second node L, and the first voltage terminal, and may perform the blanking reset signal TRST on the second node L based on the blanking reset signal TRST from the blanking reset signal terminal. Reset.
  • the blanking reset circuit 460 may be coupled to the blanking reset signal terminal to receive the blanking reset signal TRST.
  • the blanking reset circuit 460 may be coupled to the first voltage terminal to receive the first voltage VGL.
  • the blanking reset circuit 460 can provide the received first voltage VGL to the second node L under the control of the received blanking reset signal TRST, thereby pulling down the voltage of the second node L, and performing the control on the second node L. Reset.
  • the shift register 10 in FIG. 1 shows the pull-down circuit 430, the pull-down control circuit 440, the display reset circuit 450, and the blanking reset circuit 460
  • the above examples do not limit the scope of protection of the present disclosure.
  • the skilled person can choose to use or not use one or more of the above-mentioned circuits according to the situation.
  • Various combinations and modifications based on the above-mentioned circuits do not deviate from the principle of the present disclosure, and will not be repeated here.
  • FIG. 2 shows an exemplary circuit diagram of a shift register according to an embodiment of the present disclosure.
  • the shift register is, for example, the shift register 10 shown in FIG. 1.
  • the shift register may include a first transistor T1 to an eighth transistor T8, a first capacitor C1 and a second capacitor C2, and an inverter D.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the gate of the transistor can be called the gate.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage
  • the turn-off voltage is a high-level voltage
  • the turn-on voltage is a high-level voltage
  • the turn-off voltage is a low-level voltage
  • the transistors used in the shift register provided in the embodiments of the present disclosure are all N-type transistors as examples.
  • the embodiments of the present disclosure include but are not limited thereto.
  • at least part of the transistors in the shift register may also adopt P-type transistors.
  • the compensation selection circuit 100 includes a first transistor T1.
  • the control electrode of the first transistor T1 is coupled to the compensation selection control signal terminal to receive the compensation selection control signal OE, and the first electrode of the first transistor T1 is coupled to the input terminal to receive the input signal STU.
  • the second electrode of the first transistor T1 is coupled to the first node K.
  • the first transistor T1 when the compensation selection control signal OE is at a high level, the first transistor T1 is turned on to provide the received input signal STU to the first node K.
  • the storage circuit 200 includes a first capacitor C1.
  • the first pole of the first capacitor C1 is coupled to the blanking control signal terminal to receive the blanking control signal CLKS.
  • the second pole of the first capacitor C1 is coupled to the first node K.
  • the first capacitor C1 can store the voltage difference between the blanking control signal CLKS and the first node K.
  • the voltage difference between the two poles of the first capacitor C1 is 0 volts, and the first capacitor C1 is not charged.
  • the blanking control signal CLKS is low and the first node K is in a floating state. Due to the equation jump effect of the first capacitor C1, the voltage of the first node K is at a high level, and the voltage difference between the two poles of the first capacitor C1 remains at 0 volts.
  • the blanking input circuit 300 includes a second transistor T2.
  • the control electrode of the second transistor T2 is coupled to the first control node K.
  • the first electrode of the second transistor T2 is coupled to the blanking input signal terminal to receive the blanking input signal BSTU.
  • the second electrode of the second transistor T2 is coupled to the second node L.
  • the second transistor T2 when the voltage of the first node K is at a high level, the second transistor T2 is turned on, so as to provide the received blanking input signal BSTU to the second node L.
  • the display input circuit 410 includes a third transistor T3.
  • the control electrode and the first electrode of the third transistor T3 are coupled to the input terminal to receive the input signal STU.
  • the second electrode of the third transistor T3 is coupled to the second node L.
  • the third transistor T3 when the input signal STU is at a high level, the third transistor T3 is turned on to provide the received high-level input signal STU to the second node L.
  • the output circuit 420 includes a fourth transistor T4 and a second capacitor C2.
  • the control electrode of the fourth transistor T4 is coupled to the second node L.
  • the first pole of the fourth transistor T4 is coupled to the clock signal terminal to receive the clock signal CLK.
  • the second electrode of the fourth transistor T4 is coupled to the output terminal OUTPUT.
  • the first pole of the second capacitor C2 is coupled to the second node L, and the second pole of the second capacitor C2 is coupled to the output terminal OUTPUT.
  • the fourth transistor T4 when the second node L is at a high level, the fourth transistor T4 is turned on.
  • the output circuit 420 provides the received clock signal CLK to the signal output terminal OUTPUT as a scan driving signal.
  • the output circuit 420 provides the received clock signal CLK to the signal output terminal OUTPUT as a compensation driving signal.
  • the pull-down circuit 430 includes a fifth transistor T5 and a sixth transistor T6.
  • the control electrode of the fifth transistor T5 is coupled to the third node M.
  • the first electrode of the fifth transistor T5 is coupled to the second node L.
  • the second electrode of the fifth transistor T5 is coupled to the first voltage terminal to receive the first voltage VGL.
  • the fifth transistor T5 and the sixth transistor T6 are turned on, and the first voltage VGL is provided to the second node L and the output terminal OUTPUT to connect the second node L and The voltage of the output terminal OUTPUT is pulled down.
  • the pull-down control circuit 440 includes an inverter D, the first pole of the inverter D is coupled to the second node L, and the second pole of the inverter D is coupled to the third node M.
  • the voltage of the second node L is at a high level
  • the voltage of the third node M is at a low level under the action of the inverter D.
  • the voltage of the third node M is at a high level under the action of the inverter D.
  • the display reset circuit 450 includes a seventh transistor T7.
  • the control electrode of the seventh transistor T7 is coupled to the display reset signal terminal to receive the display reset signal STD.
  • the first electrode of the seventh transistor T7 is coupled to the second node L.
  • the second electrode of the seventh transistor T7 is coupled to the first voltage terminal to receive the first voltage VGL.
  • the seventh transistor T7 when the display reset signal STD is at a high level, the seventh transistor T7 is turned on and provides a low level of the first voltage VGL to the second node L to reset the second node L.
  • the blanking reset circuit 460 includes an eighth transistor T8.
  • the control electrode of the eighth transistor T8 is coupled to the blanking reset signal terminal to receive the blanking reset signal TRST.
  • the first electrode of the eighth transistor T8 is coupled to the second node L.
  • the second electrode of the eighth transistor T8 is coupled to the first voltage terminal to receive the first voltage VGL.
  • the eighth transistor T8 when the blanking reset signal TRST is at a high level, the eighth transistor T8 is turned on and provides a low level of the first voltage VGL to the second node L to reset the second node L.
  • the blanking input signal terminal may be coupled to the blanking control signal terminal to receive the blanking control signal as the blanking input signal.
  • the shift register circuit 400 may further include a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12 to prevent leakage.
  • the ninth transistor T9 may be provided in the display input circuit 410.
  • the control electrode of the ninth transistor T9 is coupled to the control electrode of the third transistor T3.
  • the first electrode of the ninth transistor T9 is coupled to the second connection of the third transistor T3 via the fourth node O.
  • the second electrode of the ninth transistor T9 is coupled to the second node L.
  • the tenth transistor T10 may be provided in the pull-down circuit 430.
  • the control electrode of the tenth transistor T10 and the control electrode of the fifth transistor T5 are coupled.
  • the first electrode of the tenth transistor T10 is coupled to the second electrode of the fifth transistor T5 via the fifth node P.
  • the second electrode of the tenth transistor T10 is coupled to the first voltage terminal VGL.
  • the eleventh transistor T11 may be provided in the display reset circuit 450.
  • the control electrode of the eleventh transistor T11 is coupled to the control electrode of the seventh transistor T7.
  • the first electrode of the eleventh transistor T11 is coupled to the second electrode of the seventh transistor T7 via the sixth node Q.
  • the second electrode of the eleventh transistor T11 is coupled to the first voltage terminal.
  • the control electrode of the twelfth transistor T12 is coupled to the second node L, and the first electrode of the twelfth transistor T12 is coupled to the blanking input signal terminal to receive the blanking input signal BSTU.
  • the second pole of the twelfth transistor T12 is sequentially coupled to the sixth node Q, the fifth node P, and the fourth node O.
  • the twelfth transistor T12 when the voltage of the second node L is at a high level, the twelfth transistor T12 is turned on to provide the blanking input signal BSTU to the sixth node Q, the fifth node P, and the fourth node O.
  • the voltages of the sixth node Q, the fifth node P, and the fourth node O are all high. Therefore, the voltage difference between the first pole and the second pole of the fifth transistor T5, the seventh transistor T7, and the ninth transistor T9 is close to 0 volts.
  • the leakage current of the fifth transistor T5, the seventh transistor T7, and the ninth transistor T9 can be reduced, thereby reducing the leakage of the charge of the second node L via the fifth transistor T5, the seventh transistor T7, and the ninth transistor T9.
  • FIG. 3 shows a schematic diagram of a gate driving circuit 30 according to an embodiment of the present disclosure.
  • the gate driving circuit 30 may include a plurality of shift registers. Any one or more shift registers may adopt the structure of the shift register 10 provided in the embodiments of the present disclosure or a modification thereof.
  • FIG. 3 only schematically shows the first three shift registers, namely, the first shift register SR_1 corresponding to the first row of pixels, the second shift register SR_2 corresponding to the second row of pixels, and the third shift register.
  • the third shift register SR_3 corresponding to the row pixels.
  • the output end of the Nth stage shift register is coupled to the input end of the N+1th stage shift register, where N is a positive integer, and N is a positive integer.
  • the input terminal of the first shift register appliance SR_1 receives the input signal STU_1 from the input signal line INPUT.
  • the output terminal OUTPUT_1 of the first shift register SR_1 is coupled to the input terminal of the second shift register SR_2 to provide the input signal STU_2.
  • the output terminal OUTPUT_2 of the second shift register SR_2 is coupled to the input terminal of the shift register SR_3 to provide the input signal STU_3.
  • the gate driving circuit 30 further includes a compensation selection control signal line CLK_A, a blanking control signal line CLK_B, a blanking input signal line VGH, a first clock signal line CLK_C, and a second clock signal line CLK_D.
  • the compensation selection control signal line CLK_A is coupled to the compensation selection control signal terminals of the three shift registers to provide the compensation selection control signal OE.
  • the blanking control signal line CLK_B is coupled to the blanking control signal ends of the three shift registers to provide the blanking control signal CLKS.
  • the blanking input signal line VGH is coupled to the blanking input signal ends of the three shift registers to provide a blanking input signal BSTU.
  • the first clock signal line CLK_C is coupled to the clock signal terminal of the 2N-1 stage shift register to provide a clock signal CLK
  • the second clock signal line CLK_D is coupled to the clock signal terminal of the 2N stage shift register to provide a clock signal CLK, where N is a positive integer.
  • the first clock signal line CLK_C is coupled to the clock signal terminal of the first shift register to provide the clock signal CLK.
  • the second clock signal line CLK_D is connected to the second shift register and the third shift register. The clock signal terminal of the register is coupled to provide a clock signal CLK.
  • the output terminal of the N+1th stage shift register is coupled to the display reset signal terminal of the Nth stage shift register, where N is a positive integer.
  • the output terminal OUTPUT_2 of the second shift register SR_2 is coupled to the display reset signal terminal of the first shift register SR_1 to provide a display reset signal STD_1.
  • the output terminal OUTPUT_3 of the third shift register SR_3 is coupled to the display reset signal terminal of the second shift register SR_2 to provide a display reset signal STD_2.
  • the gate driving circuit 30 also includes a blanking reset signal line CLK_E.
  • the blanking reset signal line CLK_E is coupled to the blanking reset signal terminals of the three shift registers to provide a blanking reset signal TRST.
  • the gate driving circuit may only include the compensation selection control signal line CLK_A, the blanking control signal line CLK_B, the first clock signal line CLK_C, the second clock signal line CLK_D, and the cancellation Hide the reset signal line CLK_E.
  • the difference between this gate drive circuit and the gate drive circuit 30 shown in FIG. 3 is that the blanking control signal line CLK_B is not only coupled to the blanking control signal terminals of the three shift registers to provide a blanking control signal CLKS, The blanking control signal line CLK_B is also coupled to the blanking input signal ends of the three shift registers to provide a blanking input signal BSTU.
  • the shift register in the gate driving circuit 30 has, for example, the circuit structure of the shift register shown in FIG. 2.
  • FIG. 4 shows a signal timing diagram of the gate driving circuit 30 for random compensation of the pixels in the second row.
  • the first clock signal line CLK_C provides the clock signal CLK1 to the first shift register SR_1 and the third shift register SR_3.
  • the second clock signal line CLK_D provides the clock signal CLK2 to the second shift register SR_2.
  • the blanking control signal line CLK_B provides the blanking control signal CLKS to the three shift registers.
  • the input signal line INPUT provides the input signal STU_1 to the first shift register SR_1 corresponding to the first row of pixels.
  • the compensation selection control signal line CLK_A provides the compensation selection control signal OE to the three shift registers.
  • the output signals OUT_1, OUT_2, and OUT_3 represent the output terminals OUTPUT_1, OUTPUT_2 of the first shift register SR_1, the second shift register SR_2, and the third shift register SR_2 corresponding to the pixels of the first row, the second row, and the third row, respectively.
  • the signals VK, VL, and VM respectively represent the voltage signals of the first node K_2, the second node L_2, and the third node M_2 of the second shift register SR_2 in the gate driving circuit 30.
  • the blanking reset signal line CLK_E provides the blanking reset signal TRST to the three shift registers. It can be understood that the signal voltage in the signal timing diagram shown in FIG. 4 is only schematic and does not represent the true voltage value.
  • one frame includes a display period and a blanking period.
  • both the blanking reset signal line CLK_E and the compensation selection control signal line CLK_A provide high-level signals. Therefore, the first transistor T1 and the eighth transistor T8 in the three shift registers are all turned on.
  • the input signal STU (low level) is provided to the first node K to pull down the voltage of the first node K
  • the first voltage VGL (low level) is provided to the second node L to transfer the first node L
  • the voltage of the second node L is pulled down.
  • the low level of the second node L makes the third node M high.
  • the fifth transistor T5, the sixth transistor T6, and the tenth transistor T10 are turned on to provide the first voltage VGL (low level) to the second node L and the output terminal OUTPUT.
  • VGL low level
  • the first node K, the second node L and the output terminal OUTPUT of the three shift registers are reset to realize a global reset.
  • the shift register SR_1 receives the high-level input signal STU_1, and the third transistor T3 and the ninth transistor T9 are turned on.
  • the received high-level input signal STU_1 is provided to the second node L_1, and the voltage of the second node L_1 is high.
  • the high-level voltage is maintained by the second capacitor C2.
  • the twelfth transistor T12 is turned on, and the voltages of the fourth node O_1, the fifth node P_1, and the sixth node Q_1 are at a high level.
  • the voltage difference between the first pole and the second pole of the fifth transistor T5, the seventh transistor T7, and the ninth transistor T9 are all close to 0V, thereby preventing the charge of the second node L_1 from passing through the fifth transistor T5, the seventh transistor T7, and the ninth transistor.
  • the transistor T9 is leaked.
  • the corresponding fifth transistor T5, seventh transistor T7, and ninth transistor T9 all have protection functions. The role of leakage will be omitted below.
  • the first shift register SR_1 receives the high-level clock signal CLK1. Under the bootstrap action of the second capacitor C2, the voltage of the second node L_1 is further pulled up. Under the control of the higher level of the second node L_1, the fourth transistor T4 is turned on.
  • the shift register SR_1 outputs a high-level scan driving signal OUT_1 through the output terminal OUTPUT_1.
  • the high-level scan driving signal OUT_1 can be used to drive the first row of pixels in the display panel, and can also be used as the input signal STU_2 of the second shift register SR_2.
  • the output terminal OUTPUT_2 of the second shift register SR_2 outputs a high-level scan driving signal OUT_2, so the display reset signal STD_1 of the first shift register SR_1 is high.
  • the seventh transistor T7 and the eleventh transistor T11 are turned on to provide the first voltage VGL (low level) to the second node L_1 to complete the reset of the second node L_1.
  • the fourth transistor T4 is turned off, and the output terminal OUTPUT_1 of the first shift register SR_1 outputs a low-level signal.
  • the low level of the second node L_1 makes the voltage of the third node M_1 high.
  • the fifth transistor T5, the sixth transistor T6 and the tenth transistor T10 are turned on to provide the first voltage VGL (low level) to the second node L_1 and the output terminal OUTPUT_1, and further reset the second node L_1 and the output terminal OUTPUT_1 .
  • the first shift register SR_1 drives the first row of pixels to complete the display, and so on, the second shift register SR_2, the third shifter SR_3, etc. sequentially drive the second and third rows of pixels in the display panel row by row Complete the scan drive.
  • the first shift register SR_1 outputs a high-level scan driving signal OUT_1, and the input signal STU_2 of the second shift register SR_2 is a high level.
  • the third transistor T3 and the ninth transistor T9 are turned on, and the received input signal STU_2 is provided to the second node L_2.
  • the voltage of the second node L_2 is high.
  • the high level voltage is maintained by the second capacitor C2
  • the first shift register SR_1 continuously outputs the high-level scan driving signal OUT_1.
  • the input signal STU_2 of the second shift register SR_2 is continuously high.
  • the third transistor T3 and the ninth transistor T9 are turned on. Therefore, the voltage of the second node L_2 is still at a high level.
  • the high-level voltage is maintained by the second capacitor C2.
  • the second shift register SR_2 receives a high-level compensation selection control signal OE and a high-level input signal STU_2, respectively.
  • the first transistor T1 is turned on.
  • the received high-level input signal STU_2 is provided to the first node K_2. Therefore, the voltage of the first node K_2 is at a high level.
  • the second shift register SR_2 receives a high-level blanking control signal CLKS.
  • the voltages of both poles of the first capacitor C1 are both high level. The first capacitor C1 is not charged and keeps the 0V voltage difference between the compensation selection control signal terminal and the first node K_2.
  • the second shift register SR_2 receives the high-level blanking input signal BSTU_2. Based on the high level of the first node K_2, the received high-level blanking input signal BSTU_2 is provided to the second node L_2. Thus, the second node L_2 is further provided with a high level.
  • the capacitance of the first capacitor C1 is generally set to be smaller than the capacitance of the second capacitor C2. Therefore, when the charging currents are similar, the required charging time is relatively small. Therefore, the high level duration of the timing sequence of the compensation selection control signal OE and the blanking control signal CLKS is shorter than the high level duration of other signals.
  • shift registers in the gate driving circuit 30 respectively receive a high-level compensation selection control signal OE and a low-level input signal STU.
  • the first transistor T1 is turned on. Based on the received high-level compensation selection control signal OE, the received low-level input signal STU is provided to the first node K. Therefore, the voltage of the first node K is low.
  • Other shift registers receive the high-level blanking control signal CLKS. Therefore, the voltages of the two poles of the first capacitor C1 are high and low respectively. The first capacitor C1 is charged and maintains the voltage difference between the high level and the low level.
  • the second shift register SR_2 receives the high-level clock signal CLK2. Under the bootstrap action of the second capacitor C2, the voltage of the second node L_2 is further pulled up. Under the control of the higher level of the second node L_2, the fourth transistor T4 is turned on. Therefore, the second shift register SR_2 outputs a high-level scan driving signal OUT_2.
  • the high-level scan driving signal OUT_2 can be used to drive the pixels in the second row, and can also be used as the input signal STU_3 of the third shift register SR_3.
  • the output terminal OUTPUT_3 of the third shift register SR_3 outputs a high-level scan driving signal OUT_3. Therefore, the display reset signal STD_2 of the second shift register SR_2 is at a high level.
  • the seventh transistor T7 and the eleventh transistor T11 are turned on.
  • the first voltage VGL (low level) is provided to the second node L_2 to complete the reset of the second node L_2.
  • the fourth transistor T4 is turned off, and the output terminal OUTPUT_2 of the second shift register SR_2 outputs a low-level signal.
  • the low level of the second node L_2 makes the voltage of the third node M_2 high.
  • the fifth transistor T5, the sixth transistor T6, and the tenth transistor T10 are turned on.
  • the first voltage VGL is provided to the second node L_2 and the output terminal OUTPUT_2 to further reset the second node L_2 and the output terminal OUTPUT_2.
  • the blanking period of one frame starts.
  • the blanking control signal CLKS is at a high level. Since the voltage difference between the first pole and the second pole of the first capacitor C1 remains 0V, the voltage of the first node K_2 is at a high level.
  • the second transistor T2 is turned on to provide the high-level blanking input signal BSTU_2 to the second node L_2. Therefore, the voltage of the second node L_2 becomes a high level. The high-level voltage is maintained by the second capacitor C2.
  • the blanking control signal CLKS is a high-level signal
  • the voltage difference between the first pole and the second pole of the first capacitor C1 remains high.
  • the voltage difference between the level and the low level therefore, the voltage of the first node K is the low level.
  • the second transistor T2 is turned off. Therefore, the second node L maintains the reset state, that is, the low level.
  • the clock signal CLK2 becomes a high-level signal, and the fourth transistor T4 is turned on. Due to the bootstrap effect of the second capacitor C2, the voltage of the second node L_2 is further pulled up. At this time, the second shift register SR_2 can output the compensation driving signal OUT_2 according to the clock signal CLK2 to drive the sensing transistors of the second row of pixels to work, and compensate the second row of pixels based on the sensed driving current.
  • the second node L remains at a low level, and the fourth transistor T4 is turned off.
  • the output terminals of other shift registers output low-level signals.
  • the compensation selection control signal OE and the blanking reset signal TRST are high.
  • the first transistor T1 and the eighth transistor T8 in the three shift registers are turned on.
  • the input signal STU low level
  • the first voltage VGL low level
  • the low level of the second node L makes the voltage of the third node M high.
  • the fifth transistor T5, the sixth transistor T6, and the tenth transistor T10 are turned on to provide the first voltage VGL to the second node L and the output terminal OUTPUT. Therefore, the first node K, the second node L and the output terminal OUTPUT are reset to realize a global reset. Then, the driving sequence for one frame 1F ends.
  • the working principle of the random compensation described above is described by taking the output of the compensation driving signal for driving the second row of pixels during the blanking period of the first frame as an example, but the present disclosure does not limit this.
  • the timing of the compensation selection control signal OE and the blanking control signal CLKS are used during the display period of the frame. The timing is the same. Further, the high-level duration of the compensation selection control signal OE and the blanking control signal CLKS falls within the high-level duration of the received input signal of the i-th stage shift register (corresponding to the i-th row of pixels).
  • the voltage difference between the blanking control signal terminal of the i-th stage shift register and the first node is stored and maintained. Then, during the blanking period, based on the high-level blanking control signal CLKS and the stored voltage difference, the clock signal CLK is output through the output terminal of the i-th stage shift register as a compensation driving signal.
  • the sensing transistor corresponding to the pixel in the i-th row is driven to work, and the pixel in the i-th row is compensated based on the sensed operating current. It should be noted here that the same timing of two signals refers to time synchronization at a high level, and the amplitude of the two signals is not required to be the same.
  • the embodiments of the present disclosure also provide an array substrate.
  • the array substrate may include a gate driving circuit according to an embodiment of the present disclosure.
  • embodiments of the present disclosure also provide a display device including the above-mentioned array substrate.
  • the display device may be any product or component with display function, such as a liquid crystal panel, a liquid crystal TV, a display, an OLED panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. .
  • FIG. 10 shows a schematic flowchart of a method for driving a shift register according to an embodiment of the present disclosure.
  • the shift register may be any applicable shift register based on the embodiment of the present disclosure.
  • step 510 during the display period, the input signal is provided to the first node according to the compensation selection control signal.
  • the duration of the high level of the compensation selection control signal OE is controlled to fall within the duration of the high level of the input signal STU of the compensation selection circuit.
  • the compensation selection circuit 100 provides the received high-level input signal STU to the storage circuit 200 according to the compensation selection control signal OE.
  • step 520 the voltage difference between the blanking control signal terminal and the first node is stored and maintained.
  • the timing of the blanking control signal CLKS is the same as the timing of the compensation selection control signal OE
  • the voltage difference between the blanking control signal terminal and the first node K is 0 volts
  • the storage circuit 200 maintains the voltage difference.
  • the display input circuit 410 may provide an input signal to the second node L during the display period. According to the voltage of the second node L and the clock signal CLK, the scan driving signal is output from the output terminal OUTPUT as the input signal STU of the next stage shift register, and the corresponding pixel is driven for display.
  • step 530 during the blanking period, the blanking input signal is provided to the second node L according to the voltage of the first node K. Since the voltage difference between the blanking control signal terminal and the first node K is 0 volts, the timing of the voltage of the first node K is consistent with the timing of the blanking control signal CLKS.
  • the blanking input circuit 300 provides the blanking input signal BSTU to the second node L based on the voltage of the first node K.
  • a compensation driving signal is output according to the voltage of the second node L and the clock signal CLK.
  • the shift register circuit 400 provides the clock signal CLK to the output terminal OUTPUT according to the high-level voltage of the second node L as a compensation driving signal.
  • the compensation drive signal can be used to compensate the pixels.

Abstract

L'invention concerne un registre à décalage (10) et son procédé d'attaque, ainsi qu'un circuit d'attaque de grille (30) et un dispositif d'affichage. Le registre à décalage (10) est apte à comprendre un circuit de sélection de compensation (100), un circuit de stockage (200), un circuit d'entrée de suppression (300) et un circuit de registre à décalage (400). Le circuit de sélection de compensation (100) est configuré pour fournir un signal d'entrée à un premier nœud. Le circuit de stockage (200) est configuré pour stocker et maintenir une différence de tension entre un terminal de signal de commande de suppression et le premier nœud. Le circuit d'entrée de suppression (300) est configuré pour fournir un signal d'entrée de suppression à un second nœud. Le circuit de registre à décalage (400) est configuré pour fournir un signal d'attaque de compensation pendant une période de suppression et pour fournir un signal d'attaque de balayage pendant une période d'affichage.
PCT/CN2019/079477 2019-03-25 2019-03-25 Registre à décalage et son procédé d'attaque, circuit d'attaque de grille et dispositif d'affichage WO2020191571A1 (fr)

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US16/649,519 US11232763B2 (en) 2019-03-25 2019-03-25 Shift register and driving method for compensating for linear pattern appearing on display device
CN201980000383.3A CN110114817B (zh) 2019-03-25 2019-03-25 移位寄存器及其驱动方法、栅极驱动电路和显示装置
PCT/CN2019/079477 WO2020191571A1 (fr) 2019-03-25 2019-03-25 Registre à décalage et son procédé d'attaque, circuit d'attaque de grille et dispositif d'affichage

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