WO2020186560A1 - Oled 背板及其制作方法 - Google Patents

Oled 背板及其制作方法 Download PDF

Info

Publication number
WO2020186560A1
WO2020186560A1 PCT/CN2019/081344 CN2019081344W WO2020186560A1 WO 2020186560 A1 WO2020186560 A1 WO 2020186560A1 CN 2019081344 W CN2019081344 W CN 2019081344W WO 2020186560 A1 WO2020186560 A1 WO 2020186560A1
Authority
WO
WIPO (PCT)
Prior art keywords
common electrode
layer
insulating layer
electrode line
metal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/081344
Other languages
English (en)
French (fr)
Inventor
李星
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Publication of WO2020186560A1 publication Critical patent/WO2020186560A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/82—Interconnections, e.g. terminals

Definitions

  • the invention relates to the field of display technology, in particular to an OLED backplane and a manufacturing method thereof.
  • OLED Organic Light Emitting Display
  • OLED is self-luminous at the same time, does not need backlight, high contrast, thin thickness, wide viewing angle, fast response speed, can be used for flexible panels, wide operating temperature range, structure And its excellent features such as relatively simple manufacturing process are considered as emerging application technologies for the next generation of flat panel displays.
  • IGZO Indium gallium zinc oxide
  • a-Si amorphous Silicon
  • IGZO is a P-type doped metal oxide semiconductor, which mainly completes thin film transistor (TFT) through hole (e+) migration.
  • TFT thin film transistor
  • the insulating layer in contact with IGZO generally can only be made of oxygen-enriched silicon oxide (SiOx) instead of hydrogen-enriched silicon nitride (SiNx).
  • SiOx oxygen-enriched silicon oxide
  • SiNx hydrogen-enriched silicon nitride
  • the dielectric coefficient of SiOx is significantly smaller than that of SiNx.
  • the thickness of the SiOx film will be selected to increase on the basis of normal SiNx; consequently, the SiOx etching time is too long
  • the risk of by-products is amplified, and eventually the contact impedance of the via hole is abnormally large, and even the problem of inability to conduction occurs, which brings about product yield loss and reliability risk.
  • the OLED backplane used in the prior art generally includes a plurality of parallel and spaced first common electrode lines 101 fabricated on a first metal layer, and a plurality of parallel and spaced alignments fabricated on a transparent metal layer.
  • the second common electrode lines 102 of the plurality of first common electrode lines 101 and the plurality of second common electrode lines 102 intersect to form a grid shape, and each second common electrode line 102 intersects the first common electrode line 103
  • a through hole 103 is formed in the area of, so that each second common electrode line 102 can be electrically connected to the first common electrode line 103 through the through hole 103, as shown in FIG.
  • the via 103 needs to pass through the three insulating layers to realize the second common electrode line 102 and the first common electrode line 103 At this time, the etching time required to make the via 103 is longer, and there are many by-products, especially when the IGZO technology is used, the by-products are more, and the by-products will cause the second common electrode line
  • the connection between 102 and the first common electrode line 103 fails, resulting in poor display.
  • the purpose of the present invention is to provide an OLED backplane, which can improve the connection stability of the common electrode line, improve the product yield and reduce the product development cost.
  • the purpose of the present invention is also to provide a manufacturing method of an OLED backplane, which can improve the connection stability of the common electrode line, improve the product yield and reduce the product development cost.
  • the present invention provides an OLED backplane, which includes a base substrate, a first metal layer provided on the base substrate, a first insulating layer provided on the first metal layer, a device A semiconductor layer on the first insulating layer, a second insulating layer on the first insulating layer and the semiconductor layer, and a second metal layer on the second insulating layer;
  • the first metal layer includes a plurality of first common electrode lines arranged in parallel at intervals
  • the second metal layer includes a plurality of second common electrode lines arranged in parallel at intervals
  • the first common electrode line is connected to the second common electrode line.
  • Common electrode lines cross;
  • a via hole penetrating the first insulating layer and the second insulating layer is formed at a position where each first common electrode line crosses the second common electrode line, and each second common electrode line passes through the via hole It is electrically connected with each first common electrode line.
  • the material of the semiconductor layer is IGZO, and the materials of the first insulating layer and the second insulating layer are both silicon oxide.
  • the first metal layer further includes a plurality of parallel and spaced gate lines, the gate lines and the first common electrode line are parallel and spaced apart, and the second metal layer further includes a plurality of parallel and spaced source electrodes. Line, the source line and the second common electrode line are spaced in parallel.
  • the OLED backplane further includes a passivation layer provided on the second metal layer and an OLED layer provided on the passivation layer.
  • the present invention also provides a manufacturing method of an OLED backplane, including the following steps:
  • Step S1 Provide a base substrate, and form a first metal layer on the base substrate, the first metal layer including a plurality of first common electrode lines arranged in parallel and spaced apart;
  • Step S2 forming a first insulating layer on the first metal layer, and forming a semiconductor layer on the first insulating layer;
  • Step S3 forming a second insulating layer on the first insulating layer and the semiconductor layer;
  • Step S4 patterning the second insulating layer and the first insulating layer to form a plurality of via holes that pass through the second insulating layer and the first insulating layer and are arranged at intervals;
  • Step S5 forming a second metal layer on the second insulating layer, the second metal layer including a plurality of second common electrode lines arranged in parallel and spaced apart;
  • the first common electrode line crosses the second common electrode line
  • the plurality of via holes are respectively located at a position where each first common electrode line crosses the second common electrode line
  • each second common electrode line The wires are electrically connected to the first common electrode wires through the via holes.
  • the material of the semiconductor layer is IGZO, and the materials of the first insulating layer and the second insulating layer are both silicon oxide.
  • the step S4 specifically includes:
  • Step S41 forming a photoresist film on the second insulating layer
  • Step S42 exposing and developing the photoresist film through a photomask to obtain a photoresist layer
  • Step S43 the photoresist layer is used to block the etching of the second insulating layer and the first insulating layer to form a plurality of via holes arranged at intervals;
  • Step S44 removing the photoresist layer.
  • the photoresist layer is a positive photoresist, and the etching is dry etching.
  • the first metal layer further includes a plurality of gate lines arranged in parallel and spaced apart, and the gate lines are spaced in parallel with the first common electrode line.
  • the second metal layer further includes A plurality of source lines arranged in parallel and spaced apart, and the source lines are spaced in parallel with the second common electrode line.
  • the manufacturing method of the OLED backplane further includes step S6, forming a passivation layer on the second metal layer and forming an OLED layer on the passivation layer.
  • the present invention provides an OLED backplane, including a base substrate, a first metal layer provided on the base substrate, a first insulating layer provided on the first metal layer, a device A semiconductor layer on the first insulating layer, a second insulating layer on the first insulating layer and the semiconductor layer, and a second metal layer on the second insulating layer;
  • the first metal The layer includes a plurality of first common electrode lines arranged in parallel at intervals
  • the second metal layer includes a plurality of second common electrode lines arranged in parallel at intervals, the first common electrode line and the second common electrode line;
  • a via hole penetrating the first insulating layer and the second insulating layer is formed at a position where each first common electrode line crosses the second common electrode line, and each second common electrode line passes through the via hole and
  • Each first common electrode line is electrically connected, and by forming a second common electrode line on the second metal layer, the thickness of the insulating layer that the via hole needs to pass through can be reduced, the by-product
  • FIG. 1 is a schematic diagram of the structure of an existing OLED backplane
  • FIG. 2 is a schematic diagram of the film layer distribution of the OLED backplane of the present invention.
  • FIG. 3 is a wiring distribution diagram of the OLED backplane of the present invention.
  • Figure 4 is a cross-sectional view at A-A in Figure 3;
  • FIG. 5 is a flowchart of the manufacturing method of the OLED backplane of the present invention.
  • FIG. 6 is a schematic diagram of step S4 of the manufacturing method of the OLED backplane of the present invention.
  • the present invention provides a OLED Backplane, including base substrate 1 , Located on the base substrate 1
  • the first metal layer 2 Located on the first metal layer 2 First insulating layer 3 , Located on the first insulating layer 3
  • Semiconductor layer 4 Located on the first insulating layer 3 And semiconductor layer 4 Second insulating layer 5 And arranged on the second insulating layer 5 Second metal layer 6 ;
  • the first metal layer 2 Including a plurality of first common electrode lines arranged at intervals in parallel twenty one
  • the second metal layer 6 Including a plurality of second common electrode lines arranged at intervals in parallel 61 , The first common electrode line twenty one With the second common electrode line 61 cross;
  • each first common electrode line twenty one With the second common electrode line 61 The crossing position is formed to penetrate the first insulating layer 3 And the second insulating layer 5 Via 7 , Each second common electrode line 61 Through the via 7 With each first common electrode line twenty one Electrical connection.
  • the semiconductor layer 4 The material is IGZO , The first insulating layer 3 And the second insulating layer 5 The materials are all silicon oxide.
  • first insulating layer 3 And the second insulating layer 5 The material can further include other materials such as silicon nitride, but it is necessary to ensure that the first insulating layer 3 And the second insulating layer 5 With semiconductor layer 4
  • the contact surface material is silicon oxide to meet IGZO Semiconductor characteristics.
  • the first metal layer 2 also includes multiple gate lines arranged in parallel and spaced apart twenty two , The gate line twenty two With the first common electrode line twenty one Parallel spacing
  • the second metal layer 6 also includes multiple parallel source lines arranged at intervals 62 , The source line 62 With the second common electrode line 61 Parallel spacing.
  • first metal layer 2 The gate line twenty two Electrically connected gate, the second metal layer 2 also includes the source line 62 Electrically connected source and drain spaced from the source, the source and the drain are connected to the semiconductor layer 4 The two ends touch.
  • the OLED The backplane also includes the second metal layer 6 Passivation layer 8 And located on the passivation layer 8 Up OLED Floor 9 .
  • the OLED Floor 9 Including the passivation layer 8
  • the anode on the upper side is located on the anode and passivation layer 8
  • the pixel defining layer on the upper side, the light emitting layer provided on the anode, and the cathode provided on the light emitting layer and the pixel defining layer, the pixel defining layer is formed with a pixel defining groove at a position corresponding to the anode, the pixel
  • the defining groove exposes a part of the anode, and the light-emitting layer is formed in the pixel defining groove.
  • the present invention is adopted in the second metal layer 2 Making the second common electrode line in 61 , Able to pass through 7
  • the thickness of the insulating layer that needs to be traversed that is, the via hole in the present invention 7 Only need to pass through the first insulating layer 3 And the second insulating layer 5 , No need to go through the passivation layer 8 , which can reduce vias 7 By-products generated during the manufacturing process to prevent the second common electrode line caused by excessive by-products 61
  • With the first common electrode line twenty one The poor connection between them guarantees the quality of the display panel, so that enterprises do not need to develop new etching schemes and reduce enterprise development costs.
  • the manufacturing method of the backplane includes the following steps:
  • step S1 Provide a base substrate 1 , On the base substrate 1 First metal layer 2 , The first metal layer 2 Including a plurality of first common electrode lines arranged at intervals in parallel twenty one .
  • the first metal layer 2 also includes multiple gate lines arranged in parallel and spaced apart twenty two The gate line twenty two With the first common electrode line twenty one Parallel spacing.
  • first metal layer 2 The gate line twenty two Electrically connected grid.
  • step S2 In the first metal layer 2 First insulating layer 3 , In the first insulating layer 3 Semiconductor layer 4 .
  • the semiconductor layer 4 The material is IGZO ,
  • the first insulating layer 3 The materials are all silicon oxide.
  • the material can further include other materials such as silicon nitride, but it is necessary to ensure that the first insulating layer 3 With semiconductor layer 4
  • the contact surface material is silicon oxide to meet IGZO Semiconductor characteristics.
  • step S3 In the first insulating layer 3 And semiconductor layer 4 A second insulating layer 5 .
  • the second insulating layer 5 The materials are all silicon oxide.
  • the second insulating layer 5 The material of can further include other materials such as silicon nitride, but it is necessary to ensure that the second insulating layer 5 With semiconductor layer 4
  • the contact surface material is silicon oxide to meet IGZO Semiconductor characteristics.
  • step S4 On the second insulating layer 5 And the first insulating layer 3 Patterning, passing through the second insulating layer 5 And the first insulating layer 3 And spaced multiple vias 7 .
  • the steps S4 It specifically includes: specifically, the steps S4 Specifically:
  • step S41 In the second insulating layer 5 A layer of photoresist film is formed on it;
  • step S42 Expose and develop the photoresist film through a photomask to obtain a photoresist layer 51 ;
  • step S43 The photoresist layer 51 To shield the second insulating layer 5 And the first insulating layer 3 Perform etching to form multiple vias arranged at intervals 7 ;
  • step S44 Remove the photoresist layer 51 .
  • the photoresist layer 51 It is a positive photoresist, and the etching is dry etching.
  • step S5 In the second insulating layer 5 The second metal layer 6 , The second metal layer 6 Including a plurality of second common electrode lines arranged at intervals in parallel 61 ;
  • first common electrode line twenty one With the second common electrode line 61 Cross the multiple vias 7 Respectively located on each first common electrode line twenty one With the second common electrode line 61 Crossing position, each second common electrode line 61 Through the via 7 With each first common electrode line twenty one Electrical connection.
  • the second metal layer 6 also includes multiple parallel source lines arranged at intervals 62 , The source line 62 With the second common electrode line 61 Parallel spacing.
  • the second metal layer 2 also includes the source line 62 Electrically connected source and drain spaced from the source, the source and the drain are connected to the semiconductor layer 4 The two ends touch.
  • step S6 In the second metal layer 6 Passivation layer 8 And on the passivation layer 8 Formed on OLED Floor 9 .
  • the OLED Floor 9 Including the passivation layer 8 The anode on the upper side is located on the anode and passivation layer 8
  • the pixel defining layer on the upper side, the light emitting layer provided on the anode, and the cathode provided on the light emitting layer and the pixel defining layer, the pixel defining layer is formed with a pixel defining groove at a position corresponding to the anode, the pixel The defining groove exposes a part of the anode, and the light-emitting layer is formed in the pixel defining groove.
  • the present invention is adopted in the second metal layer 2 Making the second common electrode line in 61 , Able to pass through 7
  • the thickness of the insulating layer that needs to be traversed that is, the via hole in the present invention 7 Only need to pass through the first insulating layer 3 And the second insulating layer 5 , No need to go through the passivation layer 8 , which can reduce vias 7 By-products produced in the manufacturing process, especially IGZO In technology, due to dry etching ( Dry ) When sulfur ( S )
  • S sulfur
  • With the first common electrode line twenty one The poor connection between them guarantees the quality of the display panel, so that enterprises do not need to develop new etching schemes and reduce enterprise development costs.
  • the backplane includes a base substrate, a first metal layer provided on the base substrate, a first insulating layer provided on the first metal layer, a semiconductor layer provided on the first insulating layer, A second insulating layer disposed on the first insulating layer and the semiconductor layer, and a second metal layer disposed on the second insulating layer;
  • the first metal layer includes a plurality of first common electrodes arranged in parallel and spaced apart
  • the second metal layer includes a plurality of second common electrode lines arranged in parallel and spaced apart, the first common electrode line and the second common electrode line; each of the first common electrode line and the second common electrode line A via hole penetrating the first insulating layer and the second insulating layer is formed at the position where the common electrode line crosses.
  • Each second common electrode line is electrically connected to each first common electrode line through the via hole, and passes Forming the second common electrode line on the second metal layer can reduce the thickness of the insulating layer that the via needs to pass through, reduce the by-products produced during the production of the via, improve the connection stability of the common electrode line, and improve the product yield while reducing Product development costs.
  • the invention also provides a OLED The manufacturing method of the backplane can improve the connection stability of the common electrode line, improve the product yield and reduce the product development cost.

Landscapes

  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种OLED背板及其制作方法。所述OLED背板包括依次层叠的衬底基板（1）、第一金属层（2）、第一绝缘层（3）、半导体层（4）、第二绝缘层（5）及第二金属层（6）；所述第一金属层（2）包括多条平行间隔排列的第一公共电极线（21），第二金属层（6）包括多条平行间隔排列的第二公共电极线（61），所述第一公共电极线（21）与第二公共电极线（61）交叉；在每一条第一公共电极线（21）与第二公共电极线（61）交叉的位置形成有贯穿所述第一绝缘层（3）和第二绝缘层（5）的过孔（7），每一条第二公共电极线（61）均通过所述过孔（7）与各条第一公共电极线（21）电性连接，通过在第二金属层（6）形成第二公共电极线（61），能够降低过孔需要穿越的绝缘层的厚度，减少过孔制作时产生的副产物，提升公共电极线的连接稳定性，改善产品良率的同时降低产品开发成本。

Description

OLED背板及其制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种OLED背板及其制作方法。
 背景技术
有机发光二极管显示器件（Organic Light Emitting Display，OLED）由于同时具备自发光，不需背光源、对比度高、厚度薄、视角广、反应速度快、可用于挠曲性面板、使用温度范围广、构造及制程较简单等优异特性，被认为是下一代平面显示器的新兴应用技术。
在OLED显示技术领域，目前业内主流多以氧化铟镓锌（IGZO，Indium Gallium Zinc Oxide）技术作为其背板制作技术的首选。相比传统非晶硅（a-Si，amorphous Silicon），IGZO的常温迁移率要高40~60倍，更有利与提升显示器开口率，也更加适合搭载分辨率要求高、响应速度快的OLED技术。与常规的非晶硅通过电子迁移（e-）实现器件开关不同，IGZO是一种P型参杂的金属氧化物半导体，主要通过空穴(e+)迁移来完成薄膜晶体管（Thin film transistor，TFT）的充放电。因其独特的半导体特性要求，故与IGZO接触的绝缘层一般都只能选用氧富集的氧化硅（SiOx）而不是氢富集的氮化硅（SiNx）。常规来讲，SiOx介电系数较SiNx明显较小，为改善上下层金属静电击伤问题，SiOx膜层的厚度会选择会在正常SiNx基础上增加；随之而来，SiOx蚀刻时间过长产生副产物的风险被放大，最终导致转接孔接触阻抗异常偏大，甚至出现无法导通的问题，带来产品良率损失和信赖性风险。而通过制程调试改善副产物导致的阻抗异常，需要评估新的蚀刻气体、逐步进行工艺参数调试、制程控制、良率监控和信赖性评价，占用企业大量生产资源，开发成本很高。
如图1所示，现有技术所采用的OLED背板一般包括制作于第一金属层上的多条平行间隔排列的第一公共电极线101以及制作于透明金属层上的多条平行间隔排列的第二公共电极线102，所述多条第一公共电极线101与多条第二公共电极线102交叉形成网格状，且每一条第二公共电极线102与第一公共电极线103交叉的区域均形成有一过孔103，使得每一条第二公共电极线102能够通过过孔103与第一公共电极线103电性连接，如图1所示，在第一金属层与透明金属层之间具有栅极绝缘层201、层间绝缘层202及钝化层203三个绝缘层，所述过孔103需要穿越该三个绝缘层才能实现第二公共电极线102与第一公共电极线103的电性连接，此时，制作所述过孔103所需的蚀刻时长较长，产生的副产物很多，尤其是采用IGZO技术时的副产物更多，该副产物会导致第二公共电极线102与第一公共电极线103之间的连接失效，进而导致显示不良。
 技术问题
本发明的目的在于提供一种OLED背板，能够提升公共电极线的连接稳定性，改善产品良率的同时降低产品开发成本。
本发明的目的还在于提供一种OLED背板的制作方法，能够提升公共电极线的连接稳定性，改善产品良率的同时降低产品开发成本。
 技术解决方案
为实现上述目的，本发明提供了一种OLED背板，包括衬底基板、设于所述衬底基板上的第一金属层、设于所述第一金属层上的第一绝缘层、设于所述第一绝缘层上的半导体层、设于所述第一绝缘层及半导体层上的第二绝缘层及设于所述第二绝缘层上的第二金属层；
所述第一金属层包括多条平行间隔排列的第一公共电极线，所述第二金属层包括多条平行间隔排列的第二公共电极线，所述第一公共电极线与所述第二公共电极线交叉；
在每一条第一公共电极线与所述第二公共电极线交叉的位置形成有贯穿所述第一绝缘层和第二绝缘层的过孔，每一条第二公共电极线均通过所述过孔与各条第一公共电极线电性连接。
所述半导体层的材料为IGZO，所述第一绝缘层及第二绝缘层的材料均为氧化硅。
所述第一金属层还包括多条平行间隔排列的栅极线，所述栅极线与所述第一公共电极线平行间隔，所述第二金属层还包括多条平行间隔排列的源极线，所述源极线与所述第二公共电极线平行间隔。
所述OLED背板还包括设于所述第二金属层上的钝化层及设于所述钝化层上的OLED层。
本发明还提供一种OLED背板的制作方法，包括如下步骤：
步骤S1、提供一衬底基板，在所述衬底基板上形成第一金属层，所述第一金属层包括多条平行间隔排列的第一公共电极线；
步骤S2、在所述第一金属层上形成第一绝缘层，在所述第一绝缘层上形成半导体层；
步骤S3、在所述第一绝缘层及半导体层上形成第二绝缘层；
步骤S4、对所述第二绝缘层及第一绝缘层进行图案化，形成穿越所述第二绝缘层及第一绝缘层且间隔排列的多个过孔；
步骤S5、在所述第二绝缘层上形成第二金属层，所述第二金属层包括多条平行间隔排列的第二公共电极线；
所述第一公共电极线与所述第二公共电极线交叉，所述多个过孔分别位于每一条第一公共电极线与所述第二公共电极线交叉的位置，每一条第二公共电极线均通过所述过孔与各条第一公共电极线电性连接。
所述半导体层的材料为IGZO，所述第一绝缘层及第二绝缘层的材料均为氧化硅。
所述步骤S4具体包括：
步骤S41、在所述第二绝缘层上形成一层光阻薄膜；
步骤S42、通过一道光罩对所述光阻薄膜进行曝光和显影，得到光阻层；
步骤S43、所述光阻层为遮挡对所述第二绝缘层及第一绝缘层进行蚀刻，形成多个间隔排列的过孔；
步骤S44、去除所述光阻层。
所述光阻层为正性光阻，所述蚀刻为干蚀刻。
所述步骤S1中第一金属层还包括多条平行间隔排列的栅极线，所述栅极线与所述第一公共电极线平行间隔，所述步骤S5中所述第二金属层还包括多条平行间隔排列的源极线，所述源极线与所述第二公共电极线平行间隔。
所述OLED背板的制作方法还包括步骤S6、在所述第二金属层上形成钝化层及在所述钝化层上形成OLED层。
 有益效果
本发明的有益效果：本发明提供一种OLED背板，包括衬底基板、设于所述衬底基板上的第一金属层、设于所述第一金属层上的第一绝缘层、设于所述第一绝缘层上的半导体层、设于所述第一绝缘层及半导体层上的第二绝缘层及设于所述第二绝缘层上的第二金属层；所述第一金属层包括多条平行间隔排列的第一公共电极线，所述第二金属层包括多条平行间隔排列的第二公共电极线，所述第一公共电极线与所述第二公共电极线；在每一条第一公共电极线与所述第二公共电极线交叉的位置形成有贯穿所述第一绝缘层和第二绝缘层的过孔，每一条第二公共电极线均通过所述过孔与各条第一公共电极线电性连接，通过在第二金属层形成第二公共电极线，能够降低过孔需要穿越的绝缘层的厚度，减少过孔制作时产生的副产物，提升公共电极线的连接稳定性，改善产品良率的同时降低产品开发成本。本发明还提供一种OLED背板的制作方法，能够提升公共电极线的连接稳定性，改善产品良率的同时降低产品开发成本。
 附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为现有的OLED背板的结构示意图；
图2为本发明的OLED背板的膜层分布示意图；
图3为本发明的OLED背板的走线分布图；
图4为图3中A-A处的剖面图；
图5为本发明的OLED背板的制作方法的流程图；
图6为本发明的OLED背板的制作方法的步骤S4的示意图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图 2 至图 4 ，本发明提供一种 OLED 背板，包括衬底基板 1 、设于所述衬底基板 1 上的第一金属层 2 、设于所述第一金属层 2 上的第一绝缘层 3 、设于所述第一绝缘层 3 上的半导体层 4 、设于所述第一绝缘层 3 及半导体层 4 上的第二绝缘层 5 及设于所述第二绝缘层 5 上的第二金属层 6 ；
所述第一金属层 2 包括多条平行间隔排列的第一公共电极线 21 ，所述第二金属层 6 包括多条平行间隔排列的第二公共电极线 61 ，所述第一公共电极线 21 与所述第二公共电极线 61 交叉；
在每一条第一公共电极线 21 与所述第二公共电极线 61 交叉的位置形成有贯穿所述第一绝缘层 3 和第二绝缘层 5 的过孔 7 ，每一条第二公共电极线 61 均通过所述过孔 7 与各条第一公共电极线 21 电性连接。
具体地，所述半导体层 4 的材料为 IGZO ，所述第一绝缘层 3 及第二绝缘层 5 的材料均为氧化硅。
进一步地，所述第一绝缘层 3 及第二绝缘层 5 的材料还可以进一步包括氮化硅等其他材料，但需要保证第一绝缘层 3 及第二绝缘层 5 与半导体层 4 接触的表面材料为氧化硅，以满足 IGZO 的半导体特性。
具体地，所述第一金属层 2 还包括多条平行间隔排列的栅极线 22 ，所述栅极线 22 与所述第一公共电极线 21 平行间隔，所述第二金属层 6 还包括多条平行间隔排列的源极线 62 ，所述源极线 62 与所述第二公共电极线 61 平行间隔。
进一步地，所述第一金属层 2 中的还包括与所述栅极线 22 电性连接的栅极，所述第二金属层 2 还包括与所述源极线 62 电性连接的源极及与所述源极间隔的漏极，所述源极和漏极与所述半导体层 4 的两端接触。
具体地，所述 OLED 背板还包括设于所述第二金属层 6 上的钝化层 8 及设于所述钝化层 8 上的 OLED 层 9 。
进一步地，所述 OLED 层 9 包括设于所述钝化层 8 上的阳极，设于所述阳极及钝化层 8 上的像素定义层、设于所述阳极上的发光层及设于所述发光层及像素定义层上的阴极，所述像素定义层对应所述阳极的位置形成有像素定义槽，所述像素定义槽暴露出所述阳极的一部分，所述发光层形成于所述像素定义槽内。
需要说明的是，本发明通过在第二金属层 2 中制作第二公共电极线 61 ，能够过孔 7 所需要穿越的绝缘层的厚度，也即本发明的中的过孔 7 仅需要穿越第一绝缘层 3 及第二绝缘层 5 ，无需再穿越钝化层 8 ，从而能够减少过孔 7 在制作过程中产生的副产物，防止因副产物过多导致的第二公共电极线 61 与第一公共电极线 21 之间的连接不良，保证显示面板的品质，使得企业无需再开发新的蚀刻方案，减少企业开发成本。
请参阅图 5 ，本发明还提供一种 OLED 背板的制作方法，包括如下步骤：
步骤 S1 、提供一衬底基板 1 ，在所述衬底基板 1 上形成第一金属层 2 ，所述第一金属层 2 包括多条平行间隔排列的第一公共电极线 21 。
具体地，具体地，所述第一金属层 2 还包括多条平行间隔排列的栅极线 22 所述栅极线 22 与所述第一公共电极线 21 平行间隔。
进一步地，述第一金属层 2 中的还包括与所述栅极线 22 电性连接的栅极。
步骤 S2 、在所述第一金属层 2 上形成第一绝缘层 3 ，在所述第一绝缘层 3 上形成半导体层 4 。
具体地，所述半导体层 4 的材料为 IGZO ，所述第一绝缘层 3 的材料均为氧化硅。
进一步地，所述第一绝缘层 3 的材料还可以进一步包括氮化硅等其他材料，但需要保证第一绝缘层 3 与半导体层 4 接触的表面材料为氧化硅，以满足 IGZO 的半导体特性。
步骤 S3 、在所述第一绝缘层 3 及半导体层 4 上形成第二绝缘层 5 。
具体地，所述第二绝缘层 5 的材料均为氧化硅。
进一步地，所述第二绝缘层 5 的材料还可以进一步包括氮化硅等其他材料，但需要保证第二绝缘层 5 与半导体层 4 接触的表面材料为氧化硅，以满足 IGZO 的半导体特性。
步骤 S4 、对所述第二绝缘层 5 及第一绝缘层 3 进行图案化，穿越所述第二绝缘层 5 及第一绝缘层 3 且间隔排列的多个过孔 7 。
具体地，如图 6 所示，所述步骤 S4 具体包括：具体地，所述步骤 S4 具体包括：
步骤 S41 、在所述第二绝缘层 5 上形成一层光阻薄膜；
步骤 S42 、通过一道光罩对所述光阻薄膜进行曝光和显影，得到光阻层 51 ；
步骤 S43 、所述光阻层 51 为遮挡对所述第二绝缘层 5 及第一绝缘层 3 进行蚀刻，形成多个间隔排列的过孔 7 ；
步骤 S44 、去除所述光阻层 51 。
具体地，所述光阻层 51 为正性光阻，所述蚀刻为干蚀刻。
步骤 S5 、在所述第二绝缘层 5 上形成第二金属层 6 ，所述第二金属层 6 包括多条平行间隔排列的第二公共电极线 61 ；
其中，所述第一公共电极线 21 与所述第二公共电极线 61 交叉，所述多个过孔 7 分别位于每一条第一公共电极线 21 与所述第二公共电极线 61 交叉的位置，每一条第二公共电极线 61 均通过所述过孔 7 与各条第一公共电极线 21 电性连接。
具体地，所述第二金属层 6 还包括多条平行间隔排列的源极线 62 ，所述源极线 62 与所述第二公共电极线 61 平行间隔。
进一步地，所所述第二金属层 2 还包括与所述源极线 62 电性连接的源极及与所述源极间隔的漏极，所述源极和漏极与所述半导体层 4 的两端接触。
步骤 S6 、在所述第二金属层 6 上形成钝化层 8 及在所述钝化层 8 上形成 OLED 层 9 。
具体地，所述 OLED 层 9 包括设于所述钝化层 8 上的阳极，设于所述阳极及钝化层 8 上的像素定义层、设于所述阳极上的发光层及设于所述发光层及像素定义层上的阴极，所述像素定义层对应所述阳极的位置形成有像素定义槽，所述像素定义槽暴露出所述阳极的一部分，所述发光层形成于所述像素定义槽内。
需要说明的是，本发明通过在第二金属层 2 中制作第二公共电极线 61 ，能够过孔 7 所需要穿越的绝缘层的厚度，也即本发明的中的过孔 7 仅需要穿越第一绝缘层 3 及第二绝缘层 5 ，无需再穿越钝化层 8 ，从而能够减少过孔 7 在制作过程中产生的副产物，尤其是 IGZO 技术中，因干蚀刻（ Dry ）时硫（ S ）与正性光阻反应凝结产生的副产物，防止因副产物过多导致的第二公共电极线 61 与第一公共电极线 21 之间的连接不良，保证显示面板的品质，使得企业无需再开发新的蚀刻方案，减少企业开发成本。
综上所述，本发明提供一种 OLED 背板，包括衬底基板、设于所述衬底基板上的第一金属层、设于所述第一金属层上的第一绝缘层、设于所述第一绝缘层上的半导体层、设于所述第一绝缘层及半导体层上的第二绝缘层及设于所述第二绝缘层上的第二金属层；所述第一金属层包括多条平行间隔排列的第一公共电极线，所述第二金属层包括多条平行间隔排列的第二公共电极线，所述第一公共电极线与所述第二公共电极线；在每一条第一公共电极线与所述第二公共电极线交叉的位置形成有贯穿所述第一绝缘层和第二绝缘层的过孔，每一条第二公共电极线均通过所述过孔与各条第一公共电极线电性连接，通过在第二金属层形成第二公共电极线，能够降低过孔需要穿越的绝缘层的厚度，减少过孔制作时产生的副产物，提升公共电极线的连接稳定性，改善产品良率的同时降低产品开发成本。本发明还提供一种 OLED 背板的制作方法，能够提升公共电极线的连接稳定性，改善产品良率的同时降低产品开发成本。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种OLED背板，包括衬底基板、设于所述衬底基板上的第一金属层、设于所述第一金属层上的第一绝缘层、设于所述第一绝缘层上的半导体层、设于所述第一绝缘层及半导体层上的第二绝缘层及设于所述第二绝缘层上的第二金属层；
    所述第一金属层包括多条平行间隔排列的第一公共电极线，所述第二金属层包括多条平行间隔排列的第二公共电极线，所述第一公共电极线与所述第二公共电极线交叉；
    在每一条第一公共电极线与所述第二公共电极线交叉的位置形成有贯穿所述第一绝缘层和第二绝缘层的过孔，每一条第二公共电极线均通过所述过孔与各条第一公共电极线电性连接。
  2. 如权利要求1所述的OLED背板，其中，所述半导体层的材料为IGZO，所述第一绝缘层及第二绝缘层的材料均为氧化硅。
  3. 如权利要求1所述的OLED背板，其中，所述第一金属层还包括多条平行间隔排列的栅极线，所述栅极线与所述第一公共电极线平行间隔，所述第二金属层还包括多条平行间隔排列的源极线，所述源极线与所述第二公共电极线平行间隔。
  4. 如权利要求1所述的OLED背板，还包括设于所述第二金属层上的钝化层及设于所述钝化层上的OLED层。
  5. 一种OLED背板的制作方法，包括如下步骤：
    步骤S1、提供一衬底基板，在所述衬底基板上形成第一金属层，所述第一金属层包括多条平行间隔排列的第一公共电极线；
    步骤S2、在所述第一金属层上形成第一绝缘层，在所述第一绝缘层上形成半导体层；
    步骤S3、在所述第一绝缘层及半导体层上形成第二绝缘层；
    步骤S4、对所述第二绝缘层及第一绝缘层进行图案化，形成穿越所述第二绝缘层及第一绝缘层且间隔排列的多个过孔；
    步骤S5、在所述第二绝缘层上形成第二金属层，所述第二金属层包括多条平行间隔排列的第二公共电极线；
    所述第一公共电极线与所述第二公共电极线交叉，所述多个过孔分别位于每一条第一公共电极线与所述第二公共电极线交叉的位置，每一条第二公共电极线均通过所述过孔与各条第一公共电极线电性连接。 
  6. 如权利要求5所述的OLED背板的制作方法，其中，所述半导体层的材料为IGZO，所述第一绝缘层及第二绝缘层的材料均为氧化硅。
  7. 如权利要求5所述的OLED背板的制作方法，其中，所述步骤S4具体包括：
    步骤S41、在所述第二绝缘层上形成一层光阻薄膜；
    步骤S42、通过一道光罩对所述光阻薄膜进行曝光和显影，得到光阻层；
    步骤S43、所述光阻层为遮挡对所述第二绝缘层及第一绝缘层进行蚀刻，形成多个间隔排列的过孔；
    步骤S44、去除所述光阻层。
  8. 如权利要求7所述的OLED背板的制作方法，其中，所述光阻层为正性光阻，所述蚀刻为干蚀刻。
  9. 如权利要求5所述的OLED背板的制作方法，其中，所述步骤S1中第一金属层还包括多条平行间隔排列的栅极线，所述栅极线与所述第一公共电极线平行间隔，所述步骤S5中所述第二金属层还包括多条平行间隔排列的源极线，所述源极线与所述第二公共电极线平行间隔。
  10. 如权利要求5所述的OLED背板的制作方法，还包括步骤S6、在所述第二金属层上形成钝化层及在所述钝化层上形成OLED层。
PCT/CN2019/081344 2019-03-21 2019-04-03 Oled 背板及其制作方法 Ceased WO2020186560A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910219441.3 2019-03-21
CN201910219441.3A CN109920829A (zh) 2019-03-21 2019-03-21 Oled背板及其制作方法

Publications (1)

Publication Number Publication Date
WO2020186560A1 true WO2020186560A1 (zh) 2020-09-24

Family

ID=66966198

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/081344 Ceased WO2020186560A1 (zh) 2019-03-21 2019-04-03 Oled 背板及其制作方法

Country Status (2)

Country Link
CN (1) CN109920829A (zh)
WO (1) WO2020186560A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112086576B (zh) * 2020-09-07 2022-09-09 武汉华星光电半导体显示技术有限公司 一种显示面板及制程方法
CN119644639B (zh) * 2024-11-14 2025-10-03 深圳市华星光电半导体显示技术有限公司 显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080121885A1 (en) * 2006-11-25 2008-05-29 Wintek Corporation Thin Film Transistor Array Panel of Active Liquid Crystal Display and Fabrication Method Thereof
CN105161455A (zh) * 2015-07-31 2015-12-16 深圳市华星光电技术有限公司 一种ffs阵列基板及其制造方法和显示装置
CN105161505A (zh) * 2015-09-28 2015-12-16 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板
CN106298813A (zh) * 2016-09-30 2017-01-04 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102023429B (zh) * 2009-09-17 2013-10-23 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造和断线修复方法
CN103077944B (zh) * 2013-01-18 2016-03-09 京东方科技集团股份有限公司 显示装置、阵列基板及其制作方法
KR20160129159A (ko) * 2015-04-29 2016-11-09 삼성디스플레이 주식회사 액정 표시 장치
CN105425492B (zh) * 2016-01-06 2018-12-11 京东方科技集团股份有限公司 阵列基板及其制备方法
CN107357105A (zh) * 2017-09-05 2017-11-17 京东方科技集团股份有限公司 一种阵列基板、显示面板、显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080121885A1 (en) * 2006-11-25 2008-05-29 Wintek Corporation Thin Film Transistor Array Panel of Active Liquid Crystal Display and Fabrication Method Thereof
CN105161455A (zh) * 2015-07-31 2015-12-16 深圳市华星光电技术有限公司 一种ffs阵列基板及其制造方法和显示装置
CN105161505A (zh) * 2015-09-28 2015-12-16 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示面板
CN106298813A (zh) * 2016-09-30 2017-01-04 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示装置

Also Published As

Publication number Publication date
CN109920829A (zh) 2019-06-21

Similar Documents

Publication Publication Date Title
CN110649043B (zh) 阵列基板、显示面板、显示装置及阵列基板的制备方法
CN108598089B (zh) Tft基板的制作方法及tft基板
CN106981520B (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
CN103217840B (zh) 一种阵列基板、制备方法以及液晶显示装置
CN104966696B (zh) Tft基板的制作方法及其结构
KR20200055774A (ko) 디스플레이 패널 및 그 제조방법
CN107424957A (zh) 柔性tft基板的制作方法
CN108376688A (zh) 一种感光组件及其制备方法、阵列基板、显示装置
WO2014166176A1 (zh) 薄膜晶体管及其制作方法、阵列基板和显示装置
US10347660B2 (en) Array substrate and manufacturing method thereof
WO2021248609A1 (zh) 一种阵列基板及其制备方法以及显示面板
WO2020200168A1 (zh) Amoled显示屏、显示设备及移动终端
CN103811503A (zh) 阵列基板及制备方法、显示面板
CN103187423A (zh) 一种氧化物薄膜晶体管阵列基板及其制作方法、显示面板
CN104952880A (zh) 双栅极tft基板的制作方法及其结构
WO2020238640A1 (zh) 一种显示基板及其制作方法、显示装置
WO2022213420A1 (zh) 一种阵列基板及其制备方法、oled显示面板
US9230995B2 (en) Array substrate, manufacturing method thereof and display device
WO2024027397A1 (zh) 阵列基板及显示面板
US10361261B2 (en) Manufacturing method of TFT substrate, TFT substrate, and OLED display panel
WO2021120378A1 (zh) 一种阵列基板及其制作方法
CN104916649A (zh) 阵列基板及其制造方法
CN104882414A (zh) Tft基板的制作方法及其结构
WO2020186560A1 (zh) Oled 背板及其制作方法
WO2021097995A1 (zh) 一种阵列基板及其制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19920383

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19920383

Country of ref document: EP

Kind code of ref document: A1