WO2020185023A1 - 패키징 기판 및 이의 제조방법 - Google Patents
패키징 기판 및 이의 제조방법 Download PDFInfo
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- WO2020185023A1 WO2020185023A1 PCT/KR2020/003483 KR2020003483W WO2020185023A1 WO 2020185023 A1 WO2020185023 A1 WO 2020185023A1 KR 2020003483 W KR2020003483 W KR 2020003483W WO 2020185023 A1 WO2020185023 A1 WO 2020185023A1
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Definitions
- the embodiment relates to a packaging substrate and a method of manufacturing the same.
- FE Front-End
- BE Back-End
- the four core technologies of the semiconductor industry that have enabled the rapid development of recent electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology.
- Semiconductor technology is developing in various forms, such as a line width of sub-micron nano units, more than 10 million cells, high-speed operation, and dissipation of a lot of heat, but the technology for packaging it relatively completely is not supported. Accordingly, the electrical performance of the semiconductor is sometimes determined by the packaging technology and the electrical connection accordingly rather than the performance of the semiconductor technology itself.
- Ceramic or resin is used as a material for the packaging substrate.
- a ceramic substrate it is difficult to mount a high-performance, high-frequency semiconductor device due to its high resistance value or high dielectric constant.
- a resin substrate it is possible to mount a relatively high-performance, high-frequency semiconductor element, but there is a limit to reducing the pitch of wiring.
- An object of the embodiment is to provide a more integrated packaging substrate and a semiconductor device including the same by applying a glass substrate.
- An object of the embodiment is to provide a substrate for semiconductor packaging including a glass substrate having a core seed layer formed inside a core via, and a method of manufacturing the same.
- the core layer includes a glass substrate and a core via
- the glass substrate has a first surface and a second surface facing each other,
- a plurality of the core vias are disposed to penetrate the glass substrate in the thickness direction
- the core layer includes a core distribution layer positioned on the surface of the glass substrate or the core via,
- the core distribution layer at least partially includes an electroconductive layer electrically connecting the electroconductive layer on the first surface and the electroconductive layer on the second surface through the core via,
- the angle of the inner diameter surface observed from the cross section of the core via from the opening of the opening contacting the first surface and the opening of the opening contacting the second surface having a large diameter to a portion having the minimum inner diameter of the core via is It may be 8 degrees or less based on the thickness direction perpendicular to the first surface.
- the core via includes a first opening in contact with the first surface; A second opening in contact with the second surface; And a minimum inner diameter portion, which is a region having the narrowest inner diameter of the entire core via connecting the first opening and the second opening.
- the diameter of the minimum inner diameter portion may have a size of 50% to 99% based on a larger diameter among the first opening and the second opening.
- the point where the minimum inner diameter portion is positioned may be positioned at a point of 40% to 60% based on the first opening when the entire length of the core via is viewed as 100%.
- the angle (Ca1) of the inner diameter surface connecting the minimum inner diameter portion and the first opening and the angle (Ca2) of the inner diameter surface connecting the minimum inner diameter portion and the second opening are 1:0.7 to 1.3. It can have a ratio.
- a glass substrate having a first surface and a second surface facing each other;
- a core layer positioned on the surface of the core via and in which a core seed layer serving as a seed for forming an electrically conductive layer is positioned;
- the ratio (thickness ratio) of the first thickness and the second thickness, which is the thickness of the core seed layer, measured at two positions facing each other among the inner diameter surfaces of the core via may be 1:0.4 to 4.5.
- the thickness deviation ratio of the core seed layer represented by Equation 1 below may be 90% or less.
- Thickness deviation rate ((maximum thickness of core seed layer-minimum thickness of core seed layer)/average thickness of core seed layer) ⁇ 100%
- the average thickness of the core seed layer may be 30 to 200 nm.
- the angle of the inner diameter surface observed from the cross section of the core via from the opening of the opening contacting the first surface and the opening of the opening contacting the second surface having a large diameter to a portion having the minimum inner diameter of the core via is It may be 8 degrees or less based on the thickness direction perpendicular to the first surface.
- the semiconductor device according to the embodiment,
- An element unit including a semiconductor element; And a packaging substrate according to an embodiment electrically connected to the device unit.
- the packaging substrate of the embodiment and the semiconductor device including the same may significantly improve electrical characteristics such as a signal transmission speed by connecting the semiconductor device and the motherboard closer to each other so that the electrical signal is transmitted over the shortest distance possible.
- the glass substrate applied as the core of the substrate is itself an insulator, there is almost no fear of occurrence of parasitic elements compared to the conventional silicon core, so that the insulating film treatment process can be more simplified and can be applied to high-speed circuits.
- FIG. 1 is a conceptual diagram illustrating a cross-section of a semiconductor device according to an embodiment.
- FIG. 2 is a conceptual diagram illustrating a cross section of a packaging substrate according to an embodiment.
- FIG. 3(a) a conceptual view illustrating a view of the glass substrate on which the core via is formed from above, and (b) a cross-sectional view taken by cutting a-a' of (a).
- 4A and 4B are conceptual diagrams each illustrating a cross-sectional shape of a core via applied in an implementation example.
- FIG. 5 is a conceptual diagram illustrating a state in which a core insulating layer is further formed in FIG. 4B.
- FIG. 6 is a detailed conceptual diagram illustrating a part of a cross section of a packaging substrate according to an embodiment.
- FIG. 7 is a detailed conceptual diagram illustrating a part of a cross section of a packaging substrate according to an embodiment.
- FIGS. 8 to 10 are flowcharts illustrating a manufacturing process of a packaging substrate according to an embodiment in cross section.
- FIG. 11 is a top view of a glass substrate having a core via according to an embodiment (a) and a conceptual view illustrating a cross section of the core via (b).
- FIG. 12 is a schematic cross-sectional view of a core via explaining a measurement point applied when evaluating a thickness deviation in an embodiment.
- FIG. 13 is a photograph showing exemplary thickness measurements of a core seed layer measured according to an embodiment.
- FIG. 14 is a top view of a glass substrate having a core via according to another embodiment (a) and a conceptual view illustrating a cross section of the core via (b).
- 15 is a cross-sectional conceptual diagram of a core via for explaining measurement points applied when evaluating thickness deviation in another embodiment.
- the term "combination of these" included in the expression of the Makushi form means one or more mixtures or combinations selected from the group consisting of the constituent elements described in the expression of the Makushi form, and the constituent elements It means to include one or more selected from the group consisting of.
- the “ ⁇ ” system may mean including a compound corresponding to “ ⁇ ” or a derivative of “ ⁇ ” in the compound.
- B is located on A means that B is located directly on A or B is located on A while another layer is located between them, and B is located so as to contact the surface of A. It is limited to that and is not interpreted.
- the inventors recognized that not only the device itself but also the packaging part is an important factor in improving performance, and were researching it. Unlike the application of two or more layers of cores on the motherboard as a packaging substrate such as an interposer and an organic substrate, the glass core is applied as a single layer, and the shape of the through via, the electrically conductive layer formed therein, etc. It was confirmed that by applying the control method, the packaging substrate can be made thinner and help improve the electrical characteristics of the semiconductor device.
- FIG. 1 is a conceptual diagram illustrating a cross-section of a semiconductor device according to an embodiment
- FIG. 2 is a conceptual diagram illustrating a cross-section of a packaging substrate according to an embodiment
- FIG. 3 (a) a view of a glass substrate on which a core via is formed from above
- (b) is a conceptual diagram illustrating a cross section seen by cutting a-a' of (a).
- 4A and 4B are conceptual diagrams for explaining the shape of a cross section of a core via applied in each implementation example
- FIG. 5 is a cross-sectional view illustrating a state in which a core insulating layer is further formed in FIG. 4B.
- FIG. 1 is a conceptual diagram illustrating a cross-section of a semiconductor device according to an embodiment
- FIG. 2 is a conceptual diagram illustrating a cross-section of a packaging substrate according to an embodiment
- FIG. 3 (a) a view of a glass substrate on which a core via is formed from above
- b is
- FIG. 6 is a detailed conceptual diagram illustrating a part of a cross section of a packaging substrate according to an embodiment
- FIG. 7 is a detailed conceptual diagram illustrating a part of a cross section of a packaging substrate according to an implementation example.
- an embodiment will be described in more detail with reference to FIGS. 1 to 7.
- a semiconductor device 100 includes a semiconductor device portion 30 in which one or more semiconductor devices 32, 34, and 36 are positioned; A packaging substrate 20 electrically connected to the semiconductor device; And a motherboard 10 that is electrically connected to the packaging substrate, transmits an external electrical signal to the semiconductor device, and connects to each other.
- the packaging substrate 20 includes a core layer 22; And an upper layer 26;
- the semiconductor device part 30 refers to devices mounted on a semiconductor device, and is mounted on the packaging substrate 20 by connection electrodes or the like.
- the semiconductor device unit 30 includes, for example, an arithmetic device such as a CPU and a GPU (first device: 32, a second device: 34), and a memory device such as a memory chip (third device, 36).
- an arithmetic device such as a CPU and a GPU
- a memory device such as a memory chip
- any semiconductor device mounted on a semiconductor device can be applied without limitation.
- the motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.
- the packaging substrate 20 includes a core layer 22; And an upper layer 26 positioned on one surface of the core layer.
- the packaging substrate 20 may further include a lower layer 29 selectively positioned under the core layer.
- the core layer 22 includes a glass substrate 21; A plurality of core vias 23 penetrating the glass substrate in the thickness direction; And a core distribution layer on which an electroconductive layer is located on the surface of the glass substrate or the core via, at least a part of which electrically connects the electroconductive layer on the first surface and the second surface through the core via ( 24); includes.
- the glass substrate 21 has a first surface 213 and a second surface 214 facing each other, and the two surfaces are substantially parallel to each other, so that the entire glass substrate has a constant thickness.
- a core via 23 penetrating the first and second surfaces is disposed on the glass substrate 21.
- a silicon substrate and an organic substrate are laminated.
- silicon substrates due to the nature of semiconductors, parasitic elements may occur when applied to high-speed circuits, and power losses are relatively large.
- organic substrates a larger area is required to form a more complex distribution pattern, but this does not correspond to the flow of manufacturing microelectronic devices.
- it is necessary to substantially refine the pattern but there is a practical limit to pattern refinement due to the characteristics of materials such as polymers applied to organic substrates.
- the glass substrate 21 is applied as a support for the core layer 22 as a method of solving these problems.
- the core via 23 formed while penetrating the glass substrate together with the glass substrate the length of the electrical flow is shorter, smaller, faster response, and a packaging substrate 20 having less loss characteristics. to provide.
- the glass substrate 21 is preferably a glass substrate applied to a semiconductor.
- a borosilicate glass substrate, an alkali-free glass substrate, etc. may be applied, but the present invention is not limited thereto.
- the glass substrate 21 may have a thickness of 1,000 ⁇ m or less, may be 100 to 1,000 ⁇ m, and may be 100 to 700 ⁇ m. More specifically, the glass substrate 21 may have a thickness of 100 to 500 ⁇ m. Forming a thinner packaging substrate is advantageous in that electrical signal transmission can be made more efficient, but it should also serve as a support, so it is preferable to apply the glass substrate 21 having the above-described thickness.
- the thickness of the glass substrate refers to the thickness of the glass substrate itself excluding the thickness of the electrically conductive layer on the glass substrate.
- the core via 23 may be formed by removing a predetermined region of the glass substrate 21, and specifically, may be formed by etching plate-shaped glass by physical and/or chemical methods.
- a method of chemically etching after forming a defect (fault) on the surface of a glass substrate by a method such as a laser, or a laser etching method may be applied, but is not limited thereto.
- the core via 23 may include a first opening 233 in contact with the first surface; A second opening 234 in contact with the second surface; And a minimum inner diameter portion 235, which is a region having the narrowest inner diameter of the entire core via connecting the first opening portion and the second opening portion.
- the diameter of the first opening (CV1) and the diameter of the second opening (CV2) may be substantially different, and the first opening 233 and the second opening 234 may have substantially the same diameter. .
- the minimum inner diameter portion may be located in the first opening or the second opening, and in this case, the core via may be a cylindrical or (cut) triangular pyramid shaped core via.
- the diameter of the minimum inner diameter (CV3) corresponds to the diameter of the smaller of the first opening and the second opening.
- the minimum inner diameter portion is located between the first opening and the second opening, and the core via may be a barrel-shaped core via.
- the diameter of the minimum inner diameter (CV3) may be smaller than a larger one of the diameter of the first opening and the diameter of the second opening.
- the average diameter of the minimum inner diameter may be specifically 50 ⁇ m to 95 ⁇ m.
- the minimum inner diameter portion may satisfy the condition of Equation 1 below.
- D 50 is a value corresponding to 50% of the diameter distribution of the minimum inner diameter
- D 90 is a value corresponding to 90% of the diameter distribution of the minimum inner diameter
- D 10 is the diameter distribution of the minimum inner diameter. It corresponds to 10% of the values.
- the average diameter of the minimum inner diameter may be 55 ⁇ m to 85 ⁇ m, and may be 60 ⁇ m to 70 ⁇ m.
- the minimum inner diameter portion may satisfy the condition of Equation 1-1 below.
- D 50 is a value corresponding to 50% of the diameter distribution of the minimum inner diameter
- D 90 is a value corresponding to 90% of the diameter distribution of the minimum inner diameter
- D 10 is It is a value corresponding to 10% of the diameter distribution.
- the target opening which is the larger of the first opening diameter and the second opening diameter, may have an average diameter of 70 ⁇ m to 120 ⁇ m.
- the target opening which is the larger of the first opening diameter and the second opening diameter, may satisfy the condition of Equation 2 below.
- D 50 is a value corresponding to 50% of the diameter distribution of the target opening
- D 90 is a value corresponding to 90% of the diameter distribution of the target opening
- D 10 is 10% of the diameter distribution of the target opening. It is a value corresponding to.
- the target opening which is the larger of the first opening diameter and the second opening diameter, may have an average diameter of 80 ⁇ m to 105 ⁇ m.
- the target opening which is the larger of the first opening diameter and the second opening diameter, may satisfy the condition of Equation 2-1 below.
- D 50 is a value corresponding to 50% of the diameter distribution of the target opening
- D 90 is a value corresponding to 90% of the diameter distribution of the target opening
- D 10 is the diameter distribution of the target opening. It is a value corresponding to 10%.
- the core via is the larger of the first opening diameter, which is a diameter at the opening contacting the first surface, and the second opening diameter, which is the diameter at the opening contacting the second surface, wherein the average diameter of the target opening is the diameter of the target opening. It may have a value greater than D 50, which is a value corresponding to 50% of the distribution.
- the diameter distribution described above was measured by dividing the prepared sample into 9 compartments (3 X 3), taking samples of 5 areas: upper left, lower left, center, upper right, and lower right, and cut them and observed with a microscope in a cross section. It evaluated based on the diameter.
- the thickness of the electrically conductive layer measured at the larger of the first opening diameter (CV1) and the second opening diameter (CV2) is the same as the thickness of the electrically conductive layer formed on the portion (CV3) having the minimum inner diameter of the core via It can be thick.
- 100 to 3000 core vias 23 may be located, 100 to 2500 may be located, and 225 to 1024 Dogs can be located.
- this pitch condition it is possible to improve the formation of an electrically conductive layer and the like and performance of the packaging substrate.
- the core via 23 may be positioned on the glass substrate 21 at a pitch of 1.2 mm or less, may be positioned at a pitch of 0.12 mm to 1.2 mm, and may be positioned at a pitch of 0.3 mm to 0.9 mm. . In this case, it is advantageous to form an electrically conductive layer or the like while maintaining the mechanical properties of the glass substrate above a certain level.
- the core distribution layer 24 includes a core distribution pattern 241, which is an electrically conductive layer electrically connecting the first and second surfaces of the glass substrate through a through via, and a core insulating layer 223 surrounding the core distribution pattern. ).
- the core layer 22 has an electrically conductive layer formed therein through a core via to serve as an electrical path across the glass substrate 21, and connects the upper and lower portions of the glass substrate over a relatively short distance to provide faster electrical It can have the characteristics of signal transmission and low loss.
- the core distribution pattern 241 is a pattern that electrically connects the first surface 213 and the second surface 214 of the glass substrate through a core via 23, and specifically, the first surface 213 A first surface distribution pattern 241a, which is an electrically conductive layer on at least part of the second surface 214, a second surface distribution pattern 241c, which is an electrically conductive layer on at least a part of the second surface 214, and the first And a core via distribution pattern 241b which is an electrically conductive layer electrically connecting the surface distribution pattern and the second surface distribution pattern to each other through the core via 23.
- the electrically conductive layers may be, for example, applied with a copper plating layer, but are not limited thereto.
- the core via 23 may include a first opening 233 in contact with the first surface; A second opening 234 in contact with the second surface; And a minimum inner diameter portion 235, which is a region having the narrowest inner diameter of the entire core via connecting the first opening portion and the second opening portion.
- the glass substrate 21 serves as an intermediate and intermediary for connecting the semiconductor device 30 and the motherboard 10 to the upper and lower portions, respectively, and the core via 23 serves as a path for transmitting their electrical signals. The signal is smoothly transmitted.
- one opening may have a larger diameter and the other opening may have a smaller diameter based on the thickness of the glass substrate (refer to FIG. 4(a) and photo), and the center It may be an overall barrel-shaped core via in which the inner diameter of the core via is slightly narrower in the portion (see Fig. 4(b) and photo).
- the core via 23 has a first surface opening diameter (CV1) that is a diameter at the first opening, a second surface opening diameter (CV2) that is a diameter at the second opening, and a diameter at the minimum inner diameter. It has the minimum inner diameter (CV3).
- the core via 23 may have the first surface opening diameter CV1 and the second surface opening diameter CV2 substantially the same or different from each other.
- One of the inner diameter surfaces connecting the first opening and the second opening of the core via 22 may have an inner diameter smaller than that of the other, and this is referred to as a minimum inner diameter (part).
- the size of the minimum inner diameter (CV3) is the larger of the first surface opening diameter (CV1) and the second surface opening diameter (CV2). It may be 50% to 99%, and may be 70% to 95%. In the case of having a size narrowed to this range, the formation of an electrically conductive layer, etc. may be performed more smoothly.
- the point where the minimum inner diameter is located is viewed as 100% of the entire length of the core via (G21), it may be located at 40% to 60% point (G23) based on the first opening, and 45% to 55% Can be located on the branch. In this way, when the minimum inner diameter portion is present in the position described above based on the entire length of the core via, the process of designing the electroconductive layer of the packaging substrate and forming the electroconductive layer may be easier.
- the diameter of the larger one of the first surface opening diameter (CV1) that is the diameter at the first opening and the second surface opening diameter (CV2) that is the diameter at the second opening and the size of the minimum inner diameter (CV3) is 1: It may be a ratio of 0.65 to 0.99, and 1: may be a ratio of 0.72 to 0.95. In the case of having the size of the inner diameter narrowed in this range, the formation of the electroconductive layer and the like may proceed more smoothly.
- the core via 22 has an angle observed from the cross section of the core via from the opening of the opening in contact with the first surface and the opening of the opening in contact with the second surface with a larger diameter to a portion having the minimum inner diameter in the core via. It may be 8 degrees or less based on the thickness direction perpendicular to the first surface.
- An angle Ca1 of an inner diameter surface connecting the minimum inner diameter portion and the first opening and an angle Ca2 of an inner diameter surface connecting the minimum inner diameter portion and the second opening may have a ratio of 1:0.7 to 1.3.
- the difference between the angle of the inner diameter surface of the core via starting from the first opening and the inner diameter surface of the core via starting from the second opening may be insignificant, so that the subsequent plating process may proceed more smoothly.
- the angle is evaluated as an angle with an imaginary reference line perpendicular to the first surface or the second surface, and is evaluated as an absolute value regardless of the direction (the same applies hereinafter).
- the larger of the angle Ca1 of the inner diameter surface connecting the minimum inner diameter portion and the first opening and the angle Ca2 of the inner diameter surface connecting the minimum inner diameter portion and the second opening may be 8 degrees or less, and 0.1 degrees. It may be to 8 degrees, and may be 0.5 to 6.5 degrees. In the case of having such an angle, subsequent processes such as plating may proceed more smoothly, and it is easier to construct an electrically conductive layer having an intended pattern.
- the thickness of the electroconductive layer measured at the larger of the first surface opening diameter (CV1) and the second surface opening diameter (CV2) is the thickness of the electroconductive layer formed on the portion (CV3) having the minimum inner diameter of the core via. It can be the same or thick.
- the core distribution layer 24 is an electrically conductive layer formed on a glass substrate, and a cross cut adhesion test value according to ASTM D3359 may satisfy 4B or more, and specifically 5B or more.
- the electroconductive layer which is the core distribution layer 24, may have an adhesive force of 3 N/cm or more with the glass substrate, and may have a bonding force of 4.5 N/cm or more. When this degree of adhesion is satisfied, it has sufficient adhesion between the substrate and the electroconductive layer to be applied as a packaging substrate.
- An upper layer 26 is positioned on the first surface 213.
- the upper layer 26 includes an upper distribution layer 25 and a top connection layer 27 positioned on the upper distribution layer, and the uppermost surface of the upper layer 26 can directly contact the connection electrodes of the semiconductor device. It may be protected by the cover layer 60 in which the opening is formed.
- the upper distribution layer 25 includes an upper insulating layer 253 positioned on the first surface;
- the core distribution layer 24 and at least a portion thereof are electrically conductive layers having a predetermined pattern and include an upper distribution pattern 251 embedded in the upper insulating layer.
- the upper insulating layer 253 may be applied as long as it is applied as an insulator layer to a semiconductor device or a packaging substrate, and for example, an epoxy resin including a filler may be applied, but is not limited thereto.
- the insulator layer may be formed by forming and curing a coating layer, or may be formed by laminating and curing an insulator film filmed in an uncured or semi-cured state on the core layer. In this case, if a pressure-sensitive lamination method or the like is applied, the insulator is inserted into the space inside the core via, thereby enabling efficient process progress. In addition, even if a plurality of insulator layers are stacked and applied, it may be difficult to distinguish between the insulator layers, and a plurality of insulator layers are collectively referred to as an upper insulating layer. In addition, the same insulating material may be applied to the core insulating layer 223 and the upper insulating layer 253, and in this case, the boundary may not be substantially separated.
- the upper distribution pattern 251 refers to an electrically conductive layer positioned within the upper insulating layer 253 in a preset shape, and may be formed in, for example, a build-up layer method. Specifically, after forming an insulator layer, removing unnecessary portions of the insulator layer, forming an electrical conductive layer by copper plating, etc., removing unnecessary portions of the electrical conductive layer, and then forming an insulator layer on the conductive layer again. After forming, removing unnecessary parts again, the method of forming the electroconductive layer by plating or the like may be repeated to form an upper distribution pattern 251 in which the battery conductive layer is formed in a vertical or horizontal direction in an intended pattern. .
- the upper distribution pattern 251 is located between the core layer 22 and the semiconductor device part 30, the transfer of the electrical signal to the semiconductor device part 30 is smoothly performed, and the intended complex pattern is sufficient. It is formed such that a fine pattern is included in at least a part of it so that it can be accommodated.
- the fine pattern may have a width and a spacing of less than 4 ⁇ m, may be 3.5 ⁇ m or less, 3 ⁇ m or less, 2.5 ⁇ m or less, and 1 to 2.3 ⁇ m. .
- the interval may be an interval between fine patterns adjacent to each other (hereinafter, the description of fine patterns is the same).
- the upper distribution pattern 251 to include a fine pattern, at least two or more methods are applied in the embodiment.
- the glass substrate 21 may have a fairly flat surface characteristic with a surface roughness Ra of 10 angstroms or less, and thus the influence of the surface morphology of the support substrate on the formation of a fine pattern can be minimized.
- the other is in the characteristics of the insulator.
- a filler component is often applied together with a resin, and inorganic particles such as silica particles may be applied as the filler.
- inorganic particles such as silica particles
- the size of the inorganic particles may affect whether or not a fine pattern is formed.
- a particulate filler having an average diameter of 150 nm or less is applied, Specifically, it includes a particulate filler having an average diameter of 1 to 100 nm.
- the top connection layer 27 is electrically connected to the top distribution pattern 251 and at least a portion thereof, and includes a top connection pattern 272 located on the top insulating layer 253, the semiconductor device part 30, and the It includes a top connection electrode 271 electrically connecting the top connection pattern 272.
- the top connection pattern 272 may be positioned on one surface of the upper insulating layer 253, or at least a portion thereof may be exposed and embedded on the upper insulating layer.
- the upper insulating layer may be formed by plating or the like, and a part of the top surface connection pattern is exposed on the upper insulating layer. If it is embedded, a part of the insulating layer or the electrically conductive layer may be removed by a method such as surface polishing or surface etching after forming a copper plating layer or the like.
- the top connection pattern 272 may include at least a portion thereof. In this way, the top connection pattern 272 including a fine pattern allows a plurality of devices to be electrically connected even under a narrow area, making electrical signal connection between devices more smooth and more integrated packaging possible. Do.
- the top connection electrode 271 may be directly connected to the semiconductor device unit 30 through a terminal or the like, or may be connected via a device connection part 51 such as a solder ball.
- the packaging substrate 20 is also connected to the motherboard 10.
- a second surface distribution pattern 241c which is a core distribution layer positioned on at least a portion of the second surface 214 of the core layer 22, may be directly connected to a terminal of the motherboard. In addition, it may be electrically connected through a board connection such as a solder ball.
- the second surface distribution pattern 241c may be connected to the motherboard 10 via a lower layer 29 positioned under the core layer 22.
- the lower layer 29 includes a lower partial double layer 291 and a lower surface connection layer 292.
- the lower partial double layer 291 includes: i) a lower insulating layer 291b in which the second surface 214 and at least a portion thereof contact; And ii) a lower part-fold pattern 291a which is embedded (buried) in the lower insulating layer and has a predetermined pattern, and in which the core distribution layer and at least a portion thereof are electrically connected.
- the lower surface connection layer 292 includes i) a lower surface connection electrode 292a that is electrically connected to the lower surface connection pattern, and ii) the lower partial belly pattern and at least a portion thereof are electrically connected, and is formed on one surface of the lower insulating layer. It may further include a lower surface connection pattern (292b) at least a part of the exposed.
- the lower surface connection pattern 292b is a portion connected to the motherboard 10 and may be formed as a non-fine pattern having a width wider than that of the fine pattern, unlike the upper surface connection pattern 272 for more efficient electrical signal transmission.
- One of the characteristics of the present invention is that substantially no other substrates other than the glass substrate 21 are applied to the packaging substrate 20 positioned between the semiconductor device unit 30 and the motherboard 10.
- an interposer and an organic substrate were stacked together to apply an interposer and an organic substrate between the device and the motherboard.
- This is understood to have been applied in a multi-stage form for at least two reasons.
- One is that there is a problem with scale in directly bonding the fine pattern of the device to the motherboard, and the other is that during the bonding process or driving the semiconductor device. This is because a problem of wiring damage due to a difference in thermal expansion coefficient may occur during the process.
- a glass substrate having a coefficient of thermal expansion similar to that of a semiconductor device is applied, and a fine pattern having a fine scale sufficient for device mounting is formed on the first surface and the upper layer of the glass substrate, thereby solving this problem.
- a thickness of a thinner one of the conductive layers of the core distribution layer 24 may be equal to or thicker than a thickness of a thinner one of the conductive layers of the upper layer 26 (Tus). In this way, electric signal transmission between the device and the motherboard is more effective than when the thickness of the thinner one of the conductive layers of the core distribution layer 24 is equal to or thicker than the thickness of the thinner one of the conductive layers of the upper layer 26. You can do it efficiently.
- the thickness Tsc of the thinner of the second surface distribution patterns 241c may be thicker than the thickness Tus of the thinner of the top connection patterns 272.
- the thickness Tds of the thicker one of the lower surface connection electrodes 292a may be thicker than the thickness Tsc of the thinner one of the second surface distribution patterns 241c.
- the semiconductor device 100 has a packaging substrate 20 having a fairly thin thickness, so that the overall thickness of the semiconductor device can be reduced, and by applying a fine pattern, an intended electrical connection pattern can be arranged even in a narrower area.
- the packaging substrate may have a thickness of about 2000 ⁇ m or less, about 1500 ⁇ m or less, and about 900 ⁇ m.
- the packaging substrate may have a thickness of about 120 ⁇ m or more and about 150 ⁇ m or more.
- the packaging substrate as described above, electrically and structurally stably connects the device and the motherboard even with a relatively thin thickness, and may contribute to a smaller and thinner semiconductor device.
- FIGS. 8 to 10 are flow charts illustrating a manufacturing process of a packaging substrate according to the embodiment in cross section.
- a method of manufacturing a packaging substrate according to another embodiment will be described with reference to FIGS. 7 to 9.
- the manufacturing method of the packaging substrate of the embodiment includes: a preparation step of forming defects at predetermined positions on a first surface and a second surface of the glass substrate; An etching step of preparing a glass substrate on which a core via is formed by applying an etching solution to the glass substrate on which the defects are formed; A core layer manufacturing step of forming a core layer by plating the surface of the glass substrate on which the core via is formed to form a core distribution layer, which is an electrically conductive layer; In addition, an upper layer manufacturing step of forming an upper distribution layer, which is an electrically conductive layer wrapped in an insulating layer, on one surface of the core layer, to manufacture the packaging substrate described above.
- the core layer manufacturing step includes a pretreatment process of forming a pretreated glass substrate by forming an organic-inorganic composite primer layer including nanoparticles having an amine group on the surface of the glass substrate on which the core via is formed; And a plating process of plating a metal layer on the pre-treated glass substrate.
- the core layer manufacturing step includes a pretreatment process of forming a pretreated glass substrate by forming a metal-containing primer layer through sputtering on the surface of the glass substrate on which the core via is formed; And a plating process of plating a metal layer on the pre-treated glass substrate.
- An insulating layer forming step may be further included between the core layer manufacturing step and the upper layer manufacturing step.
- the insulating layer forming step may be a step of forming a core insulating layer by placing an insulating film on the core layer and then performing pressure-sensitive lamination.
- the manufacturing method of the packaging substrate will be described in more detail.
- a glass substrate applied to a substrate of an electronic device may be applied.
- an alkali-free glass substrate may be applied, but is not limited thereto.
- products manufactured by manufacturers such as Corning, Short, and AGC can be applied.
- Methods such as mechanical etching and laser irradiation may be applied to the formation of the defects (grooves).
- Etching step core via formation step: The glass substrate 21a on which the defects (grooves, 21b) are formed, forms the core vias 23 through a physical or chemical etching process. During the etching process, the glass substrate forms a via in the defective portion, and at the same time, the surface of the glass substrate 21a may be etched at the same time. In order to prevent the etching of the glass surface, a masking film or the like may be applied, but the defective glass substrate itself can be etched in consideration of the hassle of applying and removing the masking film. The thickness of the glass substrate with the core via may be somewhat thinner than the thickness.
- Core layer manufacturing step An electrically conductive layer 21d is formed on a glass substrate.
- the electroconductive layer may be a metal layer including a copper metal, but is not limited thereto.
- the surface of the glass (including the surface of the glass substrate and the surface of the core via) and the surface of the copper metal have different properties, so the adhesion is poor.
- the adhesion between the glass surface and the metal was improved by two methods, a dry method and a wet method.
- the dry method is a method of applying sputtering, that is, a method of forming the seed layer 21c on the glass surface and the inner diameter surface of the core via by metal sputtering.
- sputtering that is, a method of forming the seed layer 21c on the glass surface and the inner diameter surface of the core via by metal sputtering.
- dissimilar metals such as titanium, chromium, and nickel may be sputtered together with copper, and in this case, it is believed that glass-metal adhesion is improved by an anchor effect in which the surface morphology of the glass and the metal particles interact. do.
- the wet method is a method of performing a primer treatment, and is a method of forming the primer layer 21c by pretreating with a compound having a functional group such as amine.
- a primer treatment may be performed with a compound or particle having an amine functional group after pretreatment with a silane coupling agent.
- the support substrate of the embodiment needs to be of high performance enough to form a fine pattern, and this must be maintained even after the primer treatment. Therefore, when such a primer contains nanoparticles, nanoparticles having an average diameter of 150 nm or less are preferably applied. For example, nanoparticles are preferably applied to particles having an amine group.
- the primer layer may be formed by applying an adhesion improving agent manufactured by MEC's CZ series, for example.
- the electroconductive layer may selectively form a metal layer with or without removing portions that do not require formation of the electroconductive layer.
- a portion requiring or unnecessary formation of an electroconductive layer may be selectively processed in a state activated or deactivated for metal plating, thereby performing a subsequent process.
- the activation or deactivation treatment may be applied to a light irradiation treatment such as a laser having a certain wavelength, or a chemical treatment.
- the metal layer may be formed using a copper plating method applied to semiconductor device manufacturing, but is not limited thereto.
- the thickness of the formed electrically conductive layer may be controlled by adjusting various variables such as the concentration of the plating solution, the plating time, and the type of additive to be applied.
- the core distribution layer may be removed.
- metal plating is performed to form an electrically conductive layer in a predetermined pattern, and the etching layer 21e of the core distribution layer May be formed
- the core via may undergo an insulating layer forming step in which an empty space is filled with an insulating layer after forming the core distribution layer, which is the electrically conductive layer.
- the applied insulating layer may be manufactured in the form of a film, and may be applied, for example, by a method of laminating the insulating layer in the form of a film under reduced pressure. When the pressure-sensitive lamination is performed in this way, the insulating layer is sufficiently penetrated into the empty space inside the core via, thereby forming a core insulating layer without void formation.
- Upper layer manufacturing step This is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer.
- the upper insulating layer may be performed by coating a resin composition forming the insulating layer 23a or stacking an insulating film, and simply stacking an insulating film is preferably applied. Lamination of the insulating film may be performed by laminating and curing the insulating film. In this case, if the pressure-sensitive lamination method is applied, the insulating resin may be sufficiently contained even in a layer in which an electrically conductive layer is not formed inside the core via.
- the upper insulating layer is also in direct contact with the glass substrate in at least a portion thereof, and thus, a material having sufficient adhesion is applied. Specifically, it is preferable that the glass substrate and the upper insulating layer have a property that satisfies an adhesion test value of 4B or more according to ASTM D3359.
- the upper distribution pattern may be formed by repeating the process of forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, and etching unnecessary portions to form the etching layer 23d of the electrically conductive layer.
- the blind via 23b may be formed in the insulating layer and then a plating process may be performed.
- the blind via may be formed by a dry etching method such as laser etching or plasma etching, and a wet etching method using a masking layer and an etching solution.
- the top connection pattern and the top connection electrode may be formed in a process similar to that of the formation of the top distribution layer. Specifically, formed by forming an etching layer 23f of an insulating layer on the insulating layer 23e, forming an electrically conductive layer 23g thereon again, and then forming an etching layer 23h of the electrically conductive layer. However, it may be applied as a method of selectively forming only an electrically conductive layer without applying an etching method.
- the cover layer may be formed such that an opening (not shown) is formed at a position corresponding to the top connection electrode to expose the top connection electrode, and can be directly connected to the device connection part or the terminal of the device.
- a lower surface connection layer and a cover layer In a manner similar to the above-described step of forming the upper connection layer and the cover layer, the lower partial rear layer and/or the lower surface connection layer, and optionally a cover layer (not shown) may be formed.
- FIG. 11 is a top view (a) of a glass substrate having a core via and a conceptual view (b) illustrating a cross section of a core via according to another embodiment.
- a packaging substrate including a glass substrate and a manufacturing method thereof will be described with reference to FIGS. 1 and 11.
- a semiconductor packaging substrate 215 according to another embodiment,
- a glass substrate 21 having a first surface 213 and a second surface 214 facing each other, ii) a plurality of core vias 23 and iii) the core via passing through the glass substrate in the thickness direction And a core layer on which the core seed layer 225, which is a seed for forming an electroconductive layer, is positioned on the surface of.
- the semiconductor packaging substrate 215 may be applied as a component of the packaging substrate 20 of the semiconductor device 100 described above.
- the glass substrate 21 is preferably a glass substrate applied to a semiconductor.
- a borosilicate glass substrate, an alkali-free glass substrate, etc. may be applied, but the present invention is not limited thereto.
- the glass substrate 21 may have a thickness of 1,000 ⁇ m or less, may be 100 ⁇ m to 1,000 ⁇ m, and may be 100 ⁇ m to 700 ⁇ m. More specifically, the glass substrate 21 may have a thickness of 100 ⁇ m to 500 ⁇ m. Forming a thinner packaging substrate is advantageous in that electrical signal transmission can be more efficient, but it should also serve as a support, so it is preferable to apply a glass substrate having the above-described thickness.
- the thickness of the glass substrate refers to the thickness of the glass substrate itself excluding the thickness of the electrically conductive layer on the glass substrate.
- the core via 23 may be formed by removing a predetermined region of the glass substrate 21, and specifically, may be formed by etching plate-shaped glass by physical and/or chemical methods.
- a method of chemically etching after forming a defect (fault) on the surface of a glass substrate by a method such as a laser, or a laser etching method may be applied, but is not limited thereto.
- the core via 23 may include a first opening 233 in contact with the first surface; A second opening 234 in contact with the second surface; And a minimum inner diameter portion 235, which is a region having the narrowest inner diameter of the entire core via connecting the first opening portion and the second opening portion.
- the diameter of the first opening (CV1) and the diameter of the second opening (CV2) may be substantially different, and the first opening (CV1) and the second opening (CV2) may have substantially the same diameter. .
- the minimum inner diameter portion may be located in the first opening or the second opening, and in this case, the core via may be a cylindrical or (cut) triangular pyramidal core via.
- the diameter of the minimum inner diameter (CV3) corresponds to the diameter of the smaller of the first opening and the second opening.
- the minimum inner diameter portion is located between the first opening and the second opening, and in this case, the core via may be a barrel-shaped core via.
- the diameter of the minimum inner diameter (CV3) may be smaller than a larger one of the diameter of the first opening and the diameter of the second opening.
- the core via 23 includes an opening in contact with the first surface, an opening in contact with the second surface, and a portion having a minimum inner diameter among the core vias, and a point where the minimum inner diameter is located is the entire length of the core via When viewed as 100%, it may be located at a point less than 40% or more than 60% based on the first opening. It may be more advantageous for a core via having such a shape to have a value for the thickness ratio described below.
- the core via 23 has an opening-thickness ratio of 1:2 to 4, which means the ratio of the inner diameter of the opening (the larger of the first surface opening and the second surface opening) to the thickness of the glass substrate. have.
- the core via 23 may have a minimum inner diameter portion-thickness ratio of 1:2.5 to 6, which means a ratio of the inner diameter of the minimum inner diameter portion and the thickness of the glass substrate. A core via having such a ratio is more advantageous for forming a core seed layer having features described later.
- a core seed layer may not be sufficiently formed or core seed layers having different thicknesses may be formed in some portions due to the characteristics of the shape of the narrow and long core via.
- This core seed layer is the basis for forming an electrically conductive layer such as a copper layer by plating, etc., and since the thickness distribution of this low conductivity layer can affect the speed and efficiency of electric signal transmission, I need it.
- the first thickness and the second thickness which are the thicknesses of the core seed layer 225, measured at positions facing each other among the inner diameter surfaces of the core via 23 are measured, and the overall thickness is It is checked whether or not a core seed layer is formed.
- the core via 23 in which the core seed layer 225 is located on the inner diameter surface is observed from a cross section, and the thickness of the core seed layer 225 is measured at a predetermined position. Since the core seed layer itself may also have a curved surface, the sample values measured 3 to 5 times or more are averaged and evaluated as a thickness value while finely changing positions at one point.
- the thickness deviation rate represented by Equation 1 below may be 90% or less, 83% or less, and 67% or less. In the case of having such a thickness deviation ratio, a core seed layer having a relatively uniform thickness can be provided.
- Thickness deviation rate ((maximum thickness of core seed layer-minimum thickness of core seed layer)/average thickness of core seed layer) ⁇ 100%
- the maximum thickness is a thickness having a maximum value in the measured core seed layer thickness sample
- the minimum thickness is a thickness having a minimum value in the thickness sample
- the average thickness is an average value of the thickness sample.
- the core seed layer 225 may have an average thickness of 30 nm to 200 nm, and may be 50 nm to 170 nm.
- the core seed layer having such a thickness range can form relatively uniform electrical conductivity intended by the present invention.
- the core seed layer 225 may also have the following features.
- the core seed layers observed in the cross section exist at positions facing each other at the same height, which are matched as 1-1 and 2-1, 1-2 and 2-2 in FIG. 12. Since the core seed layer itself can also have a curved surface, the values measured 3 to 5 times or more are averaged and evaluated as a thickness value while finely changing positions at one point.
- the thicknesses of the core seed layers facing each other are matched with the first thickness and the second thickness, such as 1-1 and 1-2, and these first and second thicknesses are calculated by calculating the ratio of the thickness ratio. It is called as.
- the thickness ratio may be 1:0.4 to 4.5, 1:0.5 to 3.0, and 1:0.7 to 2.0.
- the core seed layer 225 has a relatively even thickness at positions facing each other.
- the thickness ratio measured at three or five locations with different heights among the inner diameter surfaces of the core via 23 may have a standard deviation of 1.5 or less, 1 or less, and 0.8 or less. This means that three or five different heights have a relatively constant thickness. In this case, three or five different heights refer to positions designated at relatively regular intervals in consideration of the overall length of the core via, and the position intervals do not need to be completely the same.
- the inner diameter surface of the core via may have a different thickness depending on the height when the second surface is the reference, and this difference in thickness is likely to occur due to the characteristics of the narrow and long core via.
- the core seed layer 225 having the above-mentioned characteristics provides a core seed layer having a certain characteristic over an appropriate level by controlling the unbalance of the thickness.
- the core seed layer 225 includes a first surface core seed layer 225a disposed on a first surface sequentially connected to each other, a core via seed layer 225b disposed on an inner diameter surface of a core via, and a first surface. It includes a second surface core seed layer 225c positioned on the two surfaces.
- the specific characteristics of the core seed layer 225 mentioned above are applied to the core via seed layer 225b.
- the measured thickness, thickness ratio, and standard deviation of the core seed layer are presented as follows.
- the photograph shown in FIG. 13 is the data of Sample 1.
- Thickness is evaluated as a 5-point average * Thickness ratio is calculated as (1-1/2-1)
- the method of manufacturing the core seed layer includes a preparation step and a sputtering step.
- the preparation step is a step of preparing a processing electric board having a glass substrate having first and second surfaces facing each other and a plurality of core vias penetrating the glass substrate in a thickness direction. Since the detailed description of the glass substrate and the core via is duplicated with the above description, the description thereof is omitted. Further, since the detailed description of the method of forming the core via on the glass substrate and the like is duplicated with the description of the packaging substrate described above, the description thereof will be omitted.
- the sputtering step is a step of forming a core seed layer on the inner diameter surface of the core via by sputtering at a key angle (As) of 10 to 90 degrees with respect to a reference line perpendicular to the first surface.
- the gun angle may be 10 degrees to 65 degrees.
- the gun angle may be from 15 degrees to 55 degrees, and from 15 degrees to 45 degrees.
- the gun angle may be 10 to 35 degrees.
- Step 1 Glass Defect Formation Process: Prepare a glass substrate 21a having a flat first side and a second side, and form a defect (groove, 21b) on the glass surface at a predetermined position for forming a core via. I did. As the glass, borosilicate glass (Corning) was applied. Mechanical etching and laser irradiation methods were applied to the formation of the defects (grooves).
- Etching step core via formation step: The glass substrate 21a on which the defects (grooves, 21b) are formed was formed with the core via 23 through a physical or chemical etching process.
- the core via may include a first opening in contact with the first surface; A second opening in contact with the second surface;
- the inner diameter is formed to have a minimum inner diameter portion, which is the narrowest area, and the position of the minimum inner diameter portion is viewed as 100% of the entire core via length. It was positioned at 40% to 60% of the first opening.
- the angle of the inner diameter surface observed from the cross section of the core via from the largest opening of the first opening and the second opening to the minimum inner diameter is 8 degrees or less based on the thickness direction perpendicular to the second surface. .
- Core layer manufacturing step An electrically conductive layer 21d was formed on a glass substrate. A metal layer containing a copper metal was applied as the electroconductive layer. The adhesion between the surface of the glass substrate and the metal layer was improved by a dry method.
- the dry method is a method of applying sputtering, that is, a method of forming the seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering.
- sputtering that is, a method of forming the seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering.
- the seed layer at least one of titanium, chromium, and nickel was sputtered with copper or the like. In this case, the sputtering was performed at a key angle As of 45 degrees with respect to a reference line perpendicular to the first surface.
- Example 1 except that the position of the minimum inner diameter portion of 2) is less than 40% based on the first opening, and the angle at the time of sputtering of 3-1) was changed to 55 degrees, the embodiment 1 Proceeding in the same manner as, a packaging substrate was manufactured.
- Example 1 a substrate for packaging was manufactured in the same manner as in Example 1, except that the angle during sputtering in 3-1) was changed to 65 degrees.
- Example 1 except that the position of the minimum inner diameter portion of 2) is less than 40% based on the first opening, and the angle during sputtering of 3-1) was changed to 90 degrees, the embodiment 1 Proceeding in the same manner as, a packaging substrate was manufactured.
- Example 1 except that the angle of the inner diameter surface of 2) was changed to exceed 8 degrees, the same procedure as in Example 1 was performed to prepare a packaging substrate.
- Example 1 the angle of the inner diameter surface of 2) was set to exceed 8 degrees, the position of the minimum inner diameter was set to be less than 40% based on the first opening, and the angle during sputtering of 3-1) was Except for changing to 65 degrees, the same procedure as in Example 1 was performed to prepare a packaging substrate.
- Example 1 the angle of the inner diameter surface of 2) was set to exceed 8 degrees, the position of the minimum inner diameter was set to be less than 40% based on the first opening, and the angle during sputtering of 3-1) was Except for changing to 90 degrees, it proceeded in the same manner as in Example 1 to prepare a packaging substrate.
- the thickness of the core seed layer of the packaging substrate manufactured in the above Examples and Comparative Examples was measured five times, including one point and its periphery, and five times including the other point facing the one point and its periphery.
- the first thickness and the second thickness ratio, and the thickness deviation results are shown in Table 1.
- Example 1 Example 2 Example 3 Example 4 Comparative Example 1 Comparative Example 2 Comparative Example 3 Sputtering angle (degree) 45 55 65 90 45 65 90 Ca* (degrees) 8 or less 8 or less 8 or less 8 or less More than 8 More than 8 More than 8 1-n:2-n* 1:0.4 ⁇ 4.5 1:0.4 ⁇ 4.5 1:0.4 ⁇ 4.5 1:0.4 ⁇ 4.5 1:0.4 ⁇ 4.5 1:0.2 1:0.5 Thickness deviation rate*(%) 50 67 83 90 97 102 107 Min inner diameter position*(%) 40-60 Less than 40 40-60 Less than 40 40-60 Less than 40 Less than 40 Less than 40 Less than 40 Less than 40 Less than 40 Less than 40 Less than 40 Less than 40
- Ca The angle of the inner diameter surface observed from the cross section of the core via from the opening of the larger one of the first opening or the second opening to the minimum inner diameter, based on the thickness direction perpendicular to the first surface 1-n: 2-n: of the core via The ratio of the first thickness and the second thickness of the core seed layer measured at two positions facing each other among the inner surface
- Thickness deviation ratio ((maximum thickness of core seed layer-minimum thickness of core seed layer)/average thickness of core seed layer) ⁇ 100%
- Minimum inner diameter position relative to the first opening when the entire length of the core via is viewed as 100%
- the thickness deviation ratio is 90 or less
- the 1-n:2-n ratio is 1:0.4 to 4.5.
- the thickness of the seed layer is shown, and it is determined that the packaging substrate having such characteristics can sufficiently and smoothly transmit electrical signals to devices disposed above or below it.
- the packaging substrate of the embodiment does not form parasitic elements of the glass substrate, and has excellent properties such as that it can serve as a substrate support having a thin and sufficient strength, and an efficient signal transmission by forming an electrically conductive layer with an appropriate ratio of the thickness of the glass substrate. It uses its excellent properties, such as inducing it.
- the glass substrate is evaluated as having poor bonding properties with an electrically conductive layer such as a copper layer, and in order to form an electrically conductive layer of sufficient thickness by a method such as plating, a seed layer or a primer layer, etc., is formed between the glass surface and the electrically conductive layer. Need to be formed. However, when such a seed layer or primer layer is formed too thick, when formed unevenly, it may be difficult to sufficiently form an electrically conductive layer within a diameter of a predetermined core via, which may affect the electrical signal transmission speed of the upper and lower parts of the packaging substrate. It can have a bad effect.
- the thickness of the seed layer or the primer layer is uniform and thin as possible while satisfying a specific ratio, the sputtering angle is 15 degrees to 90 degrees, the Ca is 8 It is thought that it is good to be below degrees.
- semiconductor device part 32 first semiconductor device
- packaging substrate 22 core layer
- top connection layer 271 top connection electrode
- connection part 51 element connection part
- insulating layer 23b etching layer of the insulating layer
- electroconductive layer 23d etching layer of electroconductive layer
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- Ceramic Engineering (AREA)
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- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
샘플1 | 1-1 | 2-1 | 두께비율* | 1-2 | 2-2 | 두께비율 |
두께* | 175.85 | 126.5 | 1.39 | 105.63 | 96 | 1.10 |
샘플2 | 1-1 | 2-1 | 두께비율 | 1-2 | 2-2 | 두께비율 |
두께 | 51.5 | 88.14 | 0.58 | 67 | 37.5 | 1.79 |
샘플3 | 1-1 | 2-1 | 두께비율 | 1-2 | 2-2 | 두께비율 |
두께 | 59.32 | 42.54 | 1.39 | 141.04 | 36.54 | 3.86 |
샘플4 | 1-1 | 2-1 | 두께비율 | 1-2 | 2-2 | 두께비율 |
두께 | 61.3 | 158.58 | 0.39 | 36.46 | 72.54 | 0.50 |
샘플1 | 1-3 | 2-3 | 두께비율 | 1-4 | 2-4 | 두께비율 |
두께 | 49.5 | 54.5 | 0.91 | 74 | 58 | 1.28 |
샘플2 | 1-3 | 2-3 | 두께비율 | 1-4 | 2-4 | 두께비율 |
두께 | 65.5 | 98.5 | 0.66 | 61 | 76 | 0.80 |
샘플3 | 1-3 | 2-3 | 두께비율 | 1-4 | 2-4 | 두께비율 |
두께 | 193.04 | 57.04 | 3.38 | 102.64 | 77.5 | 1.32 |
샘플4 | 1-3 | 2-3 | 두께비율 | 1-4 | 2-4 | 두께비율 |
두께 | 70.04 | 40 | 1.751 | 50.04 | 71.18 | 0.70 |
샘플1 | 1-5 | 2-5 | 두께비율 | 평균 | 표준편차 | - |
두께 | 274.2 | 87 | 3.15 | 1.566 | 0.74 | - |
샘플2 | 1-5 | 2-5 | 두께비율 | 평균 | 표준편차 | - |
두께 | 123.93 | 68 | 1.82 | 1.13 | 0.51 | - |
샘플3 | 1-5 | 2-5 | 두께비율 | 평균 | 표준편차 | - |
두께 | 226.02 | 37 | 6.11 | 3.212 | 1.62 | - |
샘플4 | 1-5 | 2-5 | 두께비율 | 평균 | 표준편차 | - |
두께 | 98.66 | 51.12 | 1.93 | 1.054 | 0.60 | - |
실시예 1 | 실시예 2 | 실시예 3 | 실시예 4 | 비교예 1 | 비교예 2 | 비교예 3 | |
스퍼터링각도(도) | 45 | 55 | 65 | 90 | 45 | 65 | 90 |
Ca*(도) | 8 이하 | 8 이하 | 8 이하 | 8 이하 | 8 초과 | 8 초과 | 8 초과 |
1-n:2-n* | 1:0.4~4.5 | 1:0.4~4.5 | 1:0.4~4.5 | 1:0.4~4.5 | 1:0.4~4.5 | 1:0.2 | 1:0.5 |
두께편차율*(%) | 50 | 67 | 83 | 90 | 97 | 102 | 107 |
최소내경부위치*(%) | 40~60 | 40 미만 | 40~60 | 40 미만 | 40~60 | 40 미만 | 40 미만 |
Claims (10)
- i) 서로 마주보는 제1면과 제2면을 갖는 유리기판;ii) 상기 유리기판을 두께 방향으로 관통하는 다수의 코어비아; 및iii) 상기 코어비아의 표면 상에 위치하며 전기전도성층 형성의 시드가 되는 코어시드층이 위치하는 코어층;을 포함하는 것으로,상기 코어비아의 내경면 중에서 서로 마주보는 두 위치에서 측정한 상기 코어시드층의 두께인 제1두께와 제2두께는 그 비율(두께비율)이 1:0.4 내지 4.5인, 반도체 패키징용 기판.
- 제1항에 있어서,상기 코어시드층의 하기 식 1로 표시되는 두께편차율이 90 %이하인, 반도체 패키징용 기판.[식 1]두께편차율 = ((코어시드층의 최대두께-코어시드층의 최소두께)/코어시드층의 평균두께)×100 %
- 제1항에 있어서,상기 코어시드층의 평균 두께는 30 내지 200 nm인, 반도체 패키징용 기판.
- 제1항에 있어서,상기 코어층 상에 위치하는 상부층을 포함하고,상기 코어층은 상기 유리기판 또는 코어비아의 표면 상에 위치하는 코어분배층을 포함하고,상기 코어분배층은 적어도 그 일부가 상기 코어비아를 통하여 상기 제1면 상의 전기전도성층과 상기 제2면 상의 전기전도성층을 전기적으로 연결하는 전기전도성층을 포함하고,상기 코어비아는 상기 제1면과 접하는 개구부와 상기 제2면과 접하는 개구부 중에서 큰 직경을 갖는 것의 개구부에서 상기 코어비아 중에서 최소내경을 갖는 부분까지를 상기 코어비아 단면에서 관찰한 내경면의 각도가 상기 제1면에 수직한 두께 방향을 기준으로 8 도 이하인, 패키징 기판.
- 제1항에 있어서,상기 코어비아는 상기 제1면과 접하는 제1개구부; 상기 제2면과 접하는 제2개구부; 그리고 상기 제1개구부와 상기 제2개구부를 연결하는 전체 코어비아에서 그 내경이 가장 좁은 구역인 최소내경부를 포함하는, 패키징 기판.
- 제5항에 있어서,상기 최소내경부의 직경은 상기 제1개구부 및 상기 제2개구부 중 큰 직경을 갖는 것을 기준으로 50 % 내지 99 %의 크기를 갖는, 패키징 기판.
- 제5항에 있어서,상기 최소내경부가 위치하는 지점은 상기 코어비아 길이 전체를 100 %로 보았을 때, 상기 제1개구부를 기준으로 40 % 내지 60 % 지점에 위치하는, 패키징 기판.
- 제5항에 있어서,상기 최소내경부가 위치하는 지점은 상기 코어비아 길이 전체를 100 %로 보았을 때, 상기 제1개구부를 기준으로 40 % 미만 60 % 초과 지점에 위치하는, 패키징 기판.
- 서로 마주보는 제1면과 제2면을 갖는 유리기판과 상기 유리기판을 두께 방향으로 관통하는 다수의 코어비아를 갖는 처리전기판을 마련하는 준비단계; 그리고상기 제1면에 수직한 기준선에 대해 소정 각도로 스퍼터링하여 상기 코어비아의 내경면에 코어시드층을 형성하는 스퍼터링단계;를 포함하고,상기 코어비아는 상기 제1면과 접하는 개구부와 상기 제2면과 접하는 개구부 중에서 큰 직경을 갖는 것의 개구부에서 상기 코어비아 중에서 최소내경을 갖는 부분까지를 상기 코어비아 단면에서 관찰한 내경면의 각도가 상기 제1면에 수직한 두께 방향을 기준으로 8 도 이하이고,상기 코어비아의 내경면 중에서 서로 마주보는 두 위치에서 측정한 상기 코어시드층의 두께인 제1두께와 제2두께는 그 비율(두께비율)이 1:0.4 내지 4.5인, 반도체 패키징용 기판의 제조방법.
- 반도체 소자를 포함하는 소자부; 및 상기 소자부와 전기적으로 연결되는 패키징 기판;을 포함하고, 상기 패키징 기판은 제1항에 따른 패키징 기판인, 반도체 장치.
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JP2021534595A JP2022523898A (ja) | 2019-03-12 | 2020-03-12 | パッケージング基板及びその製造方法 |
KR1020237016450A KR102622608B1 (ko) | 2019-03-12 | 2020-03-12 | 패키징 기판 및 이의 제조방법 |
KR1020217015660A KR102537004B1 (ko) | 2019-03-12 | 2020-03-12 | 패키징 기판 및 이의 제조방법 |
EP20768931.6A EP3913662A4 (en) | 2019-03-12 | 2020-03-12 | PACKAGING SUBSTRATE AND METHOD OF MANUFACTURE THEREOF |
CN202080007185.2A CN113261093B (zh) | 2019-03-12 | 2020-03-12 | 半导体封装用基板及其制备方法以及半导体装置 |
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CN114340225B (zh) * | 2021-12-23 | 2024-02-23 | 江苏普诺威电子股份有限公司 | 适用于镭射盲孔的多层封装基板对准方法 |
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CN113261093A (zh) | 2021-08-13 |
EP3913662A4 (en) | 2022-11-02 |
CN113261093B (zh) | 2024-04-16 |
KR20230074611A (ko) | 2023-05-30 |
EP3913662A1 (en) | 2021-11-24 |
JP2023103353A (ja) | 2023-07-26 |
KR102622608B1 (ko) | 2024-01-08 |
US20220059421A1 (en) | 2022-02-24 |
KR20210071075A (ko) | 2021-06-15 |
KR102537004B1 (ko) | 2023-05-26 |
JP2022523898A (ja) | 2022-04-27 |
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