WO2020181924A1 - 栅极驱动单元、方法、栅极驱动模组、电路及显示装置 - Google Patents

栅极驱动单元、方法、栅极驱动模组、电路及显示装置 Download PDF

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Publication number
WO2020181924A1
WO2020181924A1 PCT/CN2020/073141 CN2020073141W WO2020181924A1 WO 2020181924 A1 WO2020181924 A1 WO 2020181924A1 CN 2020073141 W CN2020073141 W CN 2020073141W WO 2020181924 A1 WO2020181924 A1 WO 2020181924A1
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Prior art keywords
control
node
pull
terminal
circuit
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PCT/CN2020/073141
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English (en)
French (fr)
Inventor
冯雪欢
李永谦
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京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
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Priority to US16/768,536 priority Critical patent/US11158226B2/en
Publication of WO2020181924A1 publication Critical patent/WO2020181924A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present disclosure relates to the field of display driving technology, and in particular to a gate driving unit, a method, a gate driving module, a circuit, and a display device.
  • the gate drive unit applied to the pixel circuit with external compensation function in the related art is usually composed of the following three sub-circuits: a gate drive sub-circuit that generates a gate drive signal, and a detection signal generation sub-circuit that generates a detection signal ( In the blank period, the potential of the detection signal is an effective voltage, and in the display period, the detection signal is an invalid voltage), and a composite pulse signal that outputs the gate drive signal and the detection signal (the composite pulse signal is the external compensation Control signal), the structure of such a circuit is very complicated and cannot meet the requirements of high resolution and narrow frame.
  • the gate driving circuit in the related art is sequential scanning compensation, but the long-term sequential compensation will bring scan line during the blank period (because when external compensation is performed on the first-level gate driving unit, the blank period
  • the potential of the external compensation control signal is an effective voltage
  • the pixel circuit of the row displays black or white, and if compensation is performed sequentially, it will cause a scan line.
  • the potential of the pull-up node cannot be sufficiently pulled up, which may cause an output abnormality.
  • the embodiment of the present disclosure provides a gate drive unit, including an external compensation control signal output terminal, a gate drive signal output terminal, an external compensation control signal output circuit, a gate drive signal output circuit, a pull-up control circuit, and a pull-down node control Circuit, wherein the pull-up control circuit is used to control the potential of the first node under the control of the enable signal input from the enable terminal and the drive signal of the current level, and the potential of the first node, the first clock signal Under the control of the first clock signal input from the terminal, the second clock signal input from the second clock signal terminal and the potential of the pull-down node, the potential of the pull-up control node is controlled, and the potential of the pull-up control node is controlled Down, controlling the potential of the pull-up node so that the potential of the pull-up node can be controlled to be an effective voltage during a predetermined period of time in the blank period;
  • the pull-down node control circuit is used to control the potential of the pull-down node
  • the external compensation control signal output circuit is used to control the communication between the external compensation control signal output terminal and the external compensation clock signal terminal under the control of the potential of the pull-up node, and control the potential of the pull-down node Next, controlling the communication between the external compensation control signal output terminal and the first voltage terminal;
  • the gate drive signal output circuit is used to control the gate drive signal output terminal to output a gate drive signal under the control of the potential of the pull-up node and the potential of the pull-down node.
  • the waveform of the driving signal of the current level is the same as the waveform of the gate driving signal.
  • the pull-up control circuit includes a first node control sub-circuit, a second node control sub-circuit, a third node control sub-circuit, a pull-up control node control sub-circuit, and a pull-up control sub-circuit;
  • the first node control sub-circuit is used to control the first node to access the drive signal of the current level under the control of the enable signal, and control to maintain the potential of the first node;
  • the second node control sub-circuit is used to control the potential of the second node under the control of the second clock signal
  • the third node control sub-circuit is used to control the communication between the third node and the second voltage terminal under the control of the potential of the second node;
  • the pull-up control node control sub-circuit is used to control the connection between the pull-up control node and the first clock signal terminal under the control of the potential of the first node, and the potential of the pull-down node Under the control of, control the communication between the pull-up control node and the third node;
  • the pull-up control sub-circuit is used to control the connection between the pull-up node and the third voltage terminal under the control of the potential of the pull-up control node.
  • the second node control sub-circuit is also used to control the communication between the second node and the second voltage terminal under the control of the first clock signal.
  • the first node control sub-circuit includes a first control transistor and an energy storage capacitor
  • the control electrode of the first control transistor is connected to the enable terminal, the first electrode of the first control transistor is connected to the drive signal of the current stage, and the second electrode of the first control transistor is connected to the first electrode.
  • the first end of the energy storage capacitor is connected to the first node, and the second end of the energy storage capacitor is connected to the pull-up control node.
  • the second node control sub-circuit includes a second control transistor
  • control electrode of the second control transistor and the first electrode of the second control transistor are both connected to the second clock signal terminal, and the second electrode of the second control transistor is connected to the second node.
  • the second node control sub-circuit further includes a second node reset transistor
  • the control electrode of the second node reset transistor is connected to the first clock signal terminal, the first electrode of the second node reset transistor is connected to the second node, and the second node of the second node reset transistor Connected to the second voltage terminal.
  • the third node control sub-circuit includes a third control transistor
  • the control electrode of the third control transistor is connected to the second node, the first electrode of the third control transistor is connected to the third node, and the second electrode of the third control transistor is connected to the second node. Voltage terminal connection;
  • the pull-up control node control sub-circuit includes a fourth control transistor and a fifth control transistor;
  • the control electrode of the fourth control transistor is connected to the first node, the first electrode of the fourth control transistor is connected to the first clock signal terminal, and the second electrode of the fourth control transistor is connected to the Pull up the control node connection;
  • the control electrode of the fifth control transistor is connected to the pull-down node, the first electrode of the fifth control transistor is connected to the pull-up control node, and the second electrode of the fifth control transistor is connected to the third Node connection
  • the pull-up control sub-circuit includes a pull-up control transistor
  • the control electrode of the pull-up control transistor is connected to the pull-up control node, the first electrode of the pull-up control transistor is connected to the pull-up node, and the second electrode of the pull-up control transistor is connected to the first electrode.
  • Three voltage terminals are connected.
  • the gate driving unit described in the present disclosure further includes a pull-up node control circuit
  • the pull-up node control circuit is connected to the input terminal, the reset terminal, the pull-up node, the pull-down node, the blank area reset terminal, the third voltage terminal, and the fourth voltage terminal, respectively, for inputting at the input terminal
  • the pull-up node is controlled to communicate with the third voltage terminal under the control of the input signal, and the pull-up node and the fourth voltage terminal are controlled under the control of the reset signal input from the reset terminal
  • the connection between the pull-up node and the fourth voltage terminal is controlled under the control of the blank area reset signal input from the blank area reset terminal, and the control is controlled by the potential of the pull-down node
  • the pull-up node is connected to the fourth voltage terminal, and is used to maintain the potential of the pull-up node.
  • the pull-up node control circuit includes a first pull-up node control transistor, a second pull-up node control transistor, a third pull-up node control transistor, a fourth pull-up node control transistor, a first storage capacitor, and a second pull-up node control transistor.
  • Storage capacitor where
  • the control electrode of the first pull-up node control transistor is connected to the input terminal, the first electrode of the first pull-up node control transistor is connected to the third voltage terminal, and the first pull-up node control transistor Connected to the pull-up node;
  • the control electrode of the second pull-up node control transistor is connected to the reset terminal, the first electrode of the second pull-up node control transistor is connected to the pull-up node, and the second pull-up node controls the transistor
  • the second pole is connected to the fourth voltage terminal;
  • the control electrode of the third pull-up node control transistor is connected to the reset terminal of the blank area, the first electrode of the third pull-up node control transistor is connected to the pull-up node, and the third pull-up node controls The second pole of the transistor is connected to the fourth voltage terminal;
  • the control electrode of the fourth pull-up node control transistor is connected to the pull-down node, the first electrode of the fourth pull-up node control transistor is connected to the pull-up node, and the fourth pull-up node controls the transistor
  • the second pole is connected to the fourth voltage terminal
  • a first end of the first storage capacitor is connected to the pull-up node, and a second end of the first storage capacitor is connected to the external compensation control signal output end;
  • the first end of the second storage capacitor is connected to the pull-up node, and the second end of the second storage capacitor is connected to the gate drive signal output end.
  • the pull-down node control circuit is connected to the first control voltage terminal, the pull-up node, the pull-down node, the first node, the first clock signal terminal, the input terminal, and the fifth voltage, respectively.
  • the pull-down node control circuit includes a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, a fourth pull-down control transistor, and a fifth pull-down control transistor, wherein,
  • the control electrode of the first pull-down control transistor and the first electrode of the first pull-down control transistor are both connected to the first control voltage terminal, and the second electrode of the first pull-down control transistor is connected to the pull-down node connection;
  • the control electrode of the second pull-down control transistor is connected to the pull-up node, the first electrode of the second pull-down control transistor is connected to the pull-down node, and the second electrode of the second pull-down control transistor is connected to the pull-down node.
  • the fifth voltage terminal is connected;
  • the control electrode of the third pull-down control transistor is connected to the first clock signal terminal, and the first electrode of the third pull-down control transistor is connected to the pull-down node;
  • the control electrode of the fourth pull-down control transistor is connected to the first node, the first electrode of the fourth pull-down control transistor is connected to the second electrode of the third pull-down control transistor, and the fourth pull-down control transistor The second pole of is connected to the fifth voltage terminal;
  • the control electrode of the fifth pull-down control transistor is connected to the input terminal, the first electrode of the fifth pull-down control transistor is connected to the pull-down node, and the second electrode of the fifth pull-down control transistor is connected to the first electrode.
  • the external compensation control signal output circuit includes a first compensation output transistor and a second compensation output transistor, wherein,
  • the control electrode of the first compensation output transistor is connected to the pull-up node, the first electrode of the first compensation output transistor is connected to the external compensation clock signal terminal, and the second electrode of the first compensation output transistor Connected to the external compensation control signal output terminal;
  • the control pole of the second compensation output transistor is connected to the pull-down node, the first pole of the second compensation output transistor is connected to the external compensation control signal output terminal, and the second pole of the second compensation output transistor Communicate with the first voltage terminal.
  • the gate driving unit described in the present disclosure further includes a carry signal output terminal and a carry signal output circuit
  • the carry signal output circuit is configured to control the carry signal output terminal to output a carry signal under the control of the potential of the pull-up node and the potential of the pull-down node;
  • the driving signal of the current level is a carry signal provided by the carry signal output terminal.
  • the present disclosure also provides a gate driving method, which is applied to the above-mentioned gate driving unit, a blank period is set between two display periods, and the gate driving method includes:
  • the pull-up control circuit controls the potential of the first node to be an effective voltage under the control of the enable signal input from the enable terminal and the drive signal of the current level, and maintains the potential of the first node to be the effective voltage;
  • the pull-up control circuit controls the pull-down node under the control of the potential of the first node, the first clock signal input from the first clock signal terminal, the second clock signal input from the second clock signal terminal, and the potential of the pull-down node. Pull the potential of the control node as an invalid voltage;
  • the pull-up control circuit For a predetermined period of time in the blank period set after the display period, the pull-up control circuit maintains the potential of the first node as an effective voltage, and the pull-up control circuit maintains the potential of the first node and Under the control of the first clock signal, the potential of the pull-up control node is controlled, and under the control of the potential of the pull-up control node, the potential of the pull-up node is controlled to be an effective voltage; the external compensation control signal output circuit is at all Under the control of the potential of the pull-up node, the communication between the external compensation control signal output terminal and the external compensation clock signal terminal is controlled.
  • the pull-up control circuit includes a first node control sub-circuit, a second node control sub-circuit, a third node control sub-circuit, a pull-up control node control sub-circuit and a pull-up control sub-circuit; in the display period, the first An invalid voltage is input to a clock signal terminal, and an effective voltage is input to a second clock signal terminal; the predetermined time period includes a clock input stage and an external compensation output stage set in sequence; the gate driving method includes:
  • the enable terminal is input with an effective voltage
  • the drive signal of this stage is the effective voltage
  • the first node control sub-circuit controls the first node to access the drive signal of the current stage
  • the pull-up control node control sub-circuit controls The pull-up control node is connected to the first clock signal terminal
  • the pull-up control sub-circuit controls to disconnect the connection between the pull-up node and the third voltage terminal
  • the enable terminal is input with an invalid voltage
  • the potential of the pull-down node is the effective voltage
  • the first node control sub-circuit maintains the potential of the first node
  • the second node control sub-circuit The circuit controls the potential of the second node to be an effective voltage
  • the third node control sub-circuit controls the communication between the third node and the second voltage terminal
  • the pull-up control node control sub-circuit controls the pull-up control node and the first clock
  • the signal terminals are connected to each other and control the connection between the pull-up control node and the third node
  • the pull-up control sub-circuit controls the disconnection between the pull-up node and the third voltage terminal
  • the first node control sub-circuit maintains the potential of the first node
  • the first clock signal terminal is input with an effective voltage
  • the second clock signal terminal is input with an invalid voltage
  • the pull-up control node control sub-circuit controls the pull-up control node and the first clock signal terminal.
  • the pull-up control sub-circuit controls the pull-up node to communicate with the third voltage terminal to control the potential of the pull-up node as an effective voltage
  • the first clock signal terminal is input with an effective voltage
  • the second clock signal terminal is input with an invalid voltage
  • the first node control sub-circuit maintains the potential of the first node as the effective voltage
  • the pull-up control node controls The sub-circuit controls the connection between the pull-up control node and the first clock signal terminal, and the pull-up control sub-circuit disconnects the connection between the pull-up node and the third voltage terminal, so that the power of the pull-up node is maintained valid Voltage:
  • the external compensation clock signal terminal inputs an effective voltage
  • the external compensation control signal output circuit controls the communication between the external compensation control signal output terminal and the external compensation clock signal terminal.
  • the blank time period further includes a blank area reset phase set after the predetermined time period;
  • the gate driving method further includes:
  • the enable terminal inputs an effective voltage
  • the driving signal of the current level is an invalid voltage
  • the first node control sub-circuit controls the first node to access the current level driving signal to reset the potential of the first node .
  • the gate driving unit further includes a pull-up node control circuit; the gate driving method further includes:
  • the blank area reset terminal inputs an effective voltage to reset the potential of the pull-up node.
  • the present disclosure also provides a gate drive module, which includes the above-mentioned gate drive unit; the gate drive unit is an N-th stage gate drive unit; N is a positive integer; the gate drive module further includes N+1th stage gate driving unit;
  • the pull-up node in the N+1-th gate driving unit is the N+1 pull-up node
  • the pull-down node in the N+1-th gate driving unit is the N+1 pull-down node
  • the pull-up control node in the pole drive unit is the pull-up control node in the Nth stage gate drive unit
  • the N+1th stage gate driving unit includes an N+1th stage pull-up control circuit, an N+1th stage external compensation control signal output terminal, an N+1th stage gate drive signal output terminal, an N+1th stage External compensation control signal output circuit, N+1th gate drive signal output circuit and N+1th pull-down node control circuit;
  • the N+1th stage pull-up control circuit is connected to the Nth pull-up control node, and is used to control the N+1th pull-up node and the third voltage under the control of the potential of the Nth pull-up control node Connection between terminals;
  • the N+1th pull-down node control circuit is used to control the potential of the N+1th pull-down node
  • the N+1th external compensation control signal output circuit is used to control the N+1th stage external compensation control signal output terminal and the second external compensation clock signal under the control of the potential of the N+1th pull-up node Communication between the terminals, and under the control of the potential of the N+1th pull-down node, control the communication between the external compensation control signal output terminal and the first voltage terminal;
  • the N+1th gate drive signal output circuit is used to control the N+1th stage gate drive under the control of the potential of the N+1th pull-up node and the potential of the N+1th pull-down node
  • the signal output terminal outputs a gate drive signal.
  • the N+1th stage gate driving unit further includes an N+1th pull-up node control circuit
  • the N+1th pull-up node control circuit is connected to the input terminal, the reset terminal, the N+1th pull-up node, the N+1th pull-down node, the blank area reset terminal, the third voltage terminal, and the fourth The voltage terminal is connected to control the connection between the N+1th pull-up node and the third voltage terminal under the control of the input signal input at the input terminal, and the reset signal input at the reset terminal Under control, the N+1th pull-up node is controlled to communicate with the fourth voltage terminal, and the N+1th pull-up is controlled under the control of the blank area reset signal input from the blank area reset terminal.
  • the node is connected to the fourth voltage terminal, and under the control of the potential of the N+1th pull-down node, the connection between the N+1th pull-up node and the fourth voltage terminal is controlled, and is used for Maintain the potential of the N+1th pull-up node.
  • the pull-up control circuit in the Nth stage gate drive unit is the Nth pull-up control circuit;
  • the N pull-up control circuit includes a first node control sub-circuit, a second node control sub-circuit, and a third Node control sub-circuit, pull-up control node control sub-circuit and pull-up control sub-circuit;
  • the N+1th pull-down node control circuit is respectively connected to the second control voltage terminal, the N+1th pull-up node, the N+1th pull-down node, and the first in the Nth stage gate driving unit.
  • the node, the first clock signal terminal, the reset terminal, and the fifth voltage terminal are connected, and are used to control the N+1 pull-up node under the control of the second control voltage input by the second control voltage and the potential of the N+1 pull-up node.
  • the potential of the N+1 pull-down node is controlled by the potential of the first node and the first clock signal input from the first clock signal terminal to control the N+1 pull-down node and the fifth voltage
  • the connection between the terminals is controlled, and the connection between the pull-down node and the fifth voltage terminal is controlled under the control of the input signal input from the input terminal.
  • the external compensation control signal output circuit in the Nth stage gate drive unit is the Nth external compensation control signal output circuit
  • the gate drive signal output circuit in the Nth stage gate drive unit is the Nth Gate drive signal output circuit
  • the external compensation control signal output terminal in the Nth stage gate drive unit is the Nth stage external compensation control signal output terminal
  • the gate drive signal in the Nth stage gate drive unit The output terminal is the Nth stage gate drive signal output terminal
  • the pull-up node in the Nth stage gate drive unit is the Nth pull-up node
  • the pull-down node in the Nth stage gate drive unit is the Nth Drop down node
  • the Nth external compensation control signal output circuit is also connected to the N+1th pull-down node, and is used to reset the Nth stage external compensation control signal output terminal under the control of the potential of the N+1th pull-down node;
  • the Nth gate drive signal output circuit is also connected to the N+1th pull-down node, and is configured to reset the Nth stage gate drive signal output terminal under the control of the potential of the N+1th pull-down node;
  • the N+1th external compensation control signal output circuit is also connected to the Nth pull-down node, and is configured to reset the N+1th stage external compensation control signal output terminal under the control of the potential of the Nth pull-down node;
  • the N+1th gate drive signal output circuit is also connected to the Nth pull-down node, and is used to reset the N+1th stage gate drive signal output terminal under the control of the potential of the Nth pull-down node.
  • the present disclosure also provides a gate drive circuit, which includes multiple stages of the above-mentioned gate drive modules.
  • the nth stage gate drive module includes an Nth stage gate drive unit and an N+1th stage gate drive unit;
  • the input terminal is connected to the N-2 stage gate drive signal output terminal, and the reset terminal is connected to the N+4 stage gate drive signal output terminal; n is a positive integer.
  • the nth stage gate drive module includes an Nth stage gate drive unit and an N+1th stage gate drive unit; the Nth stage gate drive unit includes a carry signal output terminal and a carry signal output circuit;
  • the input terminal is connected to the N-2 stage carry signal output terminal, and the reset terminal is connected to the N+4 stage carry signal output terminal; n is a positive integer.
  • FIG. 1 is a structural diagram of a gate driving unit according to an embodiment of the present disclosure
  • Figure 2 is a circuit diagram of a pixel circuit with an external compensation function
  • FIG. 3 is a structural diagram of a gate driving unit according to another embodiment of the present disclosure.
  • FIG. 4 is a structural diagram of a gate driving unit according to another embodiment of the present disclosure.
  • FIG. 5 is a structural diagram of a gate driving unit according to another embodiment of the present disclosure.
  • FIG. 6 is a structural diagram of a gate driving unit according to another embodiment of the present disclosure.
  • FIG. 7 is a structural diagram of a gate driving unit according to still another embodiment of the present disclosure.
  • FIG. 8 is a structural diagram of a gate driving unit according to another embodiment of the present disclosure.
  • FIG. 9A is a circuit diagram of a specific embodiment of the gate driving unit according to the present disclosure.
  • 9B is a circuit diagram of another specific embodiment of the gate driving unit according to the present disclosure.
  • FIG. 10 is a working timing diagram of the specific embodiment of the gate driving unit shown in FIG. 9A of the present disclosure.
  • FIG. 11 is a structural diagram of a gate driving module according to an embodiment of the present disclosure.
  • FIG. 12 is a structural diagram of a gate driving module according to another embodiment of the present disclosure.
  • FIG. 13 is a circuit diagram of a specific embodiment of the gate driving module of the present disclosure.
  • FIG. 14 is a working timing diagram of the specific embodiment of the gate driving module of the present disclosure.
  • FIG. 15 is a structural diagram of a specific embodiment of the gate driving circuit according to the present disclosure.
  • the transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the poles is called the first pole and the other pole is called the second pole.
  • the control electrode when the transistor is a triode, can be a base, the first electrode can be a collector, and the second electrode can be an emitter; or, the control electrode can be a base.
  • the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
  • the control electrode when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source; or The control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain.
  • the gate drive unit includes an external compensation control signal output terminal OUT1 (N), a gate drive signal output terminal OUT2 (N), an external compensation control signal output circuit 11, and a gate
  • the pull-up control circuit 13 is respectively connected to the enable terminal OE, the first clock signal terminal, the second clock signal terminal, the pull-up node Q(N), the pull-down node QB(N), the first node H and the pull-up control node.
  • the PUCN connection is used to control the potential of the first node H under the control of the enable signal input from the enable terminal OE and the drive signal of the current level, and the potential of the first node H and the first clock signal terminal input Under the control of a clock signal CLKA, the second clock signal CLKB input from the second clock signal terminal, and the potential of the pull-down node QB(N), the potential of the pull-up control node PUCN is controlled, and the pull-up control node PUCN is Under the control of the potential of the pull-up node Q(N), the potential of the pull-up node Q(N) is controlled so that the potential of the pull-up node Q(N) can be controlled to be an effective voltage during a predetermined period of time in the blank period;
  • the pull-down node control circuit 14 is used to control the potential of the pull-down node QB(N);
  • the external compensation control signal output circuit 11 is used to control the communication between the external compensation control signal output terminal OUT1(N) and the external compensation clock signal terminal under the control of the potential of the pull-up node Q(N), Under the control of the potential of the pull-down node QB(N), the communication between the external compensation control signal output terminal OUT1(N) and the first voltage terminal is controlled; the external compensation clock signal terminal is used to input an external compensation clock Signal CLKE_N, the first voltage terminal is used to input a first voltage V1;
  • the gate drive signal output circuit 12 is used to control the gate drive signal output terminal OUT2(N) under the control of the potential of the pull-up node Q(N) and the potential of the pull-down node QB(N). ) Output the gate drive signal.
  • the first voltage terminal may be a low voltage terminal, but is not limited to this.
  • the effective voltage is the voltage that enables the transistor whose gate is connected to it to turn on.
  • the effective voltage can be a high voltage; when the transistor is a p-type transistor, the The effective voltage can be a low voltage, but is not limited to this.
  • the effective voltage is the voltage that can turn off the transistor whose gate is connected to it.
  • the effective voltage can be a low voltage; when the transistor is a p-type transistor, The effective voltage can be a high voltage, but is not limited to this.
  • a blank period is set between two display periods, and the gate driving method includes:
  • the pull-up control circuit 13 controls the potential of the first node H to be an effective voltage under the control of the enable signal input from the enable terminal OE and the drive signal SG(N) of the current level, and maintains the first node
  • the potential of H is an effective voltage
  • the pull-up control circuit 13 is at the potential of the first node H, the first clock signal CLKA input from the first clock signal terminal, the second clock signal CLKB input from the second clock signal terminal, and Controlling the potential of the pull-up control node PUCN to be an invalid voltage under the control of the potential of the pull-down node QB(N);
  • the pull-up control circuit 13 maintains the potential of the first node H as an effective voltage, and the pull-up control circuit 13 is at the first node H.
  • the potential of the pull-up control node PUCN is controlled, and under the control of the potential of the pull-up control node PUCN, the pull-up node Q( The potential of N) is the effective voltage;
  • the external compensation control signal output circuit 11 under the control of the potential of the pull-up node Q(N), controls the distance between the external compensation control signal output terminal OUT1(N) and the external compensation clock signal terminal Connected.
  • the gate driving unit described in the embodiment of the present disclosure can simultaneously output a gate driving signal and an external compensation control signal, so as to be able to provide a gate driving signal and an external compensation signal for a pixel circuit with an external compensation function at the same time, which simplifies the circuit structure
  • the gate driving unit described in the embodiment of the present disclosure can be used to perform random compensation, and the function of random compensation can eliminate the deviation of the scan line and the brightness of the panel.
  • the display period may include an input phase, an output phase, a reset phase, and an output cut-off hold phase set in sequence.
  • the potential of PU(N) is the effective voltage.
  • the gate Both the pole drive signal output terminal and the external compensation control signal output terminal output valid voltages.
  • the gate drive signal output terminal and the external compensation control signal output terminal both output invalid voltages.
  • the gate driving unit described in the embodiment of the present disclosure provides a corresponding gate driving signal for the gate line of the Nth row (N is a positive integer) on the display panel
  • the gate drive in the embodiment of the present disclosure The pole drive unit is the Nth stage gate drive unit included in the gate drive circuit, and this stage refers to the Nth stage.
  • the waveform of the current-level driving signal SG(N) is the same as the waveform of the gate driving signal.
  • the current level driving signal SG(N) may be provided by the gate driving signal output terminal OUT2(N);
  • the current stage drive signal SG(N) may be generated by the carry signal output terminal provide.
  • the pixel circuit with external compensation function may include a data writing transistor T1, a capacitor Cst, a driving transistor T2, a light-emitting element EL, and an external compensation control transistor T3.
  • the gate of T1 and the corresponding stage gate drive signal output The gate of T3 is connected to the output terminal of the external compensation control signal of the corresponding level.
  • the data line labeled Data is the data line
  • the one labeled ELVDD is high level
  • the one labeled ELVSS is low level.
  • the SL is the external compensation line
  • the GND is the ground terminal
  • the Cs is the parasitic capacitance on the external compensation line SL.
  • the pull-up control circuit may include a first node control sub-circuit, a second node control sub-circuit, a third node control sub-circuit, a pull-up control node control sub-circuit, and a pull-up control sub-circuit;
  • the first node control sub-circuit is used to control the first node to access the drive signal of the current level under the control of the enable signal, and control to maintain the potential of the first node;
  • the second node control sub-circuit is used to control the potential of the second node under the control of the second clock signal
  • the third node control sub-circuit is used to control the communication between the third node and the second voltage terminal under the control of the potential of the second node;
  • the pull-up control node control sub-circuit is used to control the connection between the pull-up control node and the first clock signal terminal under the control of the potential of the first node, and the potential of the pull-down node Under the control of, control the communication between the pull-up control node and the third node;
  • the pull-up control sub-circuit is used to control the connection between the pull-up node and the third voltage terminal under the control of the potential of the pull-up control node.
  • the second voltage terminal may be a first low voltage terminal
  • the third voltage terminal may be a high voltage terminal, but not limited to this.
  • the pull-up control circuit includes a first node control sub-circuit 131, a second node control sub-circuit 132, and a third Node control sub-circuit 133, pull-up control node control sub-circuit 134, and pull-up control sub-circuit 135, wherein,
  • the first node control sub-circuit 131 is respectively connected to the enable terminal OE and the first node H, and is used to control the first node H to access the drive signal SG( N), and control to maintain the potential of the first node H;
  • the second node control sub-circuit 132 is respectively connected to the second node J and the second clock signal terminal, and is used to control the potential of the second node J under the control of the second clock signal CLKB;
  • the third node control sub-circuit 133 is respectively connected to the second node J, the third node M, and the first low voltage terminal, and is used to control the third node M and the first low voltage terminal under the control of the potential of the second node J A low voltage terminal is connected; the first low voltage terminal is used to input a first low voltage VGL1;
  • the pull-up control node control sub-circuit 134 is connected to the pull-up control node PUCN, the first node H, the first clock signal terminal, the pull-down node QB(N), and the third node M, respectively, for Under the control of the potential of the first node H, the pull-up control node PUCN is controlled to communicate with the first clock signal terminal, and under the control of the potential of the pull-down node QB(N), the control Communication between the pull-up control node PUCN and the third node M;
  • the pull-up control sub-circuit 135 is respectively connected to the pull-up control node PUCN, the pull-up node Q(N) and the high voltage terminal, and is used to control the potential of the pull-up control node PUCN under the control of the
  • the pull-up node Q(N) is connected to the high voltage terminal; the high voltage terminal is used to input a high voltage VDD.
  • the second voltage terminal is the first low voltage terminal
  • the third voltage terminal is the high voltage terminal, but not limited to this.
  • the predetermined time period in the blank time period includes a clock input phase and an external compensation output phase that are sequentially set;
  • the gate driving method includes:
  • the enable terminal OE inputs an effective voltage
  • the current stage drive signal SG(N) is the effective voltage
  • the first node control sub-circuit 131 controls the first node H to access the current stage drive signal SG( N);
  • the pull-up control node control sub-circuit 134 controls the pull-up control node PUCN to connect to CLKA;
  • the pull-up control sub-circuit 135 controls to disconnect the pull-up node Q(N) to connect to the high voltage VDD;
  • the enable terminal OE inputs an invalid voltage
  • the potential of the pull-down node QB(N) is an effective voltage
  • the first node control sub-circuit 131 maintains the first node H
  • the second node control sub-circuit 132 controls the potential of the second node J to be an effective voltage
  • the third node control sub-circuit 133 controls the third node M to connect to the first low voltage VGL1
  • the pull-up control node control sub-circuit 134 controls the The pull-up control node PUCN accesses the first clock signal CLKA, and controls the connection between the pull-up control node PUCN and the third node M
  • the pull-up control sub-circuit 135 controls to disconnect the pull-up node Q(N) from the high Connection between voltage terminals;
  • the first node control sub-circuit 131 maintains the potential of the first node H;
  • the first clock signal CLKA is an effective voltage
  • the second clock signal CLKB is an invalid voltage
  • the pull-up control node control sub-circuit 134 controls the pull-up control node PUCN to access the first
  • the pull-up control sub-circuit 135 controls the pull-up node Q(N) to connect to the high voltage VDD, so as to control the potential of the pull-up node Q(N) as an effective voltage
  • the first clock signal CLKA is an effective voltage
  • the second clock signal CLKB is an ineffective voltage
  • the first node control sub-circuit 131 maintains the potential of the first node H as an effective voltage
  • the pull-up control The node control sub-circuit 134 controls the pull-up control node PUCN to access the first clock signal CLKA
  • the pull-up control sub-circuit 135 disconnects the pull-up node Q(N) and the high voltage terminal, so that The potential of the pull-up node Q(N) is maintained as an effective voltage
  • the external compensation clock signal CLKE_N input from the external compensation clock signal terminal is an effective voltage
  • the external compensation control signal output circuit 11 controls the external compensation control signal output terminal OUT1(N) and the The external compensation clock signal terminals are connected.
  • the second node control sub-circuit can also be used to control the communication between the second node and the second voltage terminal under the control of the first clock signal.
  • the second node control sub-circuit controls the communication between the second node and the second voltage terminal; when the first clock signal is an invalid voltage, the second node The control sub-circuit controls the disconnection between the second node and the second voltage terminal.
  • the first node control sub-circuit may include a first control transistor and an energy storage capacitor
  • the control electrode of the first control transistor is connected to the enable terminal OE, the first electrode of the first control transistor is connected to the driving signal of the current stage, and the second electrode of the first control transistor is connected to the The first node connection;
  • the first end of the energy storage capacitor is connected to the first node, and the second end of the energy storage capacitor is connected to the pull-up control node.
  • the second node control sub-circuit may include a second control transistor
  • control electrode of the second control transistor and the first electrode of the second control transistor are both connected to the second clock signal terminal, and the second electrode of the second control transistor is connected to the second node.
  • the second node control sub-circuit may further include a second node reset transistor
  • the control electrode of the second node reset transistor is connected to the first clock signal terminal, the first electrode of the second node reset transistor is connected to the second node, and the second node of the second node reset transistor Connected to the second voltage terminal.
  • the third node control sub-circuit may include a third control transistor
  • the control electrode of the third control transistor is connected to the second node, the first electrode of the third control transistor is connected to the third node, and the second electrode of the third control transistor is connected to the second node. Voltage terminal connection;
  • the pull-up control node control sub-circuit includes a fourth control transistor and a fifth control transistor;
  • the control electrode of the fourth control transistor is connected to the first node, the first electrode of the fourth control transistor is connected to the first clock signal terminal, and the second electrode of the fourth control transistor is connected to the Pull up the control node connection;
  • the control electrode of the fifth control transistor is connected to the pull-down node, the first electrode of the fifth control transistor is connected to the pull-up control node, and the second electrode of the fifth control transistor is connected to the third Node connection
  • the pull-up control sub-circuit includes a pull-up control transistor
  • the control electrode of the pull-up control transistor is connected to the pull-up control node, the first electrode of the pull-up control transistor is connected to the pull-up node, and the second electrode of the pull-up control transistor is connected to the first electrode.
  • Three voltage terminals are connected.
  • the first node control sub-circuit 131 includes a first control transistor M1 and an energy storage capacitor C1;
  • the gate of the first control transistor M1 is connected to the enable signal input from the enable terminal OE, the drain of the first control transistor M1 is connected to the drive signal SG(N) of the current stage, and the first control The source of the transistor M1 is connected to the first node H;
  • the first end of the energy storage capacitor C1 is connected to the first node H, and the second end C1 of the energy storage capacitor is connected to the pull-up control node PUCN.
  • the second node control sub-circuit 132 includes a second control transistor M42;
  • the gate of the second control transistor M42 and the drain of the second control transistor M42 are both connected to the second clock signal CLKB, and the source of the second control transistor M42 is connected to the second node J ;
  • the third node control sub-circuit 133 includes a third control transistor M43;
  • the gate of the third control transistor M43 is connected to the second node J, the drain of the third control transistor M43 is connected to the third node M, and the source of the third control transistor M43 is connected to the first node.
  • the pull-up control node control sub-circuit 134 includes a fourth control transistor M2 and a fifth control transistor M4;
  • the gate of the fourth control transistor M2 is connected to the first node H, the drain of the fourth control transistor M2 is connected to the first clock signal CLKA, and the source of the fourth control transistor M2 is connected to the The pull-up control node PUCN connection;
  • the gate of the fifth control transistor M4 is connected to the pull-down node QB(N), the drain of the fifth control transistor M4 is connected to the pull-up control node PUCN, and the source of the fifth control transistor M44 Pole is connected to the third node M;
  • the pull-up control sub-circuit 135 includes a pull-up control transistor M5;
  • the gate of the pull-up control transistor M5 is connected to the pull-up control node PUCN, the drain of the pull-up control transistor M5 is connected to the pull-up node Q(N), and the pull-up control transistor M5 The source is connected to the high voltage VDD.
  • the first node control sub-circuit 131 includes an energy storage capacitor C1 for the clock input phase in the blank period (at this time, CLKA is high voltage, and CLKB is Low voltage, the potential of QB(N) is a low voltage, M2 is turned on, M42 and M4 are turned off) to prevent the potential of the pull-up control node PUCN from decreasing due to leakage, making the potential of the first node H due to the secondary bootstrapping of C1 While rising, the pull-up control node PUCN obtains the lossless high potential of CLKA, and Q(N) is connected to VDD, which can increase the potential of Q(N), ensure that the potential of Q(N) is a high voltage, and enhance the reliability of the circuit .
  • the new circuit structure can increase the potential of the pull-up node and enhance the reliability of the circuit
  • all the transistors are n-type thin film transistors, but not limited to this; the second voltage terminal is the first low voltage terminal, the third voltage terminal is the high voltage terminal, and the effective voltage is High voltage, invalid voltage is low voltage, but not limited to this.
  • OE inputs a high voltage
  • SG(N) is a high voltage
  • M1 is turned on to control the potential of H as a high voltage
  • C1 maintains the potential of H as a high voltage
  • M2 is turned on
  • CLKA is a low voltage
  • CLKB is a high voltage
  • M2 is turned on, so that PUCN is connected to CLKA, the potential of PUCN is a low voltage
  • M5 is turned off, so as not to affect the display
  • M42 is turned on to make the potential of J a high voltage
  • M43 is turned on to make M Connect to VGL1; at this time, the potential of QB(N) is low voltage, then M4 is turned off;
  • OE inputs a low voltage
  • M1 is turned off
  • C1 maintains the potential of H as a high voltage
  • CLKA is a low voltage
  • M2 is turned on
  • CLKB is a high voltage
  • M42 is turned on to make J
  • the potential of M43 is high voltage
  • M43 is turned on
  • M is connected to VGL1
  • the potential of QB(N) is high voltage
  • M4 is turned on to control the connection between M and PUCN
  • the potential of PUCN is low voltage
  • M5 is turned off. Influence display
  • the storage capacitor includes a first storage capacitor set between Q(N) and OUT1(N) and a second storage capacitor set between Q(N) and OUT2(N)) is maintained high Voltage; at this time, CLKE_N is a high voltage, CLKF_N is a low voltage, OUT1(N) outputs a high voltage, and OUT2(N) outputs a low voltage.
  • the blank time period further includes a blank area reset stage set after the external compensation output stage;
  • the enable terminal OE inputs a high voltage, SG(N) is a low voltage, M1 is turned on, and the potential of H is a low voltage to reset the potential of the first node H.
  • the gate driving unit is connected to the gate line in the Nth row (N is a positive integer) on the display panel, and the Nth row is sense. (Detection) line, that is, during the blank period, it is necessary to provide an external compensation control signal to the pixel circuit of the Nth row on the display panel (the pixel circuit of the Nth row is a pixel circuit with an external compensation function).
  • the second node control sub-circuit may further include a second node reset transistor
  • the control electrode of the second node reset transistor is connected to the first clock signal terminal, the first electrode of the second node reset transistor is connected to the second node, and the second node of the second node reset transistor Connected to the second voltage terminal.
  • the second node reset transistor When an effective voltage is input to the first clock signal terminal, the second node reset transistor is turned on, so that the second node is connected to the second voltage, and when an invalid voltage is input to the first clock signal terminal, the second node reset transistor is turned off.
  • the gate driving unit described in the embodiment of the present disclosure may further include a pull-up node control circuit
  • the pull-up node control circuit is connected to the input terminal, the reset terminal, the pull-up node, the pull-down node, the blank area reset terminal, the third voltage terminal, and the fourth voltage terminal, respectively, for inputting at the input terminal
  • the pull-up node is controlled to communicate with the third voltage terminal under the control of the input signal, and the pull-up node and the fourth voltage terminal are controlled under the control of the reset signal input from the reset terminal
  • the connection between the pull-up node and the fourth voltage terminal is controlled under the control of the blank area reset signal input from the blank area reset terminal, and the control is controlled by the potential of the pull-down node
  • the pull-up node is connected to the fourth voltage terminal, and is used to maintain the potential of the pull-up node.
  • the third voltage terminal may be a high voltage terminal, and the fourth voltage terminal may be a first low voltage terminal, but not limited to this.
  • the gate driving unit described in the embodiment of the present disclosure further includes a pull-up node control circuit 15;
  • the pull-up node control circuit 15 is respectively connected with the input terminal Input, the reset terminal Reset, the pull-up node Q(N), the pull-down node QB(N), the blank area reset terminal TRST, the high voltage terminal and the first low
  • the voltage terminal is connected for controlling the connection between the pull-up node Q(N) and the high voltage terminal under the control of the input signal input by the input terminal Input, and the reset signal input at the reset terminal Reset
  • the pull-up node Q(N) is controlled to communicate with the first low voltage terminal, and the pull-up node is controlled under the control of the blank area reset signal input from the blank area reset terminal TRST Q(N) is connected to the first low-voltage terminal, and under the control of the potential of the pull-down node QB(N), the pull-up node Q(N) and the first low-voltage terminal are controlled It is connected with each other and used to maintain the potential of the pull-up node Q(N).
  • the blank area reset signal input by TRST is an effective voltage
  • the pull-up node control circuit 15 controls Q( under the control of the blank area reset signal input by TRST).
  • N) Connect the first low voltage VGL1 to reset the potential of the pull-up node Q(N);
  • the input signal input by Input is a high voltage
  • the pull-up node control circuit 15 controls Q(N) to connect to a high voltage VDD to increase the potential of Q(N);
  • the pull-up node control circuit 15 maintains the potential of Q(N) at a high potential
  • the reset signal input by Reset is a high voltage
  • the pull-up node control circuit 15 controls Q(N) to be connected to VGL1;
  • the potential of QB(N) is a high voltage, and the pull-up node control circuit 15 controls Q(N) to be connected to VGL1.
  • the pull-up node control circuit may include a first pull-up node control transistor, a second pull-up node control transistor, a third pull-up node control transistor, a fourth pull-up node control transistor, a first storage capacitor, and a second pull-up node control transistor.
  • the control electrode of the first pull-up node control transistor is connected to the input terminal, the first electrode of the first pull-up node control transistor is connected to the third voltage terminal, and the first pull-up node control transistor Connected to the pull-up node;
  • the control electrode of the second pull-up node control transistor is connected to the reset terminal, the first electrode of the second pull-up node control transistor is connected to the pull-up node, and the second pull-up node controls the transistor
  • the second pole is connected to the fourth voltage terminal;
  • the control electrode of the third pull-up node control transistor is connected to the reset terminal of the blank area, the first electrode of the third pull-up node control transistor is connected to the pull-up node, and the third pull-up node controls The second pole of the transistor is connected to the fourth voltage terminal;
  • the control electrode of the fourth pull-up node control transistor is connected to the pull-down node, the first electrode of the fourth pull-up node control transistor is connected to the pull-up node, and the fourth pull-up node controls the transistor
  • the second pole is connected to the fourth voltage terminal
  • a first end of the first storage capacitor is connected to the pull-up node, and a second end of the first storage capacitor is connected to the external compensation control signal output end;
  • the first end of the second storage capacitor is connected to the pull-up node, and the second end of the second storage capacitor is connected to the gate drive signal output end.
  • the pull-down node control circuit may be connected to the first control voltage terminal, the pull-up node, the pull-down node, the first node, the first clock signal terminal, the input terminal, and the The fifth voltage terminal is connected for controlling the potential of the pull-down node under the control of the first control voltage input from the first control voltage terminal and the potential of the pull-up node, and when the potential of the first node is Under the control of the first clock signal, control the connection between the pull-down node and the fifth voltage terminal, and control the pull-down node and the fifth voltage under the control of the input signal input from the input terminal Connect between ends.
  • the fifth voltage terminal may be the first low voltage terminal, but is not limited to this.
  • the pull-down node control circuit 14 is connected to the first control voltage terminal, the pull-up node Q(N), and the The pull-down node QB(N), the first node H, the first clock signal terminal, the input terminal Input and the first low voltage terminal are connected for the first control voltage VDDo input at the first control voltage terminal
  • the pull-down node QB(N) is controlled, and under the control of the potential of the first node H and the first clock signal CLKA,
  • the pull-down node QB(N) is controlled to be connected to the first low voltage VGL1, and under the control of the input signal input from the input terminal Input, the pull-down node QB(N) is controlled to be connected to the first low voltage VGL.
  • VDDo may be an effective voltage during the display period.
  • VDDo is the effective voltage.
  • the pull-down node control circuit 14 controls QB( The potential of N) is an invalid voltage; when Input inputs an effective voltage, QB(N) is connected to VGL;
  • the potential of H is an effective voltage
  • CLKA is an effective voltage
  • the pull-down node control circuit 14 controls QB(N) to be connected to VGL.
  • the pull-down node control circuit may include a first pull-down control transistor, a second pull-down control transistor, a third pull-down control transistor, a fourth pull-down control transistor, and a fifth pull-down control transistor, wherein,
  • the control electrode of the first pull-down control transistor and the first electrode of the first pull-down control transistor are both connected to the first control voltage terminal, and the second electrode of the first pull-down control transistor is connected to the pull-down node connection;
  • the control electrode of the second pull-down control transistor is connected to the pull-up node, the first electrode of the second pull-down control transistor is connected to the pull-down node, and the second electrode of the second pull-down control transistor is connected to the pull-down node.
  • the fifth voltage terminal is connected;
  • the control electrode of the third pull-down control transistor is connected to the first clock signal terminal, and the first electrode of the third pull-down control transistor is connected to the pull-down node;
  • the control electrode of the fourth pull-down control transistor is connected to the first node, the first electrode of the fourth pull-down control transistor is connected to the second electrode of the third pull-down control transistor, and the fourth pull-down control transistor The second pole of is connected to the fifth voltage terminal;
  • the control electrode of the fifth pull-down control transistor is connected to the input terminal, the first electrode of the fifth pull-down control transistor is connected to the pull-down node, and the second electrode of the fifth pull-down control transistor is connected to the first electrode.
  • the fifth voltage terminal may be the first low voltage terminal, but is not limited to this.
  • the pull-down node control circuit 14 includes a first pull-down control transistor M9, a second pull-down control transistor M10, and a third pull-down control transistor.
  • the gate of the first pull-down control transistor M9 and the drain of the first pull-down control transistor M9 are both connected to the first control voltage terminal, and the source of the first pull-down control transistor M9 is connected to the pull-down The node QB(N) is connected; the first control voltage terminal is used to input the first control voltage VDDo;
  • the gate of the second pull-down control transistor M10 is connected to the pull-up node Q(N), the drain of the second pull-down control transistor M10 is connected to the pull-down node QB(N), and the second pull-down control transistor M10
  • the source of the control transistor M10 is connected to the first low voltage VGL1;
  • the gate of the third pull-down control transistor M13 is connected to the first clock signal CLKA, and the drain of the third pull-down control transistor M13 is connected to the pull-down node QB(N);
  • the gate of the fourth pull-down control transistor M14 is connected to the first node H, the drain of the fourth pull-down control transistor M14 is connected to the source of the third pull-down control transistor M13, and the fourth pull-down control transistor M14 The source of the control transistor M14 is connected to the first low voltage VGL1;
  • the gate of the fifth pull-down control transistor M15 is connected to the input terminal Input, the drain of the fifth pull-down control transistor M15 is connected to the pull-down node QB(N), and the gate of the fifth pull-down control transistor M15 The source is connected to the first low voltage VGL1.
  • all the transistors are n-type thin film transistors, but not limited to this.
  • VDDo can be a high voltage and M9 is turned on;
  • the potential of Q(N) is a high voltage
  • M10 is turned on to pull down the potential of QB(N);
  • Input inputs high voltage and M15 is turned on to control QB(N) to connect to VGL1;
  • the potential of H is a high voltage
  • CLKA is a high voltage
  • both M13 and M14 are turned on to control QB(N) to connect to VGL1 and pull down the voltage of QB(N).
  • the external compensation control signal output circuit may include a first compensation output transistor and a second compensation output transistor, wherein,
  • the control electrode of the first compensation output transistor is connected to the pull-up node, the first electrode of the first compensation output transistor is connected to the external compensation clock signal terminal, and the second electrode of the first compensation output transistor Connected to the external compensation control signal output terminal;
  • the control pole of the second compensation output transistor is connected to the pull-down node, the first pole of the second compensation output transistor is connected to the external compensation control signal output terminal, and the second pole of the second compensation output transistor Communicate with the first voltage terminal.
  • the gate drive signal output circuit may include a first gate drive signal output transistor and a second gate drive signal output transistor, wherein,
  • the control electrode of the first gate drive signal output transistor is connected to the pull-up node, the first electrode of the first gate drive signal output transistor is connected to the gate drive output clock signal terminal, and the first gate The second electrode of the pole drive signal output transistor is connected to the gate drive signal output terminal;
  • the control electrode of the second gate drive signal output transistor is connected to the pull-down node, the first electrode of the second gate drive signal output transistor is connected to the gate drive signal output terminal, and the second gate The second pole of the pole drive signal output transistor is connected to the first voltage terminal.
  • the gate driving unit described in the embodiment of the present disclosure may further include a carry signal output terminal and a carry signal output circuit;
  • the carry signal output circuit is configured to control the carry signal output terminal to output a carry signal under the control of the potential of the pull-up node and the potential of the pull-down node;
  • the driving signal of the current level is a carry signal provided by the carry signal output terminal.
  • the embodiment of the present disclosure preferably adopts a carry signal output terminal to provide an input signal for the input terminal of an adjacent next-stage gate driving unit, and a reset signal for a reset terminal of an adjacent upper-stage gate driving unit to increase the gate drive signal The drive capability of the output terminal.
  • the drive signal of the current level may be the carry signal provided by the carry signal output terminal.
  • the gate driving unit described in the embodiment of the present disclosure further includes a carry signal output terminal CR(N) and a carry signal output circuit 16. ;
  • the carry signal output circuit 16 is connected to the pull-up node Q(N), the pull-down node QB(N), and the carry signal output terminal CR(N), respectively, and is used to connect the potential of the pull-up node Q(N) and the output terminal CR(N). Under the control of the potential of the pull-down node QB(N), controlling the carry signal output terminal CR(N) to output a carry signal;
  • the pull-up control circuit 13 is connected to CR(N), and CR(N) is used for the pull-up control circuit 13 to provide a driving signal of the current level.
  • the carry signal output circuit may include a first carry signal output transistor and a second carry signal output transistor;
  • the control electrode of the first carry signal output transistor is connected to the pull-up node, the first electrode of the first carry signal output transistor is connected to the carry output clock signal terminal, and the second electrode of the first carry signal output transistor Pole is connected to the carry signal output terminal;
  • the control electrode of the second carry signal output transistor is connected to the pull-down node, the first electrode of the second carry signal output transistor is connected to the carry signal output terminal, and the second carry signal output transistor is connected to the second The pole is connected to the second voltage terminal.
  • the carry output clock signal input from the carry output clock signal terminal and the gate drive output clock signal input from the gate drive output clock signal terminal may be the same, but not limited to this.
  • a specific embodiment of the gate driving unit described in the present disclosure includes an external compensation control signal output terminal OUT1 (N), a gate driving signal output terminal OUT2 (N), and a carry signal output terminal CR (N). ), the external compensation control signal output circuit 11, the gate drive signal output circuit 12, the pull-up control circuit, the pull-down node control circuit 14, the pull-up node control circuit and the carry signal output circuit 16, wherein,
  • the pull-up control circuit includes a first node control sub-circuit 131, a second node control sub-circuit 132, a third node control sub-circuit 133, a pull-up control node control sub-circuit 134, and a pull-up control sub-circuit 135, wherein,
  • the first node control sub-circuit 131 includes a first control transistor M1 and an energy storage capacitor C1;
  • the gate of the first control transistor M1 is connected to the enable signal input from the enable terminal OE, the drain of the first control transistor M1 is connected to the carry signal output terminal CR(N), and the first control transistor M1
  • the source of the transistor M1 is connected to the first node H;
  • the first end of the energy storage capacitor C1 is connected to the first node H, and the second end of the energy storage capacitor C1 is connected to the pull-up control node PUCN.
  • the second node control sub-circuit 132 includes a second control transistor M42;
  • the gate of the second control transistor M42 and the drain of the second control transistor M42 are both connected to the second clock signal CLKB, and the source of the second control transistor M42 is connected to the second node J ;
  • the third node control sub-circuit 133 includes a third control transistor M43;
  • the gate of the third control transistor M43 is connected to the second node J, the drain of the third control transistor M43 is connected to the third node M, and the source of the third control transistor M43 is connected to the first node.
  • the pull-up control node control sub-circuit 134 includes a fourth control transistor M2 and a fifth control transistor M4;
  • the gate of the fourth control transistor M2 is connected to the first node H, the drain of the fourth control transistor M2 is connected to the first clock signal CLKA, and the source of the fourth control transistor M2 is connected to the The pull-up control node PUCN connection;
  • the gate of the fifth control transistor M4 is connected to the pull-down node QB(N), the drain of the fifth control transistor M4 is connected to the pull-up control node PUCN, and the source of the fifth control transistor M44 Pole is connected to the third node M;
  • the pull-up control sub-circuit 135 includes a pull-up control transistor M5;
  • the gate of the pull-up control transistor M5 is connected to the pull-up control node PUCN, the drain of the pull-up control transistor M5 is connected to the pull-up node Q(N), and the pull-up control transistor M5 The source is connected to high voltage VDD;
  • the pull-up node control circuit includes a first pull-up node control transistor M6, a second pull-up node control transistor M8, a third pull-up node control transistor M7, a fourth pull-up node control transistor M12, a first storage capacitor C2 and The second storage capacitor C3, in which,
  • the gate of the first pull-up node control transistor M6 is connected to the input terminal Input, the drain of the first pull-up node control transistor M6 is connected to a high voltage VDD, and the first pull-up node control transistor M6 The source of is connected to the pull-up node Q(N);
  • the gate of the second pull-up node control transistor M8 is connected to the reset terminal Reset, the drain of the second pull-up node control transistor M8 is connected to the pull-up node Q(N), and the second The source of the pull-up node control transistor M8 is connected to the first low voltage VGL1;
  • the gate of the third pull-up node control transistor M7 is connected to the blank area reset terminal TRST, the drain of the third pull-up node control transistor M7 is connected to the pull-up node Q(N), and the The source of the third pull-up node control transistor M7 is connected to the first low voltage VGL1;
  • the gate of the fourth pull-up node control transistor M12 is connected to the pull-down node QB(N), and the drain of the fourth pull-up node control transistor M12 is connected to the pull-up node Q(N), so The source of the fourth pull-up node control transistor M12 is connected to the first low voltage VGL1;
  • the first end of the first storage capacitor C2 is connected to the pull-up node Q(N), and the second end of the first storage capacitor C1 is connected to the external compensation control signal output end OUT1(N);
  • the first end of the second storage capacitor C3 is connected to the pull-up node Q(N), and the second end of the second storage capacitor C3 is connected to the gate drive signal output end OUT2(N);
  • the pull-down node control circuit 14 includes a first pull-down control transistor M9, a second pull-down control transistor M10, a third pull-down control transistor M13, a fourth pull-down control transistor M14, and a fifth pull-down control transistor M15, wherein,
  • the gate of the first pull-down control transistor M9 and the drain of the first pull-down control transistor M9 are both connected to the first control voltage terminal, and the source of the first pull-down control transistor M9 is connected to the The pull-down node QB(N) is connected; the first control voltage terminal is used to input the first control voltage VDDo;
  • the gate of the second pull-down control transistor M10 is connected to the pull-up node Q(N), the drain of the second pull-down control transistor M10 is connected to the pull-down node QB(N), and the second pull-down control transistor M10
  • the source of the control transistor M10 is connected to the first low voltage VGL1;
  • the gate of the third pull-down control transistor M13 is connected to the first clock signal CLKA, and the drain of the third pull-down control transistor M13 is connected to the pull-down node QB(N);
  • the gate of the fourth pull-down control transistor M14 is connected to the first node H, the drain of the fourth pull-down control transistor M14 is connected to the source of the third pull-down control transistor M13, and the fourth pull-down control transistor M14
  • the second pole of the control transistor M14 is connected to the first low voltage VGL1;
  • the gate of the fifth pull-down control transistor M15 is connected to the input terminal Input, the drain of the fifth pull-down control transistor M15 is connected to the pull-down node QB(N), and the gate of the fifth pull-down control transistor M15 The source is connected to the first low voltage VGL1;
  • the external compensation control signal output circuit 11 includes a first compensation output transistor M19 and a second compensation output transistor M20, wherein,
  • the gate of the first compensation output transistor M19 is connected to the pull-up node Q(N), the drain of the first compensation output transistor M19 is connected to an external compensation clock signal CLKE_N, and the first compensation output transistor M19 Is connected to the external compensation control signal output terminal OUT1(N);
  • the gate of the second compensation output transistor M20 is connected to the pull-down node QB(N), the drain of the second compensation output transistor M20 is connected to the external compensation control signal output terminal OUT1(N), and the The source of the second compensation output transistor M20 is connected to the second low voltage VGL2;
  • the gate drive signal output circuit 12 includes a first gate drive signal output transistor M22 and a second gate drive signal output transistor M23, wherein,
  • the gate of the first gate drive signal output transistor M22 is connected to the pull-up node Q(N), and the drain of the first gate drive signal output transistor M22 is connected to the external compensation clock signal CLKE_N.
  • the source of the first gate drive signal output transistor M22 is connected to the gate drive signal output terminal OUT2(N);
  • the gate of the second gate drive signal output transistor M23 is connected to the pull-down node QB(N), and the drain of the second gate drive signal output transistor M23 is connected to the gate drive signal output terminal OUT2( N) connection, the source of the second gate drive signal output transistor M23 is connected to the second low voltage VGL2;
  • the carry signal output circuit 16 includes a first carry signal output transistor M16 and a second carry signal output transistor M17;
  • the gate of the first carry signal output transistor M16 is connected to the pull-up node Q(N), the drain of the first carry signal output transistor M16 is connected to the carry output clock signal CLKD_N, and the first carry signal The source of the output transistor M16 is connected to the carry signal output terminal CR(N);
  • the gate of the second carry signal output transistor M17 is connected to the pull-down node QB(N), the drain of the second carry signal output transistor M17 is connected to the carry signal output terminal CR(N), and the The source of the second carry signal output transistor M17 is connected to the first low voltage VGL1.
  • the input terminal Input may be connected to the N-2th stage carry signal output terminal CR(N-2), and the reset terminal Reset may be connected to the N+th stage carry signal output terminal CR(N-2).
  • the 4-level carry signal output terminal CR (N+4) is connected, but not limited to this.
  • all the transistors are n-type thin film transistors, but not limited to this.
  • the second node The control sub-circuit 132 also includes a second node control transistor M44;
  • the gate of M44 is connected to the first clock signal terminal (the gate of M44 is connected to the first clock signal CLKA), the drain of M44 is connected to the second node J, and the source of M44 is connected to the first low voltage VGL1.
  • M44 is an n-type thin film transistor, but it is not limited thereto.
  • M44 when CLKA is at a high level, M44 is turned on to control the second node J to connect to VGL1; when CLKA is at a low level, M44 is turned off.
  • the display period TD includes an input phase td1, an output phase td2, a reset phase td3, and an output cut-off holding phase td4.
  • the section TB includes a clock input stage tb1, an external compensation control signal output stage tb2, and a blank area reset stage tb3;
  • M16, M19 and M22 are all open, CR(N), OUT1(N) and OUT2(N) all output high level; and at this time OE input high level, M1 open, so that the potential of H is high voltage , M2 is turned on, PUCN is connected to CLKA, so that the potential of PUCN is low voltage; and M42 is turned on, so that the potential of the gate of M43 is high, and M43 is turned on; at this time, the potential of QB(N) is low voltage, M4 is off;
  • OE inputs high voltage
  • TRST inputs high voltage
  • M1 opens
  • CR(N) inputs low voltage to pull the potential of H low
  • M7 opens to turn Q(N) Pull down the potential of M16, M19 and M22 to turn off.
  • the same large-size drive transistor (M16) is used to form the rising and falling edges of the carry signal output by CR, and the same large-size drive transistor (M22) is used to form OUT2(N).
  • the rising and falling edges of the output gate drive signal greatly reduce the area of the layout.
  • all capacitors can be parasitic capacitors of TFTs (thin film transistors) or external capacitors.
  • the gate driving method according to the embodiment of the present disclosure is applied to the above-mentioned gate driving unit, and a blank period is set between two display periods, and the gate driving method includes:
  • the pull-up control circuit controls the potential of the first node to be an effective voltage under the control of the enable signal input from the enable terminal and the drive signal of the current level, and maintains the potential of the first node to be the effective voltage;
  • the pull-up control circuit controls the pull-down node under the control of the potential of the first node, the first clock signal input from the first clock signal terminal, the second clock signal input from the second clock signal terminal, and the potential of the pull-down node. Pull the potential of the control node as an invalid voltage;
  • the pull-up control circuit For a predetermined time set in the blank period after the display period, the pull-up control circuit maintains the potential of the first node as an effective voltage, and the pull-up control circuit maintains the potential of the first node and the second Under the control of the first clock signal input from a clock signal terminal, the potential of the pull-up control node is controlled, and under the control of the potential of the pull-up control node, the potential of the pull-up node is controlled to be an effective voltage; an external compensation control signal The output circuit controls the communication between the external compensation control signal output terminal and the external compensation clock signal terminal under the control of the potential of the pull-up node.
  • the gate driving method described in the embodiment of the present disclosure can simultaneously output a gate driving signal and an external compensation control signal. At the same time, the gate driving method described in the embodiment of the present disclosure can perform random compensation. By adopting the function of random compensation, Scan the surface line and the brightness deviation of the panel.
  • the pull-up control circuit includes a first node control sub-circuit, a second node control sub-circuit, a third node control sub-circuit, a pull-up control node control sub-circuit and a pull-up control sub-circuit; in the display period, the first node control sub-circuit An invalid voltage is input to a clock signal terminal, and an effective voltage is input to a second clock signal terminal; the predetermined time period includes a clock input stage and an external compensation output stage set in sequence; the gate driving method includes:
  • the enable terminal is input with an effective voltage
  • the drive signal of this stage is the effective voltage
  • the first node control sub-circuit controls the first node to access the drive signal of the current stage
  • the pull-up control node control sub-circuit controls The pull-up control node is connected to the first clock signal terminal
  • the pull-up control sub-circuit controls to disconnect the connection between the pull-up node and the third voltage terminal
  • the enable terminal is input with an invalid voltage
  • the potential of the pull-down node is the effective voltage
  • the first node control sub-circuit maintains the potential of the first node
  • the second node control sub-circuit The circuit controls the potential of the second node to be an effective voltage
  • the third node control sub-circuit controls the communication between the third node and the second voltage terminal
  • the pull-up control node control sub-circuit controls the pull-up control node and the first clock
  • the signal terminals are connected to each other and control the connection between the pull-up control node and the third node
  • the pull-up control sub-circuit controls the disconnection between the pull-up node and the third voltage terminal
  • the first node control sub-circuit maintains the potential of the first node
  • the first clock signal terminal is input with an effective voltage
  • the second clock signal terminal is input with an invalid voltage
  • the pull-up control node control sub-circuit controls the pull-up control node and the first clock signal terminal.
  • the pull-up control sub-circuit controls the pull-up node to communicate with the third voltage terminal to control the potential of the pull-up node as an effective voltage
  • the first clock signal terminal is input with an effective voltage
  • the second clock signal terminal is input with an invalid voltage
  • the first node control sub-circuit maintains the potential of the first node as the effective voltage
  • the pull-up control node controls The sub-circuit controls the connection between the pull-up control node and the first clock signal terminal, and the pull-up control sub-circuit disconnects the connection between the pull-up node and the third voltage terminal, so that the power of the pull-up node is maintained valid Voltage:
  • the external compensation clock signal terminal inputs an effective voltage
  • the external compensation control signal output circuit controls the communication between the external compensation control signal output terminal and the external compensation clock signal terminal.
  • the blank time period may further include a blank area reset phase set after the predetermined time period;
  • the gate driving method may further include:
  • the enable terminal inputs an effective voltage
  • the driving signal of the current level is an invalid voltage
  • the first node control sub-circuit controls the first node to access the current level driving signal to reset the potential of the first node .
  • the gate driving unit further includes a pull-up node control circuit; the gate driving method further includes:
  • the blank area reset terminal inputs an effective voltage to reset the potential of the pull-up node.
  • the gate drive module includes the above-mentioned gate drive unit; the gate drive unit is an N-th stage gate drive unit; N is a positive integer; the gate drive module further includes a first N+1 level gate drive unit;
  • the pull-up node in the N+1-th gate driving unit is the N+1 pull-up node
  • the pull-down node in the N+1-th gate driving unit is the N+1 pull-down node
  • the pull-up control node in the pole drive unit is the pull-up control node in the Nth stage gate drive unit
  • the N+1th stage gate driving unit includes an N+1th stage pull-up control circuit, an N+1th stage external compensation control signal output terminal, an N+1th stage gate drive signal output terminal, an N+1th stage External compensation control signal output circuit, N+1th gate drive signal output circuit and N+1th pull-down node control circuit;
  • the N+1th pull-up control circuit is connected to the Nth pull-up control node for controlling the N+1th pull-up node and the third voltage terminal under the control of the potential of the Nth pull-up control node Between
  • the N+1th pull-down node control circuit is used to control the potential of the N+1th pull-down node
  • the N+1th external compensation control signal output circuit is used to control the N+1th stage external compensation control signal output terminal and the second external compensation clock signal under the control of the potential of the N+1th pull-up node Communication between the terminals, and under the control of the potential of the N+1th pull-down node, control the communication between the external compensation control signal output terminal and the first voltage terminal;
  • the N+1th gate drive signal output circuit is used to control the N+1th stage gate drive under the control of the potential of the N+1th pull-up node and the potential of the N+1th pull-down node
  • the signal output terminal outputs a gate drive signal.
  • the pull-up control circuit (that is, the N+1 pull-up control circuit) and the N-th pull-up control in the N+1th stage gate driving unit Node connection, under the control of the potential of the Nth pull-up control node, control the potential of the N+1th pull-up node, that is, the N+1th pull-up control circuit does not include the first node control sub-circuit and the second node control
  • the sub-circuit, the third node control sub-circuit and the pull-up control node control sub-circuit, the N+1th pull-up control circuit only includes the pull-up control sub-circuit, and the N+1-th stage gate drive unit does not use carry signal output
  • the circuit and the corresponding stage carry signal output terminal can simplify the structure of the gate drive module and still realize the normal output of the N+1th gate drive signal and the N+1th external compensation of the N+1th stage gate drive unit control signal.
  • the first voltage terminal may be a low voltage terminal
  • the third voltage terminal may be a high voltage terminal, but it is not limited thereto.
  • the gate drive module includes the embodiment of the gate drive unit of the present disclosure as shown in FIG. 8; the gate drive unit is the Nth stage gate drive unit SN; N is a positive integer; the gate driving module further includes an N+1th stage gate driving unit SN+1;
  • the pull-up node in the gate driving unit SN+1 of the N+1 stage is the N+1 pull-up node Q(N+1), and the pull-down node in the gate driving unit of the N+1 stage is the N+1
  • the pull-up control node in the N+1-th gate driving unit is the pull-up control node PUCN in the N-th gate driving unit
  • the pull-up control node PUCN is the first N pull up the control node
  • the N+1th stage gate driving unit SN+1 includes an N+1th pull-up control circuit 23, an N+1th stage external compensation control signal output terminal OUT1(N+1), and an N+1th stage gate drive unit SN+1.
  • the N+1th pull-up control circuit 23 is connected to the Nth pull-up control node PUCN, and is used to control the N+1th pull-up node Q( N+1) is connected to the high voltage terminal; the high voltage terminal is used to input a high voltage VDD;
  • the N+1th pull-down node control circuit 24 is used to control the potential of the N+1th pull-down node QB(N+1);
  • the N+1th external compensation control signal output circuit 21 is used to control the N+1th stage external compensation control signal output terminal OUT1(N+1) under the control of the potential of the N+1th pull-up node Is connected to the second external compensation clock signal terminal CLKE_N+1, and under the control of the potential of the N+1th pull-down node QB(N+1), the external compensation control signal output terminal OUT1(N+1) is controlled Connected with the first voltage terminal; the first voltage terminal is used to input the first voltage V1;
  • the N+1th gate drive signal output circuit 22 is used to control the potential of the N+1th pull-up node Q(N+1) and the N+1th pull-down node QB(N+1) Next, the gate drive signal output terminal OUT2(N+1) of the N+1th stage is controlled to output a gate drive signal.
  • the pull-up control circuit (that is, the N+1th pull-up control circuit) in the N+1th stage gate driving unit SN+1 and the Nth The pull-up control node is connected.
  • the potential of the N+1th pull-up node Q(N+1) is controlled, that is, the N+1th pull-up control circuit does not include the first Node control sub-circuit 131, second node control sub-circuit 132, third node control sub-circuit 133, pull-up control node control sub-circuit 134
  • the N+1th pull-up control circuit only includes pull-up control sub-circuit 135, and
  • the N+1th stage gate drive unit SN+1 does not use the carry signal output circuit and the corresponding stage carry signal output terminal, so while the structure of the gate drive module can be simplified, the N+1th stage gate drive unit can still be realized SN+1 normally outputs the N+1th gate drive signal and the N+1th external
  • the control and the Nth gate are controlled during the Nth output stage of the display period.
  • the enable terminal connected to the pole drive unit inputs an effective voltage, so that the potential of PUCN can be controlled to be an effective voltage during the clock input stage of the blank period, thereby controlling the potential of Q(N+1) to be an effective voltage, and making it
  • the potential of the control Q(N+1) is maintained at an effective voltage.
  • CLKE_2 inputs an effective voltage
  • the N+1th stage external control signal in the N+1th stage gate drive unit The output terminal OUT1(N+1) outputs an effective voltage.
  • the N+1th stage gate driving unit further includes an N+1th pull-up node control circuit
  • the N+1th pull-up node control circuit is connected to the input terminal, the reset terminal, the N+1th pull-up node, the N+1th pull-down node, the blank area reset terminal, the third voltage terminal, and the fourth The voltage terminal is connected to control the connection between the N+1th pull-up node and the third voltage terminal under the control of the input signal input at the input terminal, and the reset signal input at the reset terminal Under control, the N+1th pull-up node is controlled to communicate with the fourth voltage terminal, and the N+1th pull-up is controlled under the control of the blank area reset signal input from the blank area reset terminal.
  • the node is connected to the fourth voltage terminal, and under the control of the potential of the N+1th pull-down node, the connection between the N+1th pull-up node and the fourth voltage terminal is controlled, and is used for Maintain the potential of the N+1th pull-up node.
  • the input terminal connected to the N+1th pull-up node control circuit that is, the input terminal connected to the Nth pull-up node control circuit, is connected to the N+1th pull-up node control circuit.
  • the input terminal is also the output terminal connected to the Nth pull-up node control circuit, that is, the Nth pull-up node control circuit and the N+1th pull-up node control circuit share one input terminal, and the Nth pull-up node control circuit and The N+1th pull-up node control circuit shares a reset terminal.
  • the pull-up control circuit in the N-th gate drive unit is an N-th pull-up control circuit;
  • the N pull-up control circuit includes a first node control sub-circuit, a second node control sub-circuit, A third node control sub-circuit, a pull-up control node control sub-circuit, and a pull-up control sub-circuit;
  • the N+1th pull-down node control circuit is respectively connected to the second control voltage terminal, the N+1th pull-up node, the N+1th pull-down node, and the first in the Nth stage gate driving unit.
  • the node, the first clock signal terminal, the reset terminal, and the fifth voltage terminal are connected, and are used to control the N+1 pull-up node under the control of the second control voltage input by the second control voltage and the potential of the N+1 pull-up node.
  • the potential of the N+1 pull-down node is controlled by the potential of the first node and the first clock signal input from the first clock signal terminal to control the N+1 pull-down node and the fifth voltage
  • the connection between the terminals is controlled, and the connection between the pull-down node and the fifth voltage terminal is controlled under the control of the input signal input from the input terminal.
  • the first node connected to the N+1th pull-down node control circuit is also the first node connected to the Nth pull-down node control circuit, the Nth pull-up node control circuit and the N+1th pull-up node
  • the node control circuit shares a first node.
  • the external compensation control signal output circuit in the Nth stage gate drive unit is an Nth external compensation control signal output circuit
  • the gate drive signal output circuit in the Nth stage gate drive unit is an Nth stage.
  • Gate drive signal output circuit; the external compensation control signal output terminal in the Nth stage gate drive unit is the Nth stage external compensation control signal output terminal, and the gate drive signal in the Nth stage gate drive unit
  • the output terminal is the Nth stage gate drive signal output terminal; the pull-up node in the Nth stage gate drive unit is the Nth pull-up node, and the pull-down node in the Nth stage gate drive unit is the Nth Drop down node
  • the Nth external compensation control signal output circuit is also connected to the N+1th pull-down node, and is used to reset the Nth stage external compensation control signal output terminal under the control of the potential of the N+1th pull-down node;
  • the Nth gate drive signal output circuit is also connected to the N+1th pull-down node, and is configured to reset the Nth stage gate drive signal output terminal under the control of the potential of the N+1th pull-down node;
  • the N+1th external compensation control signal output circuit is also connected to the Nth pull-down node, and is configured to reset the N+1th stage external compensation control signal output terminal under the control of the potential of the Nth pull-down node;
  • the N+1th gate drive signal output circuit is also connected to the Nth pull-down node, and is used to reset the N+1th stage gate drive signal output terminal under the control of the potential of the Nth pull-down node.
  • the gate driving unit described in the embodiment of the present disclosure may be the first-stage gate driving unit in the gate driving module described in the embodiment of the disclosure, and may be the gate driving unit described in the embodiment of the disclosure.
  • the N-level gate driving unit in the driving module, the second-level gate driving unit included in the gate driving module according to the embodiment of the present disclosure that is, the Nth level in the gate driving circuit according to the embodiment of the present disclosure +1 stage gate drive unit, the N+1 stage gate drive unit does not include a carry signal output terminal and a carry signal output circuit, and the pull-up node control circuit in the N+1 stage gate drive unit only includes A pull-up node control sub-circuit, the N+1th pull-up node control sub-circuit is connected to the pull-up control node N in the N-th stage gate driving unit, and is used to control the potential of the pull-up control node N , Controlling the potential of the pull-up node in the N+1th stage gate driving unit; and connecting the input terminal of the N+1th stage gate
  • the pull-down node in the N-th gate driving unit may be a first pull-down node, and the first pull-down node is affected by the pull-up node Q(N) and the first pull-up node Q(N) in the N-th gate driving unit.
  • the control voltage VDDo is controlled
  • the pull-down node in the N+1th stage gate driving unit may be a second pull-down node, and the second pull-down node is controlled by the pull-up node and the pull-up node in the N+1th stage gate driving unit. Control of the second control voltage.
  • the carry signal output circuit in the gate driving unit of the N+1th stage may be further connected to the second pull-down node, and the potential of the second pull-down node is controlled
  • the carry signal is reset;
  • the external compensation control signal output circuit in the N+1th stage gate drive unit may also be connected to the second pull-down node, and under the control of the potential of the second pull-down node, the external compensation The control signal is reset;
  • the gate drive signal output circuit in the gate drive unit may be further connected to the second pull-down node, and the gate drive signal is reset under the control of the potential of the second pull-down node;
  • the N+th The external compensation control signal output circuit in the level 1 gate driving unit can be connected to the first pull-down node and the second pull-down node at the same time, and the potential of the first pull-down node and the potential of the second pull-down node are controlled
  • the external compensation control signal is reset;
  • the gate drive signal output circuit in the gate drive unit may also be connected to the second pull
  • the display time may include multiple display time periods.
  • the display time period includes a first voltage supply stage and a second voltage supply stage set in sequence.
  • the first control voltage is a high voltage.
  • the second control voltage is a low voltage, during the second voltage supply phase, the first control voltage is a low voltage, and the second control voltage is a high voltage.
  • the external compensation control signal output circuit 11 in the Nth stage gate drive unit SN is the Nth external compensation control signal output circuit
  • the gate drive signal output circuit 12 in the Nth stage gate drive unit SN is the first N gate drive signal output circuit
  • the carry signal output circuit 16 in the Nth stage gate drive unit SN is an Nth carry signal output circuit
  • the external compensation control signal output in the Nth stage gate drive unit SN The terminal OUT1(N) is the Nth stage external compensation control signal output terminal
  • the gate drive signal output terminal OUT2(N) in the Nth stage gate drive unit SN is the Nth stage gate drive signal output terminal
  • the pull-up node Q(N) in the N-th gate driving unit SN is the N-th pull-up node
  • the pull-down node QB(N) in the N-th gate driving unit SN is the N-th pull-down node;
  • the Nth external compensation control signal output circuit 11 is also connected to the N+1th pull-down node QB(N+1) for controlling the potential of the N+1th pull-down node QB(N+1), Reset the Nth level external compensation control signal output terminal OUT1(N);
  • the Nth gate drive signal output circuit 12 is also connected to the N+1th pull-down node QB(N+1) for controlling the potential of the N+1th pull-down node QB(N+1), Reset the Nth gate drive signal output terminal OUT2(N);
  • the N-th carry signal output circuit 16 is also connected to the N+1-th pull-down node QB(N+1) for controlling the potential of the N+1-th pull-down node QB(N+1).
  • N-level carry signal output terminal CR(N) is reset;
  • the N+1th external compensation control signal output circuit 21 is also connected to the Nth pull-down node QB(N) for controlling the potential of the N+1th pull-down node Q(N). Reset the external compensation control signal output terminal OUT1(N);
  • the N+1th gate drive signal output circuit 22 is also connected to the Nth pull-down node QB(N) for controlling the potential of the N+1th pull-down node QB(N).
  • the gate drive signal output terminal OUT2(N) is reset.
  • SN is also connected to QB(N+1), and SN+1 is also connected to QB(N), that is, the Nth external compensation control signal output circuit 11 is at the potential of QB(N) and QB(N+ Under the control of the potential of 1), OUT1(N) is reset, and the Nth gate drive signal output circuit 12 controls the potential of QB(N) and QB(N+1) to reset OUT2(N).
  • the N+1th external compensation control signal output circuit 21 resets OUT1(N+1) under the control of the potential of QB(N) and the potential of QB(N+1), and the N+1th gate
  • the drive signal output circuit 22 resets OUT2(N+1) under the control of the potential of QB(N) and the potential of QB(N+1).
  • the gate driving module includes an Nth stage gate driving unit SN and an N+1th stage gate driving unit SN+1;
  • the Nth stage gate driving unit SN includes the specific embodiment of the gate driving unit as shown in FIG. 9A and the first reset circuit; the pull-down node QB(N) in FIG. 9A is the Nth pull-down node;
  • the first reset circuit includes a first reset transistor M18, a second reset transistor M21, a third reset transistor M24, and a fourth reset transistor M11;
  • the N+1th stage gate driving unit SN+1 includes an N+1th stage external compensation control signal output terminal OUT1(N+1), and an N+1th stage gate drive signal output terminal OUT2(N+1) , N+1th external compensation control signal output circuit, N+1th gate drive signal output circuit, N+1th pull-up control circuit 23, N+1th pull-down node control circuit and N+1th pull-up node control Circuit
  • the N+1th pull-up control circuit 23 includes an N+1th pull-up control transistor M25;
  • the gate of M25 is connected to the pull-up control node PUCN, the drain of M25 is connected to the high voltage VDD, and the source of M25 is connected to the N+1th pull-down node Q(N+1);
  • the N+1th pull-up node control circuit includes a fifth pull-up node control transistor M26, a sixth pull-up node control transistor M28, a seventh pull-up node control transistor M27, an eighth pull-up node control transistor M32, and a ninth pull-up node control transistor M28.
  • the gate of M26 is connected to the input terminal Reset, the drain of M26 is connected to the high voltage VDD, and the source of M26 is connected to the N+1th pull-up node Q(N+1);
  • the gate of M28 is connected to the reset terminal Reset, the drain of M28 is connected to Q(N+1), and the source of M28 is connected to the first low voltage VGL1;
  • the gate of M27 is connected to the blank area reset terminal TRST, the drain of M27 is connected to Q(N+1), and the source of M7 is connected to the first low voltage VGL1;
  • the gate of M32 is connected to the N+1th pull-down node QB(N+1), the drain of M32 is connected to Q(N+1), and the source of M12 is connected to the first low voltage VGL1;
  • the gate of M31 is connected to QB(N), the drain of M32 is connected to Q(N+1), and the source of M12 is connected to the first low voltage VGL1;
  • the first end of C4 is connected to Q(N+1), and the second end of C4 is connected to OUT1(N+1);
  • the first end of C5 is connected to Q(N+1), and the second end of C5 is connected to OUT2(N+1);
  • the N+1th pull-down node control circuit includes a sixth pull-down control transistor M29, a seventh pull-down control transistor M30, an eighth pull-down control transistor M33, a ninth pull-down control transistor M34, and a tenth pull-down control transistor M35.
  • the gate of M29 and the drain of M29 are both connected to the second control voltage terminal, and the source of M29 is connected to the N+1th pull-down node QB(N+1); the second control voltage terminal is used to input the second control voltage.
  • the gate of M30 is connected to Q(N+1), the drain of M30 is connected to QB(N+1), and the source of M30 is connected to the first low voltage VGL1;
  • the gate of M33 is connected to the first clock signal CLKA, and the drain of M33 is connected to QB(N+1);
  • the gate of M34 is connected to the first node H, the drain of M34 is connected to the source of M33, and the second electrode of M34 is connected to the first low voltage VGL1;
  • the gate of M35 is connected to the input terminal Input, the drain of M35 is connected to QB(N+1), and the source of M35 is connected to the first low voltage VGL1;
  • the N+1th external compensation control signal output circuit includes a third compensation output transistor M36, a fourth compensation output transistor M37, and a fifth compensation output transistor M38, wherein,
  • the gate of M36 is connected to Q(N+1), the drain of M36 is connected to the N+1th external compensation clock signal CLKE_N+1, and the source of M36 is connected to OUT1(N+1);
  • the gate of M37 is connected to the pull-down node QB(N+1), the drain of M37 is connected to OUT1(N+1), and the source of M37 is connected to the second low voltage VGL2;
  • the gate of M38 is connected to the pull-down node QB(N), the drain of M38 is connected to OUT1(N+1), and the source of M38 is connected to the second low voltage VGL2;
  • the gate drive signal output circuit includes a third gate drive signal output transistor M39, a fourth gate drive signal output transistor M40, and a fifth gate drive signal output transistor M41, wherein,
  • the gate of M39 is connected to Q(N+1), the drain of M39 is connected to the N+1th gate to drive the output clock signal CLKF_N, and the source of M39 is connected to OUT2(N+1);
  • the gate of M40 is connected to QB(N+1), the drain of M40 is connected to OUT2(N+1), and the source of M40 is connected to the second low voltage VGL2;
  • the gate of M18 is connected to QB(N+1), the drain of M18 is connected to CR(N), and the source of M18 is connected to VGL1;
  • the gate of M21 is connected to QB(N+1), the drain of M21 is connected to OUT1(N), and the source of M21 is connected to VGL2;
  • the gate of M24 is connected to QB(N+1), the drain of M24 is connected to OUT2(N), and the source of M21 is connected to VGL2;
  • the gate of M11 is connected to QB(N+1), the drain of M11 is connected to Q(N), and the source of M11 is connected to VGL1.
  • Input is connected to the carry signal output terminal CR(N-2) of the gate drive unit of stage N-2, and Reset is connected to the carry signal output of the gate drive unit of stage N+4. Terminal CR(N+4) is connected.
  • all transistors are n-type thin film transistors, but not limited to this.
  • N is equal to 5, that is, SN is the fifth-stage gate driving unit, and SN+1 is the sixth-stage gate driving unit.
  • FIG. 14 is a working timing diagram of the specific embodiment of the gate driving module shown in FIG. 13 of the present disclosure.
  • the one marked TD is the display period
  • the one marked td2 is the output time period.
  • the external compensation control signal output by the fifth-stage gate drive unit is high voltage, that is, OUT1(5 ) Output high voltage; in Figure 14, the blank time period marked TB.
  • the one labeled CLKD_1 is the first carry output clock signal
  • the one labeled CLKD_3 is the third carry output clock signal
  • the one labeled CLKD_5 is the fifth carry output clock signal
  • the one labeled CLKE_1 is the first external compensation Clock signal
  • CLKE_2 is the second external compensation clock signal
  • CLKE_3 is the third external compensation clock signal
  • CLKE_4 is the fourth external compensation clock signal
  • CLKE_5 is the fifth external compensation clock signal
  • CLKE_6 is the sixth external compensation clock signal
  • H(5) is the first node in the fifth-level gate drive unit
  • PUCN(5) is the fifth-level gate drive unit
  • the pull-up control node of Q(1) is the pull-up node in the first-level gate drive unit
  • the one marked Q(2) is the pull-up node in the second-level gate drive unit
  • Q(5) is the pull-up node in the fifth-level gate drive unit
  • Q(6) is the pull-up node in the sixth-level
  • the period of CLKE_1, the period of CLKE_2, the period of CLKE_3, the period of CLKE_4, the period of CLKE_5, and the period of CLKE_6 can all be T, but it is not limited to this;
  • the duty cycle of CLKE_1, CLKE_2, CLKE_3, CLKE_4, CLKE_5, and CLKE_6 can all be 1/3, but not limited to this;
  • CLKE_2 is later than CLK3_1 by T/6
  • CLKE_3 is later than CLK3_2 by T/6
  • CLKE_4 is later than CLK3_3 by T/6
  • CLKE_5 is later than CLK3_4 by T/6
  • CLKE_6 is later than CLK3_5 by T/6, but not limited to this.
  • STV is the start signal input to the input terminal of the first-stage gate driving unit included in the gate driving circuit
  • CLKA, CLKB, CLKD_N, CLKE_N, and CLKF_N are externally controlled clock signals
  • VDDo and VDDe It is a low-frequency clock signal, in which the signal pulse width relationship of all the above signals is adjustable
  • the first external compensation clock signal CLKE_1 is connected to the 6a-5th stage gate driving unit
  • the second external compensation clock signal CLKE_2 is connected to the 6a-4th stage gate driving unit
  • the third external The compensation clock signal CLKE_3 is connected to the 6a-3th stage gate drive unit
  • the fourth external compensation clock signal CLKE_4 is connected to the 6a-2th stage gate drive unit
  • the fifth external compensation clock signal CLKE_5 is connected to the 6a-1th stage gate
  • the driving unit is connected
  • the sixth external compensation clock signal CLKE_6 is connected to the 6a-th gate driving unit, where a is a positive integer;
  • the enable signal input by the OE is a random signal generated by the OE for an external circuit.
  • VGL1 ⁇ VGL2 that is, the potential of VGL2 is higher than the potential of VGL1 (in general, VGL1 and VGL2 are both negative voltages), and VGL1 and VGL2 are DC low voltage signals, and their values can be the same or Different, VDD is a DC high voltage signal.
  • the gate driving circuit according to the embodiment of the present disclosure includes multiple stages of the above-mentioned gate driving module.
  • the nth stage gate driving module may include an Nth stage gate driving unit and an N+1th stage gate driving unit;
  • the input terminal is connected to the N-2 stage gate drive signal output terminal, and the reset terminal is connected to the N+4 stage gate drive signal output terminal; n is a positive integer.
  • the corresponding row output stage of the display cycle in the corresponding row output stage, the corresponding stage gate drive
  • the signal output terminal outputs the effective voltage
  • the enable terminal of the corresponding stage gate drive unit included in the gate drive circuit is controlled to input the effective voltage, which can make the external compensation control signal in the corresponding stage gate drive unit in the blank period
  • the output terminal outputs the effective voltage, which can realize random compensation.
  • the gate driving unit of the corresponding stage can be randomly compensated when a display failure of the display panel is observed, so as to avoid the phenomenon of sweeping lines and brightness deviation of the display panel caused by line-by-line compensation.
  • the nth stage gate drive module includes an Nth stage gate drive unit and an N+1th stage gate drive unit; the Nth stage gate drive unit may include a carry signal output terminal and a carry signal output circuit ;
  • the input terminal is connected to the N-2 stage carry signal output terminal, and the reset terminal is connected to the N+4 stage carry signal output terminal; n is a positive integer.
  • the gate driving circuit according to the embodiment of the present disclosure includes a plurality of gate driving modules as shown in FIG. 13 is taken as an example for description;
  • the gate driving circuit includes a first gate driving module, a second gate driving module, a third gate driving module, a fourth gate driving module, and a second gate driving module.
  • the first gate driving module includes a first-stage gate driving unit S1 and a second-stage gate driving unit S2;
  • the second gate driving module includes a third-stage gate driving unit S3 and a fourth-stage gate driving unit S4;
  • the third gate driving module includes a fifth-stage gate driving unit S5 and a sixth-stage gate driving unit S6;
  • the fourth gate driving module includes a seventh-stage gate driving unit S7 and an eighth-stage gate driving unit S8;
  • S1 includes a first-stage carry signal output terminal CR(1), a first-stage external compensation control signal output terminal OUT1(1), and a first-stage gate drive signal output terminal OUT2(1); S1 is connected to the first clock signal CLKA , The second clock signal CLKB, the first carry output clock signal CLKD_1, the first external compensation clock signal CLKE_1 and the first gate drive output clock signal CLKF_1;
  • S2 includes a second-level external compensation control signal output terminal OUT1 (2) and a second-level gate drive signal output terminal OUT2 (2); S2 is connected to the first clock signal CLKA, the second external compensation clock signal CLKE_2 and the second gate Polar drive output clock signal CLKF_2;
  • S3 includes the third stage carry signal output terminal CR (3), the third stage external compensation control signal output terminal OUT1 (3) and the third stage gate drive signal output terminal OUT2 (3); the input terminal of S3 and CR (1) ) Connection, the reset terminal of S3 is connected to CR(7); S3 is connected to the first clock signal CLKA, the second clock signal CLKB, the third carry output clock signal CLKD_3, the third external compensation clock signal CLKE_3 and the third gate drive Output clock signal CLKF_3;
  • S4 includes the fourth stage external compensation control signal output terminal OUT1 (4) and the fourth stage gate drive signal output terminal OUT2 (4); the input terminal of S4 is connected to CR (1), and the reset terminal of S4 is connected to CR (7) Connection; S4 accesses the first clock signal CLKA, the fourth external compensation clock signal CLKE_4 and the fourth gate drive output clock signal CLKF_4;
  • S5 includes the fifth stage carry signal output terminal CR (5), the fifth stage external compensation control signal output terminal OUT1 (5) and the fifth stage gate drive signal output terminal OUT2 (5); the input terminal of S5 and CR (3) ) Connection, the reset terminal of S5 is connected to CR(9); S5 is connected to the first clock signal CLKA, the second clock signal CLKB, the fifth carry output clock signal CLKD_5, the fifth external compensation clock signal CLKE_5 and the fifth gate drive Output clock signal CLKF_5;
  • S6 includes the sixth stage external compensation control signal output terminal OUT1 (6) and the sixth stage gate drive signal output terminal OUT2 (6); the input terminal of S5 is connected to CR (3), and the reset terminal of S3 is connected to CR (9) Connection; S6 accesses the first clock signal CLKA, the sixth external compensation clock signal CLKE_6 and the sixth gate drive output clock signal CLKF_6;
  • S7 includes the seventh stage carry signal output terminal CR (7), the seventh stage external compensation control signal output terminal OUT1 (7) and the seventh stage gate drive signal output terminal OUT2 (7); S7 is connected to the first clock signal CLKA , The second clock signal CLKB, the first carry output clock signal CLKD_1, the first external compensation clock signal CLKE_1 and the first gate drive output clock signal CLKF_1;
  • S8 includes the eighth stage external compensation control signal output terminal OUT1 (8) and the eighth stage gate drive signal output terminal OUT2 (8); S8 is connected to the first clock signal CLKA, the second external compensation clock signal CLKE_2 and the second gate Polar drive output clock signal CLKF_2;
  • S9 includes the ninth stage carry signal output terminal CR (9), the ninth stage external compensation control signal output terminal OUT1 (9) and the ninth stage gate drive signal output terminal OUT2 (9); S9 is connected to the first clock signal CLKA , The second clock signal CLKB, the third carry output clock signal CLKD_3, the third external compensation clock signal CLKE_3 and the third gate drive output clock signal CLKF_3;
  • S10 includes a tenth-level external compensation control signal output terminal OUT1 (10) and a tenth-level gate drive signal output terminal OUT2 (10); S10 is connected to the first clock signal CLKA, the fourth external compensation clock signal CLKE_4 and the fourth gate The pole driver outputs the clock signal CLKF_4.
  • VDDo is high and VDDe is low
  • CR(1) outputs high voltage
  • CR(7) outputs low voltage
  • CLKA, CLKE_3, CLKD_3, and CLKF_3 are all low voltages
  • CLKE_4 and CLKF_4 are all low voltages to control
  • Q(3) and Q(4) are both high
  • the potential of QB(3) and QB(4) are both low
  • CR(3), OUT1(3) and OUT2 are both low
  • the potential of Q(3) and Q(4) are high, the potential of QB(3) and QB(4) are both low, CLKE_4 and CLKF_4 is high voltage, OUT1(4) and OUT2(4) both output high voltage;
  • the potential of Q(3) and the potential of Q(4) are low, and QB( The potential of 3) is high, CR(3), OUT1(3), OUT2(3), OUT1(4) and OUT2(4) all output low voltage;
  • Shifting sequentially completes the display of all rows of pixel circuits in the display period, and then enters the blank period.
  • the display device includes the above-mentioned gate driving circuit.
  • the display device may be any product or component with display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种栅极驱动单元、方法、栅极驱动模组、电路及显示装置。栅极驱动单元包括外部补偿控制信号输出端(OUT1(N))、栅极驱动信号输出端(OUT2(N))、外部补偿控制信号输出电路(11)、栅极驱动信号输出电路(12)、上拉控制电路(13)和下拉节点控制电路(14)，上拉控制电路(13)用于在使能端(OE)输入的使能信号和本级驱动信号(SG(N))的控制下，控制第一节点(H)的电位，在第一节点(H)的电位、第一时钟信号端输入的第一时钟信号(CLKA)、第二时钟信号端输入的第二时钟信号(CLKB)和下拉节点(QB(N))的电位的控制下，控制上拉控制节点(PUCN)的电位，并在上拉控制节点(PUCN)的电位的控制下，控制上拉节点(Q(N))的电位，以使得在空白时间段中的预定时间段，能够控制上拉节点(Q(N))的电位为有效电压。

Description

栅极驱动单元、方法、栅极驱动模组、电路及显示装置
相关申请的交叉引用
本申请主张在2019年3月8日在中国提交的中国专利申请号No.201910176221.7的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示驱动技术领域，尤其涉及一种栅极驱动单元、方法、栅极驱动模组、电路及显示装置。
背景技术
相关技术中应用于具有外部补偿功能的像素电路的栅极驱动单元通常主要由以下三个子电路组合而成：生成栅极驱动信号的栅极驱动子电路、生成检测信号的检测信号生成子电路(在空白时间段，检测信号的电位为有效电压，在显示周期，所述检测信号为无效电压)，以及输出该栅极驱动信号和该检测信号的复合脉冲信号(该复合脉冲信号即为外部补偿控制信号)，这样电路的结构非常复杂，无法满足高分辨率窄边框的要求。同时，相关技术中的栅极驱动电路是顺序扫描补偿的，但是长时间顺序补偿会在空白时间段带来扫面线(由于在对一级栅极驱动单元进行外部补偿时，在空白时间段，当所述外部补偿控制信号的电位为有效电压时，该行像素电路显示黑或白，则如果顺序补偿的话，会带来扫面线)。并且，在相关技术中的栅极驱动单元中，在空白时间段中，上拉节点的电位不能被充分拉高，会导致输出异常。
发明内容
本公开实施例提供了一种栅极驱动单元，包括外部补偿控制信号输出端、栅极驱动信号输出端、外部补偿控制信号输出电路、栅极驱动信号输出电路、上拉控制电路和下拉节点控制电路，其中，所述上拉控制电路用于在使能端输入的使能信号和本级驱动信号的控制下，控制第一节点的电位，在所述第一节点的电位、第一时钟信号端输入的第一时钟信号、第二时钟信号端输入 的第二时钟信号和所述下拉节点的电位的控制下，控制上拉控制节点的电位，并在所述上拉控制节点的电位的控制下，控制上拉节点的电位，以使得在空白时间段中的预定时间段，能够控制所述上拉节点的电位为有效电压；
所述下拉节点控制电路用于控制所述下拉节点的电位；
所述外部补偿控制信号输出电路用于在所述上拉节点的电位的控制下，控制所述外部补偿控制信号输出端与外部补偿时钟信号端之间连通，在所述下拉节点的电位的控制下，控制所述外部补偿控制信号输出端与第一电压端之间连通；
所述栅极驱动信号输出电路用于在所述上拉节点的电位和所述下拉节点的电位的控制下，控制所述栅极驱动信号输出端输出栅极驱动信号。
实施时，所述本级驱动信号的波形与所述栅极驱动信号的波形相同。
实施时，所述上拉控制电路包括第一节点控制子电路、第二节点控制子电路、第三节点控制子电路、上拉控制节点控制子电路和上拉控制子电路；
所述第一节点控制子电路用于在所述使能信号的控制下，控制第一节点接入所述本级驱动信号，并控制维持所述第一节点的电位；
所述第二节点控制子电路用于在所述第二时钟信号的控制下，控制第二节点的电位；
所述第三节点控制子电路用于在所述第二节点的电位的控制下，控制第三节点与第二电压端之间连通；
所述上拉控制节点控制子电路用于在所述第一节点的电位的控制下，控制所述上拉控制节点与所述第一时钟信号端之间连通，并在所述下拉节点的电位的控制下，控制所述上拉控制节点与所述第三节点之间连通；
所述上拉控制子电路用于在所述上拉控制节点的电位的控制下，控制所述上拉节点与第三电压端之间连通。
实施时，所述第二节点控制子电路还用于在所述第一时钟信号的控制下，控制所述第二节点与所述第二电压端之间连通。
实施时，所述第一节点控制子电路包括第一控制晶体管和储能电容；
所述第一控制晶体管的控制极与所述使能端连接，所述第一控制晶体管的第一极接入所述本级驱动信号，所述第一控制晶体管的第二极与所述第一 节点连接；
所述储能电容的第一端与所述第一节点连接，所述储能电容的第二端与所述上拉控制节点连接。
实施时，所述第二节点控制子电路包括第二控制晶体管；
所述第二控制晶体管的控制极和所述第二控制晶体管的第一极都与所述第二时钟信号端连接，所述第二控制晶体管的第二极与所述第二节点连接。
实施时，所述第二节点控制子电路还包括第二节点复位晶体管；
所述第二节点复位晶体管的控制极与所述第一时钟信号端连接，所述第二节点复位晶体管的第一极与所述第二节点连接，所述第二节点复位晶体管的第二极与所述第二电压端连接。
实施时，所述第三节点控制子电路包括第三控制晶体管；
所述第三控制晶体管的控制极与所述第二节点连接，所述第三控制晶体管的第一极与所述第三节点连接，所述第三控制晶体管的第二极与所述第二电压端连接；
所述上拉控制节点控制子电路包括第四控制晶体管和第五控制晶体管；
所述第四控制晶体管的控制极与所述第一节点连接，所述第四控制晶体管的第一极与所述第一时钟信号端连接，所述第四控制晶体管的第二极与所述上拉控制节点连接；
所述第五控制晶体管的控制极与所述下拉节点连接，所述第五控制晶体管的第一极与所述上拉控制节点连接，所述第五控制晶体管的第二极与所述第三节点连接；
所述上拉控制子电路包括上拉控制晶体管；
所述上拉控制晶体管的控制极与所述上拉控制节点连接，所述上拉控制晶体管的第一极与所述上拉节点连接，所述上拉控制晶体管的第二极与所述第三电压端连接。
实施时，本公开所述的栅极驱动单元还包括上拉节点控制电路；
所述上拉节点控制电路分别与输入端、复位端、所述上拉节点、所述下拉节点、空白区复位端、第三电压端和第四电压端连接，用于在所述输入端输入的输入信号的控制下，控制所述上拉节点与所述第三电压端之间连通， 在所述复位端输入的复位信号的控制下，控制所述上拉节点与所述第四电压端之间连通，在所述空白区复位端输入的空白区复位信号的控制下，控制所述上拉节点与所述第四电压端之间连通，在所述下拉节点的电位的控制下，控制所述上拉节点与所述第四电压端之间连通，并用于维持所述上拉节点的电位。
实施时，所述上拉节点控制电路包括第一上拉节点控制晶体管、第二上拉节点控制晶体管、第三上拉节点控制晶体管、第四上拉节点控制晶体管、第一存储电容和第二存储电容，其中，
所述第一上拉节点控制晶体管的控制极与所述输入端连接，所述第一上拉节点控制晶体管的第一极与所述第三电压端连接，所述第一上拉节点控制晶体管的第二极与所述上拉节点连接；
所述第二上拉节点控制晶体管的控制极与所述复位端连接，所述第二上拉节点控制晶体管的第一极与所述上拉节点连接，所述第二上拉节点控制晶体管的第二极与所述第四电压端连接；
所述第三上拉节点控制晶体管的控制极与所述空白区复位端连接，所述第三上拉节点控制晶体管的第一极与所述上拉节点连接，所述第三上拉节点控制晶体管的第二极与所述第四电压端连接；
所述第四上拉节点控制晶体管的控制极与所述下拉节点连接，所述第四上拉节点控制晶体管的第一极与所述上拉节点连接，所述第四上拉节点控制晶体管的第二极与所述第四电压端连接；
所述第一存储电容的第一端与所述上拉节点连接，所述第一存储电容的第二端与所述外部补偿控制信号输出端连接；
所述第二存储电容的第一端与所述上拉节点连接，所述第二存储电容的第二端与所述栅极驱动信号输出端连接。
实施时，所述下拉节点控制电路分别与第一控制电压端、所述上拉节点、所述下拉节点、所述第一节点、所述第一时钟信号端、所述输入端和第五电压端连接，用于在第一控制电压端输入的第一控制电压和所述上拉节点的电位的控制下，控制所述下拉节点的电位，并在所述第一节点的电位与所述第一时钟信号的控制下，控制所述下拉节点与所述第五电压端之间连通，在所 述输入端输入的输入信号的控制下，控制所述下拉节点与所述第五电压端之间连通。
实施时，所述下拉节点控制电路包括第一下拉控制晶体管、第二下拉控制晶体管、第三下拉控制晶体管、第四下拉控制晶体管和第五下拉控制晶体管，其中，
所述第一下拉控制晶体管的控制极和所述第一下拉控制晶体管的第一极都与所述第一控制电压端连接，所述第一下拉控制晶体管的第二极与下拉节点连接；
所述第二下拉控制晶体管的控制极与所述上拉节点连接，所述第二下拉控制晶体管的第一极与所述下拉节点连接，所述第二下拉控制晶体管的第二极与所述第五电压端连接；
所述第三下拉控制晶体管的控制极与所述第一时钟信号端连接，所述第三下拉控制晶体管的第一极与所述下拉节点连接；
所述第四下拉控制晶体管的控制极与所述第一节点连接，所述第四下拉控制晶体管的第一极与所述第三下拉控制晶体管的第二极连接，所述第四下拉控制晶体管的第二极与所述第五电压端连接；
所述第五下拉控制晶体管的控制极与所述输入端连接，所述第五下拉控制晶体管的第一极与所述下拉节点连接，所述第五下拉控制晶体管的第二极与所述第五电压端连接。
实施时，所述外部补偿控制信号输出电路包括第一补偿输出晶体管和第二补偿输出晶体管，其中，
所述第一补偿输出晶体管的控制极与所述上拉节点连接，所述第一补偿输出晶体管的第一极与所述外部补偿时钟信号端连接，所述第一补偿输出晶体管的第二极与所述外部补偿控制信号输出端连接；
所述第二补偿输出晶体管的控制极与所述下拉节点连接，所述第二补偿输出晶体管的第一极与所述外部补偿控制信号输出端连接，所述第二补偿输出晶体管的第二极与所述第一电压端之间连通。
实施时，本公开所述的栅极驱动单元还包括进位信号输出端和进位信号输出电路；
所述进位信号输出电路用于在所述上拉节点的电位和所述下拉节点的电位的控制下，控制所述进位信号输出端输出进位信号；
所述本级驱动信号为由所述进位信号输出端提供的进位信号。
本公开还提供了一种栅极驱动方法，应用于上述的栅极驱动单元，在两显示周期之间设置有空白时间段，所述栅极驱动方法包括：
在显示周期，上拉控制电路在使能端输入的使能信号和本级驱动信号的控制下，控制第一节点的电位为有效电压，并维持所述第一节点的电位为有效电压；所述上拉控制电路在所述第一节点的电位、第一时钟信号端输入的第一时钟信号、第二时钟信号端输入的第二时钟信号和所述下拉节点的电位的控制下，控制上拉控制节点的电位为无效电压；
在设置于该显示周期之后的空白时间段中的预定时间段，所述上拉控制电路维持所述第一节点的电位为有效电压，所述上拉控制电路在所述第一节点的电位和所述第一时钟信号的控制下，控制上拉控制节点的电位，并在所述上拉控制节点的电位的控制下，控制上拉节点的电位为有效电压；外部补偿控制信号输出电路在所述上拉节点的电位的控制下，控制外部补偿控制信号输出端与外部补偿时钟信号端之间连通。
实施时，所述上拉控制电路包括第一节点控制子电路、第二节点控制子电路、第三节点控制子电路、上拉控制节点控制子电路和上拉控制子电路；在显示周期，第一时钟信号端输入无效电压，第二时钟信号端输入有效电压；所述预定时间段包括依次设置的时钟输入阶段和外部补偿输出阶段；所述栅极驱动方法包括：
在显示周期包括的输出阶段，使能端输入有效电压，本级驱动信号为有效电压，第一节点控制子电路控制第一节点接入所述本级驱动信号；上拉控制节点控制子电路控制所述上拉控制节点与所述第一时钟信号端之间连通；上拉控制子电路控制断开上拉节点与第三电压端之间的连接；
在所述显示周期包括的复位阶段和输出截止保持阶段，使能端输入无效电压，下拉节点的电位为有效电压，第一节点控制子电路维持所述第一节点的电位；第二节点控制子电路控制第二节点的电位为有效电压，第三节点控制子电路控制第三节点与第二电压端之间连通；上拉控制节点控制子电路控 制所述上拉控制节点与所述第一时钟信号端之间连通，并控制上拉控制节点与第三节点之间连通；上拉控制子电路控制断开上拉节点与第三电压端之间的连接；
在设置于所述显示周期之后的空白时间段中的时钟输入阶段和外部补偿输出阶段，第一节点控制子电路维持所述第一节点的电位；
在该时钟输入阶段，所述第一时钟信号端输入有效电压，所述第二时钟信号端输入无效电压，上拉控制节点控制子电路控制所述上拉控制节点与所述第一时钟信号端之间连通，上拉控制子电路控制上拉节点与第三电压端之间连通，以控制上拉节点的电位为有效电压；
在该外部补偿输出阶段，所述第一时钟信号端输入有效电压，所述第二时钟信号端输入无效电压，第一节点控制子电路维持第一节点的电位为有效电压，上拉控制节点控制子电路控制上拉控制节点与所述第一时钟信号端之间连通，上拉控制子电路断开所述上拉节点与第三电压端之间的连接，使得上拉节点的电维持为有效电压；外部补偿时钟信号端输入有效电压，外部补偿控制信号输出电路控制外部补偿控制信号输出端与所述外部补偿时钟信号端之间连通。
实施时，所述空白时间段还包括设置于所述预定时间段之后的空白区复位阶段；所述栅极驱动方法还包括：
在该空白区复位阶段，使能端输入有效电压，本级驱动信号为无效电压，第一节点控制子电路控制第一节点接入所述本级驱动信号，以对第一节点的电位进行复位。
实施时，所述栅极驱动单元还包括上拉节点控制电路；所述栅极驱动方法还包括：
在所述空白区复位阶段，空白区复位端输入有效电压，以对所述上拉节点的电位进行复位。
本公开还提供了一种栅极驱动模组，包括上述的栅极驱动单元；所述栅极驱动单元为第N级栅极驱动单元；N为正整数；所述栅极驱动模组还包括第N+1级栅极驱动单元；
第N+1级栅极驱动单元中的上拉节点为第N+1上拉节点，第N+1级栅 极驱动单元中的下拉节点为第N+1下拉节点，第N+1级栅极驱动单元中的上拉控制节点为所述第N级栅极驱动单元中的上拉控制节点；
所述第N+1级栅极驱动单元包括第N+1级上拉控制电路、第N+1级外部补偿控制信号输出端、第N+1级栅极驱动信号输出端、第N+1外部补偿控制信号输出电路、第N+1栅极驱动信号输出电路和第N+1下拉节点控制电路；
所述第N+1级上拉控制电路与所述第N上拉控制节点连接，用于在该第N上拉控制节点的电位的控制下，控制第N+1上拉节点与第三电压端之间连接；
所述第N+1下拉节点控制电路用于控制第N+1下拉节点的电位；
所述第N+1外部补偿控制信号输出电路用于在该第N+1上拉节点的电位的控制下，控制所述第N+1级外部补偿控制信号输出端与第二外部补偿时钟信号端之间连通，在该第N+1下拉节点的电位的控制下，控制所述外部补偿控制信号输出端与所述第一电压端之间连通；
所述第N+1栅极驱动信号输出电路用于在该第N+1上拉节点的电位和该第N+1下拉节点的电位的控制下，控制所述第N+1级栅极驱动信号输出端输出栅极驱动信号。
实施时，所述第N+1级栅极驱动单元还包括第N+1上拉节点控制电路；
所述第N+1上拉节点控制电路分别与输入端、复位端、所述第N+1上拉节点、所述第N+1下拉节点、空白区复位端、第三电压端和第四电压端连接，用于在所述输入端输入的输入信号的控制下，控制所述第N+1上拉节点与所述第三电压端之间连通，在所述复位端输入的复位信号的控制下，控制所述第N+1上拉节点与所述第四电压端之间连通，在所述空白区复位端输入的空白区复位信号的控制下，控制所述第N+1上拉节点与所述第四电压端之间连通，在所述第N+1下拉节点的电位的控制下，控制所述第N+1上拉节点与所述第四电压端之间连通，并用于维持所述第N+1上拉节点的电位。
实施时，所述第N级栅极驱动单元中的上拉控制电路为第N上拉控制电路；所述N上拉控制电路包括第一节点控制子电路、第二节点控制子电路、第三节点控制子电路、上拉控制节点控制子电路和上拉控制子电路；
所述第N+1下拉节点控制电路分别与第二控制电压端、所述第N+1上拉 节点、所述第N+1下拉节点、所述第N级栅极驱动单元中的第一节点、第一时钟信号端、复位端和第五电压端连接，用于在所述第二控制电压输入的第二控制电压和所述N+1上拉节点的电位的控制下，控制所述第N+1下拉节点的电位，并在所述第一节点的电位与所述第一时钟信号端输入的第一时钟信号的控制下，控制所述N+1下拉节点与所述第五电压端之间连通，在输入端输入的输入信号的控制下，控制所述下拉节点与所述第五电压端之间连通。
实施时，所述第N级栅极驱动单元中的外部补偿控制信号输出电路为第N外部补偿控制信号输出电路，所述第N级栅极驱动单元中的栅极驱动信号输出电路为第N栅极驱动信号输出电路；所述第N级栅极驱动单元中的外部补偿控制信号输出端为第N级外部补偿控制信号输出端，所述第N级栅极驱动单元中的栅极驱动信号输出端为第N级栅极驱动信号输出端；所述第N级栅极驱动单元中的上拉节点为第N上拉节点，所述第N级栅极驱动单元中的下拉节点为第N下拉节点；
所述第N外部补偿控制信号输出电路还与所述第N+1下拉节点连接，用于在第N+1下拉节点的电位的控制下，对第N级外部补偿控制信号输出端进行复位；
所述第N栅极驱动信号输出电路还与所述第N+1下拉节点连接，用于在第N+1下拉节点的电位的控制下，对第N级栅极驱动信号输出端进行复位；
所述第N+1外部补偿控制信号输出电路还与所述第N下拉节点连接，用于在第N下拉节点的电位的控制下，对第N+1级外部补偿控制信号输出端进行复位；
所述第N+1栅极驱动信号输出电路还与所述第N下拉节点连接，用于在第N下拉节点的电位的控制下，对第N+1级栅极驱动信号输出端进行复位。
本公开还提供了一种栅极驱动电路，包括多级上述的栅极驱动模组。
实施时，第n级栅极驱动模组包括第N级栅极驱动单元和第N+1级栅极驱动单元；
在所述第n级栅极驱动模组中，输入端与第N-2级栅极驱动信号输出端连接，复位端与第N+4级栅极驱动信号输出端连接；n为正整数。
实施时，第n级栅极驱动模组包括第N级栅极驱动单元和第N+1级栅极 驱动单元；所述第N级栅极驱动单元包括进位信号输出端和进位信号输出电路；
在所述第n级栅极驱动模组中，输入端与第N-2级进位信号输出端连接，复位端与第N+4级进位信号输出端连接；n为正整数。
附图说明
图1是本公开实施例所述的栅极驱动单元的结构图；
图2是具有外部补偿功能的像素电路的电路图；
图3是本公开又一实施例所述的栅极驱动单元的结构图；
图4是本公开再一实施例所述的栅极驱动单元的结构图；
图5是本公开另一实施例所述的栅极驱动单元的结构图；
图6是本公开又一实施例所述的栅极驱动单元的结构图；
图7是本公开再一实施例所述的栅极驱动单元的结构图；
图8是本公开另一实施例所述的栅极驱动单元的结构图；
图9A是本公开所述的栅极驱动单元的一具体实施例的电路图；
图9B是本公开所述的栅极驱动单元的另一具体实施例的电路图；
图10是本公开如图9A所示的栅极驱动单元的具体实施例的工作时序图；
图11是本公开实施例所述的栅极驱动模组的结构图；
图12是本公开另一实施例所述的栅极驱动模组的结构图；
图13是本公开所述的栅极驱动模组的一具体实施例的电路图；
图14是本公开所述的栅极驱动模组的该具体实施例的工作时序图；
图15是本公开所述的栅极驱动电路的一具体实施例的结构图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为三极管、薄膜晶体管或场效 应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除控制极之外的两极，将其中一极称为第一极，另一极称为第二极。
在实际操作时，当所述晶体管为三极管时，所述控制极可以为基极，所述第一极可以为集电极，所述第二极可以发射极；或者，所述控制极可以为基极，所述第一极可以为发射极，所述第二极可以集电极。
在实际操作时，当所述晶体管为薄膜晶体管或场效应管时，所述控制极可以为栅极，所述第一极可以为漏极，所述第二极可以为源极；或者，所述控制极可以为栅极，所述第一极可以为源极，所述第二极可以为漏极。
如图1所示，本公开实施例所述的栅极驱动单元包括外部补偿控制信号输出端OUT1(N)、栅极驱动信号输出端OUT2(N)、外部补偿控制信号输出电路11、栅极驱动信号输出电路12、上拉控制电路13和下拉节点控制电路14，其中，
所述上拉控制电路13分别与使能端OE、第一时钟信号端、第二时钟信号端、上拉节点Q(N)、下拉节点QB(N)、第一节点H和上拉控制节点PUCN连接，用于在使能端OE输入的使能信号和本级驱动信号的控制下，控制第一节点H的电位，在所述第一节点H的电位、第一时钟信号端输入的第一时钟信号CLKA、第二时钟信号端输入的第二时钟信号CLKB和所述下拉节点QB(N)的电位的控制下，控制上拉控制节点PUCN的电位，并在所述上拉控制节点PUCN的电位的控制下，控制上拉节点Q(N)的电位，以使得在空白时间段中的预定时间段，能够控制所述上拉节点Q(N)的电位为有效电压；
所述下拉节点控制电路14用于控制所述下拉节点QB(N)的电位；
所述外部补偿控制信号输出电路11用于在所述上拉节点Q(N)的电位的控制下，控制所述外部补偿控制信号输出端OUT1(N)与外部补偿时钟信号端之间连通，在所述下拉节点QB(N)的电位的控制下，控制所述外部补偿控制信号输出端OUT1(N)与第一电压端之间连通；所述外部补偿时钟信号端用于输入外部补偿时钟信号CLKE_N，所述第一电压端用于输入第一电压V1；
所述栅极驱动信号输出电路12用于在所述上拉节点Q(N)的电位和所 述下拉节点QB(N)的电位的控制下，控制所述栅极驱动信号输出端OUT2(N)输出栅极驱动信号。
在具体实施时，所述第一电压端可以为低电压端，但不以此为限。
在具体实施时，有效电压为能够使得栅极接入其的晶体管打开的电压，例如，当该晶体管为n型晶体管时，该有效电压可以为高电压；当该晶体管为p型晶体管时，该有效电压可以为低电压，但不以此为限。
在具体实施时，有效电压为能够使得栅极接入其的晶体管关断的电压，例如，当该晶体管为n型晶体管时，该有效电压可以为低电压；当该晶体管为p型晶体管时，该有效电压可以为高电压，但不以此为限。
本公开如图1所示的栅极驱动单元的实施例在工作时，在两显示周期之间设置有空白时间段，所述栅极驱动方法包括：
在显示周期，上拉控制电路13在使能端OE输入的使能信号和本级驱动信号SG(N)的控制下，控制第一节点H的电位为有效电压，并维持所述第一节点H的电位为有效电压；所述上拉控制电路13在所述第一节点H的电位、第一时钟信号端输入的第一时钟信号CLKA、第二时钟信号端输入的第二时钟信号CLKB和所述下拉节点QB(N)的电位的控制下，控制上拉控制节点PUCN的电位为无效电压；
在设置于该显示周期之后的空白时间段中的预定时间段，所述上拉控制电路13维持所述第一节点H的电位为有效电压，所述上拉控制电路13在所述第一节点H的电位和第一时钟信号端输入的第一时钟信号CLKA的控制下，控制上拉控制节点PUCN的电位，并在所述上拉控制节点PUCN的电位的控制下，控制上拉节点Q(N)的电位为有效电压；外部补偿控制信号输出电路11在所述上拉节点Q(N)的电位的控制下，控制外部补偿控制信号输出端OUT1(N)与外部补偿时钟信号端之间连通。
本公开实施例所述的栅极驱动单元能够同时输出栅极驱动信号和外部补偿控制信号，以能够同时为具有外部补偿功能的像素电路提供栅极驱动信号和外部补偿信号，简化了电路的结构，同时采用本公开实施例所述的栅极驱动单元可以进行随机补偿，通过采用随机补偿的功能，消除扫面线以及面板的亮度偏差。
在实际操作时，所述显示周期可以包括依次设置的输入阶段、输出阶段、复位阶段和输出截止保持阶段，在输入阶段和输出阶段，PU(N)的电位为有效电压，在输出阶段，栅极驱动信号输出端和外部补偿控制信号输出端都输出有效电压，在复位阶段和输出截止保持阶段，栅极驱动信号输出端和外部补偿控制信号输出端都输出无效电压。
在实际操作时，假设本公开实施例所述的栅极驱动单元为显示面板上的第N行(N为正整数)栅线提供相应的栅极驱动信号，则本公开实施例所述的栅极驱动单元即为栅极驱动电路包括的第N级栅极驱动单元，本级指的即为第N级。
在具体实施时，所述本级驱动信号SG(N)的波形与所述栅极驱动信号的波形相同。
根据一种具体实施方式，所述本级驱动信号SG(N)可以由栅极驱动信号输出端OUT2(N)提供；
根据另一种具体实施方式，当本公开实施例所述的栅极驱动单元包括进位信号输出电路和进位信号输出端时，所述本级驱动信号SG(N)可以由所述进位信号输出端提供。
如图2所示，具有外部补偿功能的像素电路可以包括数据写入晶体管T1、电容Cst、驱动晶体管T2、发光元件EL和外部补偿控制晶体管T3，T1的栅极与相应级栅极驱动信号输出端连接，T3的栅极与相应级外部补偿控制信号输出端连接，在图2中，标号为Data的为数据线，标号为ELVDD的为高电平，标号为ELVSS的为低电平，标号为SL的为外部补偿线，标号为GND的为地端，标号为Cs的为外部补偿线SL上的寄生电容。
具体的，所述上拉控制电路可以包括第一节点控制子电路、第二节点控制子电路、第三节点控制子电路、上拉控制节点控制子电路和上拉控制子电路；
所述第一节点控制子电路用于在所述使能信号的控制下，控制第一节点接入所述本级驱动信号，并控制维持所述第一节点的电位；
所述第二节点控制子电路用于在所述第二时钟信号的控制下，控制第二节点的电位；
所述第三节点控制子电路用于在所述第二节点的电位的控制下，控制第三节点与第二电压端之间连通；
所述上拉控制节点控制子电路用于在所述第一节点的电位的控制下，控制所述上拉控制节点与所述第一时钟信号端之间连通，并在所述下拉节点的电位的控制下，控制所述上拉控制节点与所述第三节点之间连通；
所述上拉控制子电路用于在所述上拉控制节点的电位的控制下，控制所述上拉节点与第三电压端之间连通。
在具体实施时，所述第二电压端可以为第一低电压端，所述第三电压端可以为高电压端，但不以此为限。
如图3所示，在本公开图1所示的栅极驱动单元的实施例的基础上，所述上拉控制电路包括第一节点控制子电路131、第二节点控制子电路132、第三节点控制子电路133、上拉控制节点控制子电路134和上拉控制子电路135，其中，
所述第一节点控制子电路131分别与使能端OE和第一节点H连接，用于在OE输入的使能信号的控制下，控制第一节点H接入所述本级驱动信号SG(N)，并控制维持所述第一节点H的电位；
所述第二节点控制子电路132分别与第二节点J和第二时钟信号端连接，用于在所述第二时钟信号CLKB的控制下，控制第二节点J的电位；
所述第三节点控制子电路133分别与第二节点J、第三节点M和第一低电压端连接，用于在所述第二节点J的电位的控制下，控制第三节点M与第一低电压端之间连通；所述第一低电压端用于输入第一低电压VGL1；
所述上拉控制节点控制子电路134分别与上拉控制节点PUCN、所述第一节点H、所述第一时钟信号端、下拉节点QB(N)和所述第三节点M连接，用于在所述第一节点H的电位的控制下，控制所述上拉控制节点PUCN与所述第一时钟信号端之间连通，并在所述下拉节点QB(N)的电位的控制下，控制所述上拉控制节点PUCN与所述第三节点M之间连通；
所述上拉控制子电路135分别与所述上拉控制节点PUCN、所述上拉节点Q(N)和高电压端连接，用于在所述上拉控制节点PUCN的电位的控制下，控制所述上拉节点Q(N)与所述高电压端之间连通；所述高电压端用于 输入高电压VDD。
在图3所示的实施例中，第二电压端为第一低电压端，第三电压端为高电压端，但不以此为限。
本公开如图3所示的实施例在工作时，所述空白时间段中的预定时间段包括依次设置的时钟输入阶段和外部补偿输出阶段；所述栅极驱动方法包括：
在显示周期包括的输出阶段，使能端OE输入有效电压，本级驱动信号SG(N)为有效电压，第一节点控制子电路131控制第一节点H接入所述本级驱动信号SG(N)；上拉控制节点控制子电路134控制所述上拉控制节点PUCN接入CLKA；上拉控制子电路135控制断开上拉节点Q(N)接入高电压VDD；
在所述显示周期包括的复位阶段和输出截止保持阶段，使能端OE输入无效电压，下拉节点QB(N)的电位为有效电压，第一节点控制子电路131维持所述第一节点H的电位；第二节点控制子电路132控制第二节点J的电位为有效电压，第三节点控制子电路133控制第三节点M接入第一低电压VGL1；上拉控制节点控制子电路134控制所述上拉控制节点PUCN接入第一时钟信号CLKA，并控制上拉控制节点PUCN与第三节点M之间连通；上拉控制子电路135控制断开上拉节点Q(N)与所述高电压端之间的连接；
在设置于所述显示周期之后的空白时间段中的时钟输入阶段和外部补偿输出阶段，第一节点控制子电路131维持所述第一节点H的电位；
在该时钟输入阶段，所述第一时钟信号CLKA为有效电压，所述第二时钟信号CLKB为无效电压，上拉控制节点控制子电路134控制所述上拉控制节点PUCN接入所述第一时钟信号端CLKA，上拉控制子电路135控制上拉节点Q(N)接入高电压VDD，以控制上拉节点Q(N)的电位为有效电压；
在该外部补偿输出阶段，所述第一时钟信号CLKA为有效电压，所述第二时钟信号CLKB为无效电压，第一节点控制子电路131维持第一节点H的电位为有效电压，上拉控制节点控制子电路134控制上拉控制节点PUCN接入所述第一时钟信号CLKA，上拉控制子电路135断开所述上拉节点Q(N)与所述高电压端之间的连接，使得上拉节点Q(N)的电位维持为有效电压；外部补偿时钟信号端输入的外部补偿时钟信号CLKE_N为有效电压，外部补 偿控制信号输出电路11控制外部补偿控制信号输出端OUT1(N)与所述外部补偿时钟信号端之间连通。
在具体实施时，所述第二节点控制子电路还可以用于在所述第一时钟信号的控制下，控制所述第二节点与所述第二电压端之间连通。
当所述第一时钟信号为有效电压时，所述第二节点控制子电路控制第二节点与第二电压端之间连通；当所述第一时钟信号为无效电压时，所述第二节点控制子电路控制第二节点与第二电压端之间不连通。
具体的，所述第一节点控制子电路可以包括第一控制晶体管和储能电容；
所述第一控制晶体管的控制极与所述使能端OE端连接，所述第一控制晶体管的第一极接入所述本级驱动信号，所述第一控制晶体管的第二极与所述第一节点连接；
所述储能电容的第一端与所述第一节点连接，所述储能电容的第二端与所述上拉控制节点连接。
具体的，所述第二节点控制子电路可以包括第二控制晶体管；
所述第二控制晶体管的控制极和所述第二控制晶体管的第一极都与所述第二时钟信号端连接，所述第二控制晶体管的第二极与所述第二节点连接。
具体的，所述第二节点控制子电路还可以包括第二节点复位晶体管；
所述第二节点复位晶体管的控制极与所述第一时钟信号端连接，所述第二节点复位晶体管的第一极与所述第二节点连接，所述第二节点复位晶体管的第二极与所述第二电压端连接。
具体的，所述第三节点控制子电路可以包括第三控制晶体管；
所述第三控制晶体管的控制极与所述第二节点连接，所述第三控制晶体管的第一极与所述第三节点连接，所述第三控制晶体管的第二极与所述第二电压端连接；
所述上拉控制节点控制子电路包括第四控制晶体管和第五控制晶体管；
所述第四控制晶体管的控制极与所述第一节点连接，所述第四控制晶体管的第一极与所述第一时钟信号端连接，所述第四控制晶体管的第二极与所述上拉控制节点连接；
所述第五控制晶体管的控制极与所述下拉节点连接，所述第五控制晶体 管的第一极与所述上拉控制节点连接，所述第五控制晶体管的第二极与所述第三节点连接；
所述上拉控制子电路包括上拉控制晶体管；
所述上拉控制晶体管的控制极与所述上拉控制节点连接，所述上拉控制晶体管的第一极与所述上拉节点连接，所述上拉控制晶体管的第二极与所述第三电压端连接。
如图4所示，在图3所示的栅极驱动单元的实施例的基础上，所述第一节点控制子电路131包括第一控制晶体管M1和储能电容C1；
所述第一控制晶体管M1的栅极接入使能端OE输入的使能信号，所述第一控制晶体管M1的漏极接入所述本级驱动信号SG(N)，所述第一控制晶体管M1的源极与所述第一节点H连接；
所述储能电容C1的第一端与所述第一节点H连接，所述储能电容的第二端C1与所述上拉控制节点PUCN连接。
所述第二节点控制子电路132包括第二控制晶体管M42；
所述第二控制晶体管M42的栅极和所述第二控制晶体管M42的漏极都接入所述第二时钟信号CLKB，所述第二控制晶体管M42的源极与所述第二节点J连接；
所述第三节点控制子电路133包括第三控制晶体管M43；
所述第三控制晶体管M43的栅极与所述第二节点J连接，所述第三控制晶体管M43的漏极与第三节点M连接，所述第三控制晶体管M43的源极接入第一低电压VGL1；
所述上拉控制节点控制子电路134包括第四控制晶体管M2和第五控制晶体管M4；
所述第四控制晶体管M2的栅极与所述第一节点H连接，所述第四控制晶体管M2的漏极接入所述第一时钟信号CLKA，所述第四控制晶体管M2的源极与所述上拉控制节点PUCN连接；
所述第五控制晶体管M4的栅极与所述下拉节点QB(N)连接，所述第五控制晶体管M4的漏极与所述上拉控制节点PUCN连接，所述第五控制晶体管M44的源极与所述第三节点M连接；
所述上拉控制子电路135包括上拉控制晶体管M5；
所述上拉控制晶体管M5的栅极与所述上拉控制节点PUCN连接，所述上拉控制晶体管M5的漏极与所述上拉节点Q(N)连接，所述上拉控制晶体管M5的源极接入高电压VDD。
在本公开实施例所述的栅极驱动单元中，所述第一节点控制子电路131包括储能电容C1，以在空白时间段中的时钟输入阶段(此时，CLKA为高电压，CLKB为低电压，QB(N)的电位为低电压，M2打开，M42和M4关断)，阻止上拉控制节点PUCN的电位由于漏电而降低，使得第一节点H的电位由于C1的二次自举而升高，所述上拉控制节点PUCN得到CLKA的无损高电位，Q(N)接入VDD，能够提高Q(N)的电位，确保Q(N)的电位为高电压，增强电路信赖性。
利用新的电路结构能够提高上拉节点的电位，增强电路信赖性
在图4所示的实施例中，所有的晶体管都为n型薄膜晶体管，但不以此为限；第二电压端为第一低电压端，第三电压端为高电压端，有效电压为高电压，无效电压为低电压，但不以此为限。
本公开如图4所示的栅极驱动单元的实施例在工作时，如果需要在一显示周期后的空白时间段控制OUT1(N)输出有效电压，
则在该显示周期的输出阶段，OE输入高电压，SG(N)为高电压，M1打开，以控制H的电位为高电压；C1维持H的电位为高电压；M2打开，CLKA为低电压，CLKB为高电压，M2打开，以使得PUCN接入CLKA，PUCN的电位为低电压，M5关断，以不影响显示；M42打开，以使得J的电位为高电压，M43打开，以使得M接入VGL1；此时QB(N)的电位为低电压，则M4关断；
在该显示周期的复位阶段和输出截止保持阶段，OE输入低电压，M1关断，C1维持H的电位为高电压，CLKA为低电压，M2打开；CLKB为高电压，M42打开，以使得J的电位为高电压，M43打开，M接入VGL1，并QB(N)的电位为高电压，M4打开，以控制M与PUCN之间连接，PUCN的电位为低电压，M5关断，以不影响显示；
在空白时间段中的时钟输入阶段，CLKA为高电压，CLKB为低电压， QB(N)的电位为低电压，M2打开，M42和M4关断，阻止上拉控制节点PUCN的电位由于漏电而降低，使得第一节点H的电位由于二次自举而升高，所述上拉控制节点PUCN得到CLKA的无损高电位，Q(N)接入VDD，以使得Q(N)的电位为高电压；
在空白时间段中的外部补偿输出阶段，CLKA为低电压，CLKB为高电压，H的电位维持为高电压，M2打开，以将PUCN的电位拉低，M5关断，Q(N)的电位被存储电容(所述存储电容包括设置于Q(N)与OUT1(N)之间的第一存储电容和设置于Q(N)与OUT2(N)之间的第二存储电容)维持为高电压；此时CLKE_N为高电压，CLKF_N为低电压，OUT1(N)输出高电压，OUT2(N)输出低电压。
在具体实施时，所述空白时间段还包括设置于所述外部补偿输出阶段之后的空白区复位阶段；
在该空白区复位阶段，使能端OE输入高电压，SG(N)为低电压，M1打开，H的电位为低电压，以对第一节点H的电位进行复位。
本公开如图4所示的栅极驱动单元的实施例在工作时，在显示周期，M42和M43对显示无影响，在空白时间段中的时钟输入阶段，CLKA为高电位，需要对sense(检测)行的上拉节点Q(N)写入高电位，CLKB也变为低电位，阻止上拉控制节点PUCN的电位由于漏电而降低，使得第一节点H的电位由于二次自举而升高，所述上拉控制节点PUCN得到CLKA的无损高电位，Q(N)写入高电位。
本公开如图4所示的栅极驱动单元的实施例在工作时，假设该栅极驱动单元与显示面板上的位于第N行(N为正整数)的栅线连接，该第N行为sense(检测)行，也即在空白时间段，需要向显示面板上的第N行像素电路(所述第N行像素电路为具有外部补偿功能的像素电路)提供外部补偿控制信号，需要在显示周期，当扫描至第N行栅线时，也即OUT2(N)输出高电平(也即OUT2(N)输出有效电压)时，控制OE输入有效电压，以将第一节点H的电位设置为有效电压，并第一节点H的电位在显示阶段和空白时间段中的预定时间段一直维持为有效电压，在空白时间段中的时钟输入阶段，CLKA为有效电压，则上拉控制节点PUCN的电位被置为有效电压，从而控制Q(N) 的电位为有效电压，并Q(N)的电位在空白时间段中的外部补偿输出阶段一直维持为有效电压，在外部补偿输出阶段，CLKE_N为有效电压，则OUT1(N)输出有效电压，CLKF_N为无效电压，OUT2(N)输出无效电压。
具体的，所述第二节点控制子电路还可以包括第二节点复位晶体管；
所述第二节点复位晶体管的控制极与所述第一时钟信号端连接，所述第二节点复位晶体管的第一极与所述第二节点连接，所述第二节点复位晶体管的第二极与所述第二电压端连接。
当第一时钟信号端输入有效电压时，第二节点复位晶体管打开，以使得第二节点接入第二电压，当第一时钟信号端输入无效电压时，第二节点复位晶体管关断。
在具体实施时，本公开实施例所述的栅极驱动单元还可以包括上拉节点控制电路；
所述上拉节点控制电路分别与输入端、复位端、所述上拉节点、所述下拉节点、空白区复位端、第三电压端和第四电压端连接，用于在所述输入端输入的输入信号的控制下，控制所述上拉节点与所述第三电压端之间连通，在所述复位端输入的复位信号的控制下，控制所述上拉节点与所述第四电压端之间连通，在所述空白区复位端输入的空白区复位信号的控制下，控制所述上拉节点与所述第四电压端之间连通，在所述下拉节点的电位的控制下，控制所述上拉节点与所述第四电压端之间连通，并用于维持所述上拉节点的电位。
所述第三电压端可以为高电压端，所述第四电压端可以为第一低电压端，但不以此为限。
如图5所示，在本公开图1所示的栅极驱动单元的实施例的基础上，本公开实施例所述的栅极驱动单元还包括上拉节点控制电路15；
所述上拉节点控制电路15分别与输入端Input、复位端Reset、所述上拉节点Q(N)、所述下拉节点QB(N)、空白区复位端TRST、高电压端和第一低电压端连接，用于在所述输入端Input输入的输入信号的控制下，控制所述上拉节点Q(N)与所述高电压端之间连通，在所述复位端Reset输入的复位信号的控制下，控制所述上拉节点Q(N)与所述第一低电压端之间连通， 在所述空白区复位端TRST输入的空白区复位信号的控制下，控制所述上拉节点Q(N)与所述第一低电压端之间连通，在所述下拉节点QB(N)的电位的控制下，控制所述上拉节点Q(N)与所述第一低电压端之间连通，并用于维持所述上拉节点Q(N)的电位。
在具体实施时，在空白时间段中的空白区复位阶段，TRST输入的空白区复位信号为有效电压，所述上拉节点控制电路15在TRST输入的空白区复位信号的控制下，控制Q(N)接入第一低电压VGL1，以对上拉节点Q(N)的电位进行复位；
并在显示周期包括的输入阶段，Input输入的输入信号为高电压，所述上拉节点控制电路15控制Q(N)接入高电压VDD，以拉升Q(N)的电位；
在显示周期包括的输出阶段，所述上拉节点控制电路15维持Q(N)的电位为高电位；
在显示周期包括的复位阶段，Reset输入的复位信号为高电压，所述上拉节点控制电路15控制Q(N)接入VGL1；
在显示周期包括的输出截止阶段，QB(N)的电位为高电压，所述上拉节点控制电路15控制Q(N)接入VGL1。
具体的，所述上拉节点控制电路可以包括第一上拉节点控制晶体管、第二上拉节点控制晶体管、第三上拉节点控制晶体管、第四上拉节点控制晶体管、第一存储电容和第二存储电容，其中，
所述第一上拉节点控制晶体管的控制极与所述输入端连接，所述第一上拉节点控制晶体管的第一极与所述第三电压端连接，所述第一上拉节点控制晶体管的第二极与所述上拉节点连接；
所述第二上拉节点控制晶体管的控制极与所述复位端连接，所述第二上拉节点控制晶体管的第一极与所述上拉节点连接，所述第二上拉节点控制晶体管的第二极与所述第四电压端连接；
所述第三上拉节点控制晶体管的控制极与所述空白区复位端连接，所述第三上拉节点控制晶体管的第一极与所述上拉节点连接，所述第三上拉节点控制晶体管的第二极与所述第四电压端连接；
所述第四上拉节点控制晶体管的控制极与所述下拉节点连接，所述第四 上拉节点控制晶体管的第一极与所述上拉节点连接，所述第四上拉节点控制晶体管的第二极与所述第四电压端连接；
所述第一存储电容的第一端与所述上拉节点连接，所述第一存储电容的第二端与所述外部补偿控制信号输出端连接；
所述第二存储电容的第一端与所述上拉节点连接，所述第二存储电容的第二端与所述栅极驱动信号输出端连接。
在具体实施时，所述下拉节点控制电路可以分别与第一控制电压端、所述上拉节点、所述下拉节点、所述第一节点、所述第一时钟信号端、所述输入端和第五电压端连接，用于在第一控制电压端输入的第一控制电压和所述上拉节点的电位的控制下，控制所述下拉节点的电位，并在所述第一节点的电位与所述第一时钟信号的控制下，控制所述下拉节点与所述第五电压端之间连通，在所述输入端输入的输入信号的控制下，控制所述下拉节点与所述第五电压端之间连通。
在具体实施时，所述第五电压端可以为第一低电压端，但不以此为限。
如图6所示，在图1所示的栅极驱动单元的实施例的基础上，所述下拉节点控制电路14分别与第一控制电压端、所述上拉节点Q(N)、所述下拉节点QB(N)、所述第一节点H、所述第一时钟信号端、所述输入端Input和第一低电压端连接，用于在第一控制电压端输入的第一控制电压VDDo和所述上拉节点Q(N)的电位的控制下，控制所述下拉节点QB(N)的电位，并在所述第一节点H的电位与所述第一时钟信号CLKA的控制下，控制所述下拉节点QB(N)接入第一低电压VGL1，在所述输入端Input输入的输入信号的控制下，控制所述下拉节点QB(N)接入第一低电压VGL。
本公开如图6所示的栅极驱动单元的实施例在工作时，在显示周期，VDDo可以为有效电压。
本公开如图6所示的栅极驱动单元的实施例在工作时，在显示周期，VDDo为有效电压，当Q(N)的电位为有效电压时，所述下拉节点控制电路14控制QB(N)的电位为无效电压；当Input输入有效电压时，QB(N)接入VGL；
在空白时间段中的时钟输入阶段，H的电位有效电压，并CLKA为有效 电压，所述下拉节点控制电路14控制QB(N)接入VGL。
具体的，所述下拉节点控制电路可以包括第一下拉控制晶体管、第二下拉控制晶体管、第三下拉控制晶体管、第四下拉控制晶体管和第五下拉控制晶体管，其中，
所述第一下拉控制晶体管的控制极和所述第一下拉控制晶体管的第一极都与所述第一控制电压端连接，所述第一下拉控制晶体管的第二极与下拉节点连接；
所述第二下拉控制晶体管的控制极与所述上拉节点连接，所述第二下拉控制晶体管的第一极与所述下拉节点连接，所述第二下拉控制晶体管的第二极与所述第五电压端连接；
所述第三下拉控制晶体管的控制极与所述第一时钟信号端连接，所述第三下拉控制晶体管的第一极与所述下拉节点连接；
所述第四下拉控制晶体管的控制极与所述第一节点连接，所述第四下拉控制晶体管的第一极与所述第三下拉控制晶体管的第二极连接，所述第四下拉控制晶体管的第二极与所述第五电压端连接；
所述第五下拉控制晶体管的控制极与所述输入端连接，所述第五下拉控制晶体管的第一极与所述下拉节点连接，所述第五下拉控制晶体管的第二极与所述第五电压端连接。
在具体实施时，所述第五电压端可以为第一低电压端，但不以此为限。
如图7所示，在图6所示的栅极驱动单元的实施例的基础上，所述下拉节点控制电路14包括第一下拉控制晶体管M9、第二下拉控制晶体管M10、第三下拉控制晶体管M13、第四下拉控制晶体管M14和第五下拉控制晶体管M15，其中，
所述第一下拉控制晶体管M9的栅极和所述第一下拉控制晶体管M9的漏极都与所述第一控制电压端连接，所述第一下拉控制晶体管M9的源极与下拉节点QB(N)连接；所述第一控制电压端用于输入第一控制电压VDDo；
所述第二下拉控制晶体管M10的栅极与所述上拉节点Q(N)连接，所述第二下拉控制晶体管M10的漏极与所述下拉节点QB(N)连接，所述第二下拉控制晶体管M10的源极接入第一低电压VGL1；
所述第三下拉控制晶体管M13的栅极接入第一时钟信号CLKA，所述第三下拉控制晶体管M13的漏极与所述下拉节点QB(N)连接；
所述第四下拉控制晶体管M14的栅极与所述第一节点H连接，所述第四下拉控制晶体管M14的漏极与所述第三下拉控制晶体管M13的源极连接，所述第四下拉控制晶体管M14的源极接入第一低电压VGL1；
所述第五下拉控制晶体管M15的栅极与所述输入端Input连接，所述第五下拉控制晶体管M15的漏极与所述下拉节点QB(N)连接，所述第五下拉控制晶体管M15的源极接入所述第一低电压VGL1。
在图7所示的实施例中，所有的晶体管都为n型薄膜晶体管，但不以此为限。
本公开如图7所示的实施例在工作时，在显示周期，VDDo可以为高电压，M9打开；
在显示周期包括的输入阶段和输出阶段，Q(N)的电位为高电压，M10打开，以拉低QB(N)的电位；
在显示周期包括的输入阶段，Input输入高电压，M15打开，以控制QB(N)接入VGL1；
在空白时间段包括的时钟输入阶段，H的电位为高电压，CLKA为高电压，M13和M14都打开，以控制QB(N)接入VGL1，拉低QB(N)的电压。
具体的，所述外部补偿控制信号输出电路可以包括第一补偿输出晶体管和第二补偿输出晶体管，其中，
所述第一补偿输出晶体管的控制极与所述上拉节点连接，所述第一补偿输出晶体管的第一极与所述外部补偿时钟信号端连接，所述第一补偿输出晶体管的第二极与所述外部补偿控制信号输出端连接；
所述第二补偿输出晶体管的控制极与所述下拉节点连接，所述第二补偿输出晶体管的第一极与所述外部补偿控制信号输出端连接，所述第二补偿输出晶体管的第二极与所述第一电压端之间连通。
在具体实施时，所述栅极驱动信号输出电路可以包括第一栅极驱动信号输出晶体管和第二栅极驱动信号输出晶体管，其中，
所述第一栅极驱动信号输出晶体管的控制极与所述上拉节点连接，所述第一栅极驱动信号输出晶体管的第一极与栅极驱动输出时钟信号端连接，所述第一栅极驱动信号输出晶体管的第二极与所述栅极驱动信号输出端连接；
所述第二栅极驱动信号输出晶体管的控制极与所述下拉节点连接，所述第二栅极驱动信号输出晶体管的第一极与所述栅极驱动信号输出端连接，所述第二栅极驱动信号输出晶体管的第二极与所述第一电压端连接。
在优选情况下，本公开实施例所述的栅极驱动单元还可以包括进位信号输出端和进位信号输出电路；
所述进位信号输出电路用于在所述上拉节点的电位和所述下拉节点的电位的控制下，控制所述进位信号输出端输出进位信号；
所述本级驱动信号为由所述进位信号输出端提供的进位信号。
本公开实施例优选采用进位信号输出端为相邻下一级栅极驱动单元的输入端提供输入信号，为相邻上一级栅极驱动单元的复位端提供复位信号，以提升栅极驱动信号输出端的驱动能力，此时，本级驱动信号可以为由所述进位信号输出端提供的进位信号。
如图8所示，在图1所示的栅极驱动单元的实施例的基础上，本公开实施例所述的栅极驱动单元还包括进位信号输出端CR(N)和进位信号输出电路16；
所述进位信号输出电路16分别与上拉节点Q(N)、下拉节点QB(N)和进位信号输出端CR(N)连接，用于在所述上拉节点Q(N)的电位和所述下拉节点QB(N)的电位的控制下，控制所述进位信号输出端CR(N)输出进位信号；
并所述上拉控制电路13与CR(N)连接，CR(N)用于向上拉控制电路13提供本级驱动信号。
具体的，所述进位信号输出电路可以包括第一进位信号输出晶体管和第二进位信号输出晶体管；
所述第一进位信号输出晶体管的控制极与所述上拉节点连接，所述第一进位信号输出晶体管的第一极与进位输出时钟信号端连接，所述第一进位信号输出晶体管的第二极与所述进位信号输出端连接；
所述第二进位信号输出晶体管的控制极与所述下拉节点连接，所述第二进位信号输出晶体管的第一极与所述进位信号输出端连接，所述第二进位信号输出晶体管的第二极与第二电压端连接。
在具体实施时，所述进位输出时钟信号端输入的进位输出时钟信号与所述栅极驱动输出时钟信号端输入的栅极驱动输出时钟信号可以相同，但不以此为限。
下面通过一具体实施例来说明本公开所述的栅极驱动单元。
如图9A所示，本公开所述的栅极驱动单元的一具体实施例包括外部补偿控制信号输出端OUT1(N)、栅极驱动信号输出端OUT2(N)、进位信号输出端CR(N)、外部补偿控制信号输出电路11、栅极驱动信号输出电路12、上拉控制电路、下拉节点控制电路14、上拉节点控制电路和进位信号输出电路16，其中，
所述上拉控制电路包括第一节点控制子电路131、第二节点控制子电路132、第三节点控制子电路133、上拉控制节点控制子电路134和上拉控制子电路135，其中，
所述第一节点控制子电路131包括第一控制晶体管M1和储能电容C1；
所述第一控制晶体管M1的栅极接入使能端OE输入的使能信号，所述第一控制晶体管M1的漏极与所述进位信号输出端CR(N)连接，所述第一控制晶体管M1的源极与所述第一节点H连接；
所述储能电容C1的第一端与所述第一节点H连接，所述储能电容C1的第二端与所述上拉控制节点PUCN连接。
所述第二节点控制子电路132包括第二控制晶体管M42；
所述第二控制晶体管M42的栅极和所述第二控制晶体管M42的漏极都接入所述第二时钟信号CLKB，所述第二控制晶体管M42的源极与所述第二节点J连接；
所述第三节点控制子电路133包括第三控制晶体管M43；
所述第三控制晶体管M43的栅极与所述第二节点J连接，所述第三控制晶体管M43的漏极与第三节点M连接，所述第三控制晶体管M43的源极接入第一低电压VGL1；
所述上拉控制节点控制子电路134包括第四控制晶体管M2和第五控制晶体管M4；
所述第四控制晶体管M2的栅极与所述第一节点H连接，所述第四控制晶体管M2的漏极接入所述第一时钟信号CLKA，所述第四控制晶体管M2的源极与所述上拉控制节点PUCN连接；
所述第五控制晶体管M4的栅极与所述下拉节点QB(N)连接，所述第五控制晶体管M4的漏极与所述上拉控制节点PUCN连接，所述第五控制晶体管M44的源极与所述第三节点M连接；
所述上拉控制子电路135包括上拉控制晶体管M5；
所述上拉控制晶体管M5的栅极与所述上拉控制节点PUCN连接，所述上拉控制晶体管M5的漏极与所述上拉节点Q(N)连接，所述上拉控制晶体管M5的源极接入高电压VDD；
所述上拉节点控制电路包括第一上拉节点控制晶体管M6、第二上拉节点控制晶体管M8、第三上拉节点控制晶体管M7、第四上拉节点控制晶体管M12、第一存储电容C2和第二存储电容C3，其中，
所述第一上拉节点控制晶体管M6的栅极与所述输入端Input连接，所述第一上拉节点控制晶体管M6的漏极接入高电压VDD，所述第一上拉节点控制晶体管M6的源极与所述上拉节点Q(N)连接；
所述第二上拉节点控制晶体管M8的栅极与所述复位端Reset连接，所述第二上拉节点控制晶体管M8的漏极与所述上拉节点Q(N)连接，所述第二上拉节点控制晶体管M8的源极接入第一低电压VGL1；
所述第三上拉节点控制晶体管M7的栅极与所述空白区复位端TRST连接，所述第三上拉节点控制晶体管M7的漏极与所述上拉节点Q(N)连接，所述第三上拉节点控制晶体管M7的源极接入第一低电压VGL1；
所述第四上拉节点控制晶体管M12的栅极与所述下拉节点QB(N)连接，所述第四上拉节点控制晶体管M12的漏极与所述上拉节点Q(N)连接，所述第四上拉节点控制晶体管M12的源极接入第一低电压VGL1；
所述第一存储电容C2的第一端与所述上拉节点Q(N)连接，所述第一存储电容C1的第二端与所述外部补偿控制信号输出端OUT1(N)连接；
所述第二存储电容C3的第一端与所述上拉节点Q(N)连接，所述第二存储电容C3的第二端与所述栅极驱动信号输出端OUT2(N)连接；
所述下拉节点控制电路14包括第一下拉控制晶体管M9、第二下拉控制晶体管M10、第三下拉控制晶体管M13、第四下拉控制晶体管M14和第五下拉控制晶体管M15，其中，
所述第一下拉控制晶体管M9的栅极和所述第一下拉控制晶体管M9的漏极都与所述第一控制电压端连接，所述第一下拉控制晶体管M9的源极与所述下拉节点QB(N)连接；所述第一控制电压端用于输入第一控制电压VDDo；
所述第二下拉控制晶体管M10的栅极与所述上拉节点Q(N)连接，所述第二下拉控制晶体管M10的漏极与所述下拉节点QB(N)连接，所述第二下拉控制晶体管M10的源极接入第一低电压VGL1；
所述第三下拉控制晶体管M13的栅极接入第一时钟信号CLKA，所述第三下拉控制晶体管M13的漏极与所述下拉节点QB(N)连接；
所述第四下拉控制晶体管M14的栅极与所述第一节点H连接，所述第四下拉控制晶体管M14的漏极与所述第三下拉控制晶体管M13的源极连接，所述第四下拉控制晶体管M14的第二极接入第一低电压VGL1；
所述第五下拉控制晶体管M15的栅极与所述输入端Input连接，所述第五下拉控制晶体管M15的漏极与所述下拉节点QB(N)连接，所述第五下拉控制晶体管M15的源极接入所述第一低电压VGL1；
所述外部补偿控制信号输出电路11包括第一补偿输出晶体管M19和第二补偿输出晶体管M20，其中，
所述第一补偿输出晶体管M19的栅极与所述上拉节点Q(N)连接，所述第一补偿输出晶体管M19的漏极接入外部补偿时钟信号CLKE_N，所述第一补偿输出晶体管M19的源极与所述外部补偿控制信号输出端OUT1(N)连接；
所述第二补偿输出晶体管M20的栅极与所述下拉节点QB(N)连接，所述第二补偿输出晶体管M20的漏极与所述外部补偿控制信号输出端OUT1(N)连接，所述第二补偿输出晶体管M20的源极接入第二低电压VGL2；
所述栅极驱动信号输出电路12包括第一栅极驱动信号输出晶体管M22和第二栅极驱动信号输出晶体管M23，其中，
所述第一栅极驱动信号输出晶体管M22的栅极与所述上拉节点Q(N)连接，所述第一栅极驱动信号输出晶体管M22的漏极接入外部补偿时钟信号CLKE_N，所述第一栅极驱动信号输出晶体管M22的源极与所述栅极驱动信号输出端OUT2(N)连接；
所述第二栅极驱动信号输出晶体管M23的栅极与所述下拉节点QB(N)连接，所述第二栅极驱动信号输出晶体管M23的漏极与所述栅极驱动信号输出端OUT2(N)连接，所述第二栅极驱动信号输出晶体管M23的源极接入第二低电压VGL2；
所述进位信号输出电路16包括第一进位信号输出晶体管M16和第二进位信号输出晶体管M17；
所述第一进位信号输出晶体管M16的栅极与所述上拉节点Q(N)连接，所述第一进位信号输出晶体管M16的漏极接入进位输出时钟信号CLKD_N，所述第一进位信号输出晶体管M16的源极与所述进位信号输出端CR(N)连接；
所述第二进位信号输出晶体管M17的栅极与所述下拉节点QB(N)连接，所述第二进位信号输出晶体管M17的漏极与所述进位信号输出端CR(N)连接，所述第二进位信号输出晶体管M17的源极接入第一低电压VGL1。
在图9A所示的栅极驱动单元的具体实施例中，所述输入端Input可以与第N-2级进位信号输出端CR(N-2)连接，所述复位端Reset可以与第N+4级进位信号输出端CR(N+4)连接，但不以此为限。
在图9A所示的栅极驱动单元的具体实施例中，所有的晶体管都为n型薄膜晶体管，但不以此为限。
如图9B所示，在本公开所述的栅极驱动单元的另一具体实施例中，在本公开如图9A所示的栅极驱动单元的具体实施例的基础上，所述第二节点控制子电路132还包括第二节点控制晶体管M44；
M44的栅极与第一时钟信号端连接(M44的栅极接入第一时钟信号CLKA)，M44的漏极与第二节点J连接，M44的源极接入第一低电压VGL1。
在图9B所示的栅极驱动单元的另一具体实施例中，M44为n型薄膜晶体管，但不与以此为限。
在本公开所述的栅极驱动单元的另一具体实施例工作时，当CLKA为高电平时，M44打开，以控制第二节点J接入VGL1；当CLKA为低电平时，M44关断。
如图10所示，本公开如图9A所示的栅极驱动单元的具体实施例在工作时，显示周期TD包括输入阶段td1、输出阶段td2、复位阶段td3和输出截止保持阶段td4，空白时间段TB包括时钟输入阶段tb1、外部补偿控制信号输出阶段tb2和空白区复位阶段tb3；
在显示周期TD包括的输入阶段td1，Input输入高电压，Reset输入低电压，CLKB为高电压，CLKA为低电压，CLKD_N、CLKE_N和CLKF_N都为低电压，M6打开，Q(N)接入VDD，M10打开，以将QB(N)的电位拉低，M16、M19和M22都打开，CR(N)、OUT1(N)和OUT2(N)都输出低电平；M15打开，以控制QB(N)接入VGL1；
在显示周期TD包括的输出阶段td2，Input和Reset都输入低电压，CLKB为高电压，CLKA为低电压，CLKD_N、CLKE_N和CLKF_N都为高电压，C2和C3自举拉升Q(N)的电位，M16、M19和M22都打开，CR(N)、OUT1(N)和OUT2(N)都输出高电平；并此时OE输入高电平，M1打开，以使得H的电位为高电压，M2打开，PUCN接入CLKA，以使得PUCN的电位为低电压；并M42打开，以使得M43的栅极的电位为高电平，M43打开；此时QB(N)的电位为低电压，M4关断；
在输出阶段td2与复位阶段td3之间的保持阶段，Q(N)的电位维持为高电压，CLKD_N、CLKE_N和CLKF_N都为低电压，M16、M19和M22都打开，CR(N)、OUT1(N)和OUT2(N)都输出低电平；
在显示周期TD包括的复位阶段td3，CLKB为高电压，CLKA为低电压，Input输入低电压，Reset输入高电压，M8打开，以将Q(N)的电位拉低，M10关断，QB(N)的电位为高电压；M4打开，M42打开，M43打开，从而使得PUCN接入VGL1，M2打开，以使得PUCN的电位为低电平，M5关断；M17、M20和M23都打开，以控制CR(N)、OUT1(N)和OUT2(N) 都输出低电平；
在显示周期TD包括的输出截止保持节点td4，CLKB为高电压，CLKA为低电压，Input输入低电压，Reset输入低电压，QB(N)的电位为高电压，Q(N)的电位为低电压，M10关断，M4打开，M42打开，M43打开，从而使得PUCN接入VGL1，M2打开，以使得PUCN的电位为低电平，M5关断；M17、M20和M23都打开，以控制CR(N)、OUT1(N)和OUT2(N)都输出低电平；
在空白时间段TB包括的时钟输入阶段tb1，CLKA为高电压，CLKB为低电压，OE输入高电压，M1打开，以控制H的电位为高电压，C1维持H的电位，M2打开，PUCN的电位为高电压，M5打开，Q(N)的电位为高电压，QB(N)的电位为低电压，M42和M4都关断；此时CLKD_N、CLKE_N和CLKF_N都为低电压，M16、M19和M22都打开，CR(N)、OUT1(N)和OUT2(N)都输出低电平；
在空白时间段TB包括的外部补偿控制信号输出阶段td2，OE输入低电平，M1关断，C1控制H的电位为高电平，M2打开，CLKB输入高电压，CLKA输入低电压，PUCN的电位为低电压，C2和C3维持Q(N)的电位，CLKD_N和CLKF_N都为低电压，CLKE_N为高电压，M16、M19和M22都打开，OUT1(N)输出高电压，CR(N)和OUT(2)都输出低电压；
在空白时间段包括的空白区复位阶段td3，OE输入高电压，TRST输入高电压，M1打开，CR(N)输入低电压，以将H的电位拉低，M7打开，以将Q(N)的电位拉低，以控制M16、M19和M22都关断。
本公开所述的栅极驱动单元的该具体实施例在工作时，在显示周期中的输出阶段，在CR(N)输出高电压时，OE也输入高电压，以对第一节点H充电，在显示周期的输出阶段、复位阶段和输出截止保持阶段，OE输入低电位，H的高电位会一直保持到空白时间段；在显示周期，M5一直处于关断状态。隔离了Sense(检测)预存电压点(所述Sense预存电压端即为第一节点H)对于显示的影响。Q(N)的电位呈现塔状波形，采用同一大尺寸的驱动晶体管(M16)形成CR输出的进位信号的上升沿和下降沿，并采用同一大尺寸的驱动晶体管(M22)形成OUT2(N)输出的栅极驱动信号的上升沿和 下降沿，大大减小了版图的面积。
在图9A、图9B中，所有电容可以为TFT(薄膜晶体管)的寄生电容，也可以为外接电容。
本公开实施例所述的栅极驱动方法应用于上述的栅极驱动单元，在两显示周期之间设置有空白时间段，所述栅极驱动方法包括：
在显示周期，上拉控制电路在使能端输入的使能信号和本级驱动信号的控制下，控制第一节点的电位为有效电压，并维持所述第一节点的电位为有效电压；所述上拉控制电路在所述第一节点的电位、第一时钟信号端输入的第一时钟信号、第二时钟信号端输入的第二时钟信号和所述下拉节点的电位的控制下，控制上拉控制节点的电位为无效电压；
在设置于该显示周期之后的空白时间段中的预定时间，所述上拉控制电路维持所述第一节点的电位为有效电压，所述上拉控制电路在所述第一节点的电位和第一时钟信号端输入的第一时钟信号的控制下，控制上拉控制节点的电位，并在所述上拉控制节点的电位的控制下，控制上拉节点的电位为有效电压；外部补偿控制信号输出电路在所述上拉节点的电位的控制下，控制外部补偿控制信号输出端与外部补偿时钟信号端之间连通。
本公开实施例所述的栅极驱动方法能够同时输出栅极驱动信号和外部补偿控制信号，同时采用本公开实施例所述的栅极驱动方法可以进行随机补偿，通过采用随机补偿的功能，消除扫面线以及面板的亮度偏差。
具体的，所述上拉控制电路包括第一节点控制子电路、第二节点控制子电路、第三节点控制子电路、上拉控制节点控制子电路和上拉控制子电路；在显示周期，第一时钟信号端输入无效电压，第二时钟信号端输入有效电压；所述预定时间段包括依次设置的时钟输入阶段和外部补偿输出阶段；所述栅极驱动方法包括：
在显示周期包括的输出阶段，使能端输入有效电压，本级驱动信号为有效电压，第一节点控制子电路控制第一节点接入所述本级驱动信号；上拉控制节点控制子电路控制所述上拉控制节点与所述第一时钟信号端之间连通；上拉控制子电路控制断开上拉节点与第三电压端之间的连接；
在所述显示周期包括的复位阶段和输出截止保持阶段，使能端输入无效 电压，下拉节点的电位为有效电压，第一节点控制子电路维持所述第一节点的电位；第二节点控制子电路控制第二节点的电位为有效电压，第三节点控制子电路控制第三节点与第二电压端之间连通；上拉控制节点控制子电路控制所述上拉控制节点与所述第一时钟信号端之间连通，并控制上拉控制节点与第三节点之间连通；上拉控制子电路控制断开上拉节点与第三电压端之间的连接；
在设置于所述显示周期之后的空白时间段中的时钟输入阶段和外部补偿输出阶段，第一节点控制子电路维持所述第一节点的电位；
在该时钟输入阶段，所述第一时钟信号端输入有效电压，所述第二时钟信号端输入无效电压，上拉控制节点控制子电路控制所述上拉控制节点与所述第一时钟信号端之间连通，上拉控制子电路控制上拉节点与第三电压端之间连通，以控制上拉节点的电位为有效电压；
在该外部补偿输出阶段，所述第一时钟信号端输入有效电压，所述第二时钟信号端输入无效电压，第一节点控制子电路维持第一节点的电位为有效电压，上拉控制节点控制子电路控制上拉控制节点与所述第一时钟信号端之间连通，上拉控制子电路断开所述上拉节点与第三电压端之间的连接，使得上拉节点的电维持为有效电压；外部补偿时钟信号端输入有效电压，外部补偿控制信号输出电路控制外部补偿控制信号输出端与所述外部补偿时钟信号端之间连通。
具体的，所述空白时间段还可以包括设置于所述预定时间段之后的空白区复位阶段；所述栅极驱动方法还可以包括：
在该空白区复位阶段，使能端输入有效电压，本级驱动信号为无效电压，第一节点控制子电路控制第一节点接入所述本级驱动信号，以对第一节点的电位进行复位。
在具体实施时，所述栅极驱动单元还包括上拉节点控制电路；所述栅极驱动方法还包括：
在所述空白区复位阶段，空白区复位端输入有效电压，以对所述上拉节点的电位进行复位。
本公开实施例所述的栅极驱动模组包括上述的栅极驱动单元；所述栅极 驱动单元为第N级栅极驱动单元；N为正整数；所述栅极驱动模组还包括第N+1级栅极驱动单元；
第N+1级栅极驱动单元中的上拉节点为第N+1上拉节点，第N+1级栅极驱动单元中的下拉节点为第N+1下拉节点，第N+1级栅极驱动单元中的上拉控制节点为所述第N级栅极驱动单元中的上拉控制节点；
所述第N+1级栅极驱动单元包括第N+1级上拉控制电路、第N+1级外部补偿控制信号输出端、第N+1级栅极驱动信号输出端、第N+1外部补偿控制信号输出电路、第N+1栅极驱动信号输出电路和第N+1下拉节点控制电路；
所述第N+1上拉控制电路与所述第N上拉控制节点连接，用于在该第N上拉控制节点的电位的控制下，控制第N+1上拉节点与第三电压端之间连接；
所述第N+1下拉节点控制电路用于控制第N+1下拉节点的电位；
所述第N+1外部补偿控制信号输出电路用于在该第N+1上拉节点的电位的控制下，控制所述第N+1级外部补偿控制信号输出端与第二外部补偿时钟信号端之间连通，在该第N+1下拉节点的电位的控制下，控制所述外部补偿控制信号输出端与所述第一电压端之间连通；
所述第N+1栅极驱动信号输出电路用于在该第N+1上拉节点的电位和该第N+1下拉节点的电位的控制下，控制所述第N+1级栅极驱动信号输出端输出栅极驱动信号。
在本公开实施例所述的栅极驱动模组中，所述第N+1级栅极驱动单元中的上拉控制电路(也即第N+1上拉控制电路)与第N上拉控制节点连接，在第N上拉控制节点的电位的控制下，控制第N+1上拉节点的电位，也即第N+1上拉控制电路不包含第一节点控制子电路、第二节点控制子电路、第三节点控制子电路和上拉控制节点控制子电路，该第N+1上拉控制电路仅包括上拉控制子电路，并第N+1级栅极驱动单元不采用进位信号输出电路和相应级进位信号输出端，因而在能够简化栅极驱动模组的结构，依然能够实现第N+1级栅极驱动单元正常输出第N+1栅极驱动信号和第N+1外部补偿控制信号。
在本公开实施例中，所述第一电压端可以为低电压端，所述第三电压端可以为高电压端，但不以此为限。
如图11所示，本公开实施例所述的栅极驱动模组包括本公开如图8所示的栅极驱动单元的实施例；该栅极驱动单元为第N级栅极驱动单元SN；N为正整数；所述栅极驱动模组还包括第N+1级栅极驱动单元SN+1；
第N+1级栅极驱动单元SN+1中的上拉节点为第N+1上拉节点Q(N+1)，第N+1级栅极驱动单元中的下拉节点为第N+1下拉节点QB(N+1)，第N+1级栅极驱动单元中的上拉控制节点为所述第N级栅极驱动单元中的上拉控制节点PUCN；该上拉控制节点PUCN为第N上拉控制节点；
所述第N+1级栅极驱动单元SN+1包括第N+1上拉控制电路23、第N+1级外部补偿控制信号输出端OUT1(N+1)、第N+1级栅极驱动信号输出端OUT2(N+1)、第N+1外部补偿控制信号输出电路21、第N+1栅极驱动信号输出电路22和第N+1下拉节点控制电路24；
所述第N+1上拉控制电路23与所述第N上拉控制节点PUCN连接，用于在该第N上拉控制节点PUCN的电位的控制下，控制第N+1上拉节点Q(N+1)与高电压端之间连接；所述高电压端用于输入高电压VDD；
所述第N+1下拉节点控制电路24用于控制第N+1下拉节点QB(N+1)的电位；
所述第N+1外部补偿控制信号输出电路21用于在该第N+1上拉节点的电位的控制下，控制所述第N+1级外部补偿控制信号输出端OUT1(N+1)与第二外部补偿时钟信号端CLKE_N+1之间连通，在该第N+1下拉节点QB(N+1)的电位的控制下，控制所述外部补偿控制信号输出端OUT1(N+1)与所述第一电压端之间连通；所述第一电压端用于输入第一电压V1；
所述第N+1栅极驱动信号输出电路22用于在该第N+1上拉节点Q(N+1)的电位和该第N+1下拉节点QB(N+1)的电位的控制下，控制所述第N+1级栅极驱动信号输出端OUT2(N+1)输出栅极驱动信号。
在本公开实施例所述的栅极驱动模组中，所述第N+1级栅极驱动单元SN+1中的上拉控制电路(也即第N+1上拉控制电路)与第N上拉控制节点连接，在第N上拉控制节点的电位的控制下，控制第N+1上拉节点Q(N+1)的电位，也即第N+1上拉控制电路不包含第一节点控制子电路131、第二节点控制子电路132、第三节点控制子电路133、上拉控制节点控制子电路134， 该第N+1上拉控制电路仅包括上拉控制子电路135，并第N+1级栅极驱动单元SN+1不采用进位信号输出电路和相应级进位信号输出端，因而在能够简化栅极驱动模组的结构，依然能够实现第N+1级栅极驱动单元SN+1正常输出第N+1栅极驱动信号和第N+1外部补偿控制信号。
本公开如图11所示的栅极驱动模组的实施例在工作时，当需要对第N+1行像素电路进行外部补偿时，则在显示周期的第N输出阶段，控制与第N栅极驱动单元连接的使能端输入有效电压，从而能够在空白时间段中的时钟输入阶段，控制PUCN的电位为有效电压，从而控制Q(N+1)的电位为有效电压，并使得在空白时间段中的外部补偿输出阶段，控制Q(N+1)的电位保持为有效电压，此时CLKE_2输入有效电压，则第N+1级栅极驱动单元中的第N+1级外部控制信号输出端OUT1(N+1)输出有效电压。
具体的，所述第N+1级栅极驱动单元还包括第N+1上拉节点控制电路；
所述第N+1上拉节点控制电路分别与输入端、复位端、所述第N+1上拉节点、所述第N+1下拉节点、空白区复位端、第三电压端和第四电压端连接，用于在所述输入端输入的输入信号的控制下，控制所述第N+1上拉节点与所述第三电压端之间连通，在所述复位端输入的复位信号的控制下，控制所述第N+1上拉节点与所述第四电压端之间连通，在所述空白区复位端输入的空白区复位信号的控制下，控制所述第N+1上拉节点与所述第四电压端之间连通，在所述第N+1下拉节点的电位的控制下，控制所述第N+1上拉节点与所述第四电压端之间连通，并用于维持所述第N+1上拉节点的电位。
在具体实施时，与所述第N+1上拉节点控制电路连接的输入端也即与第N上拉节点控制电路连接的输入端，与所述第N+1上拉节点控制电路连接的输入端也即与第N上拉节点控制电路连接的输出端，也即第N上拉节点控制电路和第N+1上拉节点控制电路共用一输入端，并第N上拉节点控制电路和第N+1上拉节点控制电路共用一复位端。
在具体实施时，所述第N级栅极驱动单元中的上拉控制电路为第N上拉控制电路；所述N上拉控制电路包括第一节点控制子电路、第二节点控制子电路、第三节点控制子电路、上拉控制节点控制子电路和上拉控制子电路；
所述第N+1下拉节点控制电路分别与第二控制电压端、所述第N+1上拉 节点、所述第N+1下拉节点、所述第N级栅极驱动单元中的第一节点、第一时钟信号端、复位端和第五电压端连接，用于在所述第二控制电压输入的第二控制电压和所述N+1上拉节点的电位的控制下，控制所述第N+1下拉节点的电位，并在所述第一节点的电位与所述第一时钟信号端输入的第一时钟信号的控制下，控制所述N+1下拉节点与所述第五电压端之间连通，在输入端输入的输入信号的控制下，控制所述下拉节点与所述第五电压端之间连通。
在具体实施时，与所述第N+1下拉节点控制电路连接的第一节点也即与第N下拉节点控制电路连接的第一节点，第N上拉节点控制电路和第N+1上拉节点控制电路共用一第一节点。
具体的，所述第N级栅极驱动单元中的外部补偿控制信号输出电路为第N外部补偿控制信号输出电路，所述第N级栅极驱动单元中的栅极驱动信号输出电路为第N栅极驱动信号输出电路；所述第N级栅极驱动单元中的外部补偿控制信号输出端为第N级外部补偿控制信号输出端，所述第N级栅极驱动单元中的栅极驱动信号输出端为第N级栅极驱动信号输出端；所述第N级栅极驱动单元中的上拉节点为第N上拉节点，所述第N级栅极驱动单元中的下拉节点为第N下拉节点；
所述第N外部补偿控制信号输出电路还与所述第N+1下拉节点连接，用于在第N+1下拉节点的电位的控制下，对第N级外部补偿控制信号输出端进行复位；
所述第N栅极驱动信号输出电路还与所述第N+1下拉节点连接，用于在第N+1下拉节点的电位的控制下，对第N级栅极驱动信号输出端进行复位；
所述第N+1外部补偿控制信号输出电路还与所述第N下拉节点连接，用于在第N下拉节点的电位的控制下，对第N+1级外部补偿控制信号输出端进行复位；
所述第N+1栅极驱动信号输出电路还与所述第N下拉节点连接，用于在第N下拉节点的电位的控制下，对第N+1级栅极驱动信号输出端进行复位。
在具体实施时，本公开实施例所述的栅极驱动单元可以为本公开实施例所述的栅极驱动模组中的第一级栅极驱动单元，为本公开实施例所述的栅极驱动模组中的N级栅极驱动单元，本公开实施例所述的栅极驱动模组包括的 第二级栅极驱动单元也即本公开实施例所述的栅极驱动电路中的第N+1级栅极驱动单元，该第N+1级栅极驱动单元不包括进位信号输出端和进位信号输出电路，并该第N+1级栅极驱动单元中的上拉节点控制电路仅包含上拉节点控制子电路，该第N+1上拉节点控制子电路与该第N级栅极驱动单元中的上拉控制节点N连接，用于在该上拉控制节点N的电位的控制下，控制该第N+1级栅极驱动单元中的上拉节点的电位；并第N+1级栅极驱动单元中的输入端与该第N级栅极驱动单元中的输入端连接，第N+1级栅极驱动单元中的复位端与该第N级栅极驱动单元中的复位端连接。
并且，所述第N级栅极驱动单元中的下拉节点可以为第一下拉节点，该第一下拉节点受该第N级栅极驱动单元中的上拉节点Q(N)和第一控制电压VDDo的控制，所述第N+1级栅极驱动单元中的下拉节点可以为第二下拉节点，该第二下拉节点受该第N+1级栅极驱动单元中的上拉节点和第二控制电压的控制。在本公开实施例所述的栅极驱动模组中，第N+1级栅极驱动单元中的进位信号输出电路可以还与该第二下拉节点连接，在该第二下拉节点的电位的控制下，对进位信号进行复位；第N+1级栅极驱动单元中的外部补偿控制信号输出电路可以还与该第二下拉节点连接，在该第二下拉节点的电位的控制下，对外部补偿控制信号进行复位；栅极驱动单元中的栅极驱动信号输出电路可以还与该第二下拉节点连接，在该第二下拉节点的电位的控制下，对栅极驱动信号进行复位；第N+1级栅极驱动单元中的外部补偿控制信号输出电路可以同时与该第一下拉节点和该第二下拉节点连接，在该第一下拉节点的电位和该第二下拉节点的电位的控制下，对外部补偿控制信号进行复位；栅极驱动单元中的栅极驱动信号输出电路可以还与该第二下拉节点连接，在该第一下拉节点的电位和该第二下拉节点的电位的控制下，对栅极驱动信号进行复位。
在具体实施时，显示时间可以包括多个显示时间段，所述显示时间段包括依次设置的第一电压提供阶段和第二电压提供阶段，在第一电压提供阶段，第一控制电压为高电压，第二控制电压为低电压，在第二电压提供阶段，第一控制电压为低电压，第二控制电压为高电压。通过如上电压设置，第一下拉节点的电位、第二下拉节点的电位交替为有效电压，从而可改善栅极与该 第一下拉节点连接的晶体管的阈值电压漂移，以及栅极与该第二下拉节点连接的晶体管的阈值电压漂移，也可以改善栅极与第一控制电压端连接的晶体管的阈值电压漂移，并改善栅极与第二控制电压端连接的晶体管的阈值电压漂移。
如图12所示，在图11所示的栅极驱动模组的实施例的基础上，
所述第N级栅极驱动单元SN中的外部补偿控制信号输出电路11为第N外部补偿控制信号输出电路，所述第N级栅极驱动单元SN中的栅极驱动信号输出电路12为第N栅极驱动信号输出电路，所述第N级栅极驱动单元SN中的进位信号输出电路16为第N进位信号输出电路；所述第N级栅极驱动单元SN中的外部补偿控制信号输出端OUT1(N)为第N级外部补偿控制信号输出端，所述第N级栅极驱动单元SN中的栅极驱动信号输出端OUT2(N)为第N级栅极驱动信号输出端；所述第N级栅极驱动单元SN中的上拉节点Q(N)为第N上拉节点，所述第N级栅极驱动单元SN中的下拉节点QB(N)为第N下拉节点；
所述第N外部补偿控制信号输出电路11还与所述第N+1下拉节点QB(N+1)连接，用于在第N+1下拉节点QB(N+1)的电位的控制下，对第N级外部补偿控制信号输出端OUT1(N)进行复位；
所述第N栅极驱动信号输出电路12还与所述第N+1下拉节点QB(N+1)连接，用于在第N+1下拉节点QB(N+1)的电位的控制下，对第N级栅极驱动信号输出端OUT2(N)进行复位；
所述第N进位信号输出电路16还与所述第N+1下拉节点QB(N+1)连接，用于在第N+1下拉节点QB(N+1)的电位的控制下，对第N级进位信号输出端CR(N)进行复位；
所述第N+1外部补偿控制信号输出电路21还与所述第N下拉节点QB(N)连接，用于在第N下拉节点Q(N)的电位的控制下，对第N+1级外部补偿控制信号输出端OUT1(N)进行复位；
所述第N+1栅极驱动信号输出电路22还与所述第N下拉节点QB(N)连接，用于在第N下拉节点QB(N)的电位的控制下，对第N+1级栅极驱动信号输出端OUT2(N)进行复位。
在优选情况下，SN也与QB(N+1)连接，SN+1也与QB(N)连接，也即第N外部补偿控制信号输出电路11在QB(N)的电位和QB(N+1)的电位的控制下，对OUT1(N)进行复位，第N栅极驱动信号输出电路12在QB(N)的电位和QB(N+1)的电位的控制下，对OUT2(N)进行复位，第N+1外部补偿控制信号输出电路21在QB(N)的电位和QB(N+1)的电位的控制下，对OUT1(N+1)进行复位，第N+1栅极驱动信号输出电路22在QB(N)的电位和QB(N+1)的电位的控制下，对OUT2(N+1)进行复位。并且控制QB(N)的电位和QB(N+1)的电位反相，也即，当QB(N)的电位为有效电压时，QB(N+1)的电位为无效电压；当QB(N+1)的电位为有效电压时，QB(N)的电位为无效电压；从而能够改善栅极与QB(N)连接的晶体管和栅极的阈值电压漂移与QB(N+1)连接的晶体管的阈值电压漂移。
如图13所示，本公开实施例所述的栅极驱动模组包括第N级栅极驱动单元SN和第N+1级栅极驱动单元SN+1；
所述第N级栅极驱动单元SN包括如图9A所示的栅极驱动单元的具体实施例以及第一复位电路；图9A中的下拉节点QB(N)为第N下拉节点；
所述第一复位电路包括第一复位晶体管M18、第二复位晶体管M21、第三复位晶体管M24和第四复位晶体管M11；
所述第N+1级栅极驱动单元SN+1包括第N+1级外部补偿控制信号输出端OUT1(N+1)、第N+1级栅极驱动信号输出端OUT2(N+1)、第N+1外部补偿控制信号输出电路、第N+1栅极驱动信号输出电路、第N+1上拉控制电路23、第N+1下拉节点控制电路和第N+1上拉节点控制电路；
所述第N+1上拉控制电路23包括第N+1上拉控制晶体管M25；
M25的栅极与上拉控制节点PUCN连接，M25的漏极接入高电压VDD，M25的源极与第N+1下拉节点Q(N+1)连接；
所述第N+1上拉节点控制电路包括第五上拉节点控制晶体管M26、第六上拉节点控制晶体管M28、第七上拉节点控制晶体管M27、第八上拉节点控制晶体管M32、第九上拉节点控制晶体管M31、第三存储电容C4和第四存储电容C5，其中，
M26的栅极与所述输入端Reset连接，M26的漏极接入高电压VDD，M26的源极与第N+1上拉节点Q(N+1)连接；
M28的栅极与所述复位端Reset连接，M28的漏极与Q(N+1)连接，M28的源极接入第一低电压VGL1；
M27的栅极与所述空白区复位端TRST连接，M27的漏极与Q(N+1)连接，M7的源极接入第一低电压VGL1；
M32的栅极与第N+1下拉节点QB(N+1)连接，M32的漏极与Q(N+1)连接，M12的源极接入第一低电压VGL1；
M31的栅极与QB(N)连接，M32的漏极与Q(N+1)连接，M12的源极接入第一低电压VGL1；
C4的第一端与Q(N+1)连接，C4的第二端与OUT1(N+1)连接；
C5的第一端与Q(N+1)连接，C5的第二端与OUT2(N+1)连接；
第N+1下拉节点控制电路包括第六下拉控制晶体管M29、第七下拉控制晶体管M30、第八下拉控制晶体管M33、第九下拉控制晶体管M34、第十下拉控制晶体管M35，其中，
M29的栅极和M29的漏极都与第二控制电压端连接，M29的源极与第N+1下拉节点QB(N+1)连接；所述第二控制电压端用于输入第二控制电压VDDe；
M30的栅极与Q(N+1)连接，M30的漏极与QB(N+1)连接，M30的源极接入第一低电压VGL1；
M33的栅极接入第一时钟信号CLKA，M33的漏极与QB(N+1)连接；
M34的栅极与所述第一节点H连接，M34的漏极与M33的源极连接，M34的第二极接入第一低电压VGL1；
M35的栅极与所述输入端Input连接，M35的漏极与QB(N+1)连接，M35的源极接入所述第一低电压VGL1；
所述第N+1外部补偿控制信号输出电路包括第三补偿输出晶体管M36、第四补偿输出晶体管M37和第五补偿输出晶体管M38，其中，
M36的栅极与Q(N+1)连接，M36的漏极接入第N+1外部补偿时钟信号CLKE_N+1，M36的源极与OUT1(N+1)连接；
M37的栅极与所述下拉节点QB(N+1)连接，M37的漏极与OUT1(N+1)连接，M37的源极接入第二低电压VGL2；
M38的栅极与所述下拉节点QB(N)连接，M38的漏极与OUT1(N+1)连接，M38的源极接入第二低电压VGL2；
所述栅极驱动信号输出电路包括第三栅极驱动信号输出晶体管M39、第四栅极驱动信号输出晶体管M40和第五栅极驱动信号输出晶体管M41，其中，
M39的栅极与Q(N+1)连接，M39的漏极接入第N+1栅极驱动输出时钟信号CLKF_N，M39的源极与OUT2(N+1)连接；
M40的栅极与QB(N+1)连接，M40的漏极与OUT2(N+1)连接，M40的源极接入第二低电压VGL2；
M18的栅极与QB(N+1)连接，M18的漏极与CR(N)连接，M18的源极接入VGL1；
M21的栅极与QB(N+1)连接，M21的漏极与OUT1(N)连接，M21的源极接入VGL2；
M24的栅极与QB(N+1)连接，M24的漏极与OUT2(N)连接，M21的源极接入VGL2；
M11的栅极与QB(N+1)连接，M11的漏极与Q(N)连接，M11的源极接入VGL1。
在图13所示的具体实施例中，Input与第N-2级栅极驱动单元的进位信号输出端CR(N-2)连接，Reset与第N+4级栅极驱动单元的进位信号输出端CR(N+4)连接。
在图13所示的具体实施例中，所有晶体管都为n型薄膜晶体管，但不以此为限。
在图13所示的具体实施例中，N等于5，也即SN为第五级栅极驱动单元，SN+1为第六级栅极驱动单元。
图14是本公开如图13所示的栅极驱动模组的具体实施例的工作时序图。
在图14中，标号为TD的为显示周期，标号为td2的为输出时间段，在该输出时间段td2第五级栅极驱动单元输出的外部补偿控制信号为高电压，也即OUT1(5)输出高电压；在图14中，标号为TB的为空白时间段。
在图14中，标号为CLKD_1的为第一进位输出时钟信号，标号为CLKD_3的为第三进位输出时钟信号，标号为CLKD_5的为第五进位输出时钟信号，标号为CLKE_1的为第一外部补偿时钟信号，标号为CLKE_2的为第二外部补偿时钟信号，标号为CLKE_3的为第三外部补偿时钟信号，标号为CLKE_4的为第四外部补偿时钟信号，标号为CLKE_5的为第五外部补偿时钟信号，标号为CLKE_6的为第六外部补偿时钟信号，标号为H(5)的为第五级栅极驱动单元中的第一节点，标号为PUCN(5)的为第五级栅极驱动单元中的上拉控制节点，标号为Q(1)的为第一级栅极驱动单元中的上拉节点，标号为Q(2)的为第二级栅极驱动单元中的上拉节点，标号为Q(5)的为第五级栅极驱动单元中的上拉节点，标号为Q(6)的为第六级栅极驱动单元中的上拉节点，标号为OUT1(1)的为第一级外部补偿控制信号输出端，标号为OUT1(2)的为第二级外部补偿控制信号输出端，标号为OUT1(3)的为第三级外部补偿控制信号输出端，标号为OUT1(4)的为第四级外部补偿控制信号输出端，标号为OUT1(5)的为第五级外部补偿控制信号输出端，标号为OUT1(6)的为第六级外部补偿控制信号输出端。
如图14所示，在显示周期，CLKE_1的周期、CLKE_2的周期、CLKE_3的周期、CLKE_4的周期、CLKE_5的周期和CLKE_6的周期可以都为T，但不以此为限；
CLKE_1的占空比、CLKE_2的占空比、CLKE_3的占空比、CLKE_4的占空比、CLKE_5的占空比和CLKE_6的占空比可以都为1/3，但不以此为限；
CLKE_2比CLK3_1延迟T/6，CLKE_3比CLK3_2延迟T/6，CLKE_4比CLK3_3延迟T/6，CLKE_5比CLK3_4延迟T/6，CLKE_6比CLK3_5延迟T/6，但不以此为限。
在本公开实施例中，STV为输入至栅极驱动电路包括的第一级栅极驱动单元的输入端的起始信号；CLKA、CLKB、CLKD_N、CLKE_N和CLKF_N为外部控制的时钟信号；VDDo和VDDe为低频时钟信号，其中，以上所有信号的信号脉宽关系可调；
并且，在本公开实施例中，第一外部补偿时钟信号CLKE_1与第6a-5级栅极驱动单元连接，第二外部补偿时钟信号CLKE_2与第6a-4级栅极驱动单 元连接，第三外部补偿时钟信号CLKE_3与第6a-3级栅极驱动单元连接，第四外部补偿时钟信号CLKE_4与第6a-2级栅极驱动单元连接，第五外部补偿时钟信号CLKE_5与第6a-1级栅极驱动单元连接，第六外部补偿时钟信号CLKE_6与第6a级栅极驱动单元连接，其中，a为正整数；
在本公开实施例中，OE输入的使能信号是OE为外部电路产生的随机信号。
在本公开实施例中，VGL1<VGL2，即VGL2的电位高于VGL1的电位(在一般情况下，VGL1和VGL2都为负电压)，VGL1和VGL2为直流低电压信号，其值可以相同也可以不同，VDD为直流高电压信号。
本公开实施例所述的栅极驱动电路包括多级上述的栅极驱动模组。
具体的，第n级栅极驱动模组可以包括第N级栅极驱动单元和第N+1级栅极驱动单元；
在所述第n级栅极驱动模组中，输入端与第N-2级栅极驱动信号输出端连接，复位端与第N+4级栅极驱动信号输出端连接；n为正整数。
本公开实施例所述的栅极驱动电路在工作时，当需要对某一行像素驱动电路进行外部补偿时，则在显示周期的相应行输出阶段(在该相应行输出阶段，相应级栅极驱动信号输出端输出有效电压)，控制该栅极驱动电路包括的相应级栅极驱动单元中的使能端输入有效电压，即可使得在空白时间段相应级栅极驱动单元中的外部补偿控制信号输出端输出有效电压，从而可以实现随机补偿。
在具体实施时，可以在观察到显示面板出现显示不良时对相应级栅极驱动单元进行随机补偿，以避免逐行补偿引起的扫面线以及显示面板的亮度偏差现象。
具体的，第n级栅极驱动模组包括第N级栅极驱动单元和第N+1级栅极驱动单元；所述第N级栅极驱动单元可以包括进位信号输出端和进位信号输出电路；
在所述第n级栅极驱动模组中，输入端与第N-2级进位信号输出端连接，复位端与第N+4级进位信号输出端连接；n为正整数。
下面以本公开实施例所述的栅极驱动电路包括多个如图13所示的栅极 驱动模组的具体实施例为例说明；
如图15所示，本公开实施例所述的栅极驱动电路包括第一栅极驱动模组、第二栅极驱动模块、第三栅极驱动模组、第四栅极驱动模组和第五栅极驱动模组，其中，每个栅极驱动模组的结构都与图13所示的栅极驱动模组的具体实施例的结构相同；
第一栅极驱动模组包括第一级栅极驱动单元S1和第二级栅极驱动单元S2；
第二栅极驱动模组包括第三级栅极驱动单元S3和第四级栅极驱动单元S4；
第三栅极驱动模组包括第五级栅极驱动单元S5和第六级栅极驱动单元S6；
第四栅极驱动模组包括第七级栅极驱动单元S7和第八级栅极驱动单元S8；
S1包括第一级进位信号输出端CR(1)、第一级外部补偿控制信号输出端OUT1(1)和第一级栅极驱动信号输出端OUT2(1)；S1接入第一时钟信号CLKA、第二时钟信号CLKB、第一进位输出时钟信号CLKD_1、第一外部补偿时钟信号CLKE_1和第一栅极驱动输出时钟信号CLKF_1；
S2包括第二级外部补偿控制信号输出端OUT1(2)和第二级栅极驱动信号输出端OUT2(2)；S2接入第一时钟信号CLKA、第二外部补偿时钟信号CLKE_2和第二栅极驱动输出时钟信号CLKF_2；
S3包括第三级进位信号输出端CR(3)、第三级外部补偿控制信号输出端OUT1(3)和第三级栅极驱动信号输出端OUT2(3)；S3的输入端与CR(1)连接，S3的复位端与CR(7)连接；S3接入第一时钟信号CLKA、第二时钟信号CLKB、第三进位输出时钟信号CLKD_3、第三外部补偿时钟信号CLKE_3和第三栅极驱动输出时钟信号CLKF_3；
S4包括第四级外部补偿控制信号输出端OUT1(4)和第四级栅极驱动信号输出端OUT2(4)；S4的输入端与CR(1)连接，S4的复位端与CR(7)连接；S4接入第一时钟信号CLKA、第四外部补偿时钟信号CLKE_4和第四栅极驱动输出时钟信号CLKF_4；
S5包括第五级进位信号输出端CR(5)、第五级外部补偿控制信号输出端OUT1(5)和第五级栅极驱动信号输出端OUT2(5)；S5的输入端与CR(3)连接，S5的复位端与CR(9)连接；S5接入第一时钟信号CLKA、第二时钟信号CLKB、第五进位输出时钟信号CLKD_5、第五外部补偿时钟信号CLKE_5和第五栅极驱动输出时钟信号CLKF_5；
S6包括第六级外部补偿控制信号输出端OUT1(6)和第六级栅极驱动信号输出端OUT2(6)；S5的输入端与CR(3)连接，S3的复位端与CR(9)连接；S6接入第一时钟信号CLKA、第六外部补偿时钟信号CLKE_6和第六栅极驱动输出时钟信号CLKF_6；
S7包括第七级进位信号输出端CR(7)、第七级外部补偿控制信号输出端OUT1(7)和第七级栅极驱动信号输出端OUT2(7)；S7接入第一时钟信号CLKA、第二时钟信号CLKB、第一进位输出时钟信号CLKD_1、第一外部补偿时钟信号CLKE_1和第一栅极驱动输出时钟信号CLKF_1；
S8包括第八级外部补偿控制信号输出端OUT1(8)和第八级栅极驱动信号输出端OUT2(8)；S8接入第一时钟信号CLKA、第二外部补偿时钟信号CLKE_2和第二栅极驱动输出时钟信号CLKF_2；
S9包括第九级进位信号输出端CR(9)、第九级外部补偿控制信号输出端OUT1(9)和第九级栅极驱动信号输出端OUT2(9)；S9接入第一时钟信号CLKA、第二时钟信号CLKB、第三进位输出时钟信号CLKD_3、第三外部补偿时钟信号CLKE_3和第三栅极驱动输出时钟信号CLKF_3；
S10包括第十级外部补偿控制信号输出端OUT1(10)和第十级栅极驱动信号输出端OUT2(10)；S10接入第一时钟信号CLKA、第四外部补偿时钟信号CLKE_4和第四栅极驱动输出时钟信号CLKF_4。
下面以S3和S4在一显示周期的工作过程为例进行说明。
在该显示周期，VDDo为高电平，VDDe为低电平；
在显示周期包括的第三行输入时间段，CR(1)输出高电压，CR(7)输出低电压，CLKA、CLKE_3、CLKD_3和CLKF_3都为低电压，CLKE_4和CLKF_4都为低电压，以控制Q(3)的电位和Q(4)的电位都为高电平，QB(3)的电位和QB(4)的电位都为低电平，CR(3)、OUT1(3)和OUT2 (3)都输出低电压，OUT1(4)和OUT2(4)都输出低电压；
在显示周期包括的第三行输出时间段，Q(3)的电位和Q(4)的电位为高电平，QB(3)的电位和QB(4)的电位都为低电平，CLKE_3、CLKD_3和CLKF_3都为高电压，CR(3)、OUT1(3)和OUT2(3)都输出高电压；
在显示周期包括的第四行输出阶段，Q(3)的电位和Q(4)的电位为高电平，QB(3)的电位和QB(4)的电位都为低电平，CLKE_4和CLKF_4都为高电压，OUT1(4)和OUT2(4)都输出高电压；
在所述第三行输出时间段和所述第三行复位时间段之间的第三保持时间段，Q(3)的电位被S(3)包括的第一存储电容和第二存储电容维持为高低电平，但是由于此时CLKE_3、CLKD_3和CLKF_3都为低电压，CR(3)、OUT1(3)和OUT2(3)都输出低电压；
在所述第四行输出时间段和所述第四行复位时间段之间的第四保持时间段，Q(4)的电位被S4包括的第一存储电容和第二存储电容维持为高低电平，但是由于此时CLKE_4和CLKF_4都为低电压，OUT1(4)和OUT2(4)都输出低电压；
在显示周期包括的第三行复位时间段(所述第三行复位时间段也即第四行复位时间段)，Q(3)的电位和Q(4)的电位为低电平，QB(3)的电位为高电平，CR(3)、OUT1(3)、OUT2(3)、OUT1(4)和OUT2(4)都输出低电压；
依次移位完成显示周期的所有行像素电路的显示，接着进入空白时间段。
本公开实施例所述的显示装置包括上述的栅极驱动电路。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (26)

  1. 一种栅极驱动单元，包括外部补偿控制信号输出端、栅极驱动信号输出端、外部补偿控制信号输出电路、栅极驱动信号输出电路、上拉控制电路和下拉节点控制电路，其中，所述上拉控制电路用于在使能端输入的使能信号和本级驱动信号的控制下，控制第一节点的电位，在所述第一节点的电位、第一时钟信号端输入的第一时钟信号、第二时钟信号端输入的第二时钟信号和所述下拉节点的电位的控制下，控制上拉控制节点的电位，并在所述上拉控制节点的电位的控制下，控制上拉节点的电位，以使得在空白时间段中的预定时间段，能够控制所述上拉节点的电位为有效电压；
    所述下拉节点控制电路用于控制所述下拉节点的电位；
    所述外部补偿控制信号输出电路用于在所述上拉节点的电位的控制下，控制所述外部补偿控制信号输出端与外部补偿时钟信号端之间连通，在所述下拉节点的电位的控制下，控制所述外部补偿控制信号输出端与第一电压端之间连通；
    所述栅极驱动信号输出电路用于在所述上拉节点的电位和所述下拉节点的电位的控制下，控制所述栅极驱动信号输出端输出栅极驱动信号。
  2. 如权利要求1所述的栅极驱动单元，其中，所述本级驱动信号的波形与所述栅极驱动信号的波形相同。
  3. 如权利要求1所述的栅极驱动单元，其中，所述上拉控制电路包括第一节点控制子电路、第二节点控制子电路、第三节点控制子电路、上拉控制节点控制子电路和上拉控制子电路；
    所述第一节点控制子电路用于在所述使能信号的控制下，控制第一节点接入所述本级驱动信号，并控制维持所述第一节点的电位；
    所述第二节点控制子电路用于在所述第二时钟信号的控制下，控制第二节点的电位；
    所述第三节点控制子电路用于在所述第二节点的电位的控制下，控制第三节点与第二电压端之间连通；
    所述上拉控制节点控制子电路用于在所述第一节点的电位的控制下，控 制所述上拉控制节点与所述第一时钟信号端之间连通，并在所述下拉节点的电位的控制下，控制所述上拉控制节点与所述第三节点之间连通；
    所述上拉控制子电路用于在所述上拉控制节点的电位的控制下，控制所述上拉节点与第三电压端之间连通。
  4. 如权利要求3所述的栅极驱动单元，其中，所述第二节点控制子电路还用于在所述第一时钟信号的控制下，控制所述第二节点与所述第二电压端之间连通。
  5. 如权利要求3所述的栅极驱动单元，其中，所述第一节点控制子电路包括第一控制晶体管和储能电容；
    所述第一控制晶体管的控制极与所述使能端连接，所述第一控制晶体管的第一极接入所述本级驱动信号，所述第一控制晶体管的第二极与所述第一节点连接；
    所述储能电容的第一端与所述第一节点连接，所述储能电容的第二端与所述上拉控制节点连接。
  6. 如权利要求3所述的栅极驱动单元，其中，所述第二节点控制子电路包括第二控制晶体管；
    所述第二控制晶体管的控制极和所述第二控制晶体管的第一极都与所述第二时钟信号端连接，所述第二控制晶体管的第二极与所述第二节点连接。
  7. 如权利要求6所述的栅极驱动单元，其中，所述第二节点控制子电路还包括第二节点复位晶体管；
    所述第二节点复位晶体管的控制极与所述第一时钟信号端连接，所述第二节点复位晶体管的第一极与所述第二节点连接，所述第二节点复位晶体管的第二极与所述第二电压端连接。
  8. 如权利要求3所述的栅极驱动单元，其中，所述第三节点控制子电路包括第三控制晶体管；
    所述第三控制晶体管的控制极与所述第二节点连接，所述第三控制晶体管的第一极与所述第三节点连接，所述第三控制晶体管的第二极与所述第二电压端连接；
    所述上拉控制节点控制子电路包括第四控制晶体管和第五控制晶体管；
    所述第四控制晶体管的控制极与所述第一节点连接，所述第四控制晶体管的第一极与所述第一时钟信号端连接，所述第四控制晶体管的第二极与所述上拉控制节点连接；
    所述第五控制晶体管的控制极与所述下拉节点连接，所述第五控制晶体管的第一极与所述上拉控制节点连接，所述第五控制晶体管的第二极与所述第三节点连接；
    所述上拉控制子电路包括上拉控制晶体管；
    所述上拉控制晶体管的控制极与所述上拉控制节点连接，所述上拉控制晶体管的第一极与所述上拉节点连接，所述上拉控制晶体管的第二极与所述第三电压端连接。
  9. 如权利要求1至8中任一权利要求所述的栅极驱动单元，还包括上拉节点控制电路；
    所述上拉节点控制电路分别与输入端、复位端、所述上拉节点、所述下拉节点、空白区复位端、第三电压端和第四电压端连接，用于在所述输入端输入的输入信号的控制下，控制所述上拉节点与所述第三电压端之间连通，在所述复位端输入的复位信号的控制下，控制所述上拉节点与所述第四电压端之间连通，在所述空白区复位端输入的空白区复位信号的控制下，控制所述上拉节点与所述第四电压端之间连通，在所述下拉节点的电位的控制下，控制所述上拉节点与所述第四电压端之间连通，并用于维持所述上拉节点的电位。
  10. 如权利要求9所述的栅极驱动单元，其中，所述上拉节点控制电路包括第一上拉节点控制晶体管、第二上拉节点控制晶体管、第三上拉节点控制晶体管、第四上拉节点控制晶体管、第一存储电容和第二存储电容，其中，
    所述第一上拉节点控制晶体管的控制极与所述输入端连接，所述第一上拉节点控制晶体管的第一极与所述第三电压端连接，所述第一上拉节点控制晶体管的第二极与所述上拉节点连接；
    所述第二上拉节点控制晶体管的控制极与所述复位端连接，所述第二上拉节点控制晶体管的第一极与所述上拉节点连接，所述第二上拉节点控制晶体管的第二极与所述第四电压端连接；
    所述第三上拉节点控制晶体管的控制极与所述空白区复位端连接，所述第三上拉节点控制晶体管的第一极与所述上拉节点连接，所述第三上拉节点控制晶体管的第二极与所述第四电压端连接；
    所述第四上拉节点控制晶体管的控制极与所述下拉节点连接，所述第四上拉节点控制晶体管的第一极与所述上拉节点连接，所述第四上拉节点控制晶体管的第二极与所述第四电压端连接；
    所述第一存储电容的第一端与所述上拉节点连接，所述第一存储电容的第二端与所述外部补偿控制信号输出端连接；
    所述第二存储电容的第一端与所述上拉节点连接，所述第二存储电容的第二端与所述栅极驱动信号输出端连接。
  11. 如权利要求3至8中任一权利要求所述的栅极驱动单元，其中，所述下拉节点控制电路分别与第一控制电压端、所述上拉节点、所述下拉节点、所述第一节点、所述第一时钟信号端、所述输入端和第五电压端连接，用于在第一控制电压端输入的第一控制电压和所述上拉节点的电位的控制下，控制所述下拉节点的电位，并在所述第一节点的电位与所述第一时钟信号的控制下，控制所述下拉节点与所述第五电压端之间连通，在所述输入端输入的输入信号的控制下，控制所述下拉节点与所述第五电压端之间连通。
  12. 如权利要求11所述的栅极驱动单元，其中，所述下拉节点控制电路包括第一下拉控制晶体管、第二下拉控制晶体管、第三下拉控制晶体管、第四下拉控制晶体管和第五下拉控制晶体管，其中，
    所述第一下拉控制晶体管的控制极和所述第一下拉控制晶体管的第一极都与所述第一控制电压端连接，所述第一下拉控制晶体管的第二极与下拉节点连接；
    所述第二下拉控制晶体管的控制极与所述上拉节点连接，所述第二下拉控制晶体管的第一极与所述下拉节点连接，所述第二下拉控制晶体管的第二极与所述第五电压端连接；
    所述第三下拉控制晶体管的控制极与所述第一时钟信号端连接，所述第三下拉控制晶体管的第一极与所述下拉节点连接；
    所述第四下拉控制晶体管的控制极与所述第一节点连接，所述第四下拉 控制晶体管的第一极与所述第三下拉控制晶体管的第二极连接，所述第四下拉控制晶体管的第二极与所述第五电压端连接；
    所述第五下拉控制晶体管的控制极与所述输入端连接，所述第五下拉控制晶体管的第一极与所述下拉节点连接，所述第五下拉控制晶体管的第二极与所述第五电压端连接。
  13. 如权利要求1至8中任一权利要求所述的栅极驱动单元，其中，所述外部补偿控制信号输出电路包括第一补偿输出晶体管和第二补偿输出晶体管，其中，
    所述第一补偿输出晶体管的控制极与所述上拉节点连接，所述第一补偿输出晶体管的第一极与所述外部补偿时钟信号端连接，所述第一补偿输出晶体管的第二极与所述外部补偿控制信号输出端连接；
    所述第二补偿输出晶体管的控制极与所述下拉节点连接，所述第二补偿输出晶体管的第一极与所述外部补偿控制信号输出端连接，所述第二补偿输出晶体管的第二极与所述第一电压端之间连通。
  14. 如权利要求1至8中任一权利要求所述的栅极驱动单元，还包括进位信号输出端和进位信号输出电路；
    所述进位信号输出电路用于在所述上拉节点的电位和所述下拉节点的电位的控制下，控制所述进位信号输出端输出进位信号；
    所述本级驱动信号为由所述进位信号输出端提供的进位信号。
  15. 一种栅极驱动方法，应用于如权利要求1至14中任一权利要求所述的栅极驱动单元，在两显示周期之间设置有空白时间段，所述栅极驱动方法包括：
    在显示周期，上拉控制电路在使能端输入的使能信号和本级驱动信号的控制下，控制第一节点的电位为有效电压，并维持所述第一节点的电位为有效电压；所述上拉控制电路在所述第一节点的电位、第一时钟信号端输入的第一时钟信号、第二时钟信号端输入的第二时钟信号和所述下拉节点的电位的控制下，控制上拉控制节点的电位为无效电压；
    在设置于该显示周期之后的空白时间段中的预定时间段，所述上拉控制电路维持所述第一节点的电位为有效电压，所述上拉控制电路在所述第一节 点的电位和所述第一时钟信号的控制下，控制上拉控制节点的电位，并在所述上拉控制节点的电位的控制下，控制上拉节点的电位为有效电压；外部补偿控制信号输出电路在所述上拉节点的电位的控制下，控制外部补偿控制信号输出端与外部补偿时钟信号端之间连通。
  16. 如权利要求15所述的栅极驱动方法，其中，所述上拉控制电路包括第一节点控制子电路、第二节点控制子电路、第三节点控制子电路、上拉控制节点控制子电路和上拉控制子电路；在显示周期，第一时钟信号端输入无效电压，第二时钟信号端输入有效电压；所述预定时间段包括依次设置的时钟输入阶段和外部补偿输出阶段；所述栅极驱动方法包括：
    在显示周期包括的输出阶段，使能端输入有效电压，本级驱动信号为有效电压，第一节点控制子电路控制第一节点接入所述本级驱动信号；上拉控制节点控制子电路控制所述上拉控制节点与所述第一时钟信号端之间连通；上拉控制子电路控制断开上拉节点与第三电压端之间的连接；
    在所述显示周期包括的复位阶段和输出截止保持阶段，使能端输入无效电压，下拉节点的电位为有效电压，第一节点控制子电路维持所述第一节点的电位；第二节点控制子电路控制第二节点的电位为有效电压，第三节点控制子电路控制第三节点与第二电压端之间连通；上拉控制节点控制子电路控制所述上拉控制节点与所述第一时钟信号端之间连通，并控制上拉控制节点与第三节点之间连通；上拉控制子电路控制断开上拉节点与第三电压端之间的连接；
    在设置于所述显示周期之后的空白时间段中的时钟输入阶段和外部补偿输出阶段，第一节点控制子电路维持所述第一节点的电位；
    在该时钟输入阶段，所述第一时钟信号端输入有效电压，所述第二时钟信号端输入无效电压，上拉控制节点控制子电路控制所述上拉控制节点与所述第一时钟信号端之间连通，上拉控制子电路控制上拉节点与第三电压端之间连通，以控制上拉节点的电位为有效电压；
    在该外部补偿输出阶段，所述第一时钟信号端输入有效电压，所述第二时钟信号端输入无效电压，第一节点控制子电路维持第一节点的电位为有效电压，上拉控制节点控制子电路控制上拉控制节点与所述第一时钟信号端之 间连通，上拉控制子电路断开所述上拉节点与第三电压端之间的连接，使得上拉节点的电维持为有效电压；外部补偿时钟信号端输入有效电压，外部补偿控制信号输出电路控制外部补偿控制信号输出端与所述外部补偿时钟信号端之间连通。
  17. 如权利要求16所述的栅极驱动方法，其中，所述空白时间段还包括设置于所述预定时间段之后的空白区复位阶段；所述栅极驱动方法还包括：
    在该空白区复位阶段，使能端输入有效电压，本级驱动信号为无效电压，第一节点控制子电路控制第一节点接入所述本级驱动信号，以对第一节点的电位进行复位。
  18. 如权利要求17所述的栅极驱动方法，其中，所述栅极驱动单元还包括上拉节点控制电路；所述栅极驱动方法还包括：
    在所述空白区复位阶段，空白区复位端输入有效电压，以对所述上拉节点的电位进行复位。
  19. 一种栅极驱动模组，包括如权利要求1至14中任一权利要求所述的栅极驱动单元；所述栅极驱动单元为第N级栅极驱动单元；N为正整数；所述栅极驱动模组还包括第N+1级栅极驱动单元；
    第N+1级栅极驱动单元中的上拉节点为第N+1上拉节点，第N+1级栅极驱动单元中的下拉节点为第N+1下拉节点，第N+1级栅极驱动单元中的上拉控制节点为所述第N级栅极驱动单元中的上拉控制节点；
    所述第N+1级栅极驱动单元包括第N+1级上拉控制电路、第N+1级外部补偿控制信号输出端、第N+1级栅极驱动信号输出端、第N+1外部补偿控制信号输出电路、第N+1栅极驱动信号输出电路和第N+1下拉节点控制电路；
    所述第N+1级上拉控制电路与所述第N上拉控制节点连接，用于在该第N上拉控制节点的电位的控制下，控制第N+1上拉节点与第三电压端之间连接；
    所述第N+1下拉节点控制电路用于控制第N+1下拉节点的电位；
    所述第N+1外部补偿控制信号输出电路用于在该第N+1上拉节点的电位的控制下，控制所述第N+1级外部补偿控制信号输出端与第二外部补偿时钟信号端之间连通，在该第N+1下拉节点的电位的控制下，控制所述外部补偿 控制信号输出端与所述第一电压端之间连通；
    所述第N+1栅极驱动信号输出电路用于在该第N+1上拉节点的电位和该第N+1下拉节点的电位的控制下，控制所述第N+1级栅极驱动信号输出端输出栅极驱动信号。
  20. 如权利要求19所述的栅极驱动模组，其中，所述第N+1级栅极驱动单元还包括第N+1上拉节点控制电路；
    所述第N+1上拉节点控制电路分别与输入端、复位端、所述第N+1上拉节点、所述第N+1下拉节点、空白区复位端、第三电压端和第四电压端连接，用于在所述输入端输入的输入信号的控制下，控制所述第N+1上拉节点与所述第三电压端之间连通，在所述复位端输入的复位信号的控制下，控制所述第N+1上拉节点与所述第四电压端之间连通，在所述空白区复位端输入的空白区复位信号的控制下，控制所述第N+1上拉节点与所述第四电压端之间连通，在所述第N+1下拉节点的电位的控制下，控制所述第N+1上拉节点与所述第四电压端之间连通，并用于维持所述第N+1上拉节点的电位。
  21. 如权利要求19所述的栅极驱动模组，其中，所述第N级栅极驱动单元中的上拉控制电路为第N上拉控制电路；所述N上拉控制电路包括第一节点控制子电路、第二节点控制子电路、第三节点控制子电路、上拉控制节点控制子电路和上拉控制子电路；
    所述第N+1下拉节点控制电路分别与第二控制电压端、所述第N+1上拉节点、所述第N+1下拉节点、所述第N级栅极驱动单元中的第一节点、第一时钟信号端、复位端和第五电压端连接，用于在所述第二控制电压输入的第二控制电压和所述N+1上拉节点的电位的控制下，控制所述第N+1下拉节点的电位，并在所述第一节点的电位与所述第一时钟信号端输入的第一时钟信号的控制下，控制所述N+1下拉节点与所述第五电压端之间连通，在输入端输入的输入信号的控制下，控制所述下拉节点与所述第五电压端之间连通。
  22. 如权利要求21所述的栅极驱动模组，其中，所述第N级栅极驱动单元中的外部补偿控制信号输出电路为第N外部补偿控制信号输出电路，所述第N级栅极驱动单元中的栅极驱动信号输出电路为第N栅极驱动信号输出电路；所述第N级栅极驱动单元中的外部补偿控制信号输出端为第N级外部 补偿控制信号输出端，所述第N级栅极驱动单元中的栅极驱动信号输出端为第N级栅极驱动信号输出端；所述第N级栅极驱动单元中的上拉节点为第N上拉节点，所述第N级栅极驱动单元中的下拉节点为第N下拉节点；
    所述第N外部补偿控制信号输出电路还与所述第N+1下拉节点连接，用于在第N+1下拉节点的电位的控制下，对第N级外部补偿控制信号输出端进行复位；
    所述第N栅极驱动信号输出电路还与所述第N+1下拉节点连接，用于在第N+1下拉节点的电位的控制下，对第N级栅极驱动信号输出端进行复位；
    所述第N+1外部补偿控制信号输出电路还与所述第N下拉节点连接，用于在第N下拉节点的电位的控制下，对第N+1级外部补偿控制信号输出端进行复位；
    所述第N+1栅极驱动信号输出电路还与所述第N下拉节点连接，用于在第N下拉节点的电位的控制下，对第N+1级栅极驱动信号输出端进行复位。
  23. 一种栅极驱动电路，包括多级如权利要求19至22中任一权利要求所述的栅极驱动模组。
  24. 如权利要求23所述的栅极驱动电路，其中，第n级栅极驱动模组包括第N级栅极驱动单元和第N+1级栅极驱动单元；
    在所述第n级栅极驱动模组中，输入端与第N-2级栅极驱动信号输出端连接，复位端与第N+4级栅极驱动信号输出端连接；n为正整数。
  25. 如权利要求23所述的栅极驱动电路，其中，
    所述第N级栅极驱动单元包括进位信号输出端和进位信号输出电路；第n级栅极驱动模组包括第N级栅极驱动单元和第N+1级栅极驱动单元；在所述第n级栅极驱动模组中，输入端与第N-2级进位信号输出端连接，复位端与第N+4级进位信号输出端连接；n为正整数。
  26. 一种显示装置，包括如权利要求23至25中任一权利要求所述的栅极驱动电路。
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