WO2020177362A1 - 开关电源的控制方法及电路 - Google Patents

开关电源的控制方法及电路 Download PDF

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Publication number
WO2020177362A1
WO2020177362A1 PCT/CN2019/115687 CN2019115687W WO2020177362A1 WO 2020177362 A1 WO2020177362 A1 WO 2020177362A1 CN 2019115687 W CN2019115687 W CN 2019115687W WO 2020177362 A1 WO2020177362 A1 WO 2020177362A1
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switch
voltage
crossing
zero
current
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PCT/CN2019/115687
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English (en)
French (fr)
Inventor
於昌虎
曾正球
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深圳南云微电子有限公司
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Publication of WO2020177362A1 publication Critical patent/WO2020177362A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only

Definitions

  • the invention relates to a switching power supply, in particular to a control method and circuit for the negative excitation current of an active clamp flyback converter.
  • Flyback converters are widely used in small and medium power offline switching power supplies due to their low cost and simple topology.
  • the energy of the primary side of the flyback converter cannot be completely transferred to the secondary side.
  • the energy left on the primary side generates high-frequency resonance through the leakage inductance and the parasitic capacitance of the switching node, which leads to the switching node, that is, the main switching tube.
  • the drain terminal produces very high voltage spikes.
  • an absorption circuit is required.
  • Conventional absorption circuits include RCD clamp circuits, LCD clamp circuits and active clamp circuits.
  • the active clamp circuit adds an additional clamp tube and a larger clamp capacitor, which can save the leakage inductance energy and recycle it to the input end of the converter.
  • the active clamp circuit can pull down the voltage of the switching node after the recovery process of the leakage inductance energy is completed, thereby realizing the ZVS turn-on of the main switching tube and reducing the turn-on loss of the main switching tube , It is convenient to improve the power density of the converter.
  • FIG. 1 100 shown in Figure 1 is a circuit diagram of a typical active clamp flyback converter.
  • L K is the leakage inductance
  • L M is the magnetizing inductance
  • C A is the clamp capacitor
  • M A is the clamp tube
  • M P is the main switch tube
  • C PAR is the parasitic capacitance of the switch node
  • R S is the magnetizing inductance.
  • Current sampling resistor N P is the number of turns of the primary winding of the transformer
  • N S is the number of turns of the secondary winding of the transformer
  • D R is the rectifier diode
  • C OUT is the output capacitor of the converter
  • unit 101 is the main control chip of the converter
  • unit 102 It is an isolated feedback circuit.
  • the main control chip 101 by sampling the output voltage of the inverter and the voltage drop across the current sense resistor R S to achieve the dual loop peak current mode control, to determine when to open the main switch M P, when turned off.
  • a logical control M A pipe clamp conduction time. Indeed, leakage inductance alone is difficult to pull the switch node voltage to ground, and the need to reduce the sense of an appropriate amount of the magnetizing inductance L M, so that there is excitation inductance negative current. After the clamp tube is turned off, the magnetizing inductance and leakage inductance still flow negative current, extracting energy from the parasitic capacitance of the switch node, so that the switch node voltage is pulled to the ground potential.
  • a typical signal waveform 200 is a key pattern complementary to the active clamp flyback converter, wherein the gate terminal of the main switch G_M P drive waveform, G_M A driving waveform for the gate end of the clamping tube, DS_M P main switch drain voltage waveforms, I LM is the magnetizing inductance current waveform, I LK leakage inductance of the current waveform.
  • the inductance of the excitation inductance is L M
  • the inductance of the leakage inductance is L K
  • the positive peak value of the excitation inductance current is I PKP
  • the negative peak value is I PKN
  • the drain terminal voltage of the main switch is V DS_MP
  • the switch The parasitic capacitance value of the node is C PAR
  • the conditions for the main switch tube to realize ZVS turn-on are:
  • the positive peak current I PKP of the magnetizing inductance varies with the load current. Therefore, in order to reliably realize the ZVS turn-on of the main switch tube, a certain negative current of the magnetizing inductance needs to be maintained.
  • the current slope of the magnetizing inductance is constant.
  • the zero-crossing time of the excitation current can be determined, that is, I ZERO in the figure
  • the negative excitation current can be controlled by adjusting the turn-off time of the clamp tube.
  • the specific peak value of the negative excitation current is the time from the zero crossing of the current to the turn-off of the clamp tube multiplied by the slope of the current.
  • the purpose of the present invention is to provide a switching power supply control method, which is applied to an active clamp flyback converter, which can adaptively determine the zero-crossing moment of the excitation current , Further realize the control of the negative excitation current by adjusting the turn-off time of the clamp tube, so as to reliably realize the turn-on of the main switch tube ZVS, and minimize the required negative excitation current peak value to avoid excessive soft switching of the main switch tube .
  • another object of the present invention is to provide a switching power supply control circuit applied to an active clamp flyback converter.
  • the circuit can sample the switch node voltage and determine the zero-crossing moment of the excitation current based on it. Control the turn-off of the clamp tube to meet the ZVS turn-on requirement of the main switch tube and realize the control of the negative excitation current.
  • a control method of a switching power supply, applied to an active clamp flyback converter includes:
  • Sampling step the sampling unit samples the switch node voltage, and outputs the sampled voltage to the current zero-crossing judgment unit;
  • the current zero-crossing judgment unit judges the zero-crossing moment of the excitation current according to the sampled voltage waveform
  • Control steps After the zero-crossing point of the excitation current of a single cycle is judged, the control unit delays a period of time after the zero-crossing point to turn off the clamp tube.
  • the current zero-crossing judgment step includes the following process:
  • the current zero-crossing judgment unit records the time from when the main switch tube is turned off to when the voltage waveform of the switch node appears;
  • the current zero-crossing judgment step includes the following process:
  • the current zero-crossing judging unit records the time from the main switch tube being turned off to the switch node voltage falling to the converter input voltage as the reference time;
  • each cycle is advanced by 1/4 of the resonant cycle of the switching node voltage waveform on the basis of the reference time as the excitation current zero crossing point;
  • a control circuit for a switching power supply, applied to an active clamp flyback converter including: a sampling unit, a current zero-crossing judgment unit and a control unit; the sampling unit is used to sample the switch node voltage and output the sampled voltage to the current zero-crossing Judging unit; the current zero-crossing judging unit judges the zero-crossing moment of the excitation current according to the sampled voltage waveform; the control unit circuit is used to delay a period of time to turn off the clamp tube after the zero-crossing moment of the excitation current.
  • the current zero-crossing judging unit includes at least a first timing capacitor and a first storage capacitor; the current zero-crossing judging unit records the time from when the main switch is turned off to when the sampled voltage waveform appears and drops, and During the recording time period, the first reference current is used to charge the first timing capacitor, and the voltage on the first timing capacitor is stored on the first storage capacitor; except for the working period of the recording time, other working periods will be the first timing The capacitor is recharged. Once the voltage on the first timing capacitor reaches the voltage of the first storage capacitor, it is considered that the zero-crossing point of the excitation current of the current cycle has been reached.
  • the above-mentioned zero-crossing judgment unit is further configured to: record the working period of the time, and the clamp tube is turned on non-complementarily or not turned on directly.
  • the current zero-crossing judging unit includes at least a second timing capacitor and a second storage capacitor; the current zero-crossing judging unit turns off the main switch until the switch node voltage drops to the converter input voltage.
  • the time is recorded as the reference time.
  • the third reference current is used to charge the second timing capacitor, and the voltage on the second timing capacitor is saved to the second storage capacitor; at the same time, the fourth reference current is used to charge the second timing capacitor. 2.
  • the voltage on the storage capacitor is discharged, and the discharge time is 1/4 of the resonant period of the switch node voltage, and the third reference current is proportional to the fourth reference current; in addition to the period of the recording time, other work cycles will affect the first
  • the second timing capacitor is recharged. Once the voltage on the second timing capacitor reaches the voltage on the second storage capacitor, it is considered that the zero-crossing point of the excitation current of this period has been reached.
  • the above-mentioned zero-crossing judgment unit is further configured to: record the working period of the time, and the clamp tube is turned on non-complementarily or not turned on directly.
  • the zero-crossing determination unit is further that: the product of the third reference current and the second storage capacitor is equal to the product of the fourth reference current and the second timing capacitor.
  • the sampling unit includes an auxiliary winding NA, a voltage dividing resistor RS1 and a voltage dividing resistor RS2.
  • the voltage dividing resistor RS1 and the voltage dividing resistor RS2 are connected in series and connected in parallel with the auxiliary winding NA.
  • the voltage dividing resistor RS1 and the voltage dividing resistor RS2 The connection point of the resistor RS2 is the output terminal of the sampling unit for outputting the sampling voltage.
  • the current zero-crossing judgment unit includes switches K1, K2, K3, K4, K5, resistor R1, capacitors C1, C2, C3, comparators 501, 504, delay 503, D trigger 502, reference current sources IREF1, IREF2, AND gate 505; one end of switch K1 is the input end of the current zero-crossing judgment unit for inputting sampling voltage, one end of switch K1 is also connected to the positive input end of comparator 501, The other end of K1 is connected to one end of resistor R1, the control end of switch K1 is connected to the output end of delayer 503; the other end of resistor R1 is connected to the upper plate of capacitor C1 and the negative input end of comparator 501; The output terminal is connected to the reset terminal of the D flip-flop 502; the D input terminal of the D flip-flop 502 is used to input the power supply VCC, the trigger terminal is used to input the driving signal of the main switch tube, and the Q output terminal is also connected to the control terminal of the switch K2 and the delay
  • the control unit includes an adjustable current source Ictrl, a capacitor C4, a switch K6, a reference voltage source VREF1, a comparator 601, an AND gate 602 and a D flip-flop 603; one end of the adjustable current source Ictrl is used At the input power VCC, the other end is connected to the upper plate of the capacitor C4, one end of the switch K6 and the negative input end of the comparator 601; the other end of the switch K6 and the lower plate of the capacitor C4 are grounded together, and the control end of the switch K6 Connect to the inverted Q output terminal of the D flip-flop 603; one end of the reference voltage source VREF1 is connected to the positive input terminal of the comparator 601, and the other end of the reference voltage source VREF1 is grounded; the output terminal of the comparator 601 is connected to the reset of the D flip-flop 603
  • the D input terminal of the D flip-flop 603 is used to input the power supply VCC, and the trigger terminal is connected to the output terminal of
  • the current zero-crossing judgment unit includes a reference voltage source VREF2, a comparator 701, a narrow pulse generator 702, a D flip-flop 703, a reference current source IREF3, a switch K7, a switch K8, a switch K9, Switch K10, capacitor C5, capacitor C6, operational amplifier 704, reference current source IREF4, comparator 705 and AND gate 706;
  • the positive input terminal of comparator 701 is the input terminal of the current zero-crossing judging unit for inputting sampling voltage
  • the negative input end of the comparator 701 is connected to one end of the reference voltage source VREF2, the output end of the comparator 701 is connected to the input end of the narrow pulse generator 702, and the other end of the reference voltage source VREF2 is grounded;
  • the output end of the narrow pulse generator 702 is connected The reset terminal of the D flip-flop 703 and an input terminal of the AND gate 706;
  • the D input terminal of the D flip-flop 703 is used to input the power supply VCC, the trigger terminal is used to
  • the effective level of all the above switches is high, that is, the switch is closed when the control level of the switch control terminal is high, otherwise, the switch is open.
  • the control terminals of the third switch K3, the fourth switch K4, the fifth switch K5, the eighth switch K8, the ninth switch K9, and the tenth switch K10 are connected to respective control signals according to logic requirements.
  • the high level is the power supply VCC, and the low level is the ground.
  • the clamp tube shut-off signal is generated after a delay, so as to realize the control of the negative excitation current
  • Figure 1 shows the topology of a typical active clamp flyback converter
  • Figure 2 is a key signal waveform diagram of a typical complementary mode active clamp flyback converter
  • FIG. 3 is a schematic block diagram of the control circuit of the present invention.
  • Figure 4 is a key signal waveform diagram of a typical non-mutual mode active clamp flyback converter
  • FIG. 5 is a schematic diagram of a current zero-crossing judgment unit in the first embodiment of the present invention.
  • Figure 6 is a schematic diagram of a control unit in the first embodiment of the present invention.
  • FIG. 7 is a schematic diagram of the current zero-crossing judgment unit in the second embodiment of the present invention.
  • Fig. 8 is a key signal waveform of the converter of the control circuit of the present invention working in a typical complementary mode.
  • FIG. 3 of the present invention A control circuit block diagram of the switching power supply 300 shown in FIG. 3 of the present invention, wherein the auxiliary winding N A and a sampling unit dividing resistors R S1 and R S2 composed of current zero determination unit 302 and control unit 303 of the present invention, a control circuit
  • the auxiliary winding N A and a sampling unit dividing resistors R S1 and R S2 composed of current zero determination unit 302 and control unit 303 of the present invention
  • the auxiliary winding N A voltage reflects the voltage of the switching node, the voltage dividing resistors R S1 and R S2 the auxiliary output sampled voltage to current zero crossing determination unit 302 after the winding voltage dividing; zero current determining unit 302 according to the sampling voltage waveform Determine the zero-crossing moment of the excitation current; the control unit circuit is used to delay a period of time to turn off the clamp tube after the zero-crossing moment of the excitation current.
  • the clamp tube is turned on non-complementary or directly not turned on, so that the excitation current reaches the discontinuous or critical mode, which facilitates the accurate judgment of the zero-crossing point of the excitation current.
  • the non-complementary mode is selected. Excitation converter for analysis.
  • the resonance waveform of the exciting current to the switch node voltage resonance waveform A phase difference of 90°.
  • the voltage waveform of the switch node starts to resonate, the excitation current just crosses zero for the first time, and the peak of the resonant voltage of the switch node corresponds to the zero crossing point of the excitation current.
  • the first zero-crossing point of the excitation current can be determined by detecting the moment when the switching node voltage waveform starts to resonate.
  • the clamp tube is turned on at the peak of the voltage waveform corresponding to the trough of the clamp tube, which is a typical non-complementary active clamp mode. Therefore, the technical difficulty lies in how to accurately determine when the switch node voltage starts to resonate.
  • 500 is a schematic diagram of the current zero-crossing judgment unit 303 in this embodiment.
  • the excitation current zero-crossing judgment is realized based on the detection of the inflection point, which is the point where the voltage waveform of the switch node starts to drop.
  • the circuit includes switches K1, K2, K3, K4, K5, resistor R1, capacitors C1, C2, C3, comparators 501, 504, delay 503, D flip-flop 502, reference current sources IREF1, IREF2, and gate 505 .
  • one end of K1 is connected to the voltage dividing node of the auxiliary winding and the positive input end of the comparator 501, the other end is connected to one end of R1, the control end of K1 is connected to the output end of the delayer 503; the other end of R1 is connected to the output of the capacitor C1
  • the negative input terminal of the upper plate and 501; the output terminal of 501 is connected to the reset terminal of D flip-flop 502; the D input terminal of 502 is connected to the power supply VCC, the trigger terminal is connected to the main switch tube drive signal G_MP, and the Q output terminal is connected to the control of K2 Terminal, the input terminal of 503 and one input terminal of AND gate 505;
  • one end of K2 is connected to one end of IREF1, the other end is connected to one end of K3, the upper plate of C2, one end of K4, one end of K5 and the negative input terminal of 504 ,
  • the other end of the reference current source IREF1 is used to input the power supply VCC; the
  • the falling edge G_M P, Q output of the D flip-flop 502 outputs a high level after the delay 503 K1 is closed.
  • K1, R1 and C1 form a sampling circuit to sample the voltage of the auxiliary winding voltage divider node to C1. Due to the delay effect of the RC network, the voltage of C1 changes slowly.
  • the comparator 501 outputs a low level. This low level resets 502, and the Q output of 502 becomes low.
  • the above belongs to the reference time recording period. In other working periods, once the voltage on the C2 capacitor reaches the voltage stored on C3, the comparator 504 outputs a low level, and the AND gate 505 gives the excitation current zero-crossing moment signal Trig.
  • 600 is a schematic diagram of the control unit 303 in this embodiment, including an adjustable current source Ictrl, a capacitor C4, a switch K6, a reference voltage source VREF1, a comparator 601, an AND gate 602, and a D flip-flop 603.
  • one end of Ictrl is connected to the power supply VCC, the other end is connected to the upper plate of C4, one end of K6 and the negative input terminal of 601; the other end of K6 and the lower plate of C4 are grounded together, and the control terminal of K6 is connected to the reverse of 603 Phase Q output terminal; one end of the reference voltage source VREF1 is connected to the positive input terminal of 601, and the other end of VREF1 is grounded; the output terminal of 601 is connected to the reset terminal of 603; the D input terminal of 603 is connected to the power supply VCC, and the trigger terminal is connected to the AND gate 602 an output terminal; an input end 602 of the excitation current zero-crossing time signal Trig, the other input of the external trigger signal termination Trig2; Q output terminal 603 of the output tube clamp off signal SD_M a.
  • the input Trig signal of the AND gate 602 becomes a low level, and the output low level triggers 603, the inverted Q output terminal of 603 outputs a low level, and K6 is disconnected.
  • the adjustable current source Ictrl charges C4, and when it is charged to the reference voltage source VREF1, 601 outputs a low level to reset the D flip-flop 603.
  • the Q output terminal of 603 outputs the clamp tube turn-off signal SD_M A.
  • the falling slope of the excitation current remains the same. A period of time after the zero-crossing point, that is, the time when the C4 capacitor is charged to the reference voltage source, the clamp tube is disconnected, and the negative excitation current peak value control is achieved.
  • the specific peak value is:
  • C4 represents the capacitance value
  • VREF1 represents the reference voltage value
  • Ictrl represents the adjustable current value
  • C2 is a timing capacitor
  • C3 is a storage capacitor
  • C2 After power-on, when the converter works in the excitation current discontinuous mode, C2 starts charging when the main switch is turned off, and stops when the voltage waveform at the connection point of the voltage divider resistor R S1 and the voltage divider resistor R S2 drops. Charge, and then copy the voltage of C2 to C3 during the on-time of the main switch;
  • the converter is forced to work in the excitation current discontinuous mode, and the voltage of C2 is copied to C3 again, and the voltage on C3 is refreshed, that is, the time to refresh the record; in the subsequent working process, the previous processes are repeated continuously .
  • the circuit diagram of this embodiment is different from the first embodiment in that the current zero-crossing judgment unit is different.
  • 700 is a schematic diagram of the current zero-crossing judgment unit 302 in this embodiment, including a reference voltage source VREF2, a comparator 701, a narrow pulse generator 702, a D flip-flop 703, a reference current source IREF3, and a switch K7 , K8, K9, K10, capacitors C5, C6, operational amplifier 704, reference current source IREF4, comparator 705, AND gate 706.
  • the positive input terminal of 701 is connected to the auxiliary winding voltage divider node, the negative input terminal is connected to one end of VREF2, and the output terminal is connected to the input terminal of 702; the other end of VREF2 is grounded; the output terminal of 702 is connected to the reset terminal of 703 and the reset terminal of 706 an input terminal; D input terminal of the power source VCC 703, triggering termination G_M P drive signal of the main switch, Q output terminal K7 termination control; and a termination end of IREF3 of K7, K8 one end of the other end, C5
  • the upper plate of 704, the positive input of 704 and the negative input of comparator 705; the other end of IREF3 is connected to the power supply VCC; the other end of K8 and the lower plate of C5 are grounded; the negative input of 704 is connected to its own The output end is connected in parallel to one end of K9; the other end of K9 is connected to the upper plate of C6, one end of K10 and the positive input end of 705;
  • This embodiment is proposed because it is considered that the high-frequency resonance time caused by the reverse recovery of the clamp body diode has a great relationship with the selection of the device and the power level of the converter. If the high-frequency resonance time is longer than the delay time set by the delayer of the first embodiment, it may still cause errors in the inflection point detection of the first embodiment.
  • the amplitude of high-frequency resonance is small, and the valley of the oscillation is generally not lower than the input voltage V IN .
  • the voltage normally resonates to V IN it corresponds to a 1/4 resonant cycle. At this time, the excitation current resonates to the first trough.
  • the time when the excitation current starts to drop to the first trough can be recorded as the reference time.
  • advance 1/4 resonance period and save it as the comparison time. In other working cycles, once the excitation current drops to the comparison time, it is considered that the excitation current zero crossing point has been reached.
  • G_M P turned off after the corresponding switch node voltage increases, the voltage value of the reference voltage VREF2 is very low, about several tens millivolts, the comparator 701 outputs a high level.
  • the switch node voltage begins to resonate. After 1/4 of the resonant period, the voltage reaches the input voltage V IN , and the corresponding auxiliary winding voltage is lower than zero volts.
  • the comparator 701 outputs a low level and outputs a low-level narrow pulse after 702 to reset 703.
  • the Q output terminal of 703 outputs low level.
  • K7 is closed, and IREF3 charges C5.
  • the operational amplifier 704 is connected to the structure of a buffer, K9 is closed by the sampling pulse control after K7 is turned off, and the voltage on C5 is copied to C6. After that, K10 closes 1/4 switch node voltage resonance time, and discharges capacitor C6 through IREF4.
  • IREF3 IREF4
  • K8 is closed by pulse control after K9 is turned off, and the charge on C5 is discharged. In other working cycles, once the charging voltage on C5 reaches the voltage stored on C6, it is considered that the excitation current zero crossing point has been reached.
  • 705 outputs a low level, and the AND gate 705 outputs an excitation current zero-crossing signal Trig.
  • C5 is a timing capacitor
  • C6 is a storage capacitor
  • the converter in this embodiment selects the control strategy of the complementary mode.
  • Figure 8 shows the key signal waveforms of the converter of the control circuit of the present invention operating in the typical complementary mode. The operation of this embodiment is taken as a general technical solution in conjunction with Figure 8 The principle analysis is as follows:
  • the converter is forced to work in a non-complementary mode where the first peak of the clamp tube is turned on in a single cycle, so there is a resonant period.
  • C5 starts charging from the excitation current decreases until the voltage reached DS_M P 1/4 resonance cycle stop charging. After that, the voltage of C5 is copied to C6 during the on-time of the main switch, that is, the time to refresh the record;
  • the single cycle is forced to work in the non-complementary mode with the first peak turned on again, the voltage of C5 is copied to C6 again, and the voltage on C6 is refreshed, that is, the recorded time.
  • the first embodiment above is based on the analysis and design of the non-complementary mode active clamp flyback converter. Although there is no voltage resonance in the complementary mode, it can be used when a single cycle is forced to work in the non-complementary mode. Generate voltage resonance, refresh the recording time, so as to achieve the purpose of the invention. Therefore, the converter of the first embodiment can also adopt a complementary mode control strategy like the second embodiment; conversely, the converter of the second embodiment The non-complementary mode control strategy can also be adopted as in the first embodiment, which can also achieve the purpose of the invention.
  • the embodiments of the present invention are not limited to this. According to the above content, according to the common technical knowledge and conventional means in the field, the present invention has other embodiments without departing from the above basic technical ideas of the present invention; therefore, the present invention is made Various other forms of modification, replacement or alteration of, all fall within the protection scope of the present invention.

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Abstract

一种开关电源的控制方法和电路，应用于有源钳位反激变换器，用于对变换器的负向励磁电流的峰值进行控制，该控制电路包括采样单元、电流过零判断单元（302）和控制单元（303），采样单元采样开关节点电压，并输出采样电压至电流过零判断单元（302）；电流过零判断单元（302）依据采样电压波形判断励磁电流的过零时刻；控制单元（303）电路在励磁电流过零时刻后延时一段时间关断钳位管。该电路能够自适应地判断出励磁电流的过零时刻，进一步通过调节钳位管的关断实现负向励磁电流的控制，从而可靠地实现主开关管ZVS开通，并且尽量减小所需的负向励磁电流峰值，避免主开关管的过度软开关。

Description

开关电源的控制方法及电路 技术领域
本发明涉及开关电源，特别涉及有源钳位反激变换器负向励磁电流的控制方法及电路。
背景技术
反激变换器因其成本低、拓扑简单等优点被广泛应用于中小功率离线式开关电源。实际工作过程中，反激变换器的原边能量并不能够完全传递到副边，留在原边的能量通过漏感和开关节点寄生电容产生高频谐振，导致在开关节点，即主开关管的漏端，产生很高的电压尖峰。为了减小开关管的电压应力，需要吸收电路，常规的吸收电路有RCD钳位电路、LCD钳位电路和有源钳位电路。其中，有源钳位电路添加额外的钳位管及较大的钳位电容，可以将漏感能量保存下来，并回收至变换器输入端。另外，由于漏感的电惯性，有源钳位电路在漏感能量的回收过程结束后，可以将开关节点的电压拉低，从而实现主开关管的ZVS开通，减小主开关管的开通损耗，便于变换器功率密度的提升。
图1所示100就是典型有源钳位反激变换器的电路图。图中，L K为漏感、L M为励磁电感、C A为钳位电容、M A为钳位管、M P为主开关管、C PAR为开关节点的寄生电容、R S为励磁电感电流采样电阻、N P为变压器原边绕组匝数、N S为变压器副边绕组匝数、D R为整流二极管、C OUT为变换器输出电容、单元101为变换器的主控制芯片、单元102为隔离反馈电路。主控制芯片101通过采样变换器输出电压和电流采样电阻R S上的压降实现双环路峰值电流模控制，确定主开关管M P何时开通、何时关断。为了实现主开关管M P的ZVS开通，需要合理控制钳位管M A导通的时间。实际上，仅仅依靠漏感很难将开关节点的电压拉 至地电位，而需要将励磁电感L M的感量适当减小，使得励磁电感也存在负向电流。在钳位管关闭之后，励磁电感和漏感仍然流过负向电流，从开关节点的寄生电容上抽取能量，使得开关节点电压拉至地电位。
如图2所示200为典型的互补模式有源钳位反激变换器的关键信号波形，其中，G_M P为主开关管的栅端驱动波形，G_M A为钳位管的栅端驱动波形，DS_M P为主开关管漏端电压波形，I LM为励磁电感电流波形，I LK为漏感电流波形。假设，励磁电感的感量为L M，漏感的感量为L K，励磁电感电流正向的峰值为I PKP，负向的峰值为I PKN，主开关管漏端电压为V DS_MP，开关节点寄生电容容值为C PAR，主开关管实现ZVS开通的条件是：
Figure PCTCN2019115687-appb-000001
对于变换器而言，励磁电感正向峰值电流I PKP是随负载电流变化的，所以，为了可靠实现主开关管的ZVS开通，需要保持一定的励磁电感负向电流。
此外，能量守恒公式如下：
Figure PCTCN2019115687-appb-000002
因此，可知只有使得负向励磁峰值电流I PKN在多种工作条件下保持一致，正向励磁峰值电流I PKP才能够反映负载的变化，对于峰值电流模控制方式，才能够提高电流环路的控制精度。公式中，η表示变换器的转换效率，P O表示变换器输出功率，f O表示对应功率下的工作频率。为了优化变换器的整体效率往往需要自适应地调节负向励磁电流，使得主开关管恰好实现ZVS开通又不至于过度软开关造成额外损耗的增加。由于钳位管导通期间，励磁电感两端的电压降为N P/N S*V OUT，所以，励磁电感的电流斜率是一定的。如图2所示，如果能 够判断出励磁电流的过零时刻，即图中的I ZERO，就能够通过调节钳位管的关断时刻实现负向励磁电流的控制。具体的负向励磁电流峰值为电流过零到钳位管关断的时间乘以电流的斜率。
发明内容
鉴于判断励磁电流过零时刻这一技术要求，本发明的目的是，提供一种开关电源的控制方法，应用于有源钳位反激变换器，能自适应地判断出励磁电流的过零时刻，进一步通过调节钳位管的关断时刻实现负向励磁电流的控制，从而可靠地实现主开关管ZVS开通，并且尽量减小所需的负向励磁电流峰值，避免主开关管的过度软开关。
与此相应，本发明的另一个目的是，提供一种开关电源的控制电路，应用于有源钳位反激变换器，该电路能采样开关节点电压并以此判断励磁电流的过零时刻，控制钳位管的关断，从而满足主开关管的ZVS开通需求，实现负向励磁电流的控制。
本发明的第一个目的是通过以下技术方案实现的：
一种开关电源的控制方法，应用于有源钳位反激变换器，包括：
采样步骤：采样单元采样开关节点电压，输出采样电压至电流过零判断单元；
电流过零判断步骤：电流过零判断单元依据采样电压波形判断励磁电流的过零时刻；
控制步骤：当判断出单周期的励磁电流过零点之后，由控制单元在此过零点后延时一段时间将钳位管关断。
优选地，作为电流过零判断步骤的一种具体的实施方式，包括如下过程：
(1)当变换器工作在励磁电流断续模式时，电流过零判断单元将主开关管关断到开关节点电压波形出现下掉的时间记录下来；
(2)此后的若干周期，主开关管关断后达到记录的时间都认为励磁电流达到了过零点；
(3)若干周期之后，强制变换器工作在励磁电流断续模式，刷新记录的时间；
不断重复(1)、(2)、(3)过程。
优选地，作为电流过零判断步骤的另外一种具体的实施方式，包括如下过程：
(1)当变换器工作在励磁电流断续模式时，电流过零判断单元将主开关管关断到开关节点电压下掉至变换器输入电压的时间记录下来作为基准时间；
(2)此后的若干周期，每周期在基准时间的基础上提前1/4个开关节点电压波形的谐振周期，作为励磁电流过零点；
(3)若干周期之后，强制变换器工作在励磁电流断续模式，刷新记录的基准时间；
不断重复(1)、(2)、(3)过程。
对应地，本发明的另一个目的是通过以下技术方案实现的：
一种开关电源的控制电路，应用于有源钳位反激变换器，包括：采样单元、电流过零判断单元和控制单元；采样单元用于采样开关节点电压，并输出采样电压至电流过零判断单元；电流过零判断单元依据采样电压波形判断励磁电流的过零时刻；控制单元电路用于在励磁电流过零时刻后延时一段时间关断钳位管。
作为电流过零判断单元的一种具体的技术方案，至少包括第一计时电容和第一保存电容；电流过零判断单元将主开关管关断到采样电压波形出现下掉的时间记录下来，在记录时间段内利用第一基准电流给第一计时电容充电，并将第一计时电容上的电压保存到第一保存电容上；除了记录时间的工作周期之外，其它工作周期都会对第一计时电容重新充电，一旦第一计时电容上电压达到第一保存电容的电压，就认为达到了当前周期的励磁电流过零点。
优选地，上述过零判断单元还在于：记录时间的工作周期，钳位管为非互补开通或者直接不开通。
作为电流过零判断单元的另外一种具体的技术方案，至少包括第二计时电容和第二保存电容；电流过零判断单元将主开关管关断到开关节点电压下掉至变换器输入电压的时间记录下来作为基准时间，在基准时间段内利用第三基准电流给第二计时电容充电，并将第二计时电容上的电压保存到第二保存电容上；同时，利用第四基准电流给第二保存电容上的电压放电，放电时间为1/4个开关节点电压的谐振周期，并且第三基准电流与第四基准电流存在比例关系；除了记录时间的周期之外，其它工作周期都会对第二计时电容重新充电，一旦第二计时电容上的电压达到第二保存电容上的电压，就认为达到了本周期的励磁电流过零点。
优选地，上述过零判断单元还在于：记录时间的工作周期，钳位管为非互补开通或者直接不开通。
优选地，上述过零判断单元还在于：第三基准电流与第二保存电容的乘积等于第四基准电流与第二计时电容的乘积。
作为采样单元的一种具体的实施方式，包括辅助绕组NA、分压电阻RS1 和分压电阻RS2，分压电阻RS1和分压电阻RS2串联后与辅助绕组NA并联，分压电阻RS1和分压电阻RS2的连接点为采样单元的输出端，用于输出采样电压。
作为电流过零判断单元的第一种具体的实施方式，包括开关K1、K2、K3、K4、K5，电阻R1，电容C1、C2、C3，比较器501、504，延时器503，D触发器502，基准电流源IREF1、IREF2，与门505；开关K1的一端为电流过零判断单元的输入端，用于输入采样电压，开关K1的一端还连接比较器501的正向输入端，开关K1的另一端接电阻R1的一端，开关K1的控制端接延时器503的输出端；电阻R1的另一端接电容C1的上极板和比较器501的负向输入端；比较器501的输出端接D触发器502的复位端；D触发器502的D输入端用于输入电源VCC，触发端用于输入主开关管驱动信号，Q输出端同时接开关K2的控制端、延时器503的输入端和与门505的一个输入端；开关K2的一端接基准电流源IREF1的一端，另一端同时接开关K3的一端、电容C2的上极板、开关K4的一端、开关K5的一端和比较器504的负向输入端，基准电流源IREF1的另一端用于输入电源VCC；开关K3的另一端接基准电流源IREF2的一端，基准电流源IREF2的另一端、电容C2的下极板和开关K5的另一端一起接地；开关K4的另一端接电容C3的上极板和比较器504的正向输入端，电容C3的下极板接地；比较器504的输出端接与门505的另一输入端，与门505的输出端输出励磁电流过零信号。
作为控制单元的一种具体的实施方式，包括可调电流源Ictrl、电容C4、开关K6、基准电压源VREF1、比较器601、与门602和D触发器603；可调电流源Ictrl的一端用于输入电源VCC，另一端同时接电容C4的上极板、开关K6 的一端和比较器601的负向输入端；开关K6的另一端和电容C4的下极板一起接地，开关K6的控制端接D触发器603的反相Q输出端；基准电压源VREF1的一端接比较器601的正向输入端，基准电压源VREF1的另一端接地；比较器601的输出端接D触发器603的复位端；D触发器603的D输入端用于输入电源VCC，触发端接与门602的输出端；与门602的一个输入端输入励磁电流过零时刻信号，另一个输入端接外部的触发信号；D触发器603的Q输出端输出钳位管关断信号。
作为电流过零判断单元的第二种具体的实施方式，包括基准电压源VREF2、比较器701、窄脉冲发生器702、D触发器703、基准电流源IREF3、开关K7、开关K8、开关K9、开关K10、电容C5、电容C6、运算放大器704、基准电流源IREF4、比较器705和与门706；比较器701的正向输入端为电流过零判断单元的输入端，用于输入采样电压，比较器701的负向输入端接基准电压源VREF2的一端，比较器701的输出端接窄脉冲发生器702的输入端，基准电压源VREF2的另一端接地；窄脉冲发生器702的输出端接D触发器703的复位端和与门706的一个输入端；D触发器703的D输入端用于输入电源VCC，触发端用于输入主开关管的驱动信号，Q输出端接开关K7的控制端；开关K7的一端接基准电流源IREF3的一端，另一端同时接开关K8的一端、电容C5的上极板、运算放大器704的正向输入端和比较器705的负向输入端，基准电流源IREF3的另一端用于输入电源VCC；开关K8的另一端和电容C5的下极板同时接地；运算放大器704的负向输入端接自身的输出端，并接到开关K9的一端；开关K9的另一端同时接电容C6的上极板、开关K10的一端和比较器705的正向输入端；比较器705的输出端接与门706的另一输入端，与门706的输出端输出励磁电 流过零信号。
需要说明的是，上述所有开关的有效电平为高电平，即开关控制端的控制电平为高电平时开关闭合，否则，开关断开。其中，第三开关K3、第四开关K4、第五开关K5、第八开关K8、第九开关K9和第十开关K10的控制端根据逻辑需要接各自的控制信号。所述高电平即为电源VCC，低电平为地。
本发明的有益效果在于：
1、通过辅助绕组检测变换器开关节点电压波形，通过逻辑运算自适应地判断出每个工作周期的励磁电流过零点，为负向励磁电流的控制提供基准点；
2、基于励磁电流过零点经过一段延时产生钳位管关断信号，从而实现负向励磁电流的控制；
3、负向励磁电流的准确控制使得主开关管能够可靠实现ZVS开通，但又不至于过度软开关。
附图说明
图1为典型有源钳位反激变换器的拓扑图；
图2为典型互补模式有源钳位反激变换器的关键信号波形图；
图3为本发明控制电路的原理框图；
图4为典型非互模式有源钳位反激变换器的关键信号波形图；
图5为本发明第一实施例中电流过零判断单元的原理图；
图6为本发明第一实施例中控制单元的原理图；
图7为本发明第二实施例中电流过零判断单元原理图；
图8为本发明控制电路的变换器工作于典型互补模式下的关键信号波形。
具体实施方式
图3所示300为本发明开关电源控制电路的原理框图，其中辅助绕组N A以及分压电阻R S1和R S2组成的采样单元、电流过零判断单元302和控制单元303为本发明控制电路的组成部分，为了讲述本发明的构思对开关电源相关元器件也进行了绘制。辅助绕组N A端电压反映了开关节点的电压，分压电阻R S1和R S2将辅助绕组端电压分压之后输出采样电压到电流过零判断单元302；电流过零判断单元302依据采样电压波形判断励磁电流的过零时刻；控制单元电路用于在励磁电流过零时刻后延时一段时间关断钳位管。
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图4至8对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
实施例一
由于记录时间的工作周期，钳位管为非互补开通或者直接不开通，使得励磁电流达到断续或临界模式，便于励磁电流过零点的准确判断，本实施例选择非互补模式有源钳位反激变换器进行分析。
如图4所示400为典型非互补模式有源钳位反激变换器关键节点波形，从开关节点电压波形DS_M P和励磁电流波形I LM来看，励磁电流的谐振波形与开关节点电压谐振波形相差90°的相位。当开关节点电压波形开始谐振时，励磁电流刚好初次过零，并且开关节点谐振电压的波峰也对应励磁电流的过零点。鉴于此特点，可以通过检测开关节点电压波形开始谐振的时刻确定励磁电流的初次过零点。此后，在电压波形的波峰开通钳位管对应钳位管波谷导通，此为典型的非互补有源钳位模式。所以，技术难点在于如何准确地判断出开关节点电压开始谐振的时刻。
从波形上看，开关节点电压开始谐振处402存在明显的电压下掉趋势，只要将此电压下掉的时刻检测出来即可。然而，在励磁电流下降过程中，开关节点电压还存在较高频率的谐振，如图4中的401所示，此谐振由钳位管的体二极管固有的反向恢复时间引起。高频谐振401会干扰402的正常检测，需要将高频谐振屏蔽掉。
基于上述波形分析，本实施例的电流过零判断单元302和控制单元303的设计方案如下：
如图5所示500为本实施例中电流过零判断单元303的原理图，基于拐点检测实现励磁电流过零判断，所述拐点即为开关节点电压波形开始下掉的点。电路包括，开关K1、K2、K3、K4、K5，电阻R1，电容C1、C2、C3，比较器501、504，延时器503，D触发器502，基准电流源IREF1、IREF2，与门505。其中，K1的一端接辅助绕组的分压节点和比较器501的正向输入端，另一端接R1的一端，K1的控制端接延时器503的输出端；R1的另一端接电容C1的上极板和501的负向输入端；501的输出端接D触发器502的复位端；502的D输入端接电源VCC，触发端接主开关管驱动信号G_MP，Q输出端接K2的控制端、503的输入端和与门505的一个输入端；K2的一端接IREF1的一端，另一端接K3的一端、C2的上极板、K4的一端、K5的一端和504的负向输入端，基准电流源IREF1的另一端用于输入电源VCC；K3的另一端接IREF2的一端，IREF2的另一端、C2的下极板和K5的另一端一起接地；K4的另一端接C3的上极板和504的正向输入端，C3的下极板接地；504的输出端接505的另一输入端，505的输出端输出励磁电流过零信号。
图5所示电流过零判断单元的工作原理如下：
在G_M P的下降沿，D触发器502的Q输出端输出高电平，经过延时器503之后将K1闭合。K1、R1和C1组成一个采样电路，将辅助绕组分压节点的电压采样至C1。由于RC网络的延时作用，C1的电压变化缓慢，当分压节点电压开始下掉时，比较器501输出低电平。该低电平将502复位，502的Q输出端变为低电平。Q为高电平期间，K2闭合，基准电流源IREF1给电容C2充电；此后，K3短暂闭合，通过基准电流源IREF2给C2放电；K3断开后，K4短暂闭合，将C2上的电压保存至C3。C3的容值远小于C2，K3的短暂闭合是为了补偿比较器延时的影响。
以上属于基准时间记录周期，其它工作周期，C2电容上的电压一旦达到C3上保存的电压，比较器504输出低电平，与门505给出励磁电流过零时刻信号Trig。
如图6所示600为本实施例中控制单元303的原理图，包括，可调电流源Ictrl，电容C4，开关K6，基准电压源VREF1，比较器601，与门602，D触发器603。其中，Ictrl的一端接电源VCC，另一端接C4的上极板、K6的一端和601的负向输入端；K6的另一端和C4的下极板一起接地，K6的控制端接603的反相Q输出端；基准电压源VREF1的一端接601的正向输入端，VREF1的另一端接地；601的输出端接603的复位端；603的D输入端接电源VCC，触发端接与门602的输出端；602的一个输入端接上述励磁电流过零时刻信号Trig，另一个输入端接外部的触发信号Trig2；603的Q输出端输出钳位管关断信号SD_M A。
图6所示控制单元的工作原理如下：
与门602输入Trig信号变为低电平，则输出低电平触发603，603的反相Q 输出端输出低电平，K6断开。可调电流源Ictrl给C4充电，充电至基准电压源VREF1时，601输出低电平，将D触发器603复位。603的Q输出端输出钳位管关断信号SD_M A。对于变换器而言，励磁电流的下降斜率保持一致，过零点之后一段时间，即上述C4电容充电至基准电压源的时间将钳位管断开，就实现了负向励磁电流峰值的控制。具体峰值为：
Figure PCTCN2019115687-appb-000003
其中，C4为表示容值，VREF1表示基准电压值，Ictrl表示可调电流值。
本实施例C2为计时电容，C3为保存电容，鉴于变换器的工作条件会发生变化，从而励磁电流下降至过零点的时间也会发生变化，所以需要不间断地刷新记录的时间，即电容C3的电压。本实施例作为一个总的技术方案的工作原理，总结如下：
上电后，当变换器工作在励磁电流断续模式时，C2从主开关管关断时开始充电，直至分压电阻R S1和分压电阻R S2的连接点的电压波形出现下掉时停止充电，然后在主开关管导通期间将C2的电压复制到C3上；
此后的若干周期，当C2电压达到C3的电压时，认为达到了励磁电流过零点；
若干周期后，强制变换器工作在励磁电流断续模式，再次将C2的电压复制到C3上，刷新C3上的电压，即刷新记录的时间；在此后的工作过程中，不断重复前几个过程。
实施例二
本实施例电路图与第一实施例不同之处在于电流过零判断单元有所不同。 如图7所示700为本实施例中电流过零判断单元302的原理图，包括，基准电压源VREF2，比较器701，窄脉冲发生器702，D触发器703，基准电流源IREF3，开关K7、K8、K9、K10，电容C5、C6，运算放大器704，基准电流源IREF4，比较器705，与门706。其中，701的正向输入端接辅助绕组分压节点，负向输入端接VREF2的一端，输出端接702的输入端；VREF2的另一端接地；702的输出端接703的复位端和706的一个输入端；703的D输入端接电源VCC，触发端接主开关管的驱动信号G_M P，Q输出端接K7的控制端；K7的一端接IREF3的一端，另一端接K8的一端、C5的上极板、704的正向输入端和比较器705的负向输入端；IREF3的另一端接电源VCC；K8的另一端和C5的下极板接地；704的负向输入端接自身的输出端，并接到K9的一端；K9的另一端接C6的上极板、K10的一端和705的正向输入端；705的输出端接706的另一输入端，706的输出端输出励磁电流过零信号Trig。
本实施例的提出，在于考虑到钳位管体二极管的反向恢复引起的高频谐振时间与器件的选型及变换器功率等级有很大的关系。如果高频谐振时间比实施例一的延时器设置的延时时间长，则仍然可能造成实施例一的拐点检测出现误差。而高频谐振的振幅较小，振荡的谷底一般不会低于输入电压V IN。结合图4的开关节点电压波形，电压正常谐振至V IN时，对应经过1/4个谐振周期。此时，励磁电流谐振至第一个波谷。那么，可以将励磁电流开始下降到第一个波谷的时间记录下来，作为基准时间。在基准时间的基础上提前1/4个谐振周期，保存下来作为比较时间。其它工作周期，一旦励磁电流下降至比较时间就认为达到了励磁电流过零点。
图7所示电流过零判断单元的工作原理如下：
G_M P的下降沿触发703，使得Q输出端输出高电平。G_M P关断之后对应开关节点电压变高，基准电压VREF2的电压值很低，约几十毫伏，比较器701输出高电平。经过一段时间之后，开关节点电压开始谐振，1/4个谐振周期后，电压达到输入电压V IN，对应辅助绕组电压低于零伏。比较器701输出低电平，经过702后输出低电平窄脉冲，将703复位。703的Q输出端输出低电平，在Q输出高电平期间，K7闭合，IREF3给C5充电。运算放大器704接成缓冲器的结构，K9在K7关断之后由采样脉冲控制闭合，将C5上的电压复制到C6上。此后，K10闭合1/4个开关节点电压谐振的时间，通过IREF4给电容C6放电。IREF3、IREF4与C5、C6之间存在一个比例关系：IREF4*C5＝IREF3*C6。假设C5＝C6，则IREF3＝IREF4。K8在K9关断之后由脉冲控制闭合，将C5上的电荷泄放掉。其它工作周期，C5上的充电电压一旦达到C6上保存的电压，则认为达到了励磁电流过零点。705输出低电平，与门705输出励磁电流过零信号Trig。
本实施例C5为计时电容，C6为保存电容。同样地，鉴于变换器的工作条件会发生变化，从而励磁电流下降至过零点的时间会发生变化。所以本实施例也需要不间断地刷新记录的时间，即电容C6的电压。
本实施例的变换器选择互补模式的控制策略，图8所示800为本发明控制电路的变换器工作于典型互补模式下的关键信号波形，结合图8对本实施作为一个总的技术方案的工作原理分析如下：
首先，强制变换器在单个周期工作于钳位管第一个波峰开通的非互补模式，从而存在谐振周期。对应于图7的电路，C5从励磁电流下降时开始充电，直至DS_M P电压达到1/4个谐振周期停止充电。此后在主开关管导通期间将C5的电 压复制到C6上，即刷新记录的时间；
次周期，在励磁电流下降初期，对C6放电1/4个开关节点电压谐振周期，当C5电压达到C6的电压时，认为达到了励磁电流过零点；
N个互补模式的工作周期之后，重新强制单周期工作于第一个波峰开通的非互补模式，再次将C5的电压复制到C6上，刷新C6上的电压，即记录的时间。
需要说明的是，上面第一实施例是基于非互补模式有源钳位反激变换器进行的分析设计，虽然互补模式不存在电压谐振，但是当强制单个周期工作在非互补模式后，便能产生电压谐振，刷新记录的时间，从而也能实现发明目的，因此第一实施例的变换器也可如第二实施例一样采取互补模式的控制策略；反过来，第二实施例的的变换器也可如第一实施例一样采取非互补模式的控制策略，同样能实现发明目的。
本发明的实施方式不限于此，根据上述内容，按照本领域的普通技术知识和惯用手段，在不脱离本发明上述基本技术思想前提下，本发明还有其它的实施方式；因此对本发明做出的其它多种形式的修改、替换或变更，均落在本发明权利保护范围之内。

Claims (13)

  1. 一种开关电源的控制方法，应用于有源钳位反激变换器，其特征在于，包括：
    采样步骤：采样单元采样开关节点电压，输出采样电压至电流过零判断单元；
    电流过零判断步骤：电流过零判断单元依据采样电压波形判断励磁电流的过零时刻；
    控制步骤：当判断出单周期的励磁电流过零点之后，由控制单元在此过零点后延时一段时间将钳位管关断。
  2. 根据权利要求1所述的控制方法，其特征在于，电流过零判断步骤包括如下过程：
    (1)当变换器工作在励磁电流断续模式时，电流过零判断单元将主开关管关断到开关节点电压波形出现下掉的时间记录下来；
    (2)此后的若干周期，主开关管关断后达到记录的时间都认为励磁电流达到了过零点；
    (3)若干周期之后，强制变换器工作在励磁电流断续模式，刷新记录的时间；
    不断重复(1)、(2)、(3)过程。
  3. 根据权利要求1所述的控制方法，其特征在于，电流过零判断步骤包括如下过程：
    (1)当变换器工作在励磁电流断续模式时，电流过零判断单元将主开关管关断到开关节点电压下掉至变换器输入电压的时间记录下来作为基准时间；
    (2)此后的若干周期，每周期在基准时间的基础上提前1/4个开关节点电压波形的谐振周期，作为励磁电流过零点；
    (3)若干周期之后，强制变换器工作在励磁电流断续模式，刷新记录的基准时间；
    不断重复(1)、(2)、(3)过程。
  4. 一种开关电源的控制电路，应用于有源钳位反激变换器，其特征在于，包括：采样单元、电流过零判断单元和控制单元；采样单元用于采样开关节点电压，并输出采样电压至电流过零判断单元；电流过零判断单元依据采样电压波形判断励磁电流的过零时刻；控制单元电路用于在励磁电流过零时刻后延时一段时间关断钳位管。
  5. 根据权利要求4所述的控制电路，其特征在于：电流过零判断单元至少包括第一计时电容和第一保存电容；电流过零判断单元将主开关管关断到采样电压波形出现下掉的时间记录下来，在记录时间段内利用第一基准电流给第一计时电容充电，并将第一计时电容上的电压保存到第一保存电容上；除了记录时间的工作周期之外，其它工作周期都会对第一计时电容重新充电，一旦第一计时电容上电压达到第一保存电容的电压，就认为达到了当前周期的励磁电流过零点。
  6. 根据权利要求5所述的控制电路，其特征在于：记录时间的工作周期，钳位管为非互补开通或者直接不开通。
  7. 根据权利要求4所述的控制电路，其特征在于：电流过零判断单元至少包括第二计时电容和第二保存电容；电流过零判断单元将主开关管关断到开关节点电压下掉至变换器输入电压的时间记录下来作为基准时间，在基准时间段 内利用第三基准电流给第二计时电容充电，并将第二计时电容上的电压保存到第二保存电容上；同时，利用第四基准电流给第二保存电容上的电压放电，放电时间为1/4个开关节点电压的谐振周期，并且第三基准电流与第四基准电流存在比例关系；除了记录时间的周期之外，其它工作周期都会对第二计时电容重新充电，一旦第二计时电容上的电压达到第二保存电容上的电压，就认为达到了本周期的励磁电流过零点。
  8. 根据权利要求7所述的控制电路，其特征在于：记录时间的工作周期，钳位管为非互补开通或者直接不开通。
  9. 根据权利要求7所述的控制电路，其特征在于：第三基准电流与第二保存电容的乘积等于第四基准电流与第二计时电容的乘积。
  10. 根据权利要求4所述的控制电路，其特征在于：采样单元包括辅助绕组N A、分压电阻R S1和分压电阻R S2，分压电阻R S1和分压电阻R S2串联后与辅助绕组N A并联，分压电阻R S1和分压电阻R S2的连接点为采样单元的输出端，用于输出采样电压。
  11. 根据权利要求4所述的控制电路，其特征在于：电流过零判断单元包括开关K1、K2、K3、K4、K5，电阻R1，电容C1、C2、C3，比较器501、504，延时器503，D触发器502，基准电流源IREF1、IREF2，与门505；开关K1的一端为电流过零判断单元的输入端，用于输入采样电压，开关K1的一端还连接比较器501的正向输入端，开关K1的另一端接电阻R1的一端，开关K1的控制端接延时器503的输出端；电阻R1的另一端接电容C1的上极板和比较器501的负向输入端；比较器501的输出端接D触发器502的复位端；D触发器502的D输入端用于输入电源VCC，触发端用于输入主开关管驱动信号，Q输 出端同时接开关K2的控制端、延时器503的输入端和与门505的一个输入端；开关K2的一端接基准电流源IREF1的一端，另一端同时接开关K3的一端、电容C2的上极板、开关K4的一端、开关K5的一端和比较器504的负向输入端，基准电流源IREF1的另一端用于输入电源VCC；开关K3的另一端接基准电流源IREF2的一端，基准电流源IREF2的另一端、电容C2的下极板和开关K5的另一端一起接地；开关K4的另一端接电容C3的上极板和比较器504的正向输入端，电容C3的下极板接地；比较器504的输出端接与门505的另一输入端，与门505的输出端输出励磁电流过零信号。
  12. 根据权利要求4所述的控制电路，其特征在于：控制单元包括可调电流源Ictrl、电容C4、开关K6、基准电压源VREF1、比较器601、与门602和D触发器603；可调电流源Ictrl的一端用于输入电源VCC，另一端同时接电容C4的上极板、开关K6的一端和比较器601的负向输入端；开关K6的另一端和电容C4的下极板一起接地，开关K6的控制端接D触发器603的反相Q输出端；基准电压源VREF1的一端接比较器601的正向输入端，基准电压源VREF1的另一端接地；比较器601的输出端接D触发器603的复位端；D触发器603的D输入端用于输入电源VCC，触发端接与门602的输出端；与门602的一个输入端输入励磁电流过零时刻信号，另一个输入端接外部的触发信号；D触发器603的Q输出端输出钳位管关断信号。
  13. 根据权利要求4所述的控制电路，其特征在于：电流过零判断单元包括基准电压源VREF2、比较器701、窄脉冲发生器702、D触发器703、基准电流源IREF3、开关K7、开关K8、开关K9、开关K10、电容C5、电容C6、运算放大器704、基准电流源IREF4、比较器705和与门706；比较器701的正向 输入端为电流过零判断单元的输入端，用于输入采样电压，比较器701的负向输入端接基准电压源VREF2的一端，比较器701的输出端接窄脉冲发生器702的输入端，基准电压源VREF2的另一端接地；窄脉冲发生器702的输出端接D触发器703的复位端和与门706的一个输入端；D触发器703的D输入端用于输入电源VCC，触发端用于输入主开关管的驱动信号，Q输出端接开关K7的控制端；开关K7的一端接基准电流源IREF3的一端，另一端同时接开关K8的一端、电容C5的上极板、运算放大器704的正向输入端和比较器705的负向输入端，基准电流源IREF3的另一端用于输入电源VCC；开关K8的另一端和电容C5的下极板同时接地；运算放大器704的负向输入端接自身的输出端，并接到开关K9的一端；开关K9的另一端同时接电容C6的上极板、开关K10的一端和比较器705的正向输入端；比较器705的输出端接与门706的另一输入端，与门706的输出端输出励磁电流过零信号。
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