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  • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
  • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
  • H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
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  • H10H20/01—Manufacture or treatment
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  • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
  • H10H20/0137—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials the light-emitting regions comprising nitride materials
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  • H10H20/80—Constructional details
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  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
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  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
  • H10P14/2901—Materials
  • H10P14/2902—Materials being Group IVA materials
  • H10P14/2905—Silicon, silicon germanium or germanium
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  • H10P14/2901—Materials
  • H10P14/2907—Materials being Group IIIA-VA materials
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  • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
  • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
  • H10P14/2926—Crystal orientations
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  • H10W72/019—Manufacture or treatment of bond pads
  • H10W72/01951—Changing the shapes of bond pads
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  • H10W72/019—Manufacture or treatment of bond pads
  • H10W72/01951—Changing the shapes of bond pads
  • H10W72/01955—Changing the shapes of bond pads by using masks
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
  • H10W72/07231—Techniques
  • H10W72/07236—Soldering or alloying
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  • H10W72/00—Interconnections or connectors in packages
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  • H10W72/921—Structures or relative sizes of bond pads
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  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/951—Materials of bond pads
  • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
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  • H10W80/00—Direct bonding of chips, wafers or substrates
  • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
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  • H10W90/00—Package configurations
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  • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
  • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

Definitions

• the present disclosure relates to a method for manufacturing a semiconductor element and a semiconductor element body.
• Patent Document 1 A conventional semiconductor device manufacturing method is described in Patent Document 1, for example.
• Patent Document 1 Patent No. 4 6 3 8 9 5 8
• a method of manufacturing a semiconductor device is to form a semiconductor element on a base substrate, which is connected to the base substrate via a connecting portion to form a semiconductor element having an upper surface inclined with respect to a growth surface of the base substrate.
• a semiconductor element manufacturing method of the present disclosure includes an element forming step of forming a semiconductor element on a base substrate, the semiconductor element being connected to the base substrate via a connecting portion, and a step of facing the base substrate, A preparatory step of preparing a supporting substrate having an opposing surface inclined with respect to the growth surface of the base substrate; And a peeling step of peeling the semiconductor element from the base substrate.
• a method of manufacturing a semiconductor element according to the present disclosure is an element forming step of forming a semiconductor element on a base substrate, the semiconductor element being connected to the base substrate via a connecting portion; ⁇ 0 2020/175684 2 ⁇ (: 171? 2020 /008399
• a semiconductor element body has a support substrate, a first surface, and a second surface located on the opposite side of the first surface, and the first surface side is fixed to the support substrate. And a semiconductor element layer in which the second surface is inclined with respect to the surface of the supporting substrate.
• a semiconductor element body of the present disclosure has a support substrate having an inclined surface, a first surface and a second surface located on the opposite side to the first surface, and the first surface side is the above-mentioned. And a semiconductor element layer fixed to the inclined surface of the support substrate.
• a semiconductor element body according to the present disclosure has a support substrate, a first surface, and a second surface located on the opposite side to the first surface, and the first surface side is the support substrate.
• the yield of the semiconductor element can be increased.
• Fig. 1 is a process drawing of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
• FIG. 28 is a cross-sectional view showing the element formation process according to the first embodiment.
• FIG. 28 is a cross-sectional view showing the element formation process according to the first embodiment.
• FIG. 2(:) is a cross-sectional view showing the element forming process according to the first embodiment.
• FIG. 3 A photograph of a semiconductor element layer formed on a base substrate. ⁇ 0 2020/175684 ⁇ (: 17 2020 /008399
• FIG. 4 is a graph showing the inclination of the upper surface of the semiconductor element layer.
• FIG. 5 is a cross-sectional view showing a preparation step according to the first embodiment.
• FIG. 6 is a cross-sectional view showing the joining process according to the first embodiment.
• FIG. 6 is a cross-sectional view showing the joining process according to the first embodiment.
• FIG. 7 is a sectional view showing a peeling step according to the first embodiment.
• FIG. 88 is a cross-sectional view showing the element formation process according to the second embodiment.
• FIG. 88 is a cross-sectional view showing the element forming process according to the second embodiment.
• FIG. 80 A sectional view showing the element forming process according to the second embodiment.
• FIG. 9 is a cross-sectional view showing a preparation step according to the second embodiment.
• FIG. 1 A sectional view showing a joining step according to the second embodiment.
• FIG. 108 is a cross-sectional view showing the joining process according to the second embodiment.
• FIG. 11 is a cross-sectional view showing a peeling process according to the second embodiment.
• FIG. 12 is a sectional view showing a preparation step according to the third embodiment.
• FIG. 13-8 is a cross-sectional view showing the joining process according to the third embodiment.
• FIG. 136 is a cross-sectional view showing the joining process according to the third embodiment.
• FIG. 14 is a cross-sectional view showing a peeling process according to the third embodiment.
• a mask having stripe-shaped slits is formed on a base substrate such as sapphire or O (gallium nitride). Then, a semiconductor is epitaxially grown from the substrate exposed from the slit, and the formed semiconductor element is transferred to the supporting substrate. [0015]
• a base substrate such as sapphire or O (gallium nitride).
• a semiconductor is epitaxially grown from the substrate exposed from the slit, and the formed semiconductor element is transferred to the supporting substrate.
• each of the base substrate and the supporting substrate is A force perpendicular to the surface is applied to break the connection between the base substrate and the semiconductor element. At this time, force is applied between the supporting substrate and the semiconductor element.
• the electrodes of the semiconductor element may be peeled off, and the semiconductor element may not be reliably transferred to the supporting substrate. As a result, the yield of semiconductor elements may not be improved.
• FIG. 1 is a basic process diagram of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
• the manufacturing method of a semiconductor device of the present disclosure includes an element forming step 3 1 for forming a semiconductor element on a base substrate, a preparatory step 3 2 for preparing a supporting substrate, and a semiconductor element on the base substrate being bonded to the supporting substrate.
• a bonding step 33 and a peeling step 34 for peeling the semiconductor element from the base substrate are included.
• the element forming step 31 and the preparation step 32 do not have to be performed in this order, and for example, the element forming step 31 and the preparation step 32 may be performed in parallel.
• a base substrate 11 is prepared.
• ⁇ 3 1 ⁇ 1 template substrate is used.
• the base substrate 11 is an off-substrate, and the growth surface 1 1 3 of the base substrate 11 (or perpendicular to the thickness direction of the base substrate 11).
• the normal direction of this plane is inclined by 0.3 ° from the 3-axis ( ⁇ 1 1 _ 2 0>) direction.
• the off-angle with respect to the 3-axis is 0.3 ° .
• a substrate having an off angle of 0.1 ° to 1 ° that is, the growth surface 1 13 of the base substrate 11 is a crystal plane having an off angle with respect to the normal to the growth surface 1 13 3.
• Such a base substrate 11 is, for example, cut out from a single crystal ingot so that the growth surface 11 3 of the base substrate is in a predetermined plane direction.
• the base substrate 11 may be a nitride semiconductor substrate, and may be an n-type substrate or a type substrate in which impurities are doped in the nitride semiconductor.
• a N template substrate for example, sapphire, S i or S i C can be used as the G .
• a mask 12 is formed on the base substrate 11.
• a silicon oxide e.g. Si 0 2 etc.
• PCVD Physical Vapor Deposition
• a Si 0 2 layer on the growth surface 11 a.
• Stack about 100 nm.
• photolithography and a buffer Dofutsu acid by (BHF Buffered Hydrogen F luor ide) by Uetsu Toetsuchin grayed, and butter training the S i ⁇ two layers, a mask 1 2 shown in FIG. 2 A.
• the mask 12 has a stripe shape in which a plurality of strip portions 12 a are arranged in parallel at a predetermined interval.
• the width of the opening 12 b between the adjacent strips 12 a is, for example, about 5 Mm.
• the width of the strip 12a is, for example, about 50 m to 200 m.
• the width of the opening 12b is, for example, about 2 m to 20 m.
• the mask material for forming the mask 12 may be S i O 2 or any material that does not allow the semiconductor layer to grow from the mask material by vapor phase growth.
• Masking material for example, butter training capable Z R_ ⁇ x, oxides such as T i ⁇ x or A ⁇ x or, may also be used transition metals such as W or C r.
• a method for laminating the mask layer it is possible to appropriately use a method suitable for the mask material, such as a vapor deposition method, a sputtering method or a coating and hardening method.
• a semiconductor element layer 13 which is a crystal growth layer of a semiconductor crystal is vapor-grown from above 1 1 a.
• the semiconductor device layer 13 of the present disclosure is a nitride semiconductor layer.
• the crystal growth method is vapor phase growth VPE (Vapor Phase Epitaxy) by a chloride transport method using a chloride as a raw material, or MOCVD (Meta I Organic) using an organic metal as a raw material. Chemical Vapor Deposition) can be used. It is also possible to form the semiconductor element layers 13 as a multi-layer film that functions as an LED or LD by changing the ratio of the source gas for the group element and the source gas for the impurities during the growth process. is there. [0022] When the grown crystal exceeds the opening 12b of the mask 12, the crystal also grows laterally along the mask upper surface 12c. The crystal growth is completed before the semiconductor element layer 13 grown from the growth surface 11 a overlaps with the adjacent semiconductor element layer 13.
• VPE Vapor Deposition
• the semiconductor element layer 13 obtained by growing the nitride semiconductor by the ELO (Epitaxial Lateral Overgrowth) method is obtained.
• the width of the semiconductor element layer 13 is, for example, about 50 m to 200 m, and the height is about 10 yu_m to 50 yu_m.
• FIG. 3 is a photograph of the semiconductor element layer formed on the base substrate, and is a top view of the semiconductor element layer formed on the mask by the above-described method.
• FIG. 4 is a graph showing the inclination of the upper surface of the semiconductor element layer, and shows the measurement results obtained by measuring the distance between the upper surface of the semiconductor element layer shown in FIG. 3 and the reference plane.
• the width W of the band-shaped semiconductor element layer 13 is 35 M m, and the right end side is higher than the left end side in the width direction, and the height difference between both ends is 150 nm.
• the inclination angle of the first surface 13 a (upper surface) of the semiconductor element layer 13 is 0.25°.
• the off-angle of the base substrate 11 used for the growth of this semiconductor element layer 13 is 0.22°, and the inclination angle of the first surface 13a corresponds to the off-angle of the base substrate 11. Has become.
• growing the semiconductor element layer 13 with an off-angle on the base substrate 11 is good for realizing a crystalline semiconductor element layer 13 of excellent quality.
• the semiconductor element layer 13 has a first surface 13a and a second surface 13c located on the opposite side of the first surface 13a.
• a metal layer 14 is formed on the first surface 13 a of the semiconductor element layer 13 as shown in FIG. 2B.
• the entire upper surfaces of the base substrate 11, the mask 12 and the semiconductor element layer 13 are covered with a resist film. After that, an opening is provided by photolithography so that the first surface 13a of the semiconductor element layer 13 is exposed. Then, in the opening, for example, a Cr layer and an AuSn layer, which is an alloy of gold and tin, are sequentially deposited. After that, the unnecessary metal layer is removed together with the resist film by the lift-off method to form the metal layer 14.
• the thickness of this metal layer is about 1 Mm to 5 m. ⁇ 0 2020/175684 7 ⁇ (: 171? 2020 /008399
• the semiconductor element layer 13 and the metal layer 14 are soaked in the holes 1 to 1 for about 10 minutes, and the mask 12 is removed. As a result, the semiconductor element 15 is formed on the base substrate 11 as shown in FIG.
• the semiconductor element 15 and the base substrate 11 are a part of the semiconductor element layer 13 grown in the opening 12 of the mask 12; for example, the base substrate via the columnar connection 13 1 1 is connected.
• the metal layer 14 can be used as an electrode of the semiconductor element 15. However, the metal layer 14 may not necessarily be used as an electrode depending on the configuration of the semiconductor element 15.
• the upper surface 153 of the semiconductor element 15 is inclined similarly to the first surface 153 of the semiconductor element layer 13 3.
• the semiconductor element layer 13 has a first surface 1 3 3 and a second surface 1300 located on the opposite side.
• FIG. 5 is a cross-sectional view showing a preparation step according to the first embodiment. Then, a supporting substrate 16 for connecting to the semiconductor element 15 is prepared.
• the supporting substrate 16 uses a silicon substrate as the substrate 1 63.
• a metal layer 16 ⁇ such as Hori is formed on one surface of the base body 163, and the surface of the metal layer 16 ⁇ is the facing surface 160 facing the base substrate 1 1.
• the metal layer 16 makes it easy to bond the semiconductor element 15 to the supporting substrate 16.
• the semiconductor element 15 is mounted on the supporting substrate 1 using a substrate bonding apparatus (not shown).
• the base substrate 11 and the support substrate 16 are attached to the substrate bonding apparatus so that the growth surface 113 of the base substrate 11 and the facing surface 160 of the support substrate 16 are parallel to each other.
• FIG. 6 is a cross-sectional view showing a joining process according to the first embodiment. Subsequently, as shown in FIG. 6A, the facing surface 160 of the supporting substrate 16 and the upper surface 1553 of the semiconductor element 15 are brought into contact with each other. As described above, since the first surface 1 3 3 of the semiconductor element layer 13 is inclined, it is the upper surface of the metal layer 14 formed thereon, that is, the upper surface 1 5 3 of the semiconductor element 15 Is also inclined. ⁇ 0 2020/175684 8 ⁇ (: 171? 2020 /008399
• the supporting substrate 16 is pressed to form a metal layer.
• FIG. 7 is a cross-sectional view showing the peeling process according to the first embodiment.
• the base substrate 11 and the supporting substrate 16 are taken out from the substrate bonding apparatus.
• the semiconductor element 15 is bonded onto the supporting substrate 16 and the connection portion 13 is broken, the base substrate 11 can be easily peeled off.
• the columnar connection portion 13 is attached to the semiconductor element layer 13. It is conceivable that the connection part 13 remains on the base substrate 11 side, the semiconductor element 15 side or both depending on the state of breakage. Therefore, after peeling, the contact portion 13 remaining in the semiconductor element 15 is removed by polishing or the like.
• the first surface 1 3 3 of the semiconductor element layer 1 3 is parallel to the facing surface 160 which is the surface of the supporting substrate 16. ..
• the first surface 1 3 3 of the semiconductor element layer 13 is considered to be parallel to the surface of the supporting substrate 16 if the inclination is less than 0.5 ° , for example.
• the semiconductor element body 17 of the first embodiment has the support substrate 16 and the second surface 1 located on the opposite side to the first surface 1 3 3 and the first surface 1 3 3. And the first surface 1 3 3 side is fixed to the supporting substrate 16.
• the semiconductor element body 17 is provided with the semiconductor element layer 13 whose second surface 130 is inclined with respect to the surface of the supporting substrate 16. As a result, the semiconductor element layer 13 of excellent quality can be realized with a simple supporting structure. ⁇ 0 2020/175684 9 ⁇ (: 171? 2020 /008399
• the semiconductor element 15 since the semiconductor element 15 has the upper surface 1553 tilted with respect to the growth surface 1 13 of the base substrate 11, it is Shear stress concentrates on the ends of the column-shaped connection 1 3 13 and shears. Therefore, the semiconductor element 15 can be reliably separated from the base substrate 11 only by applying pressure without applying a force in the vertical direction to the surface of the base substrate 11 by ultrasonic waves or the like. In this way, the semiconductor elements 15 can be surely transferred onto the support substrate 16 without applying an excessive force to the semiconductor elements 15, so that the yield of the semiconductor elements 15 can be improved.
• FIG. 8 to 8 3 is a cross-sectional view showing the element forming process according to the second embodiment.
• a base substrate 21 is prepared.
• the first embodiment for example, to use a ⁇ 3 1 ⁇ 1 template substrate.
• the mask 2 2 is formed in the step of 2.
• the growth surface 2 1 3 is exposed through the opening 2 2 of the strip 2 2 3 of the mask 2 2.
• the nitride semiconductor is removed from above the growth surface 203 exposed from the opening 22 of the strip 223.
• the semiconductor element layer 23, which is a crystal growth layer, is vapor-phase grown.
• a metal layer 24 made of, for example, an 8-3 alloy is formed on the first surface 23 3 of the semiconductor element layer 23.
• the mask 22 on the base substrate 21 is etched to form a semiconductor element 25 on the base substrate 21.
• the first surface 2 3 3 of the semiconductor element layer 23 and the upper surface 2 5 3 of the semiconductor element 25 are substantially parallel to the growth surface 2 1 3 of the base substrate 21.
• the semiconductor element layer 23 has a first surface 2 3 3 and a second surface 2 3 0 located on the opposite side.
• FIG. 9 is a cross-sectional view showing a preparation step according to the second embodiment.
• semiconductor ⁇ 02020/175684 10 boxes (: 171?2020/008399
• a support substrate 26 for bonding to the element 25 is prepared.
• a silicon substrate is used as the base body 2 63 of the support substrate 26, for example.
• the silicon substrate is, for example, an off-substrate having an off angle of 0.3 ° from (1 1 1), that is, the supporting substrate 26 has a facing surface 260 facing the base substrate 21. ..
• an off substrate in which the facing surface 260 is a crystal plane having an off angle with respect to a normal line of the facing surface 260 can be used.
• a stripe-shaped photoresist film is formed on such an off-substrate, and anisotropic etching is performed with an aqueous solution of ⁇ 1 to 1 (potassium hydroxide) to form a sloped surface 26 on the substrate 2 63. .. Further, a metal layer 26 such as gold is formed on the silicon substrate by vapor deposition or the like.
• the support substrate 26 thus formed has the facing surface 260 having the inclined inclined surface 26. The inclination angle ⁇ of the inclined surface 26 is almost the same as the off-angle.
• the opposing surface 260 of the supporting substrate 26 is inclined by an angle ⁇ with respect to the base substrate 21.
• the facing surface 260 is formed for each row of the semiconductor elements 25 arranged on the base substrate 21. Therefore, it is preferable that the pitch of the semiconductor elements 25 arranged on the base substrate 21 and the pitch of the inclined surfaces 26 formed in large numbers on the support substrate 26 match.
• the semiconductor element 25 is connected to the supporting substrate 16 using a substrate bonding apparatus (not shown).
• the base substrate 21 is attached to the substrate bonding apparatus so that the growth surface 2 13 of the base substrate 21 and the facing surface 260 of the supporting substrate 26 face each other.
• FIG. 10 and 10 are cross-sectional views showing the joining process according to the second embodiment.
• the facing surface 260 of the supporting substrate 26 and the upper surface 25 3 of the semiconductor element 25 are brought into contact with each other. Since the facing surface 260 of the support substrate 26 is inclined. A part of the upper surface 253 of the semiconductor element 25 is in contact with the facing surface 260.
• the supporting substrate 26 is pressed to press the upper surface 25 3 of the semiconductor element 25 against the facing surface 260 of the supporting substrate 26 to make them adhere to each other. , and heated to 3 0 0 ° ⁇ performs a U S n junction.
• half ⁇ 0 2020/175684 1 1 ⁇ (: 171? 2020 /008399
• the semiconductor element 25 is displaced so that the entire upper surface 25 3 of the conductive element 25 comes into contact with the facing surface 260. As a result, a large shear stress is generated at the end portion of the connecting portion 23 of the semiconductor element layer 23, and the connecting portion 23 is broken.
• FIG. 11 is a sectional view showing a peeling step according to the second embodiment.
• the base substrate 21 and the supporting substrate 26 were taken out from the substrate bonding apparatus, and the semiconductor element 25 was bonded to the facing surface 260 of the supporting substrate 26 and was also connected. Since the part 23 is broken, the base substrate 21 can be easily peeled off.
• the columnar connecting portion 23 is attached to the semiconductor element layer 23, but the connecting portion 23 can be removed by polishing or the like.
• the facing surface 260 of the supporting substrate 26 faces the growth surface 2 13 of the base substrate 21 or the upper surface 25 3 of the semiconductor element 25. And then leaning. Therefore, in the bonding step 33, when the upper surface 25 3 of the semiconductor element 25 is pressed against the facing surface 260 of the supporting substrate 26, shear stress concentrates on the end of the connecting portion 23. Sheared. Therefore, the semiconductor element 25 can be reliably separated from the base substrate 21 only by applying pressure with the substrate bonding apparatus without applying force such as ultrasonic waves. In this way, the semiconductor element 25 can be reliably transferred onto the supporting substrate 26 by applying a smaller force to the semiconductor element 25 than before. As a result, the yield of the semiconductor elements 25 can be improved.
• the semiconductor element body 27 of the second embodiment includes the support substrate 26 and the second surface 2 located on the side opposite to the first surface 2 3 3 and the first surface 2 3 3. And the first surface 2 3 3 side is fixed to the supporting substrate 26.
• the semiconductor element body 27 is provided with the semiconductor element layer 23 whose second surface 230 is inclined with respect to the surface of the supporting substrate 26.
• the supporting substrate 26 also has an inclined surface, it is easy to cleave the semiconductor element body 27 and the work for separating into individual semiconductor elements 25 is facilitated.
• the base substrate used in the element forming step 31 and the semiconductor element formed are the same as those in the second embodiment, and therefore the description thereof will be omitted and the same reference numerals will be given.
• FIG. 12 is a cross-sectional view showing the preparation process according to the third embodiment.
• a support substrate 36 for bonding to the semiconductor element 25 is prepared.
• a silicon substrate for example, is used for the base body 3 63 of the support substrate 36.
• a layer of titanium (titanium) is used as an underlayer on the substrate 3 63, and a layer in which an octagonal layer is laminated thereon is formed.
• a strip-shaped mask is formed on the formed layer, and, for example, 8 3 is vapor-deposited.
• a supporting substrate 36 having a facing surface 360 of the metal layer 36 having stripe-shaped concavities and convexities formed thereon is obtained by a vapor deposition lift-off method in which the layer deposited on the mask is removed together with the mask. It is preferable that the pitch at which the semiconductor elements 25 are arranged on the base substrate 21 and the pitch of the stripe-shaped concavities and convexities on the supporting substrate 36 be the same.
• a step portion 36 is formed at the boundary between the concave portion and the convex portion of the facing surface 360.
• FIG. 13 are cross-sectional views showing the joining process according to the third embodiment.
• the facing surface 360 of the supporting substrate 36 and the upper surface 25 3 of the semiconductor element 25 are brought into contact with each other.
• the facing surface 360 of the supporting substrate 36 has a step portion 36. Therefore, a part of the upper surface 253 of the semiconductor element 25 is in contact with the facing surface 360.
• the supporting substrate 36 is pressed, the upper surface 25 3 is pressed against the supporting substrate 36, and the substrate is heated to 300° ⁇ , and the A U S n bonding is performed. I do.
• the step portion 36 of the facing surface 360 is brought into contact with the upper surface 2 53 of the semiconductor element 25, and the upper surface 25 3 of the semiconductor element 25 is ⁇ 0 2020/175684 13 ⁇ (: 171? 2020 /008399
• the semiconductor element 25 is displaced so as to come close to the concave portion of the facing surface 360. As a result, a large shear stress is generated in the contact part 23 of the semiconductor element layer 23 and the contact part
• FIG. 14 is a sectional view showing a peeling step according to the third embodiment.
• the semiconductor element 25 was bonded on the supporting substrate 36, and the connection part 23 was broken. Therefore, the base substrate 21 can be easily peeled off.
• the bonding step 33 the facing surface 360 is flattened, and the metal layer 36 and the metal layer 24 are integrated. That is, the first surface 233 of the semiconductor element layer 23 is also fixed to the facing surface 360 that is the surface of the supporting substrate 36 through the metal.
• the columnar connecting portion 23 is attached to the semiconductor element layer 23, but the connecting portion 23 can be removed by polishing or the like.
• the facing surface 360 of the supporting substrate 36 has the step portion 36. Therefore, when the upper surface 2 53 of the semiconductor element 25 is pressed against the facing surface 360 in the joining step 33, shear stress concentrates on the end of the connecting portion 23 in the base substrate 21 side, The joint 23 is sheared. Therefore, the semiconductor element 25 can be reliably separated from the base substrate 21 by only applying pressure without applying force such as ultrasonic waves. As described above, the semiconductor element 25 can be surely transferred onto the support substrate 36 by applying a smaller force to the semiconductor element 25, and the yield of the semiconductor element 25 can be improved.
• the semiconductor element body 37 joined and peeled by the above method has a stepped portion on the first surface 2 3 3 of the semiconductor element layer 2 3 with respect to the facing surface 360 which is the surface of the supporting substrate 36. It is inclined according to the structure of 3 6 ⁇ 1.
• the semiconductor element body 37 of the third embodiment includes the support substrate 36 and the second surface 2 located on the opposite side to the first surface 2 3 3 and the first surface 2 3 3. And the first surface 2 3 3 side is fixed to the supporting substrate 26. And the semiconductor element body
• 3 7 is at least the first surface 2 3 3 of the first surface 2 3 3 and the second surface 2 3 0. ⁇ 02020/175684 14 ⁇ (: 171? 2020 /008399
• the supporting substrate 26 can also have an inclined surface with a simple structure, and like the second embodiment, the semiconductor element body 37 can be easily cleaved and separated into individual semiconductor elements 25. The work at the time becomes easy.

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• 2020
  • 2020-02-28 CN CN202080016757.3A patent/CN113490995B/zh active Active
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  • 2020-02-28 JP JP2021502652A patent/JP7267394B2/ja active Active
  • 2020-02-28 US US17/434,253 patent/US12132142B2/en active Active
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