WO2020172920A1 - Tft基板的制作方法及tft基板 - Google Patents

Tft基板的制作方法及tft基板 Download PDF

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WO2020172920A1
WO2020172920A1 PCT/CN2019/078588 CN2019078588W WO2020172920A1 WO 2020172920 A1 WO2020172920 A1 WO 2020172920A1 CN 2019078588 W CN2019078588 W CN 2019078588W WO 2020172920 A1 WO2020172920 A1 WO 2020172920A1
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layer
gate
gate insulating
oxide semiconductor
tft substrate
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胡小波
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Definitions

  • the present invention relates to the field of display technology, and in particular to a manufacturing method of a TFT substrate and a TFT substrate.
  • Thin Film Transistor is a current liquid crystal display device (Liquid Crystal Display, LCD) and active matrix organic light-emitting display device (Active Matrix Organic Light-Emitting
  • LCD Liquid Crystal Display
  • AMOLED Active Matrix Organic Light-Emitting
  • AMOLED Active Matrix Organic Light-Emitting
  • Thin film transistors have a variety of structures, and there are also a variety of materials for preparing the active layer of thin film transistors with corresponding structures.
  • metal oxide thin film transistors metal oxide TFT
  • have high field-effect mobility ⁇ 10cm 2 /V ⁇ s
  • the characteristics of simple preparation process, good uniformity of large-area deposition, fast response speed and high transmittance in the visible light range are considered to be the most potential backplane technology for the development of displays in the direction of large size and flexibility.
  • PECVD plasma enhanced chemical vapor deposition
  • GI gate insulating
  • SiNx silicon nitride
  • SiNx silicon nitride
  • SiO 2 silicon oxide
  • the SiNx film and the SiO 2 film together form the GI layer, but the hydrogen (H) content in the SiNx Higher, it is easy to diffuse through the SiO 2 layer to the oxide semiconductor layer, which affects the electrical properties of the device, thereby greatly affecting the display effect of the display.
  • Graphene as the thinnest and hardest nanomaterial in the world currently known, has become one of the current research hotspots due to its good electrical conductivity control, mechanical properties, and thermal conductivity. According to reports, the graphene film produced by the roll-to-roll method has extremely low sheet resistance ( ⁇ 100 ⁇ / ⁇ -1 ), but after doping, a broadband two-dimensional insulating material can be formed; secondly, single-layer graphite Alkene has a good barrier effect on water/oxygen and can effectively prevent the oxidation of metals.
  • fluorinated graphene is directly used as the gate insulating layer and passivation layer, although the barrier and compactness are sufficient, when the graphene is treated with fluorine (F), F ions will affect the oxide semiconductor layer and cause device deterioration ; And the dielectric constant of fluorinated graphene is not necessarily able to be used as a gate insulating layer.
  • the graphene film layer is relatively thin. When used as a gate insulating layer, the capacitance is extremely large, and it is easy to cause a short circuit.
  • the purpose of the present invention is to provide a method for manufacturing a TFT substrate.
  • a fluorine-doped graphene film layer is formed on the gate electrode layer as a gate barrier layer, which can prevent the diffusion of metal atoms in the gate electrode layer and effectively improve the metal oxide TFT. Device characteristics.
  • the purpose of the present invention is also to provide a TFT substrate with a fluorine-doped graphene film layer on the gate electrode layer as a gate barrier layer, which can prevent the diffusion of metal atoms in the gate electrode layer and effectively improve the device of metal oxide TFT characteristic.
  • the present invention provides a method for manufacturing a TFT substrate, which includes the following steps:
  • Step S1 Provide a base substrate, and form a gate electrode layer on the base substrate;
  • Step S2 depositing and forming a graphene film layer on the base substrate and the gate electrode layer;
  • Step S3 performing fluorine doping treatment on the entire surface of the graphene film layer to form a gate barrier layer
  • Step S4 depositing and forming a gate insulating layer on the gate barrier layer, the material of the gate insulating layer is silicon oxide;
  • Step S5 forming an oxide semiconductor layer on the gate insulating layer.
  • the graphene film layer is deposited by a low-temperature chemical vapor deposition method, and the thickness of the graphene film layer is 10 ⁇ to 100 ⁇ .
  • the upper surface of the gate electrode layer is a copper layer
  • the gate electrode layer is a composite layer of a copper film and a molybdenum film, wherein the copper film is located on the upper layer of the composite layer;
  • a plasma enhanced chemical vapor deposition method is used to deposit and form the gate insulating layer.
  • the material of the oxide semiconductor layer is indium gallium zinc oxide.
  • the step S5 further includes depositing and patterning a source and drain electrode layer on the oxide semiconductor layer and the gate insulating layer, and depositing a passivation layer on the source and drain electrode layer, the oxide semiconductor layer and the gate insulating layer.
  • a layer is deposited and patterned on the passivation layer to form a pixel electrode layer.
  • the present invention also provides a TFT substrate, including: a base substrate, a gate electrode layer provided on the base substrate, a gate barrier layer provided on the gate electrode layer and the base substrate, and A gate insulating layer on the gate barrier layer and an oxide semiconductor layer provided on the gate insulating layer;
  • the material of the gate barrier layer is a fluorine-doped graphene film
  • the material of the gate insulating layer is silicon oxide.
  • the thickness of the gate barrier layer is 10 ⁇ -100 ⁇ .
  • the gate electrode layer is a composite layer of a copper film and a molybdenum film, wherein the copper film is located on the upper layer of the composite layer.
  • the material of the oxide semiconductor layer is indium gallium zinc oxide.
  • the TFT substrate further includes a source and drain electrode layer provided on the oxide semiconductor layer and the gate insulating layer, and a passivation layer provided on the source and drain electrode layer, the oxide semiconductor layer and the gate insulating layer And a pixel electrode layer provided on the passivation layer.
  • the manufacturing method of the TFT substrate of the present invention firstly deposits a graphene film layer on the gate electrode layer, and then performs fluorine doping treatment on the entire surface of the graphene film layer to increase the band gap width and make
  • the graphene film layer becomes an insulator to make it a gate barrier layer to prevent the diffusion of metal atoms in the gate electrode layer, and then a silicon oxide layer is deposited on the gate barrier layer as a gate insulating layer on the gate insulating layer
  • An oxide semiconductor layer is formed; by making a fluorine-doped graphene film layer on the gate electrode layer as a gate barrier layer, the silicon oxide layer can be directly used as the gate insulating layer, avoiding the use of hydrogen in the gate insulating layer
  • the high-volume silicon nitride layer reduces the interference of hydrogen on the oxide semiconductor layer, while avoiding direct contact between the oxide semiconductor layer and the fluorine-doped graphene film layer, preventing the interference of fluoride ions on the oxide semiconductor
  • the gate electrode layer is provided with a fluorine-doped graphene film layer as the gate barrier layer, and the silicon oxide layer can be directly used as the gate insulating layer, avoiding the use of hydrogen in the gate insulating layer
  • the high silicon nitride layer reduces the interference of hydrogen on the oxide semiconductor layer, while avoiding direct contact between the oxide semiconductor layer and the fluorine-doped graphene film layer, preventing the interference of fluorine ions on the oxide semiconductor layer, thereby The device characteristics of the metal oxide TFT are effectively improved.
  • Fig. 1 is a schematic flow chart of a method for manufacturing a TFT substrate of the present invention
  • step S1 is a schematic diagram of step S1 of the manufacturing method of the TFT substrate of the present invention.
  • step S2 is a schematic diagram of step S2 of the manufacturing method of the TFT substrate of the present invention.
  • step S3 is a schematic diagram of step S3 of the manufacturing method of the TFT substrate of the present invention.
  • step S4 is a schematic diagram of step S4 of the manufacturing method of the TFT substrate of the present invention.
  • FIG. 6 is a schematic diagram of step S5 of the manufacturing method of the TFT substrate of the present invention and a schematic structural diagram of the TFT substrate of the present invention.
  • the present invention first provides a TFT
  • the manufacturing method of the substrate includes the following steps:
  • step S1 As shown 2 As shown, a base substrate is provided 10 , On the base substrate 10 Deposited and patterned to form a gate electrode layer 20 .
  • the steps S1 , The gate electrode layer 20 The upper surface is a copper layer; further, in this embodiment, the gate electrode layer ( 20 ) Is copper film and molybdenum ( Mo ) The composite layer of the film, wherein the copper film is located on the upper layer of the composite layer and has a thickness of 3000 ⁇ -10000 ⁇ , The molybdenum film is located in the lower layer of the composite layer and has a thickness of 100 ⁇ -500 ⁇ .
  • step S2 As shown 3 As shown, on the base substrate 10 And gate electrode layer 20 Deposited on top to form a graphene film 30 , The graphene film 30 It has high conductivity, high transmittance and high resistance.
  • the steps S2 In the low temperature chemical vapor deposition method ( Chemical Vapor Deposition , CVD ) Deposition to form the graphene film 30 ,
  • the graphene film 30 The thickness is 10 ⁇ -100 ⁇ .
  • step S3 As shown, the graphene film layer 30 Fluorine doping treatment on the entire surface to form a gate barrier layer 31 , Change its band gap width, so that the graphene film becomes an insulator.
  • the graphene film layer 30 It becomes an insulator after fluorine doping treatment, but it still has high transmittance and high resistance characteristics.
  • step S4 As shown, in the gate barrier layer 31 Gate insulating layer 40 , The gate insulating layer 40 It is a silicon oxide layer, and its material is silicon oxide.
  • the gate insulating layer is deposited by plasma enhanced chemical vapor deposition 40 .
  • step S5 As shown 6 As shown, in the gate insulating layer 40 Deposited and patterned to form an oxide semiconductor layer 50 , In the oxide semiconductor layer 50 And gate insulating layer 40 Deposited and patterned to form source and drain electrode layers 60 , In the source and drain electrode layer 60 , Oxide semiconductor layer 50 And gate insulating layer 40 Passivation layer 70 , In the passivation layer 70 Deposited and patterned to form a pixel electrode layer 80 .
  • the oxide semiconductor layer 50 The material is indium gallium zinc oxide ( Indium Gallium Zinc Oxide , IGZO ).
  • TFT The manufacturing method of the substrate, in the gate electrode layer 20 Deposited to form a graphene film 30 , And then on the graphene film 30 The entire surface is doped with fluorine to increase the band gap width and make the graphene film 30 Becomes an insulator, making it a gate barrier 31 To prevent the gate electrode layer 20 The easily diffused metal atoms diffuse, and then in the gate barrier layer 31 Deposit a silicon oxide layer on top as a gate insulating layer 40 , In the gate insulating layer 40 Oxide semiconductor layer 50 ; Through the gate electrode layer 20 Fabricate a fluorine-doped graphene film layer as a gate barrier layer 31 , Can directly use the silicon oxide layer alone as the gate insulating layer 40 , Avoiding the gate insulating layer 40 The use of a silicon nitride layer with high hydrogen content reduces the impact of hydrogen on the oxide semiconductor layer 50 Interference, while avoiding the oxide semiconductor layer 50 Direct contact with the fluorine-doped graphene film layer, eliminating the
  • the manufacturing method of the substrate also provides a TFT
  • the substrate includes: base substrate 10 , Located on the base substrate 10 Gate electrode layer 20 , Located on the gate electrode layer 20 And substrate 10 Gate barrier 31 , Located on the gate barrier layer 31 Gate insulating layer 40 , Located on the gate insulating layer 40 Oxide semiconductor layer 50 , Located on the oxide semiconductor layer 50 And gate insulating layer 40 Source and drain electrode layer 60 , Located on the source and drain electrode layer 60 , Oxide semiconductor layer 50 And gate insulating layer 40 Passivation layer 70 And located on the passivation layer 70 Pixel electrode layer 80 .
  • the gate barrier layer 31 The material is a fluorine-doped graphene film, and the gate barrier layer 31 The fluorine-doped graphene film layer can prevent the gate electrode layer 20 The easily diffused metal atoms diffuse and affect the device characteristics.
  • Gate barrier layer 31 Can prevent the gate electrode layer 20
  • the gate barrier layer 31 The thickness is 10 ⁇ -100 ⁇ .
  • the gate electrode layer 20 The upper surface is a copper layer; further, in this embodiment, the gate electrode layer 20 Is a composite layer of a copper film and a molybdenum film, wherein the copper film is located on the upper layer of the composite layer and has a thickness of 3000 ⁇ -10000 ⁇ , The molybdenum film is located in the lower layer of the composite layer and has a thickness of 100 ⁇ -500 ⁇ .
  • the oxide semiconductor layer 50 The material is indium gallium zinc oxide.
  • gate electrode layer 20 A fluorine-doped graphene film layer is provided as a gate barrier layer 31 , Can directly use the silicon oxide layer alone as the gate insulating layer 40 , Avoiding the gate insulating layer 40 .
  • the use of a silicon nitride layer with high hydrogen content reduces the impact of hydrogen on the oxide semiconductor layer 50 Interference, while avoiding the oxide semiconductor layer 50 Direct contact with the fluorine-doped graphene film layer eliminates the interference of fluorine ions on the oxide semiconductor layer, thereby effectively improving the metal oxide TFT Device characteristics.
  • the present invention TFT
  • the manufacturing method of the substrate is as follows: firstly, a graphene film layer is deposited on the gate electrode layer, and then the entire surface of the graphene film layer is doped with fluorine to increase the band gap width, so that the graphene film layer becomes an insulator, As a gate barrier layer to prevent the diffusion of metal atoms in the gate electrode layer, a silicon oxide layer is deposited on the gate barrier layer as a gate insulating layer, and an oxide semiconductor layer is formed on the gate insulating layer; The fluorine-doped graphene film layer is made on the layer as the gate barrier layer, and the silicon oxide layer can be directly used as the gate insulating layer, avoiding the use of a silicon nitride layer with high hydrogen content in the gate insulating layer and reducing hydrogen Interference to the oxide semiconductor layer, while avoiding direct contact between the oxide semiconductor layer and the fluorine-doped graphene film layer, eliminating the interference of fluorine ions on the oxide semiconductor layer, thereby
  • the gate electrode layer is provided with a fluorine-doped graphene film layer as the gate barrier layer, and the silicon oxide layer can be directly used as the gate insulating layer, avoiding the use of nitridation with high hydrogen content in the gate insulating layer
  • the silicon layer reduces the interference of hydrogen on the oxide semiconductor layer, while avoiding direct contact between the oxide semiconductor layer and the fluorine-doped graphene film layer, eliminating the interference of fluorine ions on the oxide semiconductor layer, thereby effectively improving the metal Oxide TFT Device characteristics.

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  • Thin Film Transistor (AREA)

Abstract

本发明提供一种TFT基板的制作方法及TFT基板。本发明的TFT基板的制作方法，首先在栅电极层上沉积形成石墨烯膜层，再对石墨烯膜层整面进行氟掺杂处理，增大其带隙宽度，使石墨烯膜层变成绝缘体，使其作为栅极阻挡层，以防止栅电极层中金属原子的扩散，再在栅极阻挡层上方沉积氧化硅层作为栅极绝缘层；通过在栅电极层上制作掺氟的石墨烯膜层作为栅极阻挡层，能够直接单独使用氧化硅层作为栅极绝缘层，避免了在栅极绝缘层中使用含氢量高的氮化硅层，减少氢对氧化物半导体层的干扰，同时又避免了氧化物半导体层和掺氟的石墨烯膜层直接接触，杜绝了氟离子对氧化物半导体层的干扰，从而提升了金属氧化物TFT的器件特性。

Description

TFT基板的制作方法及TFT基板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板的制作方法及TFT基板。
 背景技术
薄膜晶体管（Thin Film Transistor，TFT）是目前液晶显示装置（Liquid Crystal Display，LCD）和有源矩阵驱动式有机电致发光显示装置（Active Matrix Organic Light-Emitting Diode，简称AMOLED）中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。
薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管有源层的材料也具有多种，其中，金属氧化物薄膜晶体管（metal oxide TFT）具有场效应迁移率高（≥10cm 2/V·s）、制备工艺简单、大面积沉积均匀性好、响应速度快及可见光范围内透过率高等特点，被认为是显示器朝着大尺寸及柔性化方向发展的最有潜力的背板技术。
随着平板显示技术的发展，人们对显示器尺寸、分辨率和画面刷新速率的追求越来越高，因此业内采用铜（Cu）取代铝（Al）作为TFT器件中的导电金属材料。
现有阵列基板的制作工艺中，通常在栅极形成后通过等离子体增强化学气相沉积法（Plasma Enhanced Chemical Vapor Deposition ，PECVD）沉积栅极绝缘（GI）层，由于PECVD技术是一种高温镀膜技术，对于易扩散的金属离子，很容易在PECVD制程中扩散至临近的介电层，从而影响器件特性；且PECVD机台属于环境敏感性机台，若金属离子扩散至机台反应腔（chamber）中，亦会对沉积膜层的品质产生影响。
Cu在高温和等离子环境中容易产生氧化和扩散问题，故Cu膜在高温制程中不能直接和氧化硅（SiO 2）膜层接触。现有的金属氧化物TFT制程中，通常采用氮化硅（SiNx）隔离Cu膜，再在SiNx上方沉积SiO 2，SiNx膜与SiO 2膜共同形成GI层，但SiNx里面的氢（H）含量较高，容易通过SiO 2层扩散至氧化物半导体层，影响器件电性，进而大大影响显示器的显示效果。
石墨烯作为目前已知的世界上最薄、最坚硬的纳米材料，因其具有良好的导电调控性、机械特性、导热特性，成为当前的研究热点之一。根据报道，使用卷对卷方式生产的石墨烯薄膜具有极低的方块电阻(<100Ω/□ -1)，然而经过掺杂之后，又可以形成宽带系的二维绝缘材料；其次，单层石墨烯对水/ 氧具有良好的阻绝作用，可以有效防止金属的氧化。
现阶段如直接用氟化石墨烯作为栅极绝缘层及钝化层，尽管阻挡性及致密性足够，但石墨烯进行氟（F）处理时，F离子会影响氧化物半导体层，造成器件恶化；且氟化石墨烯的介电常数并不一定能作为栅极绝缘层，石墨烯膜层较薄，作为栅极绝缘层时，电容极大，容易导致短路（short）现象的产生。
 技术问题
本发明的目的在于提供一种TFT基板的制作方法，在栅电极层上制作掺氟的石墨烯膜层作为栅极阻挡层，能够防止栅电极层中金属原子的扩散，有效提升金属氧化物TFT的器件特性。
本发明的目的还在于提供一种TFT基板，栅电极层上设有掺氟的石墨烯膜层作为栅极阻挡层，能够防止栅电极层中金属原子的扩散，有效提升金属氧化物TFT的器件特性。
 技术解决方案
为实现上述目的，本发明提供一种TFT基板的制作方法，包括以下步骤：
步骤S1、提供一衬底基板，在所述衬底基板上形成栅电极层；
步骤S2、在所述衬底基板及栅电极层上沉积形成一石墨烯膜层；
步骤S3、对所述石墨烯膜层整面进行氟摻杂处理，形成栅极阻挡层；
步骤S4、在所述栅极阻挡层上沉积形成栅极绝缘层，所述栅极绝缘层的材料为氧化硅；
步骤S5、在所述栅极绝缘层上形成氧化物半导体层。  
所述步骤S2中，采用低温化学气相沉积法沉积形成所述石墨烯膜层，所述石墨烯膜层的厚度为10Å-100Å。
所述步骤S1中，所述栅电极层的上表面为铜层，所述栅电极层为铜膜与钼膜的复合层，其中，所述铜膜位于所述复合层的上层；
所述步骤S4中，采用等离子体增强化学气相沉积法沉积形成所述栅极绝缘层。
所述步骤S5中，所述氧化物半导体层的材料为铟镓锌氧化物。
所述步骤S5还包括在所述氧化物半导体层及栅极绝缘层上沉积并图案化形成源漏电极层，在所述源漏电极层、氧化物半导体层及栅极绝缘层上沉积形成钝化层，在所述钝化层上沉积并图案化形成像素电极层。
本发明还提供一种TFT基板，包括：衬底基板、设于所述衬底基板上的栅电极层、设于所述栅电极层及衬底基板上的栅极阻挡层、设于所述栅极阻挡层上的栅极绝缘层及设于所述栅极绝缘层上的氧化物半导体层；
所述栅极阻挡层的材料为掺氟的石墨烯膜；
所述栅极绝缘层的材料为氧化硅。
所述栅极阻挡层的厚度为10Å-100Å。
所述栅电极层为铜膜与钼膜的复合层，其中，所述铜膜位于所述复合层的上层。
所述氧化物半导体层的材料为铟镓锌氧化物。
所述的TFT基板还包括设于所述氧化物半导体层及栅极绝缘层上的源漏电极层、设于所述源漏电极层、氧化物半导体层及栅极绝缘层上的钝化层及设于所述钝化层上的像素电极层。
 有益效果
本发明的有益效果：本发明的TFT基板的制作方法，首先在栅电极层上沉积形成石墨烯膜层，再对石墨烯膜层整面进行氟摻杂处理，增大其带隙宽度，使石墨烯膜层变成绝缘体，使其作为栅极阻挡层，以防止栅电极层中金属原子的扩散，再在栅极阻挡层上方沉积氧化硅层作为栅极绝缘层，在栅极绝缘层上形成氧化物半导体层；通过在栅电极层上制作掺氟的石墨烯膜层作为栅极阻挡层，能够直接单独使用氧化硅层作为栅极绝缘层，避免了在栅极绝缘层中使用含氢量高的氮化硅层，减少了氢对氧化物半导体层的干扰，同时又避免了氧化物半导体层和掺氟的石墨烯膜层直接接触，杜绝了氟离子对氧化物半导体层的干扰，从而提升了金属氧化物TFT的器件特性。本发明的TFT基板，栅电极层上设有掺氟的石墨烯膜层作为栅极阻挡层，能够直接单独使用氧化硅层作为栅极绝缘层，避免了在栅极绝缘层中使用含氢量高的氮化硅层，减少了氢对氧化物半导体层的干扰，同时又避免了氧化物半导体层和掺氟的石墨烯膜层直接接触，杜绝了氟离子对氧化物半导体层的干扰，从而有效提升了金属氧化物TFT的器件特性。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明TFT基板的制作方法的流程示意图；
图2为本发明TFT基板的制作方法的步骤S1的示意图；
图3为本发明TFT基板的制作方法的步骤S2的示意图；
图4为本发明TFT基板的制作方法的步骤S3的示意图；
图5为本发明TFT基板的制作方法的步骤S4的示意图；
图6为本发明TFT基板的制作方法的步骤S5的示意图暨本发明的TFT基板的结构示意图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图 1 ，本发明首先提供一种 TFT 基板的制作方法，包括以下步骤：
步骤 S1 、如图 2 所示，提供一衬底基板 10 ，在所述衬底基板 10 上沉积并图案化形成栅电极层 20 。
具体地，所述步骤 S1 中，所述栅电极层 20 的上表面为铜层；进一步地，在本实施例中，所述栅电极层（ 20 ）为铜膜与钼（ Mo ）膜的复合层，其中，所述铜膜位于所述复合层的上层，厚度为 3000 Å -10000Å ，所述钼膜位于所述复合层的下层，厚度为 100 Å -500 Å 。
步骤 S2 、如图 3 所示，在所述衬底基板 10 及栅电极层 20 上沉积形成一石墨烯膜层 30 ，所述石墨烯膜层 30 具有高导电性、高透过率、高阻绝性。
具体地，所述步骤 S2 中，采用低温化学气相沉积法（ Chemical Vapor Deposition ， CVD ）沉积形成所述石墨烯膜层 30 ，所述石墨烯膜层 30 的厚度为 10Å-100Å 。
步骤 S3 、如图 4 所示，对所述石墨烯膜层 30 整面进行氟摻杂处理，形成栅极阻挡层 31 ，改变其带隙宽度，使石墨烯膜层变成绝缘体。
具体地，所述步骤 S3 中，所述石墨烯膜层 30 经过氟摻杂处理后变成绝缘体，但其仍然具有高透过率、高阻绝特性。
步骤 S4 、如图 5 所示，在所述栅极阻挡层 31 上沉积形成栅极绝缘层 40 ，所述栅极绝缘层 40 为氧化硅层，其材料为氧化硅。
具体地，所述步骤 S4 中，采用等离子体增强化学气相沉积法沉积形成所述栅极绝缘层 40 。
步骤 S5 、如图 6 所示，在所述栅极绝缘层 40 上沉积并图案化形成氧化物半导体层 50 ，在所述氧化物半导体层 50 及栅极绝缘层 40 上沉积并图案化形成源漏电极层 60 ，在所述源漏电极层 60 、氧化物半导体层 50 及栅极绝缘层 40 上沉积形成钝化层 70 ，在所述钝化层 70 上沉积并图案化形成像素电极层 80 。
具体地，所述步骤 S5 中，所述氧化物半导体层 50 的材料为铟镓锌氧化物（ Indium Gallium Zinc Oxide ， IGZO ）。
本发明的 TFT 基板的制作方法，在栅电极层 20 上沉积形成石墨烯膜层 30 ，再对石墨烯膜层 30 整面进行氟摻杂处理，增大其带隙宽度，使石墨烯膜层 30 变成绝缘体，使其作为栅极阻挡层 31 ，以防止栅电极层 20 中易扩散的金属原子发生扩散，再在栅极阻挡层 31 上方沉积氧化硅层作为栅极绝缘层 40 ，在栅极绝缘层 40 上形成氧化物半导体层 50 ；通过在栅电极层 20 上制作掺氟的石墨烯膜层作为栅极阻挡层 31 ，能够直接单独使用氧化硅层作为栅极绝缘层 40 ，避免了在栅极绝缘层 40 中使用含氢量高的氮化硅层，减少了氢对氧化物半导体层 50 的干扰，同时又避免了氧化物半导体层 50 和掺氟的石墨烯膜层直接接触，杜绝了氟离子对氧化物半导体层 50 的干扰，从而提升了金属氧化物 TFT 的器件特性。
请参阅图 6 ，基于上述的 TFT 基板的制作方法，本发明还提供一种 TFT 基板包括：衬底基板 10 、设于所述衬底基板 10 上的栅电极层 20 、设于所述栅电极层 20 及衬底基板 10 上的栅极阻挡层 31 、设于所述栅极阻挡层 31 上的栅极绝缘层 40 、设于所述栅极绝缘层 40 上的氧化物半导体层 50 、设于所述氧化物半导体层 50 及栅极绝缘层 40 上的源漏电极层 60 、设于所述源漏电极层 60 、氧化物半导体层 50 及栅极绝缘层 40 上的钝化层 70 及设于所述钝化层 70 上的像素电极层 80 。
具体地，所述栅极阻挡层 31 的材料为掺氟的石墨烯膜，所述栅极阻挡层 31 为掺氟的石墨烯膜层，能够防止栅电极层 20 中易扩散的金属原子发生扩散而影响器件特性。
具体地，由于栅电极层 20 的表面上设有栅极阻挡层 31 ，能够防止栅电极层 20 中易扩散的金属原子发生扩散，从而所述栅极绝缘层 40 可以为单独的氧化硅层，避免了含氢量高的氮化硅层的使用，减少了氢对氧化物半导体层 50 的干扰。
具体地，所述栅极阻挡层 31 的厚度为 10Å-100Å 。
具体地，所述栅电极层 20 的上表面为铜层；进一步地，在本实施例中，所述栅电极层 20 为铜膜与钼膜的复合层，其中，所述铜膜位于所述复合层的上层，厚度为 3000 Å -10000Å ，所述钼膜位于所述复合层的下层，厚度为 100 Å -500 Å 。
具体地，所述氧化物半导体层 50 的材料为铟镓锌氧化物。
本发明的 TFT 基板，栅电极层 20 上设有掺氟的石墨烯膜层作为栅极阻挡层 31 ，能够直接单独使用氧化硅层作为栅极绝缘层 40 ，避免了在栅极绝缘层 40 中使用含氢量高的氮化硅层，减少了氢对氧化物半导体层 50 的干扰，同时又避免了氧化物半导体层 50 和掺氟的石墨烯膜层直接接触，杜绝了氟离子对氧化物半导体层的干扰，从而有效提升了金属氧化物 TFT 的器件特性。
综上所述，本发明的 TFT 基板的制作方法，首先在栅电极层上沉积形成石墨烯膜层，再对石墨烯膜层整面进行氟摻杂处理，增大其带隙宽度，使石墨烯膜层变成绝缘体，使其作为栅极阻挡层，以防止栅电极层中金属原子的扩散，再在栅极阻挡层上方沉积氧化硅层作为栅极绝缘层，在栅极绝缘层上形成氧化物半导体层；通过在栅电极层上制作掺氟的石墨烯膜层作为栅极阻挡层，能够直接单独使用氧化硅层作为栅极绝缘层，避免了在栅极绝缘层中使用含氢量高的氮化硅层，减少氢对氧化物半导体层的干扰，同时又避免了氧化物半导体层和掺氟的石墨烯膜层直接接触，杜绝了氟离子对氧化物半导体层的干扰，从而提升了金属氧化物 TFT 的器件特性。本发明的 TFT 基板，栅电极层上设有掺氟的石墨烯膜层作为栅极阻挡层，能够直接单独使用氧化硅层作为栅极绝缘层，避免了在栅极绝缘层中使用含氢量高的氮化硅层，减少了氢对氧化物半导体层的干扰，同时又避免了氧化物半导体层和掺氟的石墨烯膜层直接接触，杜绝了氟离子对氧化物半导体层的干扰，从而有效提升了金属氧化物 TFT 的器件特性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种TFT基板的制作方法，包括以下步骤：
    步骤S1、提供一衬底基板，在所述衬底基板上形成栅电极层；
    步骤S2、在所述衬底基板及栅电极层上沉积形成一石墨烯膜层；
    步骤S3、对所述石墨烯膜层整面进行氟摻杂处理，形成栅极阻挡层；
    步骤S4、在所述栅极阻挡层上沉积形成栅极绝缘层，所述栅极绝缘层的材料为氧化硅；
    步骤S5、在所述栅极绝缘层上形成氧化物半导体层。  
  2. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤S2中 ，采用低温化学气相沉积法沉积形成所述石墨烯膜层，所述石墨烯膜层的厚度为10Å-100Å。
  3. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤S1中，所述栅电极层为铜膜与钼膜的复合层，其中，所述铜膜位于所述复合层的上层；
    所述步骤S4中，采用等离子体增强化学气相沉积法沉积形成所述栅极绝缘层。
  4. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤S5中，所述氧化物半导体层的材料为铟镓锌氧化物。
  5. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤S5还包括在所述氧化物半导体层及栅极绝缘层上沉积并图案化形成源漏电极层，在所述源漏电极层、氧化物半导体层及栅极绝缘层上沉积形成钝化层，在所述钝化层上沉积并图案化形成像素电极层。
  6. 一种TFT基板，包括：衬底基板、设于所述衬底基板上的栅电极层、设于所述栅电极层及衬底基板上的栅极阻挡层、设于所述栅极阻挡层上的栅极绝缘层及设于所述栅极绝缘层上的氧化物半导体层；
    所述栅极阻挡层的材料为掺氟的石墨烯膜；
    所述栅极绝缘层的材料为氧化硅。
  7. 如权利要求6所述的TFT基板，其中，所述栅极阻挡层的厚度为10Å-100Å。
  8. 如权利要求6所述的TFT基板，其中，所述栅电极层为铜膜与钼膜的复合层，其中，所述铜膜位于所述复合层的上层。
  9. 如权利要求6所述的TFT基板，其中，所述氧化物半导体层的材料为铟镓锌氧化物。
  10. 如权利要求6所述的TFT基板，还包括设于所述氧化物半导体层及栅极绝缘层上的源漏电极层、设于所述源漏电极层、氧化物半导体层及栅极绝缘层上的钝化层及设于所述钝化层上的像素电极层。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579310A (zh) * 2012-07-23 2014-02-12 三星电子株式会社 晶体管及其制造方法
CN105097478A (zh) * 2015-07-24 2015-11-25 深圳市华星光电技术有限公司 在栅极表面生长石墨烯的方法及在源漏极表面生长石墨烯的方法
US20160005881A1 (en) * 2013-04-18 2016-01-07 Fuji Electric Co., Ltd. Stacked films and method for producing stacked films
CN106847930A (zh) * 2017-04-01 2017-06-13 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
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KR20170019338A (ko) * 2014-06-13 2017-02-21 인텔 코포레이션 그래핀을 절연체 및 디바이스에 집적화를 위한 그래핀 플루오르화
CN107331646A (zh) * 2016-04-28 2017-11-07 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN107359169B (zh) * 2017-07-17 2019-08-02 深圳市华星光电半导体显示技术有限公司 一种阵列基板、显示装置及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103579310A (zh) * 2012-07-23 2014-02-12 三星电子株式会社 晶体管及其制造方法
US20160005881A1 (en) * 2013-04-18 2016-01-07 Fuji Electric Co., Ltd. Stacked films and method for producing stacked films
CN105097478A (zh) * 2015-07-24 2015-11-25 深圳市华星光电技术有限公司 在栅极表面生长石墨烯的方法及在源漏极表面生长石墨烯的方法
CN106847930A (zh) * 2017-04-01 2017-06-13 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及制备方法

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