WO2020164303A1 - 显示基板及其制作方法、显示装置 - Google Patents

显示基板及其制作方法、显示装置 Download PDF

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Publication number
WO2020164303A1
WO2020164303A1 PCT/CN2019/125626 CN2019125626W WO2020164303A1 WO 2020164303 A1 WO2020164303 A1 WO 2020164303A1 CN 2019125626 W CN2019125626 W CN 2019125626W WO 2020164303 A1 WO2020164303 A1 WO 2020164303A1
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Prior art keywords
groove
base substrate
sub
substrate
connection line
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PCT/CN2019/125626
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English (en)
French (fr)
Inventor
刘冬妮
玄明花
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京东方科技集团股份有限公司
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Priority to US16/766,603 priority Critical patent/US11114424B2/en
Publication of WO2020164303A1 publication Critical patent/WO2020164303A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the present disclosure relates to the field of display technology, in particular to a display substrate, a manufacturing method thereof, and a display device.
  • the display market is currently booming, and as consumer demand for various display products such as laptops, smart phones, TVs, tablets, smart watches and fitness wristbands continues to increase, more new displays will emerge in the future product.
  • a display substrate including:
  • the display function layer located on the first side surface of the base substrate, the first groove that is provided on the first side surface and is recessed from the first side surface toward the base substrate, and the A first sub-connection line in the first groove and covering the bottom and side walls of the first groove, and the first sub-connection line is connected to the signal input terminal of the display function layer;
  • the integrated circuit located on the second side surface of the base substrate opposite to the first side surface is arranged on the second side surface and faces the base substrate from the second side surface A second groove recessed to the first sub-connection line, and a second sub-connection line located in the second groove, the second sub-connection line being connected to the first sub-connection line and the The signal output terminal of the integrated circuit is connected,
  • the orthographic projection of the first groove on the base substrate and the orthographic projection of the second groove on the base substrate at least partially overlap, and the first groove and the first groove The two grooves communicate with each other and penetrate the base substrate.
  • the cross-sectional area of the first groove parallel to the base substrate in a direction from the first side surface to the second side surface is gradually reduced.
  • the cross-sectional area of the second groove parallel to the base substrate in a direction from the second side surface to the first side surface is gradually reduced.
  • the depth of the first groove in the direction from the first side surface to the second side surface is the depth of the base substrate in the direction from the first side surface to the second side surface.
  • the depth of the first groove in the direction from the first side surface to the second side surface is the depth of the base substrate in the direction from the first side surface to the second side surface. Half of the thickness in the direction of the two side surfaces.
  • the display function layer has a protrusion that protrudes from the first side surface toward the base substrate, and the first sub-connection line covers the protrusion.
  • the first sub-connection line and the second sub-connection line are sequentially stacked on the protrusion in a direction from the first side surface to the second side surface.
  • the embodiment of the present disclosure also provides a display device including the display substrate as described above.
  • the embodiment of the present disclosure also provides a manufacturing method of a display substrate, including:
  • the orthographic projection of the first groove on the base substrate and the orthographic projection of the second groove on the base substrate at least partially overlap, and the first groove and the first groove The two grooves communicate with each other and penetrate the base substrate.
  • the cross-sectional area of the first groove parallel to the base substrate in a direction from the first side surface to the second side surface is gradually reduced.
  • the cross-sectional area of the second groove parallel to the base substrate in a direction from the second side surface to the first side surface is gradually reduced.
  • the integrated circuit is bound on the second side surface, and the signal output terminal of the integrated circuit is connected to the second sub-connection line.
  • the method further includes:
  • a protective layer covering the display function layer is formed.
  • the base substrate is a flexible base
  • the providing the base substrate includes:
  • the flexible base is formed on a rigid carrier, and the second side surface of the flexible base is in contact with the rigid carrier.
  • etching the base substrate to form a first groove recessed from the first side surface toward the base substrate on the first side surface of the base substrate includes:
  • the flexible substrate is etched to form a first groove on the first side surface of the flexible substrate.
  • the etching the base substrate from the second side surface of the base substrate includes:
  • the flexible substrate formed with the display function layer is peeled off from the rigid carrier, and the flexible substrate is etched from the second side surface of the flexible substrate.
  • the method further includes:
  • the transfer of the micro light emitting diode is performed on the first side surface.
  • the depth of the first groove in the direction from the first side surface to the second side surface is the depth of the base substrate in the direction from the first side surface to the second side surface.
  • the depth of the first groove in the direction from the first side surface to the second side surface is the depth of the base substrate in the direction from the first side surface to the second side surface. Half of the thickness in the direction of the two side surfaces.
  • Figure 1 is a schematic diagram of a signal connection line breaking
  • FIG. 2 is a schematic diagram showing the uneven surface of the signal connection line formed by electroplating
  • FIG. 3 is a schematic diagram of forming a flexible substrate on a rigid carrier board according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of forming a first groove on a flexible substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of forming a first sub-connection line according to an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of the embodiment of the disclosure after forming a display functional layer and a protective film;
  • FIG. 7 is a schematic diagram of etching the flexible substrate to expose the first sub-connecting line according to the embodiment of the disclosure
  • FIG. 8 is a schematic diagram of forming a second sub-connection line according to an embodiment of the disclosure.
  • FIG. 9 is a schematic diagram of an embodiment of the disclosure after an integrated circuit is bonded.
  • FIG. 10 is a schematic diagram of the embodiment of the disclosure after the transfer of the MicroLED.
  • FIG. 11 is a schematic diagram of a specific display substrate after the transfer of the MicroLED according to the embodiment of the disclosure.
  • the front surface of the substrate is designed with display film layers such as thin film transistors, and an integrated circuit bonding area is provided on the back of the display substrate, the base substrate of the display substrate is punched, and then metal is filled in the hole to realize the connection of the front and back signals.
  • the signal connection line 4 is prone to open circuit, and then the connection is abnormal, which affects the display effect of the display product; the other is the electroplating method, which is After the through hole is made, as shown in Figure 2, the signal connection line 4 connecting the front and back of the display substrate is formed in the through hole by electroplating. However, after the signal connection line 4 is formed by electroplating, the surface of the signal connection line 4 is uneven.
  • the surface of the signal connection line 4 needs to be planarized, that is, the thicker metal is removed by the chemical mechanical polishing (CMP) process, but the adhesion between the metal and the base substrate is relatively high. Poor, during the CMP process, the metal is easy to fall off, and then the connection is abnormal, which affects the display effect of the display product.
  • CMP chemical mechanical polishing
  • the embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device, which can ensure the display effect of the display device.
  • An embodiment of the present disclosure provides a display substrate, including:
  • a display function layer located on the first side surface of the base substrate, a first recess provided on the first side surface and recessed from the first side surface toward the base substrate, And a first sub-connection line located in the first groove and covering the bottom and side walls of the first groove, the first sub-connection line being connected to the signal input terminal of the display function layer;
  • the integrated circuit located on the second side surface of the base substrate opposite to the first side surface is arranged on the second side surface and faces the base substrate from the second side surface A second groove recessed to the first sub-connection line, and a second sub-connection line located in the second groove, the second sub-connection line being connected to the first sub-connection line and the The signal output terminal of the integrated circuit is connected,
  • the orthographic projection of the first groove on the base substrate and the orthographic projection of the second groove on the base substrate at least partially overlap, and the first groove and the first groove The two grooves communicate with each other and penetrate the base substrate.
  • the cross-sectional area of the first groove parallel to the base substrate gradually decreases in a direction from the first side surface to the second side surface.
  • the cross-sectional area of the second groove parallel to the base substrate in a direction from the second side surface to the first side surface becomes gradually smaller.
  • the signal connection line connecting the integrated circuit and the display function layer is composed of a first sub-connection line and a second sub-connection line.
  • first sub-connection line When the first sub-connection line is made, a first recess that only penetrates part of the base substrate is formed. Groove, and form the first sub-connection line in the first groove, because the depth of the first groove in the direction from the first side surface to the second side surface is smaller than that of the base substrate in the direction from the first side surface to the second side surface. The thickness in the direction that one side surface points to the second side surface.
  • the slope angle of the first groove is relatively large, which can ensure that the first sub-connecting line is not prone to open circuit; when making the second sub-connecting line, form Only part of the second groove of the base substrate is penetrated. Since the depth of the second groove is smaller than the thickness of the base substrate in the direction from the first side surface to the second side surface, the slope of the second groove is The angle is large, so it can ensure that the second sub-connection line is not prone to breakage, thereby ensuring that the signal connection line is not prone to breakage, optimizing the connection between the integrated circuit and the display function layer, and ensuring the display effect of the display device.
  • the display function layer includes film layers such as thin film transistors, insulating layers, contact layers, etc., which can make the micro light-emitting diode display under the drive of electrical signals.
  • the first groove The depth in the direction in which the first side surface points to the second side surface may be one third of the thickness of the base substrate in the direction from the first side surface to the second side surface To two thirds. If the depth of the first groove is greater than two-thirds of the thickness of the base substrate, the slope angle of the first groove is too small, so that the first sub-connection line is likely to be disconnected. If the depth of the first groove is less than one third of the thickness of the base substrate, the slope angle of the second groove directly opposite to the first groove is too small, so that the second sub-connection line is prone to open circuit.
  • the display function layer has a protruding part that protrudes from the first side surface toward the base substrate, and the first sub-connection line covers the protruding part.
  • the first sub-connection line and the second sub-connection line are sequentially stacked and arranged on the protrusion in a direction from the first side surface to the second side surface.
  • the depth of the first groove in the direction from the first side surface to the second side surface is the depth of the base substrate from the first side surface to the second side surface.
  • the depth of the first groove and the second groove are each half of the thickness of the base substrate, which can make the slope angle of the first groove larger and ensure that the first sub-connection line is not easy
  • the slope angle of the second groove can be made larger, which can ensure that the second sub-connecting line is not prone to open circuit, so as to ensure that the signal connection line is not prone to open circuit, and optimize the gap between the integrated circuit and the display function layer
  • the connection status guarantees the display effect of the display device.
  • the embodiment of the present disclosure also provides a display device including the display substrate as described above.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board, and a backplane.
  • the embodiment of the present disclosure also provides a manufacturing method of a display substrate, including:
  • the orthographic projection of the first groove on the base substrate and the orthographic projection of the second groove on the base substrate at least partially overlap, and the first groove and the first groove The two grooves communicate with each other and penetrate the base substrate.
  • the cross-sectional area of the first groove parallel to the base substrate gradually decreases in a direction from the first side surface to the second side surface.
  • the cross-sectional area of the second groove parallel to the base substrate in a direction from the second side surface to the first side surface becomes gradually smaller.
  • the bonding of the integrated circuit is performed on the second side surface, and the signal output terminal of the integrated circuit is connected to the second sub-connection line.
  • the signal connection line connecting the integrated circuit and the display function layer is composed of a first sub-connection line and a second sub-connection line.
  • first sub-connection line When the first sub-connection line is made, a first recess that only penetrates part of the base substrate is formed. Groove, and form the first sub-connection line in the first groove, because the depth of the first groove in the direction from the first side surface to the second side surface is smaller than that of the base substrate in the direction from the first side surface to the second side surface. The thickness in the direction that one side surface points to the second side surface.
  • the slope angle of the first groove is relatively large, which can ensure that the first sub-connecting line is not prone to open circuit; when making the second sub-connecting line, form It only penetrates part of the second groove of the base substrate. Since the depth of the second groove is smaller than the thickness of the base substrate, the slope angle of the second groove is relatively large. Therefore, it can be ensured that the second sub-connecting line is not prone to disconnection, thereby It can ensure that the signal connection line is not easily broken, optimize the connection between the integrated circuit and the display function layer, and ensure the display effect of the display device.
  • the display function layer includes film layers such as thin film transistors, insulating layers, contact layers, etc., which can make the micro light-emitting diode display under the drive of electrical signals.
  • the method further includes:
  • a protective layer covering the display function layer is formed, and the protective layer can protect the display function layer from being damaged in subsequent processes.
  • the base substrate is a flexible base, and the providing of the base substrate includes:
  • the flexible base is formed on a rigid carrier, and the second side surface of the flexible base is in contact with the rigid carrier.
  • Etching the base substrate, and forming a first groove recessed from the first side surface toward the base substrate on the first side surface of the base substrate includes:
  • the flexible substrate is etched to form a first groove on the first side surface of the flexible substrate.
  • the etching the base substrate from the second side surface of the base substrate includes:
  • the flexible substrate formed with the display function layer is peeled off from the rigid carrier, and the flexible substrate is etched from the second side surface of the flexible substrate.
  • the method further includes:
  • the transfer of the micro light emitting diode is performed on the first side surface.
  • the first groove The depth in the direction in which the first side surface points to the second side surface may be one third of the thickness of the base substrate in the direction from the first side surface to the second side surface To two thirds. If the depth of the first groove is greater than two-thirds of the thickness of the base substrate, the slope angle of the first groove is too small, so that the first sub-connection line is likely to be disconnected. If the depth of the first groove is less than one third of the thickness of the base substrate, the slope angle of the second groove directly opposite to the first groove is too small, so that the second sub-connection line is prone to open circuit.
  • the depth of the first groove in the direction from the first side surface to the second side surface is the depth of the base substrate from the first side surface to the second side surface.
  • the depth of the first groove and the second groove each occupies half of the thickness of the base substrate, which can make the slope angle of the first groove larger and ensure that the first sub-connection line is not easy to appear
  • the slope angle of the second groove can also be made larger, which can ensure that the second sub-connecting line is not prone to open circuit, so as to ensure that the signal connection line is not prone to open circuit, and optimize the gap between the integrated circuit and the display function layer
  • the connection status ensures the display effect of the display device.
  • the manufacturing method of the display substrate of this embodiment includes the following steps.
  • Step 1 As shown in FIG. 3, a rigid carrier 5 is provided, and a flexible substrate 1 is formed on the rigid carrier 5.
  • the rigid carrier 5 can be a glass substrate or a quartz substrate, and a layer of polyimide can be coated on the rigid carrier 5 as the flexible base 1.
  • Step 2 As shown in FIG. 4, a first groove 6 is formed on the flexible substrate 1, and the depth of the first groove 6 is half the thickness of the flexible substrate 1.
  • Step 3 As shown in FIG. 5, a first sub-connection line 41 is formed on the flexible substrate 1, and the first sub-connection line 41 covers the bottom and side walls of the first groove 6.
  • a conductive layer may be formed on the flexible substrate 1, and the conductive layer may be patterned to form the first sub-connection line 41.
  • Step 4 As shown in FIG. 6, a display function layer 2 is formed on the flexible substrate 1, and a protective layer 3 covering the display function layer 2 is formed.
  • the display function layer 2 includes thin film transistors, insulating layers, contact layers and other film layers, which can make the micro light-emitting diode display under the drive of electric signals, and the signal input end of the display function layer 2 is connected to the first sub-connection line 41, The electrical signal input through the first sub-connection line 41 can drive the display function layer 2 for display.
  • the protective layer 3 is resistant to high temperature and can protect the display function layer 2 in the subsequent manufacturing process.
  • Step 5 As shown in Figure 7, the protective film 3, the display function layer 2 and the flexible substrate 1 are peeled off the rigid carrier board 5, and the flexible substrate 1 is punched from the side of the flexible substrate 1 away from the display function layer 2.
  • the position of the second groove 7 is directly opposite to the position of the first groove 6 and the first sub-connection line 41 can be exposed.
  • Step 6 As shown in FIG. 8, a second sub-connection line 42 is formed in the second groove 7.
  • a conductive layer such as a Cu layer
  • the Cu layer is patterned to form IC bonding pins and first The second sub-connection line 42 connected by the sub-connection line 41. Since the protective layer 3 is attached to the display function layer 2, it can be ensured that the display function layer 2 is not affected during the evaporation process.
  • Step 7 As shown in FIG. 9, the bonding of the integrated circuit 8 is completed on the side of the flexible substrate 1 away from the display function layer 2.
  • Step 8 As shown in FIG. 10, the protective layer 3 is removed, and the transfer of the micro light-emitting diode 9 is completed on the side of the flexible substrate 1 facing the display function layer 2.
  • the display substrate of this embodiment can be obtained.
  • the integrated circuit 8 is located on the side of the flexible substrate 1 away from the display function layer 2, and the micro light emitting diode 9 and the display function layer 2 are located The other side of the flexible substrate 1.
  • the signal input end of the display function layer 2 is connected to the first sub-connection line 41
  • the signal output end of the integrated circuit 8 is connected to the second sub-connection line 42
  • the first sub-connection line 41 is connected to the second sub-connection line 42
  • the first The sub-connection line 41 and the second sub-connection line 42 constitute a signal connection line connecting the integrated circuit and the display function layer.
  • the first sub-connection line When making the first sub-connection line, a first groove that only penetrates part of the base substrate is formed, and the first sub-connection line is formed in the first groove. Since the depth of the first groove is less than the thickness of the base substrate, Therefore, the slope angle of the first groove is relatively large, which can ensure that the first sub-connecting line is not prone to disconnection; when making the second sub-connecting line, a second groove that only penetrates part of the base substrate is formed.
  • the depth of the groove is smaller than the thickness of the base substrate, and the slope angle of the second groove is large, so it can ensure that the second sub-connection line is not prone to open circuit, thereby ensuring that the signal connection line is not prone to open circuit, and optimize the integrated circuit and display function
  • the connection status between the layers ensures the display effect of the display device.
  • the display function layer 2 includes: a black matrix 10, a bonding contact layer 11, a protective insulating layer 12, a flat layer 13, and a connection electrode (signal of the display function layer) Input terminal) 14, first interlayer insulating layer 15, source and drain electrodes 16 and 17, gate insulating layer 19, gate 20, second interlayer insulating layer 21, active layer 22, and barrier layer 23.
  • the barrier layer 23 is arranged on the side of the flexible substrate 1 away from the second sub-connection line 42 and directly contacts it. The barrier layer 23 is used to prevent the flexible substrate from affecting the active layer 22.
  • the active layer 22 is disposed on the side of the barrier layer 23 away from the flexible substrate 1 and covers only a part of the barrier layer 23.
  • the second interlayer insulating layer 21 is disposed on and in direct contact with the active layer 22 and the barrier layer 23.
  • the gate 20 is disposed on a side of the second interlayer insulating layer 21 away from the flexible substrate 1 and covers only a part of the second interlayer insulating layer 21. Wherein, a part of the first sub-connection line 41 passes through the second interlayer insulating layer 21, the barrier layer 23 and a part of the flexible substrate 1 to directly contact the second sub-connection line 42.
  • the gate insulating layer 19 is disposed on and in direct contact with the gate electrode 20, the second interlayer insulating layer 21 and the first sub-connection line 41.
  • the first interlayer insulating layer 15 is provided on and in direct contact with the gate insulating layer 19.
  • the source and drain electrodes 16, 17 are arranged on the side of the first interlayer insulating layer 15 away from the flexible substrate 1, and part of them pass through the first interlayer insulating layer 15, the gate insulating layer 19, and the second interlayer insulating layer 21, So as to be in direct contact with the active layer 22.
  • the connection electrode (signal input terminal of the display function layer) 14 is provided on the side of the first interlayer insulating layer 15 away from the flexible substrate 1, and a part of it passes through the first interlayer insulating layer 15 and the gate insulating layer 19 to be in contact with The first sub-connection line 41 is in direct contact.
  • the flat layer 13 is provided on and directly in contact with the source and drain electrodes 16, 17, the connection electrode 14, and the first interlayer insulating layer 15.
  • Two bonding contact layers 11 are provided on the side of the flat layer 13 away from the flexible substrate 1, and a part of them penetrates the flat layer 13 to directly contact the source and drain electrodes 16 and 17 and the connection electrode 14 respectively.
  • the bonding contact layer 11 is used to contact the LED electrode 24 of the micro light emitting diode 9, and the bonding contact layer 11 may be made of Cu, Ni, Au or ITO, for example.
  • the protective insulating layer 12 is provided on both sides of the two bonding contact layers 11 and covers the flat layer 13. Wherein, the protective insulating layer 12 may be made of silicon nitride, for example.
  • the black matrix 11 is arranged on the side of the protective insulating layer 12 away from the flexible substrate 1 and in direct contact therewith.
  • the connecting electrode 14 can be considered as a signal input terminal of the display function layer.
  • an additional protective layer (not shown) is provided on the side of the flexible substrate 1 away from the first sub-connection line 41 to cover the flexible substrate 1 and the second sub-connection line 42 and expose the second sub-connection line.
  • a part of the connecting wire 42 is used to connect to the signal output terminal of the integrated circuit 8; the additional protective layer may be made of molybdenum or silicon nitride, for example.

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Abstract

一种显示基板及其制作方法、显示装置。显示基板包括：柔性基底(1)；位于所述柔性基底(1)的第一侧表面上的显示功能层(2)、设置于所述第一侧表面上且自所述第一侧表面朝向所述柔性基底(1)内凹的第一凹槽(6)，和位于所述第一凹槽(6)内且覆盖所述第一凹槽(6)的底部和侧壁的第一子连接线(41)，所述第一子连接线(41)与所述显示功能层(2)的信号输入端连接；位于所述柔性基底(1)的与所述第一侧表面相背的第二侧表面上的集成电路(8)、设置于所述第二侧表面上且自所述第二侧表面朝向所述柔性基底(1)内凹至所述第一子连接线(41)的第二凹槽(7)，和位于所述第二凹槽(7)内的第二子连接线(42)，所述第二子连接线(42)分别与所述第一子连接线(41)和所述集成电路(8)的信号输出端连接。

Description

显示基板及其制作方法、显示装置
相关申请的交叉引用
本公开主张在2019年2月15日在中国提交的中国专利申请号No.201910116828.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，特别是指一种显示基板及其制作方法、显示装置。
背景技术
显示市场目前正在蓬勃发展，并且随着消费者对笔记本电脑、智能手机、电视、平板电脑、智能手表和健身腕带等各类显示产品的需求的持续提升，将来会涌现出更多的新显示产品。
发明内容
一方面，提供一种显示基板，包括：
衬底基板；
位于所述衬底基板的第一侧表面上的显示功能层、设置于所述第一侧表面上且自所述第一侧表面朝向所述衬底基板内凹的第一凹槽和位于所述第一凹槽内且覆盖所述第一凹槽的底部和侧壁的第一子连接线，所述第一子连接线与所述显示功能层的信号输入端连接；
位于所述衬底基板的与所述第一侧表面相背的第二侧表面上的集成电路、设置于所述第二侧表面上且自所述第二侧表面朝向所述衬底基板内凹至所述第一子连接线的第二凹槽，和位于所述第二凹槽内的第二子连接线，所述第二子连接线分别与所述第一子连接线和所述集成电路的信号输出端连接，
其中，所述第一凹槽在所述衬底基板上的正投影与所述第二凹槽在所述衬底基板上的正投影至少部分重叠，并且所述第一凹槽与所述第二凹槽彼此连通而贯穿所述衬底基板。
在一些实施例中，所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上与所述衬底基板平行的截面面积逐渐变小。
在一些实施例中，所述第二凹槽在从所述第二侧表面指向所述第一侧表面的方向上与所述衬底基板平行的截面面积逐渐变小。
在一些实施例中，所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上的深度为所述衬底基板在从所述第一侧表面指向所述第二侧表面的方向上的厚度的三分之一至三分之二。
在一些实施例中，所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上的深度为所述衬底基板在从所述第一侧表面指向所述第二侧表面的方向上的厚度的一半。
在一些实施例中，所述显示功能层具有自所述第一侧表面朝向所述衬底基板外凸的凸出部，所述第一子连接线覆盖所述凸出部。
在一些实施例中，所述第一子连接线和所述第二子连接线在从所述第一侧表面指向所述第二侧表面的方向上依次层叠设置在所述凸出部上。
本公开的实施例还提供了一种显示装置，包括如上所述的显示基板。
本公开的实施例还提供了一种显示基板的制作方法，包括：
提供衬底基板；
对所述衬底基板进行刻蚀，在所述衬底基板的第一侧表面上形成自所述第一侧表面朝向所述衬底基板内凹的第一凹槽；
在所述第一凹槽内形成覆盖所述第一凹槽的底部和侧壁的第一子连接线；
在所述第一侧表面上形成显示功能层，所述显示功能层的信号输入端与所述第一子连接线连接；
从所述衬底基板的与所述第一侧表面相背的第二侧表面对所述衬底基板进行刻蚀，形成暴露出所述第一子连接线的第二凹槽；以及
在所述第二凹槽内形成与所述第一子连接线连接的第二子连接线，
其中，所述第一凹槽在所述衬底基板上的正投影与所述第二凹槽在所述衬底基板上的正投影至少部分重叠，并且所述第一凹槽与所述第二凹槽彼此连通而贯穿所述衬底基板。
在一些实施例中，所述第一凹槽在从所述第一侧表面指向所述第二侧表 面的方向上与所述衬底基板平行的截面面积逐渐变小。
在一些实施例中，所述第二凹槽在从所述第二侧表面指向所述第一侧表面的方向上与所述衬底基板平行的截面面积逐渐变小。
在一些实施例中，在所述第二侧表面进行集成电路的绑定，所述集成电路的信号输出端与所述第二子连接线连接。
在一些实施例中，所述在所述第一侧表面上形成显示功能层之后，所述方法还包括：
形成覆盖所述显示功能层的保护层。
在一些实施例中，所述衬底基板为柔性基底，所述提供衬底基板，包括：
在刚性载板上形成所述柔性基底，所述柔性基底的第二侧表面与所述刚性载板接触。
在一些实施例中，对所述衬底基板进行刻蚀在所述衬底基板的第一侧表面上形成自所述第一侧表面朝向所述衬底基板内凹的第一凹槽包括：
对所述柔性基底进行刻蚀，在所述柔性基底的第一侧表面上形成第一凹槽。
在一些实施例中，所述从所述衬底基板的第二侧表面对所述衬底基板进行刻蚀包括：
将形成有所述显示功能层的柔性基底从所述刚性载板上剥离，从所述柔性基底的第二侧表面对所述柔性基底进行刻蚀。
在一些实施例中，所述在所述第二侧表面进行集成电路的绑定之后，所述方法还包括：
在所述第一侧表面进行微发光二极管的转印。
在一些实施例中，所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上的深度为所述衬底基板在从所述第一侧表面指向所述第二侧表面的方向上的厚度的三分之一至三分之二。
在一些实施例中，所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上的深度为所述衬底基板在从所述第一侧表面指向所述第二侧表面的方向上的厚度的一半。
附图说明
图1为信号连接线出现断路的示意图；
图2为采用电镀方式形成信号连接线的表面凹凸不平的示意图；
图3为本公开的实施例在刚性载板上形成柔性基底的示意图；
图4为本公开的实施例在柔性基底上形成第一凹槽的示意图；
图5为本公开的实施例形成第一子连接线的示意图；
图6为本公开的实施例形成显示功能层和保护膜后的示意图；
图7为本公开的实施例对柔性基底进行刻蚀，暴露出第一子连接线的示意图；
图8为本公开的实施例形成第二子连接线的示意图；
图9为本公开的实施例绑定集成电路后的示意图；
图10为本公开的实施例进行MicroLED转印后的示意图。
图11为本公开的实施例进行MicroLED转印后的一具体显示基板的示意图。
附图标记
1柔性基底；2显示功能层；3保护膜；4信号连接线；41第一子连接线；42第二子连接线；5刚性载板；6第一凹槽；7第二凹槽；8集成电路；9微发光二极管；10黑矩阵；11绑定接触层；12保护绝缘层；13平坦层；14连接电极；15第一层间绝缘层；16、17源漏极；19栅绝缘层；20栅极；21第二层间绝缘层；22有源层；23阻隔层；24LED电极。
具体实施方式
为使本公开的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
目前大多的显示产品都是有边框的，其通常将接线端子(例如集成电路绑定区)设置在显示面板的显示区的外围。而全屏无边框的显示产品，可以使用户获得更好的观看体验，必将引爆新的消费市场。基于此，如何实现全屏无边框的显示产品，是本领域技术人员亟待解决的技术问题。全面屏技术逐渐成为手机等手持设备的主流技术，为了实现真正的无边框显示产品，提 出通过背板正反面工艺和微型发光二极管(MicroLED)转印方式结合实现无边框显示的技术，即在显示基板的正面设计薄膜晶体管等显示膜层，在显示基板的背面设置集成电路绑定区，对显示基板的衬底基板进行打孔，再在孔中填入金属实现正面和背面信号的连接。
目前孔中填入金属的方式有2种，一种为溅射方式，即在制作通孔后，通过溅射方式在通孔中形成连接显示基板正面和背面的信号连接线，但由于衬底基板较厚，通孔的坡度角小，深度大，如图1所示，导致信号连接线4容易出现断路，进而出现连接异常，影响显示产品的显示效果；另一种为电镀方式，即在制作通孔后，如图2所示，通过电镀方式在通孔中形成连接显示基板正面和背面的信号连接线4，但电镀形成信号连接线4后，信号连接线4的表面凹凸不平，为进行后续的集成电路绑定(IC bonding)工艺，需对信号连接线4表面进行平坦化，即采用化学机械抛光(CMP)工艺去除较厚的金属，但金属与衬底基板的粘附力较差，在进行CMP工艺时，金属容易脱落，进而出现连接异常，影响显示产品的显示效果。
本公开的实施例针对上述问题，提供一种显示基板及其制作方法、显示装置，能够保证显示装置的显示效果。
本公开的实施例提供一种显示基板，包括：
衬底基板；
位于所述衬底基板的第一侧表面上的显示功能层、设置于所述第一侧表面上设置有且自所述第一侧表面朝向所述衬底基板内凹的第一凹槽，和位于所述第一凹槽内且覆盖所述第一凹槽的底部和侧壁的第一子连接线，所述第一子连接线与所述显示功能层的信号输入端连接；
位于所述衬底基板的与所述第一侧表面相背的第二侧表面上的集成电路、设置于所述第二侧表面上且自所述第二侧表面朝向所述衬底基板内凹至所述第一子连接线的第二凹槽，和位于所述第二凹槽内的第二子连接线，所述第二子连接线分别与所述第一子连接线和所述集成电路的信号输出端连接，
其中，所述第一凹槽在所述衬底基板上的正投影与所述第二凹槽在所述衬底基板上的正投影至少部分重叠，并且所述第一凹槽与所述第二凹槽彼此连通而贯穿所述衬底基板。
所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上与所述衬底基板平行的截面面积逐渐变小。
所述第二凹槽在从所述第二侧表面指向所述第一侧表面的方向上与所述衬底基板平行的截面面积逐渐变小。
本实施例中，连接集成电路和显示功能层的信号连接线由第一子连接线和第二子连接线组成，在制作第一子连接线时，形成仅贯穿部分衬底基板的第一凹槽，并在第一凹槽内形成第一子连接线，由于第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上的深度小于衬底基板在从所述第一侧表面指向所述第二侧表面的方向上的厚度，因此，第一凹槽的坡度角较大，可以保证第一子连接线不容易出现断路；在制作第二子连接线时，形成仅贯穿部分衬底基板的第二凹槽，由于第二凹槽的深度小于衬底基板在从所述第一侧表面指向所述第二侧表面的方向上的厚度，第二凹槽的坡度角较大，因此可以保证第二子连接线不容易出现断路，从而能够保证信号连接线不容易出现断路，优化集成电路和显示功能层之间的连接状况，保证显示装置的显示效果。
其中，显示功能层包括薄膜晶体管、绝缘层、接触层等膜层，能够在电信号的驱动下使微发光二极管实现显示。
为了使得第一凹槽的坡度角较大，第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上的深度不能过大，因此，所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上的深度可以为所述衬底基板在从所述第一侧表面指向所述第二侧表面的方向上的厚度的三分之一至三分之二。若第一凹槽的深度大于衬底基板的厚度的三分之二，则第一凹槽的坡度角过小，使得第一子连接线容易出现断路。若第一凹槽的深度小于衬底基板的厚度的三分之一，则与第一凹槽正对的第二凹槽的坡度角过小，使得第二子连接线容易出现断路。
所述显示功能层具有自所述第一侧表面朝向所述衬底基板外凸的凸出部，所述第一子连接线覆盖所述凸出部。
所述第一子连接线和所述第二子连接线在从所述第一侧表面指向所述第二侧表面的方向上依次层叠设置在所述凸出部上。
优选地，所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上的深度为所述衬底基板在从所述第一侧表面指向所述第二侧表面的方向上的厚度的一半，这样第一凹槽和第二凹槽的深度各为衬底基板厚度的一半，能够使得第一凹槽的坡度角较大，可以保证第一子连接线不容易出现断路；同时，也可以使得第二凹槽的坡度角较大，可以保证第二子连接线不容易出现断路，从而能够保证信号连接线不容易出现断路，优化集成电路和显示功能层之间的连接状况，保证显示装置的显示效果。
本公开的实施例还提供了一种显示装置，包括如上所述的显示基板。所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
本公开的实施例还提供了一种显示基板的制作方法，包括：
提供衬底基板；
对所述衬底基板进行刻蚀，在所述衬底基板的第一侧表面上形成自所述第一侧表面朝向所述衬底基板内凹的第一凹槽；
在所述第一凹槽内形成覆盖所述第一凹槽的底部和侧壁的第一子连接线；
在所述第一侧表面上形成显示功能层，所述显示功能层的信号输入端与所述第一子连接线连接；
从所述衬底基板的与所述第一侧表面相背的第二侧表面对所述衬底基板进行刻蚀，形成暴露出所述第一子连接线的第二凹槽；以及
在所述第二凹槽内形成与所述第一子连接线连接的第二子连接线，
其中，所述第一凹槽在所述衬底基板上的正投影与所述第二凹槽在所述衬底基板上的正投影至少部分重叠，并且所述第一凹槽与所述第二凹槽彼此连通而贯穿所述衬底基板。
所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上与所述衬底基板平行的截面面积逐渐变小。
所述第二凹槽在从所述第二侧表面指向所述第一侧表面的方向上与所述衬底基板平行的截面面积逐渐变小。
在所述第二侧表面进行集成电路的绑定，所述集成电路的信号输出端与 所述第二子连接线连接。
本实施例中，连接集成电路和显示功能层的信号连接线由第一子连接线和第二子连接线组成，在制作第一子连接线时，形成仅贯穿部分衬底基板的第一凹槽，并在第一凹槽内形成第一子连接线，由于第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上的深度小于衬底基板在从所述第一侧表面指向所述第二侧表面的方向上的厚度，因此，第一凹槽的坡度角较大，可以保证第一子连接线不容易出现断路；在制作第二子连接线时，形成仅贯穿部分衬底基板的第二凹槽，由于第二凹槽的深度小于衬底基板的厚度，第二凹槽的坡度角较大，因此可以保证第二子连接线不容易出现断路，从而能够保证信号连接线不容易出现断路，优化集成电路和显示功能层之间的连接状况，保证显示装置的显示效果。
其中，显示功能层包括薄膜晶体管、绝缘层、接触层等膜层，能够在电信号的驱动下使微发光二极管实现显示。
所述在所述第一侧表面上形成显示功能层之后，所述方法还包括：
形成覆盖所述显示功能层的保护层，保护层可以保护显示功能层在后续工艺中不会被损坏。
所述衬底基板为柔性基底，所述提供衬底基板包括：
在刚性载板上形成所述柔性基底，所述柔性基底的第二侧表面与所述刚性载板接触。
对所述衬底基板进行刻蚀，在所述衬底基板的第一侧表面上形成自所述第一侧表面朝向所述衬底基板内凹的第一凹槽包括：
对所述柔性基底进行刻蚀，在所述柔性基底的第一侧表面上形成第一凹槽。
所述从所述衬底基板的第二侧表面对所述衬底基板进行刻蚀包括：
将形成有所述显示功能层的柔性基底从所述刚性载板上剥离，从所述柔性基底的第二侧表面对所述柔性基底进行刻蚀。
在显示基板为微发光二极管显示基板时，所述在所述第二侧表面进行集成电路的绑定之后，所述方法还包括：
在所述第一侧表面进行微发光二极管的转印。
为了使得第一凹槽的坡度角较大，第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上的深度不能过大，因此，所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上的深度可以为所述衬底基板在从所述第一侧表面指向所述第二侧表面的方向上的厚度的三分之一至三分之二。若第一凹槽的深度大于衬底基板的厚度的三分之二，则第一凹槽的坡度角过小，使得第一子连接线容易出现断路。若第一凹槽的深度小于衬底基板的厚度的三分之一，则与第一凹槽正对的第二凹槽的坡度角过小，使得第二子连接线容易出现断路。
优选地，所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上的深度为所述衬底基板在从所述第一侧表面指向所述第二侧表面的方向上的厚度的一半，这样第一凹槽和第二凹槽的深度各占衬底基板的一半，能够使得第一凹槽的坡度角较大，可以保证第一子连接线不容易出现断路；同时，也可以使得第二凹槽的坡度角较大，可以保证第二子连接线不容易出现断路，从而能够保证信号连接线不容易出现断路，优化集成电路和显示功能层之间的连接状况，保证显示装置的显示效果。
下面以显示基板为柔性微发光二极管显示基板为例，结合附图以及具体的实施例对本公开的显示基板的制作方法进行进一步介绍，本实施例的显示基板的制作方法包括以下步骤。
步骤1、如图3所示，提供刚性载板5，在刚性载板5上形成柔性基底1。
具体地，刚性载板5可以采用玻璃基板或石英基板，可以在刚性载板5上涂覆一层聚酰亚胺作为柔性基底1。
步骤2、如图4所示，在柔性基底1上形成第一凹槽6，第一凹槽6的深度为柔性基底1的厚度的一半。
步骤3、如图5所示，在柔性基底1上形成第一子连接线41，第一子连接线41覆盖第一凹槽6的底部和侧壁。
具体地，可以在柔性基底1上形成一层导电层，对导电层进行构图形成第一子连接线41。
步骤4、如图6所示，在柔性基底1上形成显示功能层2，并形成覆盖显示功能层2的保护层3。
其中，显示功能层2包括薄膜晶体管、绝缘层、接触层等膜层，能够在电信号的驱动下使微发光二极管实现显示，显示功能层2的信号输入端与第一子连接线41连接，通过第一子连接线41输入的电信号能够驱动显示功能层2进行显示。
保护层3耐高温，能够在后续的制程中对显示功能层2进行保护。
步骤5、如图7所示，将保护膜3、显示功能层2以及柔性基底1从刚性载板5上剥离，从柔性基底1远离显示功能层2的一侧对柔性基底1进行打孔，第二凹槽7的位置正对第一凹槽6的位置，能够暴露出第一子连接线41。
步骤6、如图8所示，在第二凹槽7内形成第二子连接线42。
具体地，可以采用蒸镀方式在柔性基底1远离显示功能层2的一侧形成导电层，比如Cu层，对Cu层进行构图，形成与集成电路绑定引脚(IC bonding pin)及第一子连接线41连接的第二子连接线42。由于显示功能层2上贴附有保护层3，因此可以保证显示功能层2在蒸镀工艺中不受影响。
步骤7、如图9所示，在柔性基底1远离显示功能层2的一侧完成集成电路8的绑定。
步骤8、如图10所示，去除保护层3，在柔性基底1朝向显示功能层2的一侧完成微发光二极管9的转印。
经过上述步骤即可得到本实施例的显示基板，如图10所示，本实施例中，集成电路8位于柔性基底1远离显示功能层2的一侧，微发光二极管9和显示功能层2位于柔性基底1的另一侧。显示功能层2的信号输入端与第一子连接线41连接，集成电路8的信号输出端与第二子连接线42连接，第一子连接线41与第二子连接线42连接，第一子连接线41与第二子连接线42组成连接集成电路和显示功能层的信号连接线。在制作第一子连接线时，形成仅贯穿部分衬底基板的第一凹槽，并在第一凹槽内形成第一子连接线，由于第一凹槽的深度小于衬底基板的厚度，因此，第一凹槽的坡度角较大，可以保证第一子连接线不容易出现断路；在制作第二子连接线时，形成仅贯穿部分衬底基板的第二凹槽，由于第二凹槽的深度小于衬底基板的厚度，第二凹槽的坡度角较大，因此可以保证第二子连接线不容易出现断路，从而能够保证信号连接线不容易出现断路，优化集成电路和显示功能层之间的连接状况， 保证显示装置的显示效果。
在一些实施例中，如图11所示，本实施例中，显示功能层2包括：黑矩阵10、绑定接触层11、保护绝缘层12、平坦层13、连接电极(显示功能层的信号输入端)14、第一层间绝缘层15、源漏极16和17、栅绝缘层19、栅极20、第二层间绝缘层21、有源层22和阻隔层23。阻隔层23设置在柔性基底1远离第二子连接线42的一侧上并与之直接接触。其中，阻隔层23用于防止柔性基底影响有源层22。有源层22设置在阻隔层23远离柔性基底1的一侧上并仅覆盖阻隔层23的一部分。第二层间绝缘层21设置在有源层22和阻隔层23上并与之直接接触。栅极20设置在第二层间绝缘层21远离柔性基底1的一侧上并仅覆盖第二层间绝缘层21的一部分。其中，第一子连接线41的一部分穿过第二层间绝缘层21、阻隔层23和一部分柔性基底1，以与第二子连接线42直接接触。栅绝缘层19设置在栅极20、第二层间绝缘层21和第一子连接线41上并与之直接接触。第一层间绝缘层15设置在栅绝缘层19上并与之直接接触。源漏极16、17设置在第一层间绝缘层15远离柔性基底1的一侧上，并且其一部分穿过第一层间绝缘层15、栅绝缘层19和第二层间绝缘层21，以与有源层22直接接触。连接电极(显示功能层的信号输入端)14设置在第一层间绝缘层15远离柔性基底1的一侧上，并且其一部分穿过第一层间绝缘层15和栅绝缘层19，以与第一子连接线41直接接触。平坦层13设置在源漏极16、17、连接电极14和第一层间绝缘层15上并与之直接接触。两个绑定接触层11设置在平坦层13远离柔性基底1的一侧上，并且其一部分穿过平坦层13，以分别与源漏极16、17和连接电极14直接接触。其中，绑定接触层11用于与微发光二极管9的LED电极24接触，并且绑定接触层11例如可以由Cu、Ni、Au或ITO制成。保护绝缘层12设置在两个绑定接触层11的两侧并且覆盖平坦层13。其中，保护绝缘层12例如可以由氮化硅制成。黑矩阵11设置在保护绝缘层12远离柔性基底1的一侧上并与之直接接触。
在一些实施例中，可以认为连接电极14为显示功能层的信号输入端。
在一些实施例中，额外的保护层(未示出)设置在柔性基底1远离第一子连接线41的一侧上，以覆盖柔性基底1和第二子连接线42，并露出第二 子连接线42的一部分用于与集成电路8的信号输出端连接；额外的保护层例如可以由钼或氮化硅制成。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一半技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (19)

  1. 一种显示基板，包括：
    衬底基板；
    位于所述衬底基板的第一侧表面上的显示功能层、设置于所述第一侧表面上且自所述第一侧表面朝向所述衬底基板内凹的第一凹槽，和位于所述第一凹槽内且覆盖所述第一凹槽的底部和侧壁的第一子连接线，所述第一子连接线与所述显示功能层的信号输入端连接；
    位于所述衬底基板的与所述第一侧表面相背的第二侧表面上的集成电路、设置于所述第二侧表面上且自所述第二侧表面朝向所述衬底基板内凹至所述第一子连接线的第二凹槽，和位于所述第二凹槽内的第二子连接线，所述第二子连接线分别与所述第一子连接线和所述集成电路的信号输出端连接，
    其中，所述第一凹槽在所述衬底基板上的正投影与所述第二凹槽在所述衬底基板上的正投影至少部分重叠，并且所述第一凹槽与所述第二凹槽彼此连通而贯穿所述衬底基板。
  2. 根据权利要求1所述的显示基板，其中，所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上与所述衬底基板平行的截面面积逐渐变小。
  3. 根据权利要求1所述的显示基板，其中，所述第二凹槽在从所述第二侧表面指向所述第一侧表面的方向上与所述衬底基板平行的截面面积逐渐变小。
  4. 根据权利要求1所述的显示基板，其中，所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上的深度为所述衬底基板在从所述第一侧表面指向所述第二侧表面的方向上的厚度的三分之一至三分之二。
  5. 根据权利要求1所述的显示基板，其中，所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上的深度为所述衬底基板在从所述第一侧表面指向所述第二侧表面的方向上的厚度的一半。
  6. 根据权利要求1所述的显示基板，其中，所述显示功能层具有自所述第一侧表面朝向所述衬底基板外凸的凸出部，所述第一子连接线覆盖所述凸 出部。
  7. 根据权利要求6所述的显示基板，其中，所述第一子连接线和所述第二子连接线在从所述第一侧表面指向所述第二侧表面的方向上依次层叠设置在所述凸出部上。
  8. 一种显示装置，包括如权利要求1-7中任一项所述的显示基板。
  9. 一种显示基板的制作方法，包括：
    提供衬底基板；
    对所述衬底基板进行刻蚀，在所述衬底基板的第一侧表面上形成自所述第一侧表面朝向所述衬底基板内凹的第一凹槽；
    在所述第一凹槽内形成覆盖所述第一凹槽的底部和侧壁的第一子连接线；
    在所述第一侧表面上形成显示功能层，所述显示功能层的信号输入端与所述第一子连接线连接；
    从所述衬底基板的与所述第一侧表面相背的第二侧表面对所述衬底基板进行刻蚀，形成暴露出所述第一子连接线的第二凹槽；以及
    在所述第二凹槽内形成与所述第一子连接线连接的第二子连接线，
    其中，所述第一凹槽在所述衬底基板上的正投影与所述第二凹槽在所述衬底基板上的正投影至少部分重叠，并且所述第一凹槽与所述第二凹槽彼此连通而贯穿所述衬底基板。
  10. 根据权利要求9所述的显示基板的制作方法，其中，所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上与所述衬底基板平行的截面面积逐渐变小。
  11. 根据权利要求9所述的显示基板的制作方法，其中，所述第二凹槽在从所述第二侧表面指向所述第一侧表面的方向上与所述衬底基板平行的截面面积逐渐变小。
  12. 根据权利要求9所述的显示基板的制作方法，其中，在所述第二侧表面进行集成电路的绑定，所述集成电路的信号输出端与所述第二子连接线连接。
  13. 根据权利要求9所述的显示基板的制作方法，其中，所述在所述第一侧表面上形成显示功能层之后，所述方法还包括：
    形成覆盖所述显示功能层的保护层。
  14. 根据权利要求9所述的显示基板的制作方法，其中，所述衬底基板为柔性基底，所述提供衬底基板包括：
    在刚性载板上形成所述柔性基底，所述柔性基底的第二侧表面与所述刚性载板接触。
  15. 根据权利要求14所述的显示基板的制作方法，其中，对所述衬底基板进行刻蚀，在所述衬底基板的第一侧表面上形成自所述第一侧表面朝向所述衬底基板内凹的第一凹槽包括：
    对所述柔性基底进行刻蚀，在所述柔性基底的第一侧表面上形成第一凹槽。
  16. 根据权利要求14所述的显示基板的制作方法，其中，所述从所述衬底基板的第二侧表面对所述衬底基板进行刻蚀包括：
    将形成有所述显示功能层的柔性基底从所述刚性载板上剥离，从所述柔性基底的第二侧表面对所述柔性基底进行刻蚀。
  17. 根据权利要求12所述的显示基板的制作方法，其中，所述在所述第二侧表面进行集成电路的绑定之后，所述方法还包括：
    在所述第一侧表面进行微发光二极管的转印。
  18. 根据权利要求11所述的显示基板的制作方法，其中，所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上的深度为所述衬底基板在从所述第一侧表面指向所述第二侧表面的方向上的厚度的三分之一至三分之二。
  19. 根据权利要求18所述的显示基板的制作方法，其中，所述第一凹槽在从所述第一侧表面指向所述第二侧表面的方向上的深度为所述衬底基板在从所述第一侧表面指向所述第二侧表面的方向上的厚度的一半。
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