WO2020155466A1 - 一种∑-δ调制器及降低非线性和增益误差的方法 - Google Patents

一种∑-δ调制器及降低非线性和增益误差的方法 Download PDF

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WO2020155466A1
WO2020155466A1 PCT/CN2019/086824 CN2019086824W WO2020155466A1 WO 2020155466 A1 WO2020155466 A1 WO 2020155466A1 CN 2019086824 W CN2019086824 W CN 2019086824W WO 2020155466 A1 WO2020155466 A1 WO 2020155466A1
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Prior art keywords
sampling
voltage signal
reference voltage
input voltage
sigma
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PCT/CN2019/086824
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English (en)
French (fr)
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张明
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江苏润石科技有限公司
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Priority to US17/041,085 priority Critical patent/US11075646B2/en
Publication of WO2020155466A1 publication Critical patent/WO2020155466A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems
    • H03M3/496—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
    • H03M3/326—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors
    • H03M3/338—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by averaging out the errors by permutation in the time domain, e.g. dynamic element matching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/50—Digital/analogue converters using delta-sigma modulation as an intermediate step
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/43—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a single bit one
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/436—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type
    • H03M3/456—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the order of the loop filter, e.g. error feedback type the modulator having a first order loop filter in the feedforward path

Definitions

  • This application relates to the field of ADC analog-to-digital conversion and amplification, and in particular to a sigma-delta modulator.
  • ADC is the English abbreviation of analog-to-digital converter converter. It is an electronic component that can convert analog signals into digital signals. Usually, the signal is sampled and held, and then quantized and encoded. These two processes are at the same time of conversion Achieved.
  • ADC conversion generally has to go through the steps of sampling, holding, quantization, and coding.
  • some processes are combined, such as sampling and holding, quantization and coding are implemented simultaneously in the conversion process.
  • Sampling theorem When the sampling frequency is greater than twice the highest frequency component in the analog signal, the sampled value can reflect the original analog signal without distortion.
  • ADC ADC The main parameters of ADC are:
  • Conversion error which refers to the deviation between the actual measurement range and the theoretical range of the analog input voltage corresponding to each digital quantity after the calibration of the zero point and the full scale and the entire conversion range.
  • the maximum deviation is taken as The index of conversion error usually appears in the form of relative error and expressed in LSB.
  • Conversion speed the time required to complete an analog-to-digital conversion is called conversion time. In most cases, the conversion speed is the inverse of the conversion time.
  • the ADC conversion circuits currently on the market are mainly divided into three types:
  • the conversion speed of pipelined ADC is the highest (conversion time can be less than 50ns)
  • the successive approximation ADC is the second (conversion time is between 10 and 100 ⁇ s)
  • the ⁇ - ⁇ ADC has the lowest conversion speed (conversion time is between tens of milliseconds to hundreds of milliseconds).
  • the ADCs of these three architectures have their own characteristics.
  • the pipeline ADC has higher speed but lower accuracy;
  • the ⁇ - ⁇ ADC can achieve high accuracy and is mainly used in low-speed measurement fields, such as wearable, electronic scale, and medical Electronics, etc.; the successive approximation type is somewhere in between.
  • the existing CN201080018375.0 is used in the 2-stage gain calibration and scaling scheme of switched capacitor ⁇ - ⁇ modulators, as shown in Figure 2.
  • the sampling capacitor pair is divided into R groups of capacitors of the same size.
  • S capacitor groups
  • the R-S capacitor groups are sampling the common-mode voltage signal (or the ground of the single-ended circuit), which contributes zero to the total charge transferred.
  • all R capacitor groups are used to sample and transmit the DAC voltage.
  • the S/R ratio is well achieved by using this technique.
  • S capacitor groups are selected differently among the R groups in a certain sequence at each sampling, so that all R capacitor groups have sampled the input signal after a certain period of time The same amount of times.
  • This sequence is to rotate the input capacitor (the capacitor that samples the input voltage) to average the mismatch error, and if the average is completed for a certain amount of sampling, this technique can significantly reduce the gain error to a low ppm Level.
  • the above method reduces the gain error and introduces the following problems: 1.
  • the size of the integrating capacitor is increased, which increases the overall cost; 2.
  • the integrating capacitor is enlarged and the output swing is large; 3. Overshoot during the conversion of the integrating capacitor Big!
  • This application provides a sigma-delta modulator.
  • This application adopts the following technical solutions: including: multiple sampling capacitors for sampling the input voltage, or sampling the input voltage and the reference voltage signal simultaneously;
  • Integrating capacitor to integrate and superimpose the collected input voltage and reference voltage signal by the sampling capacitor
  • the control component is used to control the switching action, select to sample the reference voltage signal in one cycle, or sample the input voltage and the reference voltage signal at the same time, and in the next cycle, simultaneously sample the input voltage and the reference voltage signal for sampling capacitor clock control.
  • the reference voltage signal is provided by a digital/analog converter.
  • the aforementioned digital/analog converter is controlled by a control component.
  • the reference voltage provided by the digital-to-analog converter is allocated to any pair of sampling capacitors through a switching action, or allocated to an idle sampling capacitor while the input voltage signal is being sampled.
  • each sampling period includes: 1/4 period input voltage signal sampling, 1/2 period charge integration, and 1/2 period reference voltage signal sampling.
  • 1/2 integrated input voltage signal 1/2 integrated reference voltage signal, wherein when integrating the input voltage signal, the integrated reference voltage signal is also superimposed.
  • the sampling method of the sigma-delta modulator, S1, switching action, the sampling capacitor samples the input voltage and the reference voltage signal at the same time; S2, the integrating capacitor integrates and superimposes the input voltage and the reference voltage signal; S3, the switching action, the sampling capacitor performs sampling Input the reference voltage signal; S4, the integrating capacitor performs integration and superposition of the reference voltage signal; S5, repeat S1-S4.
  • a capacitor pair is used to sample the input voltage, and an idle capacitor is used to collect the reference voltage signal.
  • control component controls any pair of switches on the input sampling circuit to close to realize input voltage sampling; controls any switch of the reference voltage signal sampling circuit to close to realize reference voltage signal sampling.
  • any pair of switches on the reference voltage signal is closed, and the corresponding sampling capacitor samples the reference voltage signal.
  • any pair of switches corresponding to the sampling reference voltage signal includes or does not include any switch of the reference voltage signal sampling circuit in S1.
  • control component sequentially controls the switches in S1-S4 to realize periodic sampling and integral coupling.
  • control component controls the pseudo-random number generation sequence to control the switch.
  • control component controls the proportion of the work cycles of S1-S4.
  • this patent When sampling the input, this patent samples the Vref signals of two capacitors at the same time, which can offset the problem of excessive integration capacitor area.
  • this patent uses pseudo-random numbers to control the polling sequence of the capacitors, thereby solving the problem of ⁇ - ⁇ The common Idle tone problem of modulators.
  • the patent can effectively reduce the area of the integrating capacitor while improving the gain error of the sigma-delta modulator, thereby reducing the manufacturing cost of integrated circuits and reducing the output swing.
  • This patent is used in analog-to-digital conversion. The field has a very wide range of practical value!
  • Figure 1 is the technical principle diagram of the existing common ⁇ - ⁇ ADC:
  • Figure 2 is a schematic diagram of the prior art of the ⁇ - ⁇ ADC patent
  • Figure 3 is a schematic diagram of the circuit of the application.
  • FIG. 4 is a control sequence diagram of the application
  • FIG. 5 is a schematic diagram of the allocation of sampling capacitor pairs corresponding to FIG. 4;
  • FIG. 6 is a control sequence diagram of the application
  • FIG. 7 is a schematic diagram of the allocation of sampling capacitor pairs corresponding to FIG. 6;
  • FIG. 8 is a control sequence diagram of the application
  • FIG. 9 is a schematic diagram of the allocation of sampling capacitor pairs corresponding to FIG. 8.
  • FIG. 10 is a control sequence diagram of the application
  • FIG. 11 is a schematic diagram of the allocation of sampling capacitor pairs corresponding to FIG. 10.
  • Figure 1 shows the existing ordinary sigma-delta ADC, which uses the most traditional oversampling technology plus the principle of noise shaping to make low-frequency noise relatively small, thereby achieving high-precision requirements, but nonlinearity is difficult to solve.
  • Figure 2 is based on the ⁇ - ⁇ ADC shown in Figure 1, the input signal and the feedback signal are periodically changed at a fixed frequency, which basically solves the nonlinear problem and solves the nonlinear problem.
  • the control is slightly more complicated.
  • the balanced timing issue makes the integrator very demanding, which causes a huge problem on the chip area and introduces the Idle Tone problem.
  • This application performs special processing on the input signal and feedback signal on the basis of the ordinary ⁇ - ⁇ ADC to solve the nonlinear problem.
  • this application includes: multiple sampling capacitors for sampling the input voltage, or sampling the input voltage and the reference voltage signal simultaneously;
  • Integrating capacitor to integrate and superimpose the collected input voltage and reference voltage signal by the sampling capacitor
  • the control component is used to control the switching action, select to sample the reference voltage signal in one cycle, or sample the input voltage and the reference voltage signal at the same time, and in the next cycle, simultaneously sample the input voltage and the reference voltage signal for sampling capacitor clock control.
  • the reference voltage signal is provided by a digital/analog converter.
  • the aforementioned digital/analog converter is controlled by a control component.
  • the reference voltage provided by the digital-to-analog converter is allocated to any pair of sampling capacitors through a switching action, or allocated to an idle sampling capacitor while the input voltage signal is being sampled.
  • each sampling period includes: 1/4 period input voltage signal sampling, 1/2 period charge integration, and 1/2 period reference voltage signal sampling.
  • 1/2 integrated input voltage signal 1/2 integrated reference voltage signal, wherein when integrating the input voltage signal, the integrated reference voltage signal is also superimposed.
  • Figure 3 shows the principle diagram of this patent, which includes three pairs of sampling capacitors, X, Y, and Z.
  • the six capacitors are the same for sampling the input voltage or sampling the input voltage and the reference voltage signal at the same time.
  • each pair of switches is symmetrically distributed forward input terminal and reverse input terminal; X, Y, Z three pairs of sampling capacitors, Each pair of sampling capacitors is also symmetrically connected to the forward input terminal and the reverse input terminal of the operational amplifier.
  • control components used to control the switching of S1X, S1Y, S1Z, S2X, S2Y, S2Z, S3X, S3Y, S3Z9 pairs of switches, to achieve the switching of X, Y, Z three pairs of sampling capacitors.
  • the sampling method of the sigma-delta modulator, S1, switching action, the sampling capacitor samples the input voltage and the reference voltage signal at the same time; S2, the integrating capacitor integrates and superimposes the input voltage and the reference voltage signal; S3, the switching action, the sampling capacitor performs sampling Input the reference voltage signal; S4, the integrating capacitor performs integration and superposition of the reference voltage signal; S5, repeat S1-S4.
  • a capacitor pair is used to sample the input voltage, and an idle capacitor is used to collect the reference voltage signal.
  • control component controls any pair of switches on the input sampling circuit to close to realize input voltage sampling; controls any switch of the reference voltage signal sampling circuit to close to realize reference voltage signal sampling.
  • any pair of switches on the reference voltage signal is closed, and the corresponding sampling capacitor samples the reference voltage signal.
  • any pair of switches corresponding to the sampling reference voltage signal includes or does not include any switch of the reference voltage signal sampling circuit in S1.
  • control component sequentially controls the switches in S1-S4 to realize periodic sampling and integral coupling.
  • control component controls the pseudo-random number generation sequence to control the switch.
  • control component controls the proportion of the work cycles of S1-S4.
  • the loop of the sampling and integration process uses a pseudo-random number mode to control the cycle sequence of the switch, thereby achieving the overall process control.
  • the pseudo-random number is generated by the control component.

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Abstract

一种∑-Δ调制器及降低非线性和增益误差的方法，包括：多个采样电容器，用于采样输入电压，或同时采样输入电压和基准电压信号；运算放大器；多个开关，用于选择采样输入电压、基准电压信号；积分电容器，对采样电容器对所采集的输入电压和基准电压信号进行积分叠加；控制组件，用于控制一个周期内选择采样基准电压信号，或同时采样输入电压和基准电压信号，以及下个周期内，同时采样输入电压和基准电压信号的采样电容器的时钟控制，在采样输入时，同时采样2个电容的Vref信号，抵消积分电容面积过大，采用伪随机数来控制电容的轮询时序，解决Σ-Δ调制器的Idle tone问题，有效减小积分电容面积，从而减小集成电路的制造成本，减少输出摆幅。

Description

一种∑-Δ调制器及降低非线性和增益误差的方法 技术领域
本申请涉及ADC模数转换及放大领域，尤其涉及∑-Δ调制器。
背景技术
ADC是模数转换器转换器英文简称，是一种能将模拟信号转变为数字信号的电子元件，通常是将信号采样并保持以后，再进行量化和编码，这两个过程是在转化的同时实现的。
ADC的转换一般要经过采样、保持和量化、编码这几个步骤，在实际电路中，有些过程是合并进行的，如采样和保持，量化和编码在转换过程中是同时实现的。
采样定理：当采样频率大于模拟信号中最高频率成分的两倍时，采样值才能不失真的反映原来模拟信号。
ADC的主要参数有：
1.转换精度，集成ADC用分辨率和转换误差来描述转换精度。
2.分辨率，通常以输出二进制或十进制数字的位数表示分辨率的高低，因为位数越多，量化单位越小，对输入信号的分辨能力就越高，例如：输入模拟电压的变化范围为0～5V，输出8位二进制数可以分辨的最小模拟电压为5V×2－8＝20mV；而输出12位二进制数可以分辨的最小模拟电压为5V×2－12≈1.22mV。
3.转换误差，它是指在零点和满度都校准以后，在整个转换范围内，分别测量各个数字量所对应的模拟输入电压实测范围与理论范围之间的偏差，取其中的最大偏差作为转换误差的指标，通常以相对误差的形式出现，并以LSB为单位表示。
4.转换速度，完成一次模数转换所需要的时间称为转换时间，大多数情况下，转换速度是转换时间的倒数。
当前市面上的ADC转换电路主要分成三种类型：
1,流水线型ADC的转换速度最高(转换时间可小于50ns)
2,逐次逼近型ADC次之(转换时间在10～100μs之间)
3,∑-Δ型ADC转换速度最低(转换时间在几十毫秒至数百毫秒之间)。
这3种架构的ADC各有特点，其中流水线型ADC速度较高，但是精度比较低；∑-Δ型ADC是可以做到高精度，主要应用于低速测量领域，譬如穿戴式，电子称，医疗电子等；逐次逼近型介于两者之间。
传统的∑-Δ型ADC由于电容器对不匹配导致存在增益误差、非线性误差，现有CN201080018375.0用于切换式电容器Σ-Δ调制器的2阶段增益校准与缩放方案，图2所示，采用将采样电容器对划分为R个群组的相同大小电容器，每一取样时，在前两个阶段期间使用若干个电容器群组S(其中S≤R)取样及传 送输入信号电压。同时，R-S个电容器群组正对共模电压信号(或单端电路的接地)进行取样，所述信号对所传送总电荷的贡献为零。在最后两个阶段期间使用所有R个电容器群组来取样及传送DAC电压。此处通过使用此技术良好地实现S/R比率。为了使不匹配效应最小化，以某一序列在每一取样时在R个群组当中不同地选择S个电容器群组，使得所有R个电容器群组在某一时间周期之后已对输入信号取样相同量的次数。此序列是使输入电容器(对输入电压进行取样的电容器)旋转以对不匹配误差求平均，且如果针对某一量的取样完成平均值，那么此技术可将增益误差显著减小到低的ppm水平。
采用上述方法减小了增益误差，同时引入了以下问题：1、增加了积分电容器的大小，增加了整体成本；2、积分电容器增大，输出摆幅大；3、积分电容器转换过程中过冲大！
发明内容
本申请提供了∑-Δ调制器，本申请采用以下技术方案：包括：多个采样电容器，用于采样输入电压，或同时采样输入电压和基准电压信号；
运算放大器；
多个开关，用于选择采样输入电压、基准电压信号；
积分电容器，对采样电容器对所采集的输入电压和基准电压信号进行积分叠加；
控制组件，用于控制开关动作，在一个周期内选择采样基准电压信号，或同时采样输入电压和基准电压信号，以及下个周期内，同时采样输入电压和基准电压信号的采样电容器的时钟控制。
优选的，基准电压信号由数/模转换器提供。
优选的，上述数/模转换器由控制组件控制。
优选的，数/模转换器所提供的基准电压通过开关动作，分配给任一对采样电容器，或者在输入电压信号采样的同时分配给闲置的采样电容器。
优选的，每个采样周期内，包括：1/4周期输入电压信号采样、1/2周期电荷积分、1/2周期基准电压信号采样。
优选的，1/2周期电荷积分过程中：1/2积分输入电压信号，1/2积分基准电压信号，其中积分输入电压信号时还叠加积分基准电压信号。
∑-Δ调制器进行采样的方法，S1、开关动作，采样电容器同时采样输入电压和基准电压信号；S2、积分电容器对输入电压和基准电压信号进行积分叠加；S3、开关动作，采样电容器对采样输入基准电压信号；S4、积分电容器对基准电压信号进行积分叠加；S5、重复S1-S4。
优选的，S1中，采用电容器对采样输入电压，并利用闲置电容器采集基准电压信号。
优选的，S1中，控制组件控制输入采样电路上的任一对开关闭合，实现输入电压采样；控制基准电压信号采样电路的任一开关闭合，实现基准电压信号采样。
优选的，S3中，基准电压信号上的任一对开关闭合，对应的采样电容器对采样基准电压信号。
优选的，S3中，采样基准电压信号所对应的任一对开关，包含或不包含S1中的基准电压信号采样电路的任一开关。
优选的，控制组件时序控制S1-S4中的开关切换，实现周期采样、积分耦合。
优选的，控制组件控制伪随机数产生时序来控制开关切换。
优选的，控制组件控制S1-S4的工作周期占比。
本专利在采样输入的时候，同时采样2个电容的Vref信号，可以抵消积分电容面积过大的问题，另外，本专利通过采用伪随机数来控制电容的轮询时序，从而能够解决Σ-Δ调制器普遍存在的Idle tone问题，专利在提高∑-Δ调制器增益误差的同时，能够有效减小积分电容面积，从而减小集成电路的制造成本，减少输出摆幅，本专利在模数转换领域有着非常广泛的实用价值！
附图说明
图1为现有普通∑-ΔADC的技术原理图：
图2为∑-ΔADC专利的现有技术原理图；
图3为本申请电路原理图；
图4为本申请的控制时序图；
图5为图4所对应的采样电容器对的分配示意图；
图6为本申请的控制时序图；
图7为图6所对应的采样电容器对的分配示意图；
图8为本申请的控制时序图；
图9为图8所对应的采样电容器对的分配示意图；
图10为本申请的控制时序图；
图11为图10所对应的采样电容器对的分配示意图。
具体实施方式
图1所示为现有普通的∑-ΔADC，采用最传统的过采样技术加上噪声整形的原理，使得低频噪声比较小，从而实现高精度的要求，但是非线性很难解决。
图2为在图1所示的∑-ΔADC的基础上，对输入信号和反馈信号进行固定频率的周期变化，基本解决非线性问题，解决了非线性问题，但是，控制稍微复杂，由于采用的均衡的时序问题，使得积分器要求很高，从而造成了对芯片的面积巨大的问题，同时引入了Idle Tone问题。
本申请在普通的∑-ΔADC的基础上，对输入信号和反馈信号进行特殊处理，解决非线性问题。
具体的为：本申请中，包括：多个采样电容器，用于采样输入电压，或同时采样输入电压和基准电压信号；
运算放大器；
多个开关，用于选择采样输入电压、基准电压信号；
积分电容器，对采样电容器对所采集的输入电压和基准电压信号进行积分叠加；
控制组件，用于控制开关动作，在一个周期内选择采样基准电压信号，或同时采样输入电压和基准电压信号，以及下个周期内，同时采样输入电压和基准电压信号的采样电容器的时钟控制。
优选的，基准电压信号由数/模转换器提供。
优选的，上述数/模转换器由控制组件控制。
优选的，数/模转换器所提供的基准电压通过开关动作，分配给任一对采样电容器，或者在输入电压信号采样的同时分配给闲置的采样电容器。
优选的，每个采样周期内，包括：1/4周期输入电压信号采样、1/2周期电荷积分、1/2周期基准电压信号采样。
优选的，1/2周期电荷积分过程中：1/2积分输入电压信号，1/2积分基准电压信号，其中积分输入电压信号时还叠加积分基准电压信号。
图3所示为本专利的原理图，包括X、Y、Z三对采样电容器对，六个电容器相同，用于采样输入电压，或同时采样输入电压和基准电压信号。
包括S1X、S1Y、S1Z、S2X、S2Y、S2Z、S3X、S3Y、S3Z9对开关，每对开关的闭合控制一对采样电容器的充电采样。
包括运算放大器，S1X、S1Y、S1Z、S2X、S2Y、S2Z、S3X、S3Y、S3Z9对开关，每对开关对称分布正向输入端、反向输入端；X、Y、Z三对采样电容器对，每对采样电容器对也对称连接在运算放大器的正向输入端、反向输入端。
包括积分电容器，一对积分电容器，分别连接在输出端和正向输入端，输出端和反向输入端。
包括控制组件，用于控制S1X、S1Y、S1Z、S2X、S2Y、S2Z、S3X、S3Y、S3Z9对开关的切换，实现X、Y、Z三对采样电容器对的切换。
∑-Δ调制器进行采样的方法，S1、开关动作，采样电容器同时采样输入电压和基准电压信号；S2、积分电容器对输入电压和基准电压信号进行积分叠加；S3、开关动作，采样电容器对采样输入基准电压信号；S4、积分电容器对基准电压信号进行积分叠加；S5、重复S1-S4。
优选的，S1中，采用电容器对采样输入电压，并利用闲置电容器采集基准电压信号。
优选的，S1中，控制组件控制输入采样电路上的任一对开关闭合，实现输入电压采样；控制基准电压信号采样电路的任一开关闭合，实现基准电压信号采样。
优选的，S3中，基准电压信号上的任一对开关闭合，对应的采样电容器对采样基准电压信号。
优选的，S3中，采样基准电压信号所对应的任一对开关，包含或不包含S1中的基准电压信号采样电路的任一开关。
优选的，控制组件时序控制S1-S4中的开关切换，实现周期采样、积分耦 合。
优选的，控制组件控制伪随机数产生时序来控制开关切换。
优选的，控制组件控制S1-S4的工作周期占比。
结合图4至图11给出一个周期的工作的介绍，让采样输入和采样Vref同时进行，具体为当采样输入时11,12号开关闭合，同时33开关闭合，实现同时在S1时钟项采样输入和反馈的Vref信号，然后I1时钟项把电荷积分到积分电容上；接着在S2时钟项31和32开关闭合，完成采样剩余的反馈信号Vref，然后在I2时钟把电荷再积分到积分电容上；完成一次的采样积分过程。图4中，开关11、12、13闭合。图6中，开关31、32闭合；图8中，开关12、13、21闭合；图10为中，开关22、23闭合；
实际操作中，不限于上述的工作时序以及上述的工作模式，本申请仅给出其中一种采样电容器对的分配情况。
把采样积分Vref过程分开来实现，这样可以解决对放大器要求过高的问题，同时控制采样积分过程的循环采用了伪随机数的模式来控制开关的循环循序，从而实现了对整体过程控制，对于伪随机数的的产生，由控制组件产生。
上述实施例仅例示性说明本申请的原理及其功效，而非用于限制本申请。任何熟悉此技术的人士皆可在不违背本申请的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本申请所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本专利请的权利要求所涵盖。

Claims (14)

  1. [根据细则26改正19.06.2019]
    ∑-Δ调制器，包括：多个采样电容器，用于采样输入电压，或同时采样输入电压和基准电压信号；
    运算放大器；
    多个开关，用于选择采样输入电压、基准电压信号；
    积分电容器，对采样电容器对所采集的输入电压和基准电压信号进行积分叠加；控制组件，用于控制开关动作，在一个周期内选择采样基准电压信号，或同时采样输入电压和基准电压信号，以及下个周期内，同时采样输入电压和基准电压信号的采样电容器的时钟控制。
  2. [根据细则26改正19.06.2019]
    根据权利要求1所述的∑-Δ调制器，其特征在于：基准电压信号由数/模转换器提供。
  3. [根据细则26改正19.06.2019]
    根据权利要求2所述的∑-Δ调制器，其特征在于：上述数/模转换器由控制组件控制。
  4. [根据细则26改正19.06.2019]
    根据权利要求2所述的∑-Δ调制器，其特征在于：数/模转换器所提供的基准电压通过开关动作，分配给任一对采样电容器，或者在输入电压信号采样的同时分配给闲置的采样电容器。
  5. [根据细则26改正19.06.2019]
    根据权利要求1所述的∑-Δ调制器，其特征在于：每个采样周期内，包括：1/4周期输入电压信号采样、1/2周期电荷积分、1/2周期基准电压信号采样。
  6. [根据细则26改正19.06.2019]
    根据权利要求5所述的∑-Δ调制器，其特征在于：1/2周期电荷积分过程中：1/2积分输入电压信号，1/2积分基准电压信号，其中积分输入电压信号时还叠加积分基准电压信号。
  7. [根据细则26改正19.06.2019]
    根据权利要求1所述的∑-Δ调制器进行采样的方法，其特征在于：S1、开关动作，采样电容器同时采样输入电压和基准电压信号；S2、积分电容器对输入电压和基准电压信号进行积分叠加；S3、开关动作，采样电容器对采样输入基准电压信号；S4、积分电容器对基准电压信号进行积分叠加；S5、重复S1-S4。
  8. [根据细则26改正19.06.2019]
    根据权利要求7所述的∑-Δ调制器进行采样的方法，其特征在于：S1中，采用电容器对采样输入电压，并利用闲置电容器采集基准电压信号。
  9. [根据细则26改正19.06.2019]
    根据权利要求8所述的∑-Δ调制器进行采样的方法，其特征在于：S1中，控制组件控制输入采样电路上的任一对开关闭合，实现输入电压采样；控制基准电压信号采样电路的任一开关闭合，实现基准电压信号采样。
  10. [根据细则26改正19.06.2019]
    根据权利要求7所述的∑-Δ调制器进行采样的方法，其特征在于：S3中，基准电压信号上的任一对开关闭合，对应的采样电容器对采样基准电压信号。
  11. [根据细则26改正19.06.2019]
    根据权利要求9所述的∑-Δ调制器进行采样的方法，其特征在于：S3中，采样基准电压信号所对应的任一对开关，包含或不包含S1中的基准电压信号采样电路的任一开关。
  12. [根据细则26改正19.06.2019]
    根据权利要求7所述的∑-Δ调制器进行采样的方法，其特征在于：控 制组件时序控制S1-S4中的开关切换，实现周期采样、积分耦合。
  13. [根据细则26改正19.06.2019]
    根据权利要求12所述的∑-Δ调制器进行采样的方法，其特征在于：控制组件控制伪随机数产生时序来控制开关切换。
  14. [根据细则26改正19.06.2019]
    根据权利要求7所述的∑-Δ调制器进行采样的方法，其特征在于：控制组件控制S1-S4的工作周期占比。
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