WO2020149128A1 - Procédé de production de cellules solaires - Google Patents

Procédé de production de cellules solaires Download PDF

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Publication number
WO2020149128A1
WO2020149128A1 PCT/JP2019/050858 JP2019050858W WO2020149128A1 WO 2020149128 A1 WO2020149128 A1 WO 2020149128A1 JP 2019050858 W JP2019050858 W JP 2019050858W WO 2020149128 A1 WO2020149128 A1 WO 2020149128A1
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layer
semiconductor layer
type semiconductor
forming step
optical adjustment
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PCT/JP2019/050858
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English (en)
Japanese (ja)
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貴久 藤本
寛隆 石橋
足立　大輔
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株式会社カネカ
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Priority to JP2020566179A priority Critical patent/JP7101264B2/ja
Publication of WO2020149128A1 publication Critical patent/WO2020149128A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer

Definitions

  • the present invention relates to a method for manufacturing a back electrode type (back contact type) solar cell.
  • a solar cell using a semiconductor substrate there are a double-sided electrode type solar cell in which electrodes are formed on both the light-receiving surface side and the back surface side, and a back electrode type solar cell in which electrodes are formed only on the back surface side.
  • a double-sided electrode type solar cell since an electrode is formed on the light receiving surface side, sunlight is blocked by this electrode.
  • the back surface electrode type solar cell since no electrode is formed on the light receiving surface side, the light receiving rate of sunlight is higher than that in the double sided electrode type solar cell.
  • Patent Documents 1 and 2 disclose back electrode type solar cells.
  • the solar cell described in Patent Document 1 includes a semiconductor substrate that functions as a photoelectric conversion layer, a first intrinsic semiconductor layer, a first conductivity type semiconductor layer, and a first electrode layer that are sequentially stacked on a part of the back surface side of the semiconductor substrate. And a second intrinsic semiconductor layer, a second conductivity type semiconductor layer, and a second electrode layer, which are sequentially stacked on another portion on the back surface side of the semiconductor substrate.
  • the solar cell also includes a third intrinsic semiconductor layer and an optical adjustment layer, which are sequentially stacked on the light-receiving surface side of the semiconductor substrate.
  • the optical adjustment layer functions as an antireflection layer that reduces reflection of incident light.
  • an etching method using a photolithography technique is used.
  • an alkaline solution as the solution for stripping the photoresist.
  • the alkaline solution will dissolve the third intrinsic semiconductor layer via the pinholes in the optical adjustment layer. Therefore, the lifetime of the carrier is reduced and the performance of the solar cell is reduced.
  • Patent Document 1 describes a technique of forming a protective layer on the optical adjustment layer on the light-receiving surface side of a semiconductor substrate.
  • the protective layer remains on the light receiving surface side of the solar cell, the effect of reducing the reflection of incident light is reduced, and the performance of the solar cell is reduced.
  • Patent Document 2 describes a technique of forming an optical adjustment layer on the light receiving surface side of a semiconductor substrate after patterning the first conductivity type semiconductor layer and patterning the second conductivity type semiconductor layer.
  • An object of the present invention is to provide a method for manufacturing a solar cell, which can reduce the cost of the solar cell and suppress the performance deterioration.
  • a method for manufacturing a solar cell according to the present invention includes a semiconductor substrate, a first intrinsic semiconductor layer, and a first conductivity type semiconductor layer, which are sequentially stacked on a part of the other main surface side opposite to the one main surface side of the semiconductor substrate.
  • a back electrode type solar cell including a first electrode layer, a second intrinsic semiconductor layer, a second conductivity type semiconductor layer, and a second electrode layer, which are sequentially stacked on another part of the other main surface side of the semiconductor substrate.
  • a sacrificial layer, the sacrificial layer is a third intrinsic semiconductor layer from a solution for removing a resist used for patterning in at least one of the first conductive type semiconductor layer forming step and the second conductive type semiconductor layer forming step. While protecting the optical adjustment layer, a part is removed in the first conductive type semiconductor layer forming step, the second conductive type semiconductor layer forming step, or the electrode layer forming step, and all are removed after the electrode layer forming step. There is.
  • FIG. 1 is a view of the solar cell according to the present embodiment as viewed from the back surface side.
  • the solar cell 1 shown in FIG. 1 is a back electrode type solar cell.
  • the solar cell 1 includes an n-type (second conductivity type) semiconductor substrate 11 having two main surfaces, and a p-type (first conductivity type) region 7 and an n-type (second conductivity type) on the main surface of the semiconductor substrate 11. ) Region 8 and.
  • the p-type region 7 has a so-called comb shape, and has a plurality of finger portions 7f corresponding to comb teeth and a bus bar portion 7b corresponding to a supporting portion of the comb teeth.
  • the bus bar portion 7b extends in the first direction (X direction) along one side portion of the semiconductor substrate 11, and the finger portion 7f extends from the bus bar portion 7b in the first direction (X direction).
  • the n-type region 8 has a so-called comb shape, and has a plurality of finger portions 8f corresponding to comb teeth and a bus bar portion 8b corresponding to a supporting portion for the comb teeth.
  • the bus bar portion 8b extends in the first direction (X direction) along the other side portion facing the one side portion of the semiconductor substrate 11, and the finger portion 8f extends from the bus bar portion 8b in the second direction (Y direction). Direction).
  • the finger portions 7f and the finger portions 8f are alternately provided in the first direction (X direction).
  • the p-type region 7 and the n-type region 8 may be formed in stripes.
  • the p-type semiconductor layer and the n-type semiconductor layer overlap with each other, as described later.
  • the solar cell 1 includes an intrinsic semiconductor layer (third intrinsic semiconductor layer) 13 sequentially stacked on the light receiving surface side which is one of the main surfaces of the semiconductor substrate 11 on the light receiving side. And an optical adjustment layer 15.
  • the solar cell 1 has an intrinsic semiconductor layer sequentially laminated on a part (mainly, p-type region 7) of the back surface which is the other main surface of the main surface of the semiconductor substrate 11 opposite to the light receiving surface.
  • a (first intrinsic semiconductor layer) 23, a p-type (first conductivity type) semiconductor layer 25, and a first electrode layer 27 are provided.
  • the solar cell 1 includes an intrinsic semiconductor layer (second intrinsic semiconductor layer) 33 and an n-type (second conductive layer) that are sequentially stacked on another part (mainly, the n-type region 8) on the back surface side of the semiconductor substrate 11.
  • (Type) semiconductor layer 35 and a second electrode layer 37 are sequentially stacked on another part (mainly, the n-type region 8) on the back surface side of the semiconductor substrate 11.
  • the semiconductor substrate 11 is formed of a crystalline silicon material such as single crystal silicon or polycrystalline silicon.
  • the semiconductor substrate 11 is, for example, an n-type semiconductor substrate in which a crystalline silicon material is doped with an n-type dopant. Examples of the n-type dopant include phosphorus (P).
  • the semiconductor substrate 11 functions as a photoelectric conversion substrate that absorbs incident light from the light receiving surface side and generates photocarriers (electrons and holes).
  • crystalline silicon as a material of the semiconductor substrate 11
  • the intrinsic semiconductor layer 13 is formed on the light receiving surface side of the semiconductor substrate 11.
  • the intrinsic semiconductor layer 23 is formed in the p-type region 7 and the boundary region 9 on the back surface side of the semiconductor substrate 11.
  • the intrinsic semiconductor layer 33 is formed in the n-type region 8 and the boundary region 9 on the back surface side of the semiconductor substrate 11.
  • the intrinsic semiconductor layers 13, 23, 33 are formed of, for example, a material whose main component is intrinsic (i-type) amorphous silicon.
  • the intrinsic semiconductor layers 13, 23, 33 function as so-called passivation layers, suppress recombination of carriers generated in the semiconductor substrate 11, and improve carrier recovery efficiency.
  • the optical adjustment layer 15 is formed on the intrinsic semiconductor layer 13 on the light receiving surface side of the semiconductor substrate 11.
  • the optical adjustment layer 15 functions as an antireflection layer that prevents reflection of incident light, and also functions as a protective layer that protects the light receiving surface side of the semiconductor substrate 11 and the intrinsic semiconductor layer 13.
  • the optical adjustment layer 15 is formed of an insulating material such as silicon oxide (SiO), silicon nitride (SiN), or a composite material thereof such as silicon oxynitride (SiON).
  • the optical adjustment layer 15 is a layer that remains when the solar cell is completed, although it may be dissolved to some extent by etching because it is protected by the sacrificial layers 41 and 43 described later.
  • the p-type semiconductor layer 25 is formed on the intrinsic semiconductor layer 23, that is, in the p-type region 7 and the boundary region 9 on the back surface side of the semiconductor substrate 11.
  • the p-type semiconductor layer 25 is made of, for example, an amorphous silicon material.
  • the p-type semiconductor layer 25 is, for example, a p-type semiconductor layer obtained by doping an amorphous silicon material with a p-type dopant. Examples of p-type dopants include boron (B).
  • the n-type semiconductor layer 35 is formed on the intrinsic semiconductor layer 33, that is, in the n-type region 8 and the boundary region 9 on the back surface side of the semiconductor substrate 11.
  • the n-type semiconductor layer 35 is formed of, for example, an amorphous silicon material.
  • the n-type semiconductor layer 35 is, for example, an n-type semiconductor layer in which an amorphous silicon material is doped with an n-type dopant (for example, phosphorus (P) described above).
  • the first electrode layer 27 is formed on the p-type semiconductor layer 25, and the second electrode layer 37 is formed on the n-type semiconductor layer 35.
  • the first electrode layer 27 has a transparent electrode layer 28 and a metal electrode layer 29 that are sequentially stacked on the p-type semiconductor layer 25.
  • the second electrode layer 37 has a transparent electrode layer 38 and a metal electrode layer 39 which are sequentially stacked on the n-type semiconductor layer 35.
  • the transparent electrode layers 28 and 38 are made of a transparent conductive material. Examples of the transparent conductive material include ITO (Indium Tin Oxide: composite oxide of indium oxide and tin oxide).
  • the metal electrode layers 29 and 39 are formed of a conductive paste material containing a metal powder such as silver.
  • FIG. 6A is a diagram showing a part of an optical adjustment layer forming step and a first conductivity type semiconductor layer forming step in a conventional solar cell manufacturing method
  • FIGS. 6B to 6D show a conventional solar cell manufacturing method. It is a figure which shows the remainder of the 1st conductivity type semiconductor layer formation process
  • 6E and 6F are diagrams showing a second conductivity type semiconductor layer forming step in the conventional solar cell manufacturing method
  • FIGS. 6G to 6I are electrode layer forming steps in the conventional solar cell manufacturing method.
  • FIG. 7 and 8 are diagrams for explaining the first problem and the second problem in the conventional method for manufacturing a solar cell, respectively.
  • the intrinsic semiconductor layer material film 23ZX and the p-type semiconductor layer material film 25ZX are sequentially stacked on the entire rear surface of the semiconductor substrate 11X by using, for example, a CVD method (chemical vapor deposition method). (Film formation) (first conductivity type semiconductor layer forming step). Further, an insulating layer such as SiO may be laminated on the p-type semiconductor layer material film 25ZX.
  • the intrinsic semiconductor layer 13X and the optical adjustment layer 15X are sequentially laminated (formed into a film) on the entire light-receiving surface side of the semiconductor substrate 11X by using, for example, the CVD method (optical adjustment layer forming step).
  • the order of forming the intrinsic semiconductor layer material film 23ZX and the p-type semiconductor layer material film 25ZX, and the intrinsic semiconductor layer 13X and the optical adjustment layer 15X is not limited.
  • the intrinsic semiconductor layer material film 23ZX and the p-type semiconductor layer material film 25ZX in the n-type region 8 are removed on the back surface side of the semiconductor substrate 11X by using the photolithography method.
  • the intrinsic semiconductor layer 23X and the p-type semiconductor layer 25X are patterned (first conductivity type semiconductor layer forming step).
  • the photoresist 90X in the n-type region 8 on the back surface side is exposed and developed to be removed.
  • the intrinsic semiconductor layer 23X and the p-type semiconductor layer 25X are patterned by using an etching method using the photoresist 90X as a mask.
  • an etching solution for the p-type semiconductor layer material film for example, an acidic solution such as a mixed solution of hydrofluoric acid and nitric acid is used.
  • the photoresist 90X is removed.
  • An inexpensive alkaline solution is used as an etching solution for the photoresist 90X. At this time, the first problem occurs (details will be described later).
  • the p-type semiconductor layer 25X is patterned so that part or all of the intrinsic semiconductor layer material film 23ZX in the n-type region 8 on the back surface side of the semiconductor substrate 11X is left. Good.
  • first cleaning step both sides of the semiconductor substrate 11X are cleaned.
  • hydrofluoric acid treatment includes not only hydrofluoric acid but also treatment with a mixture of hydrofluoric acid and another type of acid (for example, hydrochloric acid in the first washing step).
  • the second problem occurs (details will be described later).
  • the intrinsic semiconductor layer material film 33ZX and the n-type semiconductor layer material film 35ZX are sequentially laminated (film formation) on the entire rear surface of the semiconductor substrate 11X by using, for example, the CVD method. Second conductive type semiconductor layer forming step).
  • the intrinsic semiconductor layer material film 33ZX and the n-type semiconductor layer material film 35ZX in the p-type region 7 are removed on the back surface side of the semiconductor substrate 11X.
  • the intrinsic semiconductor layer 33X and the n-type semiconductor layer 35X are patterned (second conductivity type semiconductor layer forming step).
  • etching is performed using an alkaline solution with the photoresist 90X as a mask, and then the photoresist 90X is peeled off using an organic solvent.
  • the second conductivity type semiconductor layer forming step may include the intrinsic semiconductor layer material.
  • the n-type semiconductor layer 35X may be patterned without stacking (depositing) the film.
  • the first conductivity type semiconductor layer forming step when a part of the intrinsic semiconductor layer material film 23ZX in the n-type region 8 on the back surface side of the semiconductor substrate 11X remains, it is removed in the second conductivity type semiconductor layer forming step.
  • the intrinsic semiconductor layer material film may be stacked (formed) by the amount, and the intrinsic semiconductor layer and the n-type semiconductor layer 35X may be patterned.
  • a transparent electrode layer material film 28ZX is laminated (film formation) on the entire back surface side of the semiconductor substrate 11X by using a PVD method (physical vapor deposition method) such as a sputtering method. (Electrode layer forming step).
  • the transparent electrode layers 28X and 38X are patterned by removing a part of the transparent electrode layer material film 28ZX by using, for example, an etching method using an etching paste (electrode layer). Forming process).
  • an etching method using an etching paste (electrode layer). Forming process).
  • the etching solution for the transparent electrode layer material film for example, hydrochloric acid or ferric chloride aqueous solution is used.
  • a metal electrode layer 29X is formed on the transparent electrode layer 28X and a metal electrode layer 39X is formed on the transparent electrode layer 38X by using, for example, a printing method or a coating method.
  • the first electrode layer 27X and the second electrode layer 37X are formed.
  • the conventional back electrode type solar cell 1X is completed.
  • the pin of the optical adjustment layer 15X is formed.
  • the dissolution of the intrinsic semiconductor layer 13X through the holes 15h is suppressed, the cost is increased.
  • .Thickening the thickness of the optical adjustment layer, or .Multilayered optical adjustment layer Is possible. However, a clean film forming environment (work in a clean room) requires a large capital investment cost. Increasing the thickness of the optical adjustment layer is not preferable in terms of solar cell performance. Multilayering of the optical adjustment layer is not easy because of an increase in manufacturing process and cost.
  • the inventors of the present application protect the intrinsic semiconductor layer 13 and the optical adjustment layer 15 during the manufacturing process of the solar cell 1 and protect the sacrificial layer that is naturally removed during the manufacturing process from the light receiving surface side. It was devised to form it on the optical adjustment layer 15.
  • FIG. 3A is a diagram showing a part of the optical adjustment layer forming step, the sacrificial layer forming step, and the first conductivity type semiconductor layer forming step in the method for manufacturing a solar cell according to the present embodiment
  • FIGS. 3B to 3D are It is a figure which shows the remainder of the 1st conductivity type semiconductor layer formation process in the manufacturing method of the solar cell which concerns on this embodiment.
  • 3E is a diagram showing a first cleaning step in the method for manufacturing a solar cell according to this embodiment, and FIGS.
  • 3F and 3G are second conductivity type semiconductors in the method for manufacturing a solar cell according to this embodiment. It is a figure which shows a layer formation process. 3H and 3I are diagrams showing an electrode layer forming step in the method for manufacturing the solar cell according to the present embodiment.
  • the intrinsic semiconductor layer material film 23Z and the p-type semiconductor layer material film 25Z are sequentially laminated (film-formed) on the entire back surface of the semiconductor substrate 11 by using, for example, a CVD method. 1-conductivity type semiconductor layer forming step).
  • the intrinsic semiconductor layer 13 and the optical adjustment layer 15 are sequentially stacked (formed) on the entire surface of the semiconductor substrate 11 on the light receiving surface side by using, for example, the CVD method (optical adjustment layer forming step).
  • the lower sacrifice layer 41 and the upper sacrifice layer 43 are sequentially laminated (film formation) on the entire surface of the semiconductor substrate 11 on the light receiving surface side, specifically, on the entire surface of the optical adjustment layer 15 by using the CVD method.
  • the lower sacrificial layer 41 is formed of a material whose main component is silicon.
  • the lower sacrificial layer 41 has resistance to acid treatment, for example, hydrofluoric acid treatment (treatment with hydrofluoric acid or a mixture of hydrofluoric acid and another type of acid), and the lower sacrificial layer 41 can be easily treated with an alkaline solution. To be removed.
  • the upper sacrificial layer 43 is formed of a material such as silicon oxide (SiO), silicon nitride (SiN), or a composite thereof such as silicon oxynitride (SiON). As a result, the upper sacrificial layer 43 has resistance to an alkaline solution and is easily removed by hydrofluoric acid treatment (treatment with hydrofluoric acid or a mixture of hydrofluoric acid and another type of acid).
  • the film thickness of the upper sacrificial layer 43 is preferably, for example, 5 nm or more and 300 nm or less.
  • the intrinsic semiconductor layer material film 23Z and the p-type semiconductor layer material film 25Z in the n-type region 8 are removed on the back surface side of the semiconductor substrate 11 by using a photolithography method.
  • the intrinsic semiconductor layer 23 and the p-type semiconductor layer 25 are patterned. That is, the patterned intrinsic semiconductor layer 23 and the p-type semiconductor layer 25 are formed on the back surface side of the semiconductor substrate 11 (first conductivity type semiconductor layer forming step).
  • the photoresist 90 in the n-type region 8 is exposed and developed on the back surface side to be removed.
  • the intrinsic semiconductor layer 23 and the p-type semiconductor layer 25 are patterned by using the etching method using the photoresist 90 as a mask.
  • the etching solution for the p-type semiconductor layer material film for example, an acidic solution such as a mixed solution of hydrofluoric acid and nitric acid is used.
  • the photoresist 90 is removed.
  • An inexpensive alkaline solution is used as an etching solution for the photoresist 90.
  • the upper sacrificial layer 43 protects the intrinsic semiconductor layer 13 and the optical adjustment layer 15 from the alkaline solution that removes the photoresist 90. Therefore, even if the optical adjustment layer 15 has pinholes, dissolution of the intrinsic semiconductor layer 13 by the alkaline solution is suppressed.
  • the p-type semiconductor layer 25 is patterned so as to leave a part or all of the intrinsic semiconductor layer material film 23Z in the n-type region 8 on the back surface side of the semiconductor substrate 11. Good.
  • both surface sides of the semiconductor substrate 11 are cleaned (first cleaning step).
  • first cleaning step for example, after performing ozone treatment, hydrofluoric acid treatment (treatment with hydrofluoric acid or a mixture of hydrofluoric acid and another type of acid) is performed.
  • the upper sacrificial layer 43 is removed by the hydrofluoric acid treatment.
  • the lower sacrificial layer 41 protects the surface of the optical adjustment layer 15 from the hydrofluoric acid treatment. Therefore, the etching of the surface of the optical adjustment layer 15 is suppressed.
  • the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer material film 35Z are sequentially laminated (formed) on the entire back surface side of the semiconductor substrate 11 by using, for example, a CVD method ( Second conductive type semiconductor layer forming step).
  • the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer material film 35Z in the p-type region 7 are removed on the back surface side of the semiconductor substrate 11 by using a photolithography method.
  • the intrinsic semiconductor layer 33 and the n-type semiconductor layer 35 are patterned. That is, the patterned intrinsic semiconductor layer 33 and the n-type semiconductor layer 35 are formed on the back surface side of the semiconductor substrate 11 (second conductivity type semiconductor layer forming step).
  • etching is performed using an alkaline solution with the photoresist 90 as a mask, and then the photoresist 90 is peeled off using an organic solvent. At this time, the lower sacrificial layer 41 is removed by an alkaline solution that performs etching.
  • the alkaline concentration of the alkaline solution for etching the n-type semiconductor layer 35 is lower than the alkaline concentration of the alkaline solution for stripping the photoresist 90 in the above-described first conductivity type semiconductor layer forming step (for example, n.
  • the alkaline concentration of the alkaline solution for etching the semiconductor layer is less than half the alkaline concentration of the alkaline solution for stripping the photoresist. Therefore, it is not necessary to protect the intrinsic semiconductor layer 13 and the optical adjustment layer 15 from the alkaline solution for etching the n-type semiconductor layer 35.
  • the second conductive type semiconductor layer forming step may include the intrinsic semiconductor layer material.
  • the n-type semiconductor layer 35 may be patterned without stacking (forming) the films. Further, in the first conductivity type semiconductor layer forming step, when a part of the intrinsic semiconductor layer material film 23Z in the n-type region 8 on the back surface side of the semiconductor substrate 11 remains, it is removed in the second conductivity type semiconductor layer forming step.
  • the intrinsic semiconductor layer material film may be stacked (formed) by the amount and the intrinsic semiconductor layer and the n-type semiconductor layer 35 may be patterned.
  • the transparent electrode layer material film 28Z is laminated (formed) on the entire rear surface of the semiconductor substrate 11 by PVD method such as sputtering method (electrode layer forming step). ..
  • the transparent electrode layers 28 and 38 are patterned by removing a part of the transparent electrode layer material film 28Z by using an etching method using an etching paste, for example. That is, the patterned transparent electrode layers 28 and 38 are formed (electrode layer forming step).
  • the etching solution for the transparent electrode layer material film for example, hydrochloric acid or ferric chloride aqueous solution is used.
  • the metal electrode layer 29 is formed on the transparent electrode layer 28 and the metal electrode layer 39 is formed on the transparent electrode layer 38 by using, for example, a printing method or a coating method, whereby the first electrode layer 27 and The second electrode layer 37 is formed.
  • the back electrode type solar cell 1 of the present embodiment shown in FIG. 2 is obtained.
  • the sacrificial layers 41 and 43 are formed on the optical adjustment layer 15 on the light receiving surface side of the semiconductor substrate 11, and the sacrificial layers 41 and 43 are In the one-conductivity-type semiconductor layer forming step, the intrinsic semiconductor layer 13 and the optical adjustment layer 15 are protected from an alkaline solution that removes the photoresist. Thereby, even if the optical adjustment layer 15 has a pinhole, dissolution of the intrinsic semiconductor layer 13 by the alkaline solution is suppressed. Therefore, the decrease in the carrier lifetime is suppressed, and the deterioration in the performance of the solar cell is suppressed. Moreover, since an inexpensive alkaline solution can be used as a solution for removing the photoresist, the cost of the solar cell can be reduced.
  • the sacrificial layers 41 and 43 are partially removed in the first conductive type semiconductor layer forming step, the first cleaning step, the second conductive type semiconductor layer forming step or the electrode layer forming step, and all are removed after the electrode layer forming step. Have been removed. In this way, since the sacrificial layers 41 and 43 are removed during the existing manufacturing process, the performance degradation of the solar cell is suppressed without increasing the number of processes as much as possible.
  • the sacrificial layers 41, 43 are formed by the hydrofluoric acid treatment (hydrofluoric acid or a mixture of hydrofluoric acid and another type of acid in the cleaning treatment in the first cleaning step.
  • Surface treatment to protect the surface of the optical adjustment layer 15.
  • the sacrificial layer may be formed of a single layer including only the sacrificial layer 41.
  • the sacrificial layer 41 may be an intrinsic semiconductor layer containing silicon as a main component, a p-type semiconductor layer in which silicon is doped with a p-type dopant, or an n-type semiconductor layer in which silicon is doped with an n-type dopant.
  • the thickness of the sacrificial layer 41 is preferably 5 nm or more and 300 nm or less.
  • the sacrificial layer 41 protects the intrinsic semiconductor layer 13 and the optical adjustment layer 15 from the alkaline solution that removes the photoresist. Therefore, even if the optical adjustment layer 15 has pinholes, dissolution of the intrinsic semiconductor layer 13 by the alkaline solution is suppressed. Further, a part of the sacrificial layer 41 in the stacking direction of each layer is removed by the alkaline solution.
  • the rest of the sacrificial layer 41 protects the surface of the optical adjustment layer 15 from hydrofluoric acid treatment (treatment with hydrofluoric acid or a mixture of hydrofluoric acid and another type of acid). Therefore, the etching of the surface of the optical adjustment layer 15 is suppressed.
  • the rest of the sacrificial layer 41 is removed by an alkaline solution for etching.
  • a second cleaning step of cleaning both main surfaces of the semiconductor substrate 11 may be provided after the second conductivity type semiconductor layer forming step and before the electrode layer forming step. Also in the second conductive type semiconductor layer forming step, an inexpensive alkaline solution may be used as a solution for removing the photoresist 90. Further, in the electrode layer forming step, an alkaline solution may be used in the developing step when patterning the transparent conductive layer.
  • FIG. 5A is a diagram showing a part of the optical adjustment layer forming step, the sacrifice layer forming step, and the first conductivity type semiconductor layer forming step in the method for manufacturing a solar cell according to the modification of the present embodiment
  • FIG. 5D is a diagram showing the rest of the first conductivity type semiconductor layer forming step in the method for manufacturing the solar cell according to the modification of the present embodiment
  • FIG. 5E is a diagram showing a first cleaning step in the method for manufacturing a solar cell according to the modification of the present embodiment
  • FIG. 5F and 5G are the method for manufacturing a solar cell according to the modification of the present embodiment.
  • FIG. 6 is a diagram showing a step of forming a second conductivity type semiconductor layer in FIG.
  • FIG. 5H is a diagram showing a second cleaning step in the method for manufacturing a solar cell according to the modification of the present embodiment
  • FIGS. 5I and 5J are the method for manufacturing a solar cell according to the modification of the present embodiment.
  • FIG. 6 is a diagram showing an electrode layer forming step in FIG.
  • the intrinsic semiconductor layer material film 23Z and the p-type semiconductor layer material film 25Z are formed on the entire back surface of the semiconductor substrate 11 by using, for example, the CVD method.
  • the layers are sequentially laminated (film formation) (first conductivity type semiconductor layer forming step).
  • the intrinsic semiconductor layer 13 and the optical adjustment layer 15 are sequentially laminated (film formation) on the entire light-receiving surface side of the semiconductor substrate 11 by using, for example, the CVD method (optical adjustment layer). Forming process).
  • the lower sacrifice layer 41 and the upper sacrifice layer 41 are formed on the entire surface of the semiconductor substrate 11 on the light-receiving surface side, specifically, on the entire surface of the optical adjustment layer 15 by using, for example, the CVD method.
  • the layers 43 are sequentially laminated (film formation) (sacrifice layer forming step).
  • the upper sacrificial layer 43 is thicker than the upper sacrificial layer 43 of the above-described embodiment.
  • the intrinsic semiconductor layer material films 23Z and p in the n-type region 8 are formed on the back surface side of the semiconductor substrate 11 by using the photolithography method.
  • the type semiconductor layer material film 25Z By removing the type semiconductor layer material film 25Z, the intrinsic semiconductor layer 23 and the p-type semiconductor layer 25 are patterned. That is, the patterned intrinsic semiconductor layer 23 and the p-type semiconductor layer 25 are formed on the back surface side of the semiconductor substrate 11 (first conductivity type semiconductor layer forming step).
  • the photoresist 90 in the n-type region 8 on the back surface side is exposed and developed to be removed.
  • the intrinsic semiconductor layer 23 and the p-type semiconductor layer 25 are patterned using an etching method using the photoresist 90 as a mask.
  • the photoresist 90 is peeled off using an inexpensive alkaline solution.
  • the upper sacrificial layer 43 protects the intrinsic semiconductor layer 13 and the optical adjustment layer 15 from the alkaline solution that removes the photoresist 90. Therefore, even if the optical adjustment layer 15 has pinholes, dissolution of the intrinsic semiconductor layer 13 by the alkaline solution is suppressed.
  • the p-type semiconductor layer 25 is left so as to leave a part or all of the intrinsic semiconductor layer material film 23Z in the n-type region 8 on the back surface side of the semiconductor substrate 11. Patterning may be performed.
  • both surface sides of the semiconductor substrate 11 are cleaned (first cleaning step), as in the above-described present embodiment.
  • first cleaning step for example, after performing ozone treatment, hydrofluoric acid treatment (treatment with hydrofluoric acid or a mixture of hydrofluoric acid and another type of acid) is performed.
  • hydrofluoric acid treatment treatment with hydrofluoric acid or a mixture of hydrofluoric acid and another type of acid
  • a part of the upper sacrificial layer 43 in the stacking direction of each layer is removed by hydrofluoric acid treatment.
  • the rest of the upper sacrificial layer 43 protects the surface of the optical adjustment layer 15 from the hydrofluoric acid treatment. Therefore, the etching of the surface of the optical adjustment layer 15 is reduced.
  • the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer material film 35Z are formed on the entire rear surface of the semiconductor substrate 11 by using, for example, the CVD method.
  • the CVD method are sequentially laminated (film formation) (second conductivity type semiconductor layer forming step).
  • a layer which has resistance to an alkaline solution for peeling the photoresist 90 described later and which can be removed in the second cleaning step described later may be laminated (not shown).
  • Examples of the material of this layer include SiO and SiN.
  • a PVD method such as a CVD method or a sputtering method can be used.
  • the intrinsic semiconductor layer material film 33Z and the n-type semiconductor layer in the p-type region 7 are formed on the back surface side of the semiconductor substrate 11 by using the photolithography method.
  • the intrinsic semiconductor layer 33 and the n-type semiconductor layer 35 are patterned by removing the material film 35Z. That is, the patterned intrinsic semiconductor layer 33 and the n-type semiconductor layer 35 are formed on the back surface side of the semiconductor substrate 11 (second conductivity type semiconductor layer forming step).
  • etching is performed using an alkaline solution with the photoresist 90 as a mask, and then the photoresist 90 is peeled off using an inexpensive alkaline solution. ..
  • the rest of the upper sacrificial layer 43 protects the intrinsic semiconductor layer 13 and the optical adjustment layer 15 from the alkaline solution that removes the photoresist 90. Therefore, even if the optical adjustment layer 15 has pinholes, dissolution of the intrinsic semiconductor layer 13 by the alkaline solution is suppressed.
  • the second conductivity type semiconductor layer forming step when all of the intrinsic semiconductor layer material film 23Z in the n-type region 8 on the back surface side of the semiconductor substrate 11 remains in the first conductivity type semiconductor layer forming step, in the second conductivity type semiconductor layer forming step.
  • the n-type semiconductor layer 35 may be patterned without stacking (forming) the intrinsic semiconductor layer material film.
  • the first conductivity type semiconductor layer forming step when a part of the intrinsic semiconductor layer material film 23Z in the n-type region 8 on the back surface side of the semiconductor substrate 11 remains, it is removed in the second conductivity type semiconductor layer forming step.
  • the intrinsic semiconductor layer material film may be stacked (formed) by the amount and the intrinsic semiconductor layer and the n-type semiconductor layer 35 may be patterned.
  • both surface sides of the semiconductor substrate 11 are cleaned (second cleaning step).
  • the second cleaning step for example, after performing ozone treatment, hydrofluoric acid treatment (treatment with hydrofluoric acid or a mixture of hydrofluoric acid and another type of acid) is performed.
  • hydrofluoric acid treatment treatment with hydrofluoric acid or a mixture of hydrofluoric acid and another type of acid
  • the rest of the upper sacrificial layer 43 is removed by the hydrofluoric acid treatment.
  • the lower sacrificial layer 41 protects the surface of the optical adjustment layer 15 from the hydrofluoric acid treatment. Therefore, the etching of the surface of the optical adjustment layer 15 is reduced.
  • a transparent electrode layer material film 28Z is laminated (formed) on the entire rear surface of the semiconductor substrate 11 by PVD method such as sputtering method (electrode layer forming step). ..
  • the transparent electrode layers 28 and 38 are patterned by removing a part of the transparent electrode layer material film 28Z by using, for example, an etching method using an etching paste. That is, the patterned transparent electrode layers 28 and 38 are formed (electrode layer forming step).
  • the etching solution for the transparent electrode layer material film for example, hydrochloric acid or ferric chloride aqueous solution is used.
  • the lower sacrificial layer 41 protects the intrinsic semiconductor layer 13 and the optical adjustment layer 15 from the alkaline solution used in the developing step when patterning the transparent conductive layer. Further, the lower sacrificial layer 41 is removed by the alkaline solution.
  • the metal electrode layer 29 is formed on the transparent electrode layer 28 and the metal electrode layer 39 is formed on the transparent electrode layer 38 by using, for example, a printing method or a coating method.
  • the first electrode layer 27 and the second electrode layer 37 are formed.
  • the back electrode type solar cell 1 of the present embodiment shown in FIG. 2 is obtained.
  • the sacrificial layers 41 and 43 are provided on the optical adjustment layer 15 on the light receiving surface side of the semiconductor substrate 11 in the same manner as in the solar cell manufacturing method of the present embodiment.
  • the formed sacrificial layers 41 and 43 protect the intrinsic semiconductor layer 13 and the optical adjustment layer 15 from the alkaline solution that strips the photoresist in the first conductive type semiconductor layer forming step.
  • the intrinsic semiconductor layer 13 and the optical adjustment layer 15 are protected from the alkaline solution that strips the photoresist even in the second conductive type semiconductor layer forming step.
  • the optical adjustment layer 15 has a pinhole, dissolution of the intrinsic semiconductor layer 13 by the alkaline solution is suppressed. Therefore, the decrease in the carrier lifetime is suppressed, and the deterioration in the performance of the solar cell is suppressed. Moreover, since an inexpensive alkaline solution can be used as a solution for removing the photoresist, the cost of the solar cell can be reduced.
  • the sacrifice layers 41 and 43 are partially removed in the first conductivity type semiconductor layer forming step, the first cleaning step, the second conductivity type semiconductor layer forming step, the second cleaning step or the electrode layer forming step, so that the electrode layer All have been removed after the forming process. In this way, since the sacrificial layers 41 and 43 are removed during the existing manufacturing process, the performance degradation of the solar cell is suppressed without increasing the number of processes as much as possible.
  • the sacrificial layers 41 and 43 are treated with hydrofluoric acid (hydrofluoric acid or other types of hydrofluoric acid and other types in the cleaning process in the first cleaning process and the second cleaning process.
  • Hydrofluoric acid hydrofluoric acid or other types of hydrofluoric acid and other types in the cleaning process in the first cleaning process and the second cleaning process.
  • Surface of the optical adjustment layer 15 is protected from the treatment with a mixture with an acid). Thereby, the etching of the surface of the optical adjustment layer 15 is reduced, and the appearance defect of the light receiving surface of the solar cell is improved.
  • the sacrificial layer may be formed of a single layer including only the sacrificial layer 41.
  • the sacrificial layer 41 may be an intrinsic semiconductor layer containing silicon as a main component, a p-type semiconductor layer in which silicon is doped with a p-type dopant, or an n-type semiconductor layer in which silicon is doped with an n-type dopant.
  • the thickness of the sacrificial layer 41 is preferably 5 nm or more and 300 nm or less.
  • the sacrificial layer 41 protects the intrinsic semiconductor layer 13 and the optical adjustment layer 15 from the alkaline solution that removes the photoresist 90. Therefore, even if the optical adjustment layer 15 has pinholes, dissolution of the intrinsic semiconductor layer 13 by the alkaline solution is suppressed. Further, a part of the sacrificial layer 41 in the stacking direction of each layer is removed by the alkaline solution.
  • the rest of the sacrificial layer 41 protects the surface of the optical adjustment layer 15 from the hydrofluoric acid treatment. Therefore, the etching of the surface of the optical adjustment layer 15 is suppressed.
  • the rest of the sacrificial layer 41 protects the intrinsic semiconductor layer 13 and the optical adjustment layer 15 from an alkaline solution that removes the photoresist. Therefore, even if the optical adjustment layer 15 has pinholes, dissolution of the intrinsic semiconductor layer 13 by the alkaline solution is suppressed.
  • the remaining part of the sacrificial layer 41 in the stacking direction of the layers is removed by an alkaline solution for etching and an alkaline solution for removing the photoresist.
  • the rest of the sacrificial layer 41 protects the surface of the optical adjustment layer 15 from the hydrofluoric acid treatment. Therefore, the etching of the surface of the optical adjustment layer 15 is reduced.
  • the rest of the sacrificial layer 41 protects the intrinsic semiconductor layer 13 and the optical adjustment layer 15 from the alkaline solution used in the developing step when patterning the transparent conductive layer. Further, the rest of the sacrificial layer 41 is removed by the alkaline solution.
  • the present invention is not limited to the above-described embodiments, and various changes and modifications can be made.
  • the intrinsic semiconductor layer 23 and the p-type semiconductor layer 25 are patterned using a photoresist (photolithography method) that can be stripped with an alkaline solution in the first conductive type semiconductor layer forming step.
  • the form to perform is illustrated.
  • the present invention is not limited to this, and can be applied to a mode in which the intrinsic semiconductor layer and the p-type semiconductor layer are patterned using various resists such as a printing resist that can be peeled off with an alkaline solution.
  • a mode in which an alkaline solution is used as a solution for stripping the resist is illustrated only in the first conductive type semiconductor layer forming step.
  • the embodiment in which the alkaline solution is used as the solution for stripping the resist is illustrated in both the first conductive type semiconductor layer forming step and the second conductive type semiconductor layer forming step.
  • the present invention is not limited to this, and is applicable to a mode in which an alkaline solution is used as a solution for stripping the resist in at least one of the first conductive type semiconductor layer forming step and the second conductive type semiconductor layer forming step. is there.
  • an organic solvent is used as a solution for removing the resist
  • an alkaline solution is used as a solution for removing the resist. ..
  • the first conductivity type semiconductor layer 25 is the n-type semiconductor layer
  • the second conductivity type semiconductor layer 35 is the p-type semiconductor layer
  • the first conductivity type region 7 is the n-type region
  • the second conductivity type region is 8 is a p-type region
  • the first conductivity type semiconductor layer 25 is a p-type semiconductor layer
  • the second conductivity type semiconductor layer 35 is an n-type semiconductor layer
  • the first conductivity type region 7 is a p-type region
  • the region 8 may be replaced with an n-type region.
  • the method for manufacturing the heterojunction solar cell 1 is illustrated as shown in FIG. 2, but the feature of the present invention is not limited to the heterojunction solar cell, but is a homojunction solar cell. It is applicable to various solar cell manufacturing methods such as batteries.
  • the semiconductor substrate 11 is a p-type semiconductor in which a crystalline silicon material is doped with a p-type dopant (for example, the above-described boron (B)). It may be a substrate.
  • a p-type dopant for example, the above-described boron (B)
  • a solar cell having the crystalline silicon substrate is illustrated, but the present invention is not limited to this.
  • a solar cell may have a gallium arsenide (GaAs) substrate.
  • GaAs gallium arsenide
  • 1,1X Solar cell 7 1st conductivity type area

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  • Engineering & Computer Science (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Energy (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Photovoltaic Devices (AREA)

Abstract

L'invention concerne un procédé de production de cellules solaires permettant de réduire le coût des cellules solaires et de supprimer une baisse de leurs performances. L'invention concerne un procédé de production de cellules solaires de type à électrode arrière, comprenant : une étape consistant à former une couche semiconductrice intrinsèque (13) et une couche de réglage optique (15), dans cet ordre, sur un côté surface principale d'un substrat semiconducteur (11) ; une étape de formation de couches sacrificielles (41, 43) sur la couche de réglage optique (15) ; une étape de formation d'une couche semiconductrice d'un premier type conducteur à motif (25) sur l'autre côté surface principale du substrat semiconducteur (11) ; et une étape de formation d'une couche semiconductrice d'un deuxième type conducteur à motif sur l'autre côté surface principale du substrat semiconducteur (11), les couches sacrificielles (41, 43) protégeant la couche semiconductrice intrinsèque (13) et la couche de réglage optique (15) contre une solution de décollage de résine photosensible (90) pendant les étapes de formation de couche semiconductrice de premier et/ou de deuxième type de conductivité, tandis que les couches sacrificielles sont éliminées partiellement pendant l'étape de formation de la couche semiconductrice de premier ou deuxième type conducteur ou l'étape de formation de couche d'électrode, et sont éliminées complètement après l'étape de formation de couche d'électrode.
PCT/JP2019/050858 2019-01-18 2019-12-25 Procédé de production de cellules solaires WO2020149128A1 (fr)

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JP2010258043A (ja) * 2009-04-21 2010-11-11 Sanyo Electric Co Ltd 太陽電池
JP2012049193A (ja) * 2010-08-24 2012-03-08 Sanyo Electric Co Ltd 太陽電池の製造方法
JP2012182167A (ja) * 2011-02-28 2012-09-20 Sanyo Electric Co Ltd 太陽電池及び太陽電池の製造方法
WO2012132836A1 (fr) * 2011-03-28 2012-10-04 三洋電機株式会社 Dispositif de conversion photoélectrique, et procédé de production de dispositif de conversion photoélectrique
JP2016066709A (ja) * 2014-09-25 2016-04-28 パナソニックＩｐマネジメント株式会社 太陽電池
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JP2010199416A (ja) * 2009-02-26 2010-09-09 Sanyo Electric Co Ltd 太陽電池の製造方法
JP2010258043A (ja) * 2009-04-21 2010-11-11 Sanyo Electric Co Ltd 太陽電池
JP2012049193A (ja) * 2010-08-24 2012-03-08 Sanyo Electric Co Ltd 太陽電池の製造方法
JP2012182167A (ja) * 2011-02-28 2012-09-20 Sanyo Electric Co Ltd 太陽電池及び太陽電池の製造方法
WO2012132836A1 (fr) * 2011-03-28 2012-10-04 三洋電機株式会社 Dispositif de conversion photoélectrique, et procédé de production de dispositif de conversion photoélectrique
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Publication number Priority date Publication date Assignee Title
JP7495341B2 (ja) 2020-12-21 2024-06-04 株式会社カネカ 太陽電池の製造方法

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