WO2020143582A1 - 显示面板、阵列基板及其制备方法 - Google Patents

显示面板、阵列基板及其制备方法 Download PDF

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Publication number
WO2020143582A1
WO2020143582A1 PCT/CN2020/070498 CN2020070498W WO2020143582A1 WO 2020143582 A1 WO2020143582 A1 WO 2020143582A1 CN 2020070498 W CN2020070498 W CN 2020070498W WO 2020143582 A1 WO2020143582 A1 WO 2020143582A1
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Prior art keywords
layer
wiring layer
array substrate
backplane
wiring
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PCT/CN2020/070498
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English (en)
French (fr)
Inventor
田宏伟
牛亚男
刘政
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/772,971 priority Critical patent/US11307689B2/en
Publication of WO2020143582A1 publication Critical patent/WO2020143582A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04102—Flexible digitiser, i.e. constructional details for allowing the whole digitising part of a device to be flexed or rolled like a sheet of paper
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting

Definitions

  • the present invention relates to the field of display technology, and in particular, to an array substrate, a display panel including the array substrate, and a preparation method of the array substrate.
  • Organic electroluminescent display panels have gradually become the mainstream of the display field due to their excellent performances such as low power consumption, high color saturation, wide viewing angle, thin thickness, and flexibility, and can be widely used in smartphones, tablets, TVs, etc. End products.
  • the flexible device since the flexible device has an arbitrary shape and can be arranged in various areas with a small thickness, it is becoming more and more important. Combining touch electrodes such as FMLOC (Flexible Metal Line On Common) and flexible devices is the focus of current development.
  • FMLOC Flexible Metal Line On Common
  • an array substrate including:
  • Backplane including display area and bonding area
  • a wiring layer is provided on the backplane, and the wiring layer in the bonding area is exposed;
  • a protective layer is provided on the side of the wiring layer far away from the backplane, and covers the wiring layer located in the display area and the bonding area, and a passivation layer is provided on the protective layer located in the bonding area hole;
  • connection layer is provided on a side of the protective layer away from the backplane, and the connection layer is connected to the wiring layer through the through hole.
  • the array substrate further includes:
  • a pixel definition layer provided between the wiring layer and the protective layer, and covering the wiring layer in the display area, or covering the wiring layer in the display area and the wiring layer in the bonding area, A via hole communicating with the through hole is provided on the pixel definition layer located in the bonding area.
  • the backplane further includes:
  • the transition area is provided between the display area and the bonding area.
  • the protective layer includes:
  • the second sub-protection layer covers the display area, or covers the display area and the bonding area.
  • the number of the through holes is multiple.
  • a display panel including:
  • the array substrate according to any one of the above.
  • a method for preparing an array substrate including:
  • the backplane includes a display area and a bonding area
  • the wiring layer covers the backplane, and the wiring layer above the bonding area is exposed;
  • connection layer is formed on a side of the protective layer away from the backplane, and the connection layer is connected to the wiring layer through the through hole.
  • the method for preparing the array substrate further includes:
  • a pixel definition layer is formed on a side of the wiring layer away from the backplane, the pixel definition layer covering the wiring layer located in the display area, or covering the wiring layer located in the display area and located in the state Wiring layer in fixed area;
  • a via hole is formed on the pixel definition layer located in the bonding area, and the via hole communicates with the through hole.
  • the backplane further includes:
  • the transition area is provided between the display area and the bonding area.
  • forming the protective layer on the side of the wiring layer far from the backplane includes:
  • first sub-protection layer Forming a first sub-protection layer on a side of the wiring layer away from the backplane, the first sub-protection layer covering the display area and the bonding area;
  • a second sub-protection layer is formed on a side of the first sub-protection layer away from the backplane, the second sub-protection layer covering the display area, or covering the display area and the bonding area.
  • FIG. 1 is a schematic structural diagram of an array substrate in the related art
  • FIG. 2 is a schematic structural diagram of an array substrate covering a bonding area with a first sub-protection layer according to an embodiment of the present invention
  • FIG. 3 is a schematic structural view of an array substrate covering a bonding area by a first sub-protection layer and a second sub-protection layer in an embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of an array substrate with no step difference between a bonding area and a display area in an embodiment of the present invention
  • FIG. 5 is a plan view of the array substrate in the embodiment of the array substrate of the present invention.
  • FIG. 6 is a flowchart of a method for manufacturing an array substrate of the present invention.
  • the touch function is widely used and can be seen in almost all modern display devices.
  • the mainstream is now made externally and then attached to the panel, that is, the externally attached TSP (Touch sensor panel), due to its cost and complexity of the process, has a higher cost and is in a small radius During the bending process, the ability to match the bending of existing flexible devices is poor. Therefore, the integration of FMLOC with touch function on flexible devices has become the focus of current development.
  • connection layer 4 due to the etching problem caused by the step difference and the problem of the FMLOC metal itself, no matter how the patterning process is performed, the peripheral leads, especially the routing of the bonding area C, are always the remaining heavy disaster area.
  • the residual connection layer metal is more likely to lead to the complexity and high risk of the C process in the bonding area.
  • the array substrate may include a backplane 1, a wiring layer 2, a protective layer 3, and a connection layer 4.
  • the backplane 1 includes a display area A and a bonding area C; wiring Layer 2 is provided on the backplane 1 and the wiring layer 2 in the bonding area C is exposed; the protective layer 3 is provided on the side of the wiring layer 2 away from the backplane 1 and covers the wiring in the display area A and the bonding area C Layer 2 is provided with a through hole 33 on the protective layer 3 in the bonding area C.
  • the connecting layer 4 is provided on the side of the protective layer 3 away from the backplane 1. The connecting layer 4 is connected to the wiring layer 2 through the through hole 33.
  • the exposed wiring layer 2 of the bonding area C is covered by the protective layer 3, so that the height of the bonding area C is increased, the step difference between the display area A and the bonding area C is reduced, and it is located in the bonding area
  • the protective layer 3 of C is provided with a through hole 33, so that the connection layer 4 is connected to the wiring layer 2 through the through hole 33, and the protective layer 3 covers and protects the wiring layer 2 to prevent the connection layer remaining due to the etching process when the connection layer 4 is formed
  • the metal causes the wiring layer 2 to short-circuit, which reduces the short-circuit risk and improves the safety of the array substrate.
  • the backplane 1 may include a display area A, a transition area B, and a bonding area C.
  • the backplane 1 has a multi-layer structure.
  • the backplane 1 may include a buffer layer, a gate insulation layer, a first gate layer, a second gate layer, an interlayer insulation layer, a planarization layer, a support layer, and the like.
  • the wiring layer 2 may be one or more of a source-drain layer and an anode layer.
  • the wiring layer is provided on the backplane 1 and the wiring layer 2 located in the bonding area C is exposed for use.
  • the wiring layer 2 may include multiple wires.
  • the wiring layer 2 is provided on the backplane 1, covering the entire backplane 1, that is, covering the display area A, the transition area B, and the bonding area C of the backplane 1.
  • the protective layer 3 is provided on the wiring layer 2 and covers the wiring layer 2 located in the display area A and the bonding area C.
  • the protective layer 3 may include a first sub-protective layer 31 and a second sub-protective layer 32
  • the first sub-protection layer 31 can be formed by chemical vapor deposition method, and the second sub-protection layer 32 can also be formed by chemical vapor deposition method;
  • the first sub-protection layer 31 is provided on the side of the wiring layer 2 away from the backplane 1,
  • the second sub-protection layer 32 is disposed on the side of the first sub-protection layer 31 away from the backplane 1, that is, the first sub-protection layer 31 is disposed on the wiring layer 2, and the second sub-protection layer 32 is disposed on the first sub-protection layer 31;
  • the second sub-protection layer 32 may only cover the wiring layer 2 of the display area A, only the first sub-protection layer 31 reduces the step difference between the display area A and the bond
  • the second sub-protection layer 32 may also cover the wiring layer 2 located in the display area A and the bonding area C; so that the step difference between the display area A and the bonding area C is further reduced.
  • the through hole 33 is provided on the protective layer 3, and the through hole 33 is provided on the protective layer 3 located in the bonding area C, that is, when the bonding area C is covered with the first sub-protective layer 31 and the second sub-protective layer 32, the The through-hole 33 penetrates the first sub-protection layer 31 and the second sub-protection layer 32.
  • the through-hole 33 is provided only on the first sub-protection layer 31.
  • the number may be multiple, and the through holes 33 may correspond to the wires of the wiring layer 2 one by one, that is, one through hole 33 corresponds to one wire, or multiple wires may correspond to one through hole 33.
  • the shape of the cross section of the through hole 33 may be a circle, an ellipse, a rectangle, a triangle, or other shapes.
  • connection layer 4 is provided on a layer of the protective layer 3 far away from the backplane 1, that is, the connection layer 4 is located above the protective layer 3, the connection layer 4 may be a flexible metal wire layer, and the connection layer 4 passes The through hole 33 is connected to the wiring layer 2, the connection layer 4 is provided on the protective layer 3 of the display area A and the bonding area C, and the transition area B of the backplane 1, so that the connection layer of the display area A and the bonding area C 4 Connected, and all connected to the wiring layer 2.
  • the connection layer 4 may have a touch function. In this case, it may include a touch electrode layer located in the display area A and a touch extending from the touch electrode layer, passing through the transition area B, and connected to the wiring layer 2 via the via 33 in the bonding area C Electrode lead.
  • the array substrate of the present invention may further include a pixel definition layer 5, the pixel definition layer 5 is disposed on the side of the wiring layer 2 away from the backplane 1, that is, the pixel definition layer 5 is disposed on the wiring layer 2, the pixel definition The layer 5 may cover only the wiring layer 2 located in the display area A.
  • the pixel definition layer 5 may define pixels of the display layer on the side of the wiring layer 2 away from the backplane 1.
  • the pixel definition layer 5 may also cover the wiring layer 2 located in the display area A and the bonding area B.
  • the pixel definition layer 5 located in the bonding area C needs to be provided with Via 51;
  • Via 51 communicates with via 33, the number of via 51 can also be multiple, the number of via 51 can be the same as the number of via 33, the cross-sectional shape of via 51 can be circular, or Can be elliptical, rectangular, triangular and other shapes.
  • the present invention further provides a display panel, which may include the above-mentioned array substrate.
  • a display panel which may include the above-mentioned array substrate. The specific details of the array substrate have been described in detail above, therefore, they will not be repeated here.
  • the present invention also provides a method for preparing an array substrate.
  • the method for preparing the array substrate may include:
  • Step S110 a backplane 1 is provided, and the backplane 1 includes a display area A and a bonding area C.
  • step S120 a wiring layer 2 is formed on the backplane 1, the wiring layer 2 covers the backplane 1, and the wiring layer 2 on the bonding area C is exposed.
  • a protective layer 3 is formed on the side of the wiring layer 2 away from the backplane 1, and the protective layer 3 covers the wiring layer 2 located in the display area A and the bonding area C.
  • Step S140 forming a through hole 33 on the protective layer 3.
  • step S150 a connection layer 4 is formed on the side of the protective layer 3 away from the backplane 1, and the connection layer 4 is connected to the wiring layer 2 through the through hole 33.
  • a backplane 1 is provided, and the backplane 1 includes a display area A and a bonding area C.
  • the backplane 1 may include a display area A, a transition area B, and a bonding area C.
  • the backplane 1 has a multi-layer structure.
  • the backplane 1 may include a buffer layer, a gate insulation layer, a first gate layer, a second gate layer, an interlayer insulation layer, a planarization layer, a support layer, and the like.
  • step S120 a wiring layer 2 is formed on the backplane 1, the wiring layer 2 covers the backplane 1, and the wiring layer 2 above the bonding area C is exposed.
  • a wiring layer 2 is formed on the backplane 1.
  • the wiring layer 2 may be one or more of a source-drain layer and an anode layer.
  • the wiring layer 2 is provided on the backplane 1 and is located in Bonding.
  • the wiring layer 2 in the area C is exposed for connection with the subsequent connection layer 4.
  • the wiring layer 2 may include multiple wires, and the multiple wires are arranged side by side in parallel, and the distance between each adjacent two wires may be the same.
  • the wiring layer 2 is provided on the backplane 1, covering the entire backplane 1, that is, covering the display area A, the transition area B, and the bonding area C of the backplane 1.
  • a protective layer 3 is formed on the side of the wiring layer 2 away from the backplane 1, and the protective layer 3 covers the wiring layer 2 located in the display area A and the bonding area C.
  • a protective layer 3 is formed on the wiring layer 2.
  • the protective layer 3 covers the wiring layer 2 located in the display area A and the bonding area C.
  • the protective layer 3 may include a first sub-protection layer 31 and a second sub-layer
  • the protective layer 32, the first sub-protective layer 31 may be formed by a chemical vapor deposition method, and the second sub-protective layer 32 may also be formed by a chemical vapor deposition method;
  • the first sub-protective layer 31 is provided on the wiring layer 2 away from the backplane 1
  • the second sub-protection layer 32 is disposed on the side of the first sub-protection layer 31 away from the backplane 1, that is, the first sub-protection layer 31 is disposed on the wiring layer 2, and the second sub-protection layer 32 is disposed on the first On the sub-protection layer 31;
  • the first sub-protection layer 31 covers the wiring layer 2 located in the display area A and the bonding area C, the second sub-protection layer 32
  • the second sub-protection layer 32 may also cover the wiring layer 2 located in the display area A and the bonding area C; so that the step difference between the display area A and the bonding area C is further reduced.
  • step S140 a through hole 33 is formed on the protective layer 3.
  • a through hole 33 is formed on the protective layer 3, the through hole 33 is provided on the protective layer 3, the through hole 33 is provided on the wiring layer 2 located in the bonding area C, that is, when bonding area When C is covered with the first sub-protection layer 31 and the second sub-protection layer 32, the through hole 33 penetrates the first sub-protection layer 31 and the second sub-protection layer 32, when the second sub-protection layer 32 is only disposed in the display area A At this time, only the through holes 33 are provided on the first sub-protection layer 31, and the number of the through holes 33 may be multiple.
  • the through holes 33 may correspond to the wires of the wiring layer 2 one by one, that is, one through hole 33 corresponds to one wire. There may be multiple wires corresponding to one through hole 33.
  • the shape of the cross section of the through hole 33 may be a circle, an ellipse, a rectangle, a triangle, or other shapes.
  • step S150 a connection layer 4 is formed on the side of the protective layer 3 away from the backplane 1, and the connection layer 4 is connected to the wiring layer 2 through the through hole 33.
  • connection layer 4 is formed on the protective layer 3.
  • the connection layer 4 may be a flexible metal wire layer.
  • the connection layer 4 is connected to the wiring layer 2 through the via 33.
  • the connection layer 4 is provided in the display area A and the protective layer 3 of the bonding area C and the transition area B of the backplane 1 connect the connection layer 4 between the display area A and the bonding area C, and both are connected to the wiring layer 2.
  • the connection layer 4 may have a touch function. In this case, it may include a touch electrode layer located in the display area A and a touch extending from the touch electrode layer, passing through the transition area B, and connected to the wiring layer 2 via the via 33 in the bonding area C Electrode lead.
  • the method for manufacturing an array substrate of the present invention may further include forming a pixel definition layer 5 on the side of the wiring layer 2 away from the backplane 1, that is, the pixel definition layer 5 is disposed on the wiring layer 2 and the pixels
  • the definition layer 5 may cover the wiring layer 2 located in the display area A and the bonding area C.
  • the pixel definition layer 5 may also cover only the wiring layer 2 located in the display area A.
  • the manufacturing method of the array substrate of the present invention may further include forming on the pixel definition layer 5 located in the bonding area C Via 51, via 51 communicates with through hole 33, the number of via 51 may also be multiple, the number of via 51 may be the same as the number of via 33, the cross-sectional shape of via 51 may be circular, or It can be elliptical, rectangular, triangular or other shapes.
  • a via 51 is provided in the pixel definition layer 5, and the first sub-protection layer 31 and the second sub-protection layer A through hole 33 is provided on the 32, and the via hole 51 communicates with the through hole 33.
  • the display area A and the bonding area C have a uniform stacking coverage, that is, the difference between the display area A and the bonding area C is small or does not exist
  • Step difference when forming the connection layer 4, there will be no more metal residue in the connection layer 4 due to the step difference, the connection layer 4 can be connected to the wiring layer 2 through the via 51 and the through hole 33, and the bonding area C is adopted by the protective layer 3
  • the bare wiring layer 2 is covered.
  • the connection layer 4 is formed, the wiring layer 2 will not cause a short circuit due to residual metal, which reduces the short circuit risk and improves the safety of the array substrate.
  • the method for manufacturing an array substrate of the present disclosure may further include forming a display layer.
  • the display layer is provided between the wiring layer 2 and the protective layer 3 in the display area A, and the pixels of the display layer are defined by the pixel definition layer 5.
  • the terms “a”, “a”, “the”, “said” and “at least one” are used to indicate the presence of one or more elements/components/etc; the terms “including”, “including” and “Having” is meant to mean an open-ended inclusion and means that there can be additional elements/components/etc in addition to the listed elements/components/etc; the terms “first”, “second “And “Third” are only used as marks, not to limit the number of objects.

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Abstract

一种阵列基板，该阵列基板包括背板(1)、布线层(2)、保护层(3)以及连接层(4)，背板(1)包括显示区(A)和邦定区(C)；布线层(2)设于所述背板(1)之上，位于所述邦定区(C)的所述布线层(2)裸露；保护层(3)设于所述布线层(2)远离所述背板(1)的一侧，且覆盖位于所述显示区(A)以及所述邦定区(C)的布线层(2)，位于所述邦定区(C)的所述保护层(3)上设有通孔(33)；连接层(4)设于所述保护层(3)远离所述背板(1)的一侧，所述连接层(4)通过所述通孔(33)与所述布线层(2)连接。

Description

显示面板、阵列基板及其制备方法
交叉引用
本申请要求于2019年1月8日提交的申请号为201910016840.X、发明名称为“显示面板、阵列基板及其制备方法”的中国发明专利申请的优先权，该中国发明专利申请的全部内容通过引用全部并入本文。
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板、包含该阵列基板的显示面板以及该阵列基板的制备方法。
背景技术
有机电致发光显示面板凭借其低功耗、高色饱和度、广视角、薄厚度、能实现柔性化等优异性能，逐渐成为显示领域的主流，可以广泛应用于智能手机、平板电脑、电视等终端产品。
在显示器件中，由于柔性器件具有可以制作成任意形状，并且可以以厚度很小的方式布置在各种区域，因此正在呈现越来越重要的地位。将例如FMLOC(Flexible Metal Line On Common，通用柔性金属线)的触控电极与柔性器件结合为目前开发的重点。
现有技术中，FMLOC与柔性器件结合时可能会导致在邦定区线路存在短路风险。
所述背景技术部分公开的上述信息仅用于加强对本发明的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本发明的一方面，提供了一种阵列基板，包括：
背板，包括显示区和邦定区；
布线层，设于所述背板之上，位于所述邦定区的所述布线层裸露；
保护层，设于所述布线层远离所述背板的一侧，且覆盖位于所述显示区以及所述邦定区的布线层，位于所述邦定区的所述保护层上设有通孔；
连接层，设于所述保护层远离所述背板的一侧，所述连接层通过所述通孔与所述布线层连接。
在本公开的一种示例性实施例中，所述阵列基板还包括：
像素定义层，设于所述布线层与保护层之间，且覆盖位于所述显示区的所述布 线层，或覆盖位于所述显示区的所述布线层以及位于邦定区的布线层，位于所述邦定区的像素定义层上设有与所述通孔连通的过孔。
在本公开的一种示例性实施例中，所述背板还包括：
过渡区，设于所述显示区与所述邦定区之间。
在本公开的一种示例性实施例中，所述保护层包括：
第一子保护层，覆盖所述显示区以及所述邦定区；
第二子保护层，覆盖所述显示区，或覆盖所述显示区以及所述邦定区。
在本公开的一种示例性实施例中，所述通孔的数量为多个。
根据本公开的一个方面，提供一种显示面板，包括：
上述任意一项所述的阵列基板。
根据本公开的一个方面，提供一种阵列基板的制备方法，包括：
提供背板，所述背板包括显示区和邦定区；
在所述背板之上形成布线层，所述布线层覆盖所述背板，所述邦定区之上的所述布线层裸露；
在布线层远离所述背板的一侧形成保护层，所述保护层覆盖位于所述显示区以及所述邦定区的布线层；
在所述保护层上形成通孔；
在所述保护层远离背板的一侧形成连接层，所述连接层通过所述通孔与所述布线层连接。
在本公开的一种示例性实施例中，在形成布线层之后，所述阵列基板的制备方法还包括：
在所述布线层远离所述背板的一侧形成像素定义层，所述像素定义层覆盖位于所述显示区的所述布线层，或覆盖位于所述显示区的所述布线层以及位于邦定区的布线层；
在位于所述邦定区的像素定义层上形成过孔，所述过孔与所述通孔连通。
在本公开的一种示例性实施例中，所述背板还包括：
过渡区，设于所述显示区与所述邦定区之间。
在本公开的一种示例性实施例中，在布线层远离所述背板一侧的形成保护层，包括：
在所述布线层远离所述背板的一侧形成第一子保护层，所述第一子保护层覆盖所述显示区以及所述邦定区；
在所述第一子保护层远离所述背板的一侧形成第二子保护层，所述第二子保护层覆盖所述显示区，或覆盖所述显示区以及所述邦定区。
附图说明
通过参照附图详细描述其示例实施方式，本发明的上述和其它特征及优点将变得更加明显。
图1是相关技术中阵列基板的结构示意图；
图2是本发明实施方式中第一子保护层覆盖邦定区的阵列基板的结构示意图；
图3是本发明实施方式中第一子保护层以及第二子保护层覆盖邦定区的阵列基板的结构示意图；
图4是本发明实施方式中邦定区与显示区没有段差的阵列基板的结构示意图；
图5是本发明阵列基板实施方式中阵列基板的俯视图；
图6是本发明阵列基板的制备方法的流程图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本发明将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
现代的各种应用中，触控功能受到广泛的应用，在几乎现代所有显示器件中可以看到。然而，现在主流为外部制作然后再贴合到面板上，也即外贴的TSP(Touch sensor panel，触摸传感器面板)，由于其成本及工艺的复杂性，具有较高的成本，且在小半径弯折过程中，与现有柔性器件弯折相匹配的能力较差。由此，将带有触控功能FMLOC集成在柔性器件上，成为目前开发的重点。
在相关技术中，参照图1所示，由于FMLOC建立于基于TFE(Thin Film Encap，薄膜封装)封装的封装层之上，而现有的TFE封装厚度较大，显示区A与邦定区C之间的段差导致在成膜、曝光和显影、蚀刻工艺时，过渡区B以及邦定区C难以完全移除需要移除的图形。同时，由于现有产品背板1的外围引线普遍采用源漏极层或阳极层的走线，即布线层2在邦定区C通常裸露在外。后继的形成连接层4工艺中，由于段差引发的蚀刻问题，以及FMLOC金属本身的问题，无论通过何种方式进行图形化处理，外围引线特别是邦定区C的走线始终是残留发生的重灾区。残留的连接层金属较易导致邦定区C工艺的复杂性与高风险。
本发明首先提供一种阵列基板，参照图2所示，该阵列基板可以包括背板1、布线层2、保护层3以及连接层4，背板1包括显示区A和邦定区C；布线层2设于背板1之上，位于邦定区C的布线层2裸露；保护层3设于布线层2远离背板1的一侧，且覆盖位于显示区A以及邦定区C的布线层2，位于邦定区C的保护层3上设有通孔33；连接层4设于保护层3远离背板1的一侧，连接层4通过通孔33与布线层2连接。
本发明阵列基板，邦定区C裸露出来的布线层2被保护层3覆盖，使得邦定区C 的高度提升，减小了显示区A与邦定区C之间的段差，位于邦定区C的保护层3上设有通孔33，使得连接层4通过通孔33与布线层2连接，保护层3将布线层2覆盖保护，防止在形成连接层4时由于蚀刻工艺残留的连接层金属导致布线层2短路，降低了短路风险，提高了阵列基板的安全性。
在本示例实施方式中，参照图2所示，背板1可以包括显示区A、过渡区B以及邦定区C。背板1为多层结构，背板1可以包括缓冲层、栅绝绝缘层、第一栅极层、第二栅极层、层间绝缘层、平坦化层、支撑层等。
参照图2所示，布线层2可以为源漏极层和阳极层中的一种或多种，布线层设于背板1之上，位于邦定区C的布线层2裸露在外，用于与后继的连接层4连接，布线层2可以包括多条导线。布线层2设于背板1之上，覆盖整个背板1，即覆盖背板1的显示区A、过渡区B以及邦定区C。
参照图2所示，保护层3设于布线层2之上，覆盖位于显示区A与邦定区C的布线层2，保护层3可以包括第一子保护层31与第二子保护层32，第一子保护层31可以通过化学气相淀积方法形成，第二子保护层32也可以通过化学气相沉积方法形成；第一子保护层31设于布线层2远离背板1的一侧，第二子保护层32设于第一子保护层31远离背板1的一侧，即第一子保护层31设于布线层2之上，第二子保护层32设于第一子保护层31之上；第二子保护层32可以只覆盖显示区A的布线层2，只由第一子保护层31来减小显示区A与邦定区C之间的段差以及对邦定区C裸露的布线层2进行覆盖保护。
参照图3所示，第二子保护层32还可以覆盖位于显示区A与邦定区C的布线层2；使得显示区A与邦定区C的段差进一步减小。
通孔33设置在保护层3上，通孔33设于位于邦定区C的保护层3上，即当邦定区C覆盖有第一子保护层31与第二子保护层32时，该通孔33贯穿第一子保护层31以及第二子保护层32，当第二子保护层32只设置在显示区A时，只在第一子保护层31上设置通孔33，通孔33的数量可以是多个，通孔33可以与布线层2的导线一一对应，即一个通孔33对应一条导线，也可以多条导线对应一个通孔33。通孔33截面的形状可以是圆形，也可以是椭圆形、矩形、三角形或其他形状。
参照图2和图5所示，连接层4设于保护层3远离背板1的一层，即连接层4位于保护层3之上，连接层4可以是柔性金属线层，连接层4通过通孔33与布线层2连接，连接层4设于显示区A与邦定区C的保护层3之上，以及背板1的过渡区B，使得显示区A与邦定区C的连接层4连接，且均与布线层2连接。根据本公开的实施例，连接层4可以具有触控功能。在这种情况下，其可以包括位于显示区A中的触控电极层以及从触控电极层延伸出、经过过渡区B并在绑定区C经由通孔33连接到布线层2的触控电极引线。
参照图3所示，本发明阵列基板还可以包括像素定义层5，像素定义层5设于布 线层2远离背板1的一侧，即像素定义层5设于布线层2之上，像素定义层5可以只覆盖位于显示区A的布线层2。像素定义层5可以限定位于布线层2的远离背板1一侧的显示层的像素。
参照图4所示，像素定义层5还可以覆盖位于显示区A与邦定区B的布线层2，此时需要在位于邦定区C的像素定义层5上设置与上述通孔33连通的过孔51；过孔51与通孔33连通，过孔51的数量也可以是多个，过孔51的数量可以与通孔33的数量相同，过孔51截面的形状可以是圆形，也可以是椭圆形、矩形、三角形以及其他形状。
进一步的，本发明还提供一种显示面板，该显示面板可以包括上述所述的阵列基板，该阵列基板的具体细节上述已经进行了详细说明，因此，此处不再赘述。
在进一步的，本发明还提供一种阵列基板的制备方法，参照图6所示，该阵列基板的制备方法可以包括：
步骤S110，提供背板1，所述背板1包括显示区A和邦定区C。
步骤S120，在所述背板1之上形成布线层2，所述布线层2覆盖所述背板1，所述邦定区C之上的所述布线层2裸露。
步骤S130，在布线层2远离所述背板1的一侧形成保护层3，所述保护层3覆盖位于所述显示区A以及所述邦定区C的布线层2。
步骤S140，在所述保护层3上形成通孔33。
步骤S150，在所述保护层3远离背板1的一侧形成连接层4，所述连接层4通过所述通孔33与所述布线层2连接。
以下对上述阵列基板的制备方法的各个步骤进行详细说明。
在步骤S110中，提供背板1，所述背板1包括显示区A和邦定区C。
参照图2所示，提供一背板1，背板1可以包括显示区A、过渡区B以及邦定区C。背板1为多层结构，背板1可以包括缓冲层、栅绝绝缘层、第一栅极层、第二栅极层、层间绝缘层、平坦化层、支撑层等。
在步骤S120中，在所述背板1之上形成布线层2，所述布线层2覆盖所述背板1，所述邦定区C之上的所述布线层2裸露。
参照图2所示，在背板1上形成布线层2，布线层2可以为源漏极层和阳极层中的一种或多种，布线层2设于背板1之上，位于邦定区C的布线层2裸露在外，用于与后继的连接层4连接，布线层2可以包括多条导线，多条导线并排平行设置，每相邻两条导线之间的距离可以相同。布线层2设于背板1之上，覆盖整个背板1，即覆盖背板1的显示区A、过渡区B以及邦定区C。
在步骤S130中，在布线层2远离所述背板1的一侧形成保护层3，所述保护层3覆盖位于所述显示区A以及所述邦定区C的布线层2。
参照图2所示，在布线层2之上形成保护层3，保护层3覆盖位于显示区A与邦 定区C的布线层2，保护层3可以包括第一子保护层31与第二子保护层32，第一子保护层31可以通过化学气相淀积方法形成，第二子保护层32也可以通过化学气相沉积方法形成；第一子保护层31设于布线层2远离背板1的一侧，第二子保护层32设于第一子保护层31远离背板1的一侧，即第一子保护层31设于布线层2之上，第二子保护层32设于第一子保护层31之上；第一子保护层31覆盖位于显示区A与邦定区C的布线层2，第二子保护层32可以只覆盖显示区A的布线层2，只由第一子保护层31来减小显示区A与邦定区C之间的段差以及对邦定区C裸露的布线层2进行覆盖保护。
参照图3所示，第二子保护层32也可以覆盖位于显示区A与邦定区C的布线层2；使得显示区A与邦定区C的段差进一步减小。
在步骤S140，在所述保护层3上形成通孔33。
参照图2和图3所示，在保护层3上形成通孔33，通孔33设置在保护层3上，通孔33设于位于邦定区C的布线层2上，即当邦定区C覆盖有第一子保护层31与第二子保护层32时，该通孔33贯穿第一子保护层31以及第二子保护层32，当第二子保护层32只设置在显示区A时，只在第一子保护层31上设置通孔33，通孔33的数量可以是多个，通孔33可以与布线层2的导线一一对应，即一个通孔33对应一条导线，也可以多条导线对应一个通孔33。通孔33截面的形状可以是圆形，也可以是椭圆形、矩形、三角形或其他形状。
在步骤S150，在所述保护层3远离背板1的一侧形成连接层4，所述连接层4通过所述通孔33与所述布线层2连接。
参照图2和图5所示，在保护层3之上形成连接层4，连接层4可以是柔性金属线层，连接层4通过通孔33与布线层2连接，连接层4设于显示区A与邦定区C的保护层3之上，以及背板1的过渡区B，使得位于显示区A与邦定区C的连接层4连接，且均与布线层2连接。根据本公开的实施例，连接层4可以具有触控功能。在这种情况下，其可以包括位于显示区A中的触控电极层以及从触控电极层延伸出、经过过渡区B并在绑定区C经由通孔33连接到布线层2的触控电极引线。
参照图3和图4所示，本发明阵列基板的制备方法还可以包括在布线层2远离背板1的一侧形成像素定义层5，即像素定义层5设置于布线层2之上，像素定义层5可以覆盖位于显示区A与邦定区C的布线层2，像素定义层5也可以只覆盖位于显示区A的布线层2。
参照图4所示，当像素定义层5覆盖位于显示区A与邦定区C的布线层2时，本发明阵列基板的制备方法还可以包括在位于邦定区C的像素定义层5上形成过孔51，过孔51与通孔33连通，过孔51的数量也可以是多个，过孔51的数量可以与通孔33的数量相同，过孔51截面的形状可以是圆形，也可以是椭圆形、矩形、三角形或其他形状。
在邦定区C形成像素定义层5、第一子保护层31以及第二子保护层32时，在像素定义层5上设置过孔51，在第一子保护层31与第二子保护层32上设置通孔33，过孔51与通孔33连通，此时显示区A与邦定区C具有一致的层叠覆盖，即显示区A与邦定区C之间的段差较小或者不存在段差，在形成连接层4时，不会因为段差而造成连接层4金属残留较多，连接层4可以通过过孔51以及通孔33与布线层2连接，采用保护层3将邦定区C裸露的布线层2覆盖，在形成连接层4时，不会因为残留金属而使得布线层2产生短路，降低了短路风险，提高了阵列基板的安全性。
本公开的阵列基板的制备方法还可以包括形成显示层。显示层在显示区A内设于布线层2与保护层3之间，显示层的像素由像素定义层5限定。
上述所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中，如有可能，各实施例中所讨论的特征是可互换的。在上面的描述中，提供许多具体细节从而给出对本发明的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本发明的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组件、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本发明的各方面。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
本说明书中，用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包含”、“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
应可理解的是，本发明不将其应用限制到本说明书提出的部件的详细结构和布置方式。本发明能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本发明的范围内。应可理解的是，本说明书公开和限定的本发明延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本发明的多个可替代方面。本说明书所述的实施方式说明了已知用于实现本发明的最佳方式，并且将使本领域技术人员能够利用本发明。

Claims (18)

  1. 一种阵列基板，包括：
    背板，包括显示区和邦定区；
    布线层，设于所述背板之上；
    保护层，设于所述布线层远离所述背板的一侧，且覆盖位于所述显示区以及所述邦定区的布线层，位于所述邦定区的所述保护层上设有通孔；
    连接层，设于所述保护层远离所述背板的一侧，所述连接层通过所述通孔与所述布线层连接。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括：
    像素定义层，设于所述布线层与保护层之间，且覆盖位于所述显示区的所述布线层，或覆盖位于所述显示区的所述布线层以及位于邦定区的布线层，位于所述邦定区的像素定义层上设有与所述通孔连通的过孔。
  3. 根据权利要求1或2所述的阵列基板，其中，所述背板还包括：
    过渡区，设于所述显示区与所述邦定区之间。
  4. 根据权利要求1至3中任意一项所述的阵列基板，其中，所述保护层包括：
    第一子保护层，覆盖所述显示区以及所述邦定区；
    第二子保护层，覆盖所述显示区，或覆盖所述显示区以及所述邦定区。
  5. 根据权利要求1至4中任意一项所述的阵列基板，其中，所述通孔的数量为多个。
  6. 根据权利要求1至5中所述的阵列基板，还包括：
    显示层，在显示区内设于所述布线层与所述保护层之间，
    其中，显示层的像素由像素定义层限定。
  7. 根据权利要求6所述的阵列基板，其中，所述布线层包括用于驱动显示层发光的电极布线、晶体管的源极布线和/或漏极布线。
  8. 根据权利要求1至7中任意一项所述的阵列基板，其中，所述连接层包括：触控电极层，设于所述显示区内；以及触控电极引线，从所述触控电极层延伸出，并经由所述通孔连接到所述布线层。
  9. 根据权利要求1至8中任意一项所述的阵列基板，其中，位于所述邦定区的所述布线层裸露。
  10. 一种显示面板，包括：
    权利要求1-9任一项所述的阵列基板。
  11. 一种阵列基板的制备方法，包括：
    提供背板，所述背板包括显示区和邦定区；
    在所述背板之上形成布线层，所述布线层覆盖所述背板；
    在布线层远离所述背板的一侧形成保护层，所述保护层覆盖位于所述显示区以及所述 邦定区的布线层；
    在所述保护层上形成通孔；
    在所述保护层远离背板的一侧形成连接层，所述连接层通过所述通孔与所述布线层连接。
  12. 根据权利要求11所述的阵列基板的制备方法，其中，在形成布线层之后，所述阵列基板的制备方法还包括：
    在所述布线层远离所述背板的一侧形成像素定义层，所述像素定义层覆盖位于所述显示区的所述布线层，或覆盖位于所述显示区的所述布线层以及位于邦定区的布线层；
    在位于所述邦定区的像素定义层上形成过孔，所述过孔与所述通孔连通。
  13. 根据权利要求11或12所述的阵列基板的制备方法，其中，所述背板还包括：
    过渡区，设于所述显示区与所述邦定区之间。
  14. 根据权利要求11至13中任意一项所述的阵列基板的制备方法，其中，在布线层远离所述背板一侧的形成保护层，包括：
    在所述布线层远离所述背板的一侧形成第一子保护层，所述第一子保护层覆盖所述显示区以及所述邦定区；
    在所述第一子保护层远离所述背板的一侧形成第二子保护层，所述第二子保护层覆盖所述显示区，或覆盖所述显示区以及所述邦定区。
  15. 根据权利要求12所述的阵列基板的制备方法，还包括：
    形成显示层，
    其中，显示层在显示区内设于所述布线层与所述保护层之间，显示层的像素由像素定义层限定。
  16. 根据权利要求15所述的阵列基板的制备方法，其中，所述布线层包括用于驱动显示层发光的电极布线、晶体管的源极布线和/或漏极布线。
  17. 根据权利要求11至16中任意一项所述的阵列基板的制备方法，其中，所述连接层包括：触控电极层，设于所述显示区内；以及触控电极引线，从所述触控电极层延伸出，并经由所述通孔连接到所述布线层。
  18. 根据权利要求11至17中任意一项所述的阵列基板的制备方法，其中，位于所述邦定区的所述布线层裸露。
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