WO2020143100A1 - 一种显示面板及其制作方法以及显示装置 - Google Patents

一种显示面板及其制作方法以及显示装置 Download PDF

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Publication number
WO2020143100A1
WO2020143100A1 PCT/CN2019/075523 CN2019075523W WO2020143100A1 WO 2020143100 A1 WO2020143100 A1 WO 2020143100A1 CN 2019075523 W CN2019075523 W CN 2019075523W WO 2020143100 A1 WO2020143100 A1 WO 2020143100A1
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Prior art keywords
area
transparent conductive
conductive layer
region
substrate
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PCT/CN2019/075523
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English (en)
French (fr)
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李文英
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020143100A1 publication Critical patent/WO2020143100A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present invention relates to the field of display technology, and in particular, to a display panel, a manufacturing method thereof, and a display device.
  • a polymer stabilized vertical alignment (PSVA) type liquid crystal display panel as shown in FIG. 1, generally includes a first substrate 10 and a second substrate 20.
  • the first substrate 10 includes a base substrate 11 and a base substrate 11 It includes a display area 101, a gate driving circuit area 102 and a signal bus area 103, wherein the display area 101 includes a switch array layer 12 and a first transparent electrode layer 13, and the first transparent electrode layer 13 is a patterned electrode.
  • the gate driving circuit area 102 is used for setting a gate driving circuit, which includes a driving thin film transistor, the cross-sectional structure includes a metal layer 15, and the signal bus area 103 is used for setting a signal bus 14, through which the driving thin film transistor is connected to a signal source.
  • the second substrate 20 includes a second base substrate 21 and a second transparent conductive layer 22.
  • the second transparent conductive layer 22 is not patterned, that is, the second transparent conductive layer 22 covers the entire surface of the second substrate 20.
  • a capacitance is formed between the second transparent conductive layer 22 and the metal layer (gate metal layer, source-drain metal layer) in the first substrate 10 and the first transparent conductive layer 13.
  • the loss of the signal source (clock signal) input by the gate driving circuit in the gate driving circuit region 102 is excessive Big.
  • An object of the present invention is to provide a display panel, a manufacturing method thereof, and a display device, which can reduce the loss of the input signal source of the gate drive circuit and improve the display effect.
  • the present invention provides a display panel, which includes:
  • a first substrate the cross-sectional structure of which includes a first substrate substrate; when viewed from above, the first substrate substrate includes a display area, a gate driving circuit area, and a signal bus area, and the first substrate is located in the display area A switch array layer and a first transparent conductive layer are provided on the substrate; a driving thin film transistor is provided on the first base substrate in the gate drive circuit area, and a first base substrate in the signal bus area is provided At least one signal bus, the driving thin film transistor is connected to the signal source through the signal bus;
  • the cross-sectional structure of the second substrate includes a second transparent conductive layer, and the capacitance between the signal bus and the second transparent conductive layer is smaller than the first preset capacitance.
  • the present invention also provides a display device including any one of the above display panels.
  • the invention also provides a method for manufacturing a display panel, which includes:
  • a first substrate is provided, wherein the cross-sectional structure of the first substrate includes a first base substrate; in a top view, the first base substrate includes a display area, a gate driving circuit area, and a signal bus area, which are located in the The first base substrate in the display area is provided with a switch array layer and a first transparent conductive layer; the first base substrate in the gate drive circuit area is provided with a driving thin film transistor, which is located in the first portion of the signal bus area At least one signal bus is provided on a base substrate, and the driving thin film transistor is connected to the signal source through the signal bus;
  • a second base substrate is provided, and a second transparent conductive layer is not formed on the second base substrate corresponding to the signal bus area.
  • the display panel, the manufacturing method and the display device of the present invention by improving the second transparent conductive layer of the second substrate, reduce the capacitance between the signal bus and the second transparent conductive layer, and reduce the input gate drive circuit The loss of the signal source, thereby improving the display effect.
  • FIG. 1 is a schematic structural diagram of an existing display panel
  • FIG. 2 is a schematic structural diagram of a display panel according to Embodiment 1 of the present invention.
  • FIG. 3 is a first plan view of the second substrate in FIG. 2;
  • FIG. 4 is a second top view of the second substrate in FIG. 2;
  • FIG. 5 is a schematic structural diagram of a display panel according to Embodiment 2 of the present invention.
  • FIG. 6 is a first plan view of the second substrate in FIG. 5;
  • FIG. 7 is a second top view of the second substrate in FIG. 5;
  • FIG. 8 is a schematic structural diagram of a display panel according to Embodiment 3 of the present invention.
  • FIG. 9 is a top view of the second substrate in FIG. 8.
  • FIG. 10 is a schematic structural diagram of a display panel according to Embodiment 4 of the present invention.
  • FIG. 11 is a schematic structural diagram of a display panel according to Embodiment 5 of the present invention.
  • FIG. 12 is a schematic structural diagram of the first step of the manufacturing method of the display panel corresponding to FIG. 6.
  • FIG. 2 is a schematic structural diagram of a display panel according to Embodiment 1 of the present invention.
  • the display panel of this embodiment includes a first substrate 10 and a second substrate 20.
  • the first substrate 10 includes a display area 101, a gate driving circuit area 102, and a signal bus area 103.
  • the cross-sectional structure of the first substrate 10 includes a first base substrate 11 located in the display area 101.
  • a switch array layer 12 and a first transparent conductive layer 13 are sequentially arranged on the first base substrate 11, the switch array layer 12 and the first transparent conductive layer 13 are sequentially located on the first base substrate 11, and the switch array layer 12 includes switch elements , Such as thin film transistors.
  • the first transparent conductive layer 13 is a pixel electrode, and its material is ITO (indium tin oxide).
  • a driving thin film transistor is provided on the first base substrate 11 in the gate driving circuit region 102, and the cross-sectional structure of the driving thin film transistor includes a metal layer 15 including a source and drain metal layer and a gate metal Floor.
  • the cross-sectional structure of the driving thin film transistor includes source and drain metal layers and a gate metal layer.
  • the driving thin film transistor in the gate driving circuit area 102 is connected to a signal source through a signal bus 14; wherein the signal source is a bit clock signal.
  • At least one signal bus 14 is disposed on the first base substrate 11 in the signal bus area 103.
  • the cross-sectional structure of the second substrate 20 includes a second base substrate 21 and a second transparent conductive layer 23.
  • the capacitance between the signal bus 14 and the second transparent conductive layer 23 is smaller than the first preset capacitance.
  • the first preset capacitance can be set according to empirical values.
  • the second substrate 20 includes a first area 201, a second area 202, and a third area 203.
  • the position of the first area 201 corresponds to the position of the signal bus area 103.
  • the position of the second area 202 corresponds to the position of the gate driving circuit area 102, and the position of the third area 203 corresponds to the position of the display area 101.
  • part of the first region 201, the second region 202 and the third region 203 are all provided with a second transparent conductive layer 23. That is, the entire second area 202 and the third area 203 are provided with the second transparent conductive layer 23.
  • the area of the second transparent conductive layer 231 of the first area 201 is smaller than the area of the first area 201. Since the area between the signal bus and the second transparent conductive layer is reduced by reducing the area of the second transparent conductive layer in the first area, thereby reducing the capacitance between the signal bus and the second transparent conductive layer, That is, the load of the signal bus is reduced, thereby reducing the loss of the signal source.
  • a second transparent conductive layer 23 may be deposited on a part of the second base substrate 21 of the first region 201, the second region 202, and the third region 203.
  • a second transparent conductive layer may be deposited on the entire second base substrate 21 of the first area 201, the second area 202, and the third area 203, and then part of the second area of the first area 202 The transparent conductive layer 23 is removed.
  • the capacitance between the metal layer 15 and the first transparent conductive layer 23 is smaller than the second preset capacitance, and the second preset capacitance may be set according to an empirical value.
  • part of the first region 201, part of the second region 202 and part of the third region 203 are all provided with a second transparent conductive layer 23. That is, the entire third region 203 is provided with the second transparent conductive layer 23.
  • the area of the second transparent conductive layer 231 of the first region 201 is smaller than the area of the first region 201, and the area of the second transparent conductive layer 232 of the second region 202 is also smaller than the area of the second region 202.
  • the area of the second transparent conductive layer 231 of the first region 201 may be less than or equal to the area of the second transparent conductive layer 232 of the second region 202. Since the area of the second transparent conductive layer in the first area and the second area is reduced, the area directly facing between the signal bus and the second transparent conductive layer is reduced, and between the metal layer and the second transparent conductive layer Directly facing the area, thus reducing the capacitance between the signal bus and the second transparent conductive layer and the capacitance between the metal layer and the second transparent conductive layer, which further reduces the loss of the signal source, thus further improving display effect.
  • FIG. 5 is a schematic structural diagram of a display panel according to Embodiment 2 of the present invention.
  • the second region 202 and the third region 203 are provided with the second transparent conductive layer 23, that is, the first region 201 is not provided with the second transparent conductive layer 23.
  • the entire second region 202 and the entire third region 203 are provided with a second transparent conductive layer 23.
  • a second transparent conductive layer may be deposited on the second base substrate 21 of the second region 202 and the third region 203.
  • the second transparent conductive layer 23 may be deposited on the entire second base substrate 21, and then the second transparent conductive layer 23 of the second region 201 and the second transparent conductive layer 23 of the first region 202 Cut (for example, by laser cutting), and then remove the second transparent conductive layer of the first region 202 to obtain the structure shown in FIG. 6.
  • the specific manufacturing method please refer to the following. Since the area of the second transparent conductive layer in the first area is further reduced, the capacitance between the signal bus and the second transparent conductive layer is further reduced, that is, the loss of the signal source is further reduced, thus further improving the display effect.
  • part of the second region 202 and the entire third region 203 are provided with the second transparent conductive layer 23.
  • the area of the second transparent conductive layer 222 of the second area 202 is smaller than the area of the second area 202.
  • the area of the second transparent conductive layer 23 in the second region 202 can be set according to specific requirements. Since the area of the second transparent conductive layer in the second area is reduced, the capacitance between the metal layer and the second transparent conductive layer is reduced, that is, the loss of the signal source is further reduced, and the display effect is further improved.
  • FIG. 8 is a schematic structural diagram of a display panel according to Embodiment 3 of the present invention.
  • the third region 203 is provided with the second transparent conductive layer 23, that is, neither the first region 201 nor the second region 202 is provided with the second transparent conductive layer 23.
  • a second transparent conductive layer may be deposited on the second base substrate 21 of the third region 203.
  • a second transparent conductive layer may be deposited on the entire second base substrate 21, and then the second transparent conductive layer of the third region and the second transparent conductive layer of the second region 201 and the first region 202 23 Cut (for example, by laser cutting), and then remove the second transparent conductive layer of the second region 201 and the first region 202.
  • the capacitance between the metal layer in the gate driving circuit area and the second transparent conductive layer is reduced, That is to further reduce the loss of the signal source.
  • FIG. 10 is a schematic structural diagram of a display panel according to Embodiment 4 of the present invention.
  • the thickness of the second transparent conductive layer of the first region 201 is smaller than the thickness of the second transparent conductive layer of the second region 202 and the thickness of the third region 203 The thickness of the second transparent conductive layer. That is, the thickness of the second transparent conductive layer of the second region 202 and the thickness of the second transparent conductive layer of the third region 203 are both greater than the thickness of the second transparent conductive layer of the first region 201.
  • the transparent conductive layer on the second base substrate can be deposited, and then the transparent conductive layer on the first region 201 can be thinned to reduce the second transparent conductive layer on the first region 201 thickness of.
  • the thickness of the second transparent conductive layer of the first region 201 is reduced, the distance between the signal bus and the second transparent conductive layer is increased, so that the capacitance between the signal bus and the second transparent conductive layer becomes Small, which reduces the loss of the signal source.
  • the thickness of the second transparent conductive layer of the second region 202 is equal to the thickness of the second transparent conductive layer of the third region 203.
  • FIG. 11 is a schematic structural diagram of a display panel according to Embodiment 5 of the present invention.
  • the thickness of the second transparent conductive layer of the first region 201 and the thickness of the second transparent conductive layer of the second region 202 are both smaller than that of the third region 203 The thickness of the second transparent conductive layer. That is, the thickness of the transparent conductive layer in the first region 201 and the second transparent conductive layer in the second region 202 are relatively thin.
  • the thickness of the second transparent conductive layer of the second region 202 is thinned, so the gap between the metal layer in the gate driving circuit area and the second transparent conductive layer can be increased To reduce the capacitance between the metal layer and the second transparent conductive layer in the gate driving circuit area, thereby further reducing the loss of the signal source.
  • the thickness of the second transparent conductive layer of the first region 201 is equal to the thickness of the second transparent conductive layer of the second region 202.
  • the thickness of the second transparent conductive layer of the first region 201 is smaller than the thickness of the second transparent conductive layer of the second region 202, and the thickness of the second transparent conductive layer of the second region 202 The thickness is smaller than the thickness of the second transparent conductive layer of the third region 203.
  • the capacitance between the metal layer and the second transparent conductive layer can also be reduced, thereby reducing the signal in the gate driving circuit area and the signal bus area
  • the loss of the source avoids the attenuation of the signal source, which is beneficial to the output signal of the gate drive circuit (GOA circuit) being closer to the square wave signal, improving the stability of the scanning signal, and thus improving the display effect.
  • the design space of the GOA circuit can be reduced, which is favorable for forming a narrow bezel panel.
  • the invention also provides a method for manufacturing a display panel, which includes:
  • the cross-sectional structure of the first substrate 10 includes a first base substrate 11, a switch array layer 12 and a first transparent conductive layer are sequentially arranged on the first base substrate 11 in the display area 101
  • the layer 13, the switch array layer 12 and the first transparent conductive layer 13 are sequentially located on the first base substrate 11, and the switch array layer 12 includes switching elements, such as thin film transistors.
  • the first transparent conductive layer 13 is a pixel electrode, and its material is ITO (indium tin oxide).
  • a driving thin film transistor is provided on the first base substrate 11 in the gate driving circuit region 102, and the cross-sectional structure of the driving thin film transistor includes a metal layer 15 including a source and drain metal layer and a gate metal Floor.
  • the driving thin film transistor in the gate driving circuit area 102 is connected to a signal source through a signal bus 14; wherein the signal source is a bit clock signal.
  • At least one signal bus 14 is disposed on the first base substrate 11 in the signal bus area 103.
  • step S102 that is, the second transparent conductive layer not formed on the second base substrate corresponding to the signal bus area includes:
  • an entire second transparent conductive layer 23 is formed on the second base substrate 21.
  • the second transparent conductive layer corresponding to the signal bus area (that is, the second transparent conductive layer of the first area 201) and the rest (the second area 202 and the third area 203) are The second transparent conductive layer is separated.
  • the second transparent conductive layer corresponding to the signal bus area is removed by edge washing, that is, the second transparent conductive layer of the first area 201 is removed, so that the second area 202 and the third area 203 The second transparent conductive layer remains.
  • part of the second transparent conductive layer of the first region 201 may also be removed.
  • step S102 includes:
  • a light shielding plate is provided on the second base substrate 21 corresponding to the signal bus area, and a second transparent conductive layer is deposited on the second base substrate, so as to connect the display area and the gate A second transparent conductive layer is deposited on the second base substrate corresponding to the driving circuit area.
  • a light shielding plate is provided on the second base substrate 21 corresponding to the signal bus area, and a second transparent conductive layer is deposited on the second base substrate 21 above the light shielding plate, So that the second transparent conductive layer 23 is deposited on the second base substrate 21 corresponding to the display area and the gate driving circuit area, and the second base substrate 21 corresponding to the signal bus area is not deposited ⁇ transparent conductive layer 23.
  • step S102 that is, the step of not forming the second transparent conductive layer on the second base substrate corresponding to the signal bus area includes:
  • No second transparent conductive layer is formed on the second base substrate corresponding to the signal bus area and the gate driving circuit area.
  • the second transparent conductive layer 23 is not formed on the second base substrate 21 corresponding to the signal bus region and the gate driving circuit region, that is, in the first region 201 and the second region In 202, the second transparent conductive layer 23 is not provided.
  • an entire second transparent conductive layer is made, and then the second transparent conductive layer of the first region 201 and the second region 202 and the second transparent conductive layer of the third region 203 are cut with a laser, and then the first The second transparent conductive layer of the region 201 and the second region 202 is removed; or a light blocking plate is provided above the first region 201 and the second region 202 to avoid depositing the second transparent conductive layer on the first region 201 and the second region 202, In order to deposit the second transparent conductive layer on the second base substrate 21 of the third region 203.
  • the specific manufacturing method is the same as the above manufacturing method, and will not be repeated here.
  • part of the second transparent conductive layer in the first region and the second region may also be removed.
  • the present invention also provides a display device including any one of the above display panels.
  • the display panel, the manufacturing method and the display device of the present invention by improving the second transparent conductive layer of the second substrate, reduce the capacitance between the signal bus area and the second transparent conductive layer, and reduce the input gate drive circuit The loss of the signal source thus improves the display effect.

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Abstract

一种显示面板及其制作方法以及显示装置，该显示面板包括：第一基板（10），其截面结构包括第一衬底基板（11），包括显示区（101）、栅极驱动电路区（102）以及信号总线区（103），位于信号总线区（103）的第一衬底基板（11）上设置有至少一信号总线（14）；第二基板（20），其截面结构包括第二透明导电层（23），信号总线（14）与第二透明导电层（23）之间的电容小于第一预设电容。

Description

一种显示面板及其制作方法以及显示装置 技术领域
本发明涉及显示技术领域，特别是涉及一种显示面板及其制作方法以及显示装置。
 背景技术
聚合物稳定垂直对齐（Polymer Stabilized Vertical Alignment，PSVA）型液晶显示面板，如图1所示，通常包括第一基板10、第二基板20，第一基板10包括衬底基板11，衬底基板11包括显示区101、栅极驱动电路区102以及信号总线区103，其中显示区101包括开关阵列层12以及第一透明电极层13，第一透明电极层13为图案化电极。栅极驱动电路区102用于设置栅极驱动电路，其包括驱动薄膜晶体管，截面结构包括金属层15，信号总线区103用于设置信号总线14，驱动薄膜晶体管通过该信号总线与信号源连接。
第二基板20包括第二衬底基板21和第二透明导电层22，第二透明导电层22未图案化，也即，第二透明导电层22整面覆盖第二基板20。第二透明导电层22与第一基板10中的金属层（栅极金属层、源漏极金属层）以及第一透明导电层13之间形成电容。
 技术问题
由于信号总线区103中的信号总线14和第二透明导电层22之间形成的电容较大，导致栅极驱动电路区102中的栅极驱动电路所输入的信号源（clock信号）的损耗过大。
 技术解决方案
本发明的目的在于提供一种显示面板及其制作方法以及显示装置，能够降低栅极驱动电路的所输入的信号源的损耗，提高显示效果。
为解决上述技术问题，本发明提供一种显示面板，其包括：
第一基板，其截面结构包括第一衬底基板；在俯视角下，所述第一衬底基板包括显示区、栅极驱动电路区以及信号总线区，位于所述显示区的第一衬底基板上设置有开关阵列层和第一透明导电层；位于所述栅极驱动电路区的第一衬底基板上设置有驱动薄膜晶体管，位于所述信号总线区的第一衬底基板上设置有至少一信号总线，所述驱动薄膜晶体管通过所述信号总线与信号源连接；
第二基板，其截面结构包括第二透明导电层，所述信号总线与所述第二透明导电层之间的电容小于第一预设电容。
本发明还提供一种显示装置，其包括上述任意一种显示面板。
本发明还提供一种显示面板的制作方法，其包括：
提供第一基板，其中所述第一基板的截面结构包括第一衬底基板；在俯视角下，所述第一衬底基板包括显示区、栅极驱动电路区以及信号总线区，位于所述显示区的第一衬底基板上设置有开关阵列层和第一透明导电层；位于所述栅极驱动电路区的第一衬底基板上设置有驱动薄膜晶体管，位于所述信号总线区的第一衬底基板上设置有至少一信号总线，所述驱动薄膜晶体管通过所述信号总线与信号源连接；
提供第二衬底基板，在与所述信号总线区对应的第二衬底基板上未制作第二透明导电层。
 有益效果
本发明的显示面板及其制作方法以及显示装置，通过对第二基板的第二透明导电层进行改进，减少了信号总线与第二透明导电层之间的电容，降低了输入栅极驱动电路的信号源的损耗，从而提高了显示效果。
 附图说明
图1为现有的显示面板的结构示意图；
图2为本发明实施例一的显示面板的结构示意图；
图3为图2中的第二基板的第一种俯视图；
图4为图2中的第二基板的第二种俯视图；
图5为本发明实施例二的显示面板的结构示意图；
图6为图5中的第二基板的第一种俯视图；
图7为图5中的第二基板的第二种俯视图；
图8为本发明实施例三的显示面板的结构示意图；
图9为图8中的第二基板的俯视图；
图10为本发明实施例四的显示面板的结构示意图；
图11为本发明实施例五的显示面板的结构示意图；
图12为图6对应的显示面板的制作方法第一步的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图2至4，图2为本发明实施例一的显示面板的结构示意图。
如图2所示，本实施例的显示面板包括第一基板10和第二基板20。
在俯视角下，第一基板10包括显示区101、栅极驱动电路区102以及信号总线区103，所述第一基板10的截面结构包括第一衬底基板11，位于所述显示区101的第一衬底基板11上依次设置有开关阵列层12和第一透明导电层13，开关阵列层12和第一透明导电层13依次位于第一衬底基板11上，开关阵列层12包括开关元件，比如薄膜晶体管。其中所述第一透明导电层13为像素电极，其材料为ITO（氧化铟锡）。位于所述栅极驱动电路区102的第一衬底基板11上设置有驱动薄膜晶体管，驱动薄膜晶体管的截面结构包括金属层15，该金属层15包括源极和漏极金属层、栅极金属层。例如，在俯视角下，驱动薄膜晶体管的截面结构包括源极和漏极金属层、栅极金属层。所述栅极驱动电路区102中的驱动薄膜晶体管通过信号总线14与信号源连接；其中信号源比如位时钟信号。位于所述信号总线区103的第一衬底基板11上设置有至少一信号总线14。
所述第二基板20的截面结构包括第二衬底基板21和第二透明导电层23，所述信号总线14与所述第二透明导电层23之间的电容小于第一预设电容，该第一预设电容为可以根据经验值设置。
其中，在俯视角下，所述第二基板20包括第一区域201和第二区域202以及第三区域203，所述第一区域201的位置与所述信号总线区103的位置对应，所述第二区域202的位置与所述栅极驱动电路区102的位置对应，所述第三区域203的位置与所述显示区101的位置对应。
在一实施方式中，如图3所示，部分所述第一区域201、第二区域202以及第三区域203均设置有第二透明导电层23。也即整个第二区域202和第三区域203都设置有第二透明导电层23。所述第一区域201的第二透明导电层231的面积小于第一区域201的面积。由于通过减小第一区域的第二透明导电层的面积，减小信号总线与第二透明导电层之间的正对面积，从而减小了信号总线与第二透明导电层之间的电容，也即减小了信号总线的负载量，进而减小了信号源的损耗。
在具体制作过程中，一实施方式中，可以在部分所述第一区域201、第二区域202以及第三区域203的第二衬底基板21上沉积第二透明导电层23。另一实施方式中，可以在整个所述第一区域201、第二区域202以及第三区域203的第二衬底基板21上沉积第二透明导电层，之后将部分第一区域202的第二透明导电层23去除。
其中，为了进一步减小信号源的损耗，所述金属层15与所述第一透明导电层23之间的电容小于第二预设电容，第二预设电容可以根据经验值设置。如图4所示，部分所述第一区域201、部分第二区域202以及第三区域203均设置有第二透明导电层23。也即整个第三区域203设置有第二透明导电层23。所述第一区域201的第二透明导电层231的面积小于第一区域201的面积，所述第二区域202的第二透明导电层232的面积也小于第二区域202的面积。所述第一区域201的第二透明导电层231的面积可以小于或者等于所述第二区域202的第二透明导电层232的面积。由于通过减小第一区域和第二区域的第二透明导电层的面积，从而减小了信号总线与第二透明导电层之间的正对面积，以及金属层与第二透明导电层之间的正对面积，因而减小了信号总线与第二透明导电层之间的电容以及金属层与第二透明导电层之间的电容，也即进一步减小了信号源的损耗，因此进一步提高了显示效果。
请参照图5至7，图5为本发明实施例二的显示面板的结构示意图。
在另一实施例中，如图5所示，第二区域202和第三区域203设置有第二透明导电层23，也即第一区域201未设置第二透明导电层23。在一实施方式中，如图6所示，整个第二区域202和整个第三区域203设置有第二透明导电层23。在具体制作过程中，一实施方式中，可以在第二区域202和第三区域203的第二衬底基板21上沉积第二透明导电层。在另一实施方式中，可以在整个第二衬底基板21上沉积第二透明导电层23，之后将第二区域201的第二透明导电层23与第一区域202的第二透明导电层23切割开（比如采用激光切割开），再将第一区域202的第二透明导电层去除，得到图6所示的结构，具体制作方法请参照下文。由于进一步减小第一区域的第二透明导电层的面积，从而进一步减小了信号总线与第二透明导电层之间的电容，也即进一步减小了信号源的损耗，因而进一步提高了显示效果。
在一实施方式中，如图7所示，部分第二区域202和整个第三区域203设置有第二透明导电层23。其中所述第二区域202的第二透明导电层222的面积小于第二区域202的面积。此时可以根据具体需求设置所述第二区域202中第二透明导电层23的面积大小。由于减小第二区域的第二透明导电层的面积，从而减小了金属层与第二透明导电层之间的电容，也即进一步减小了信号源的损耗，也进一步提高了显示效果。
请参照图8至9，图8为本发明实施例三的显示面板的结构示意图。
在另一实施例中，如图8和9所示，第三区域203设置有第二透明导电层23，也即第一区域201和第二区域202均未设置第二透明导电层23。在具体制作过程中，一实施方式中，可以在第三区域203的第二衬底基板21上沉积第二透明导电层。另一实施方式中，可以在整个第二衬底基板21上沉积第二透明导电层，之后将第三区域的第二透明导电层与第二区域201和第一区域202的第二透明导电层23切割开（比如采用激光切割开），再将第二区域201和第一区域202的第二透明导电层去除。在上一实施例的基础上，由于进一步减小了第二区域的第二透明导电层的面积，从而减小了栅极驱动电路区中的金属层与第二透明导电层之间的电容，也即进一步减小了信号源的损耗。
请参照图10，图10为本发明实施例四的显示面板的结构示意图。
在另一实施例中，如图10所示，所述第一区域201的第二透明导电层的厚度小于所述第二区域202的第二透明导电层的厚度以及所述第三区域203的第二透明导电层的厚度。也即所述第二区域202的第二透明导电层的厚度以及所述第三区域203的第二透明导电层的厚度均大于所述第一区域201的第二透明导电层的厚度。在一实施方式中，可以通过在第二衬底基板上沉积透明导电层，之后再对第一区域201的透明导电层进行打薄，以减小所述第一区域201的第二透明导电层的厚度。由于通过减小所述第一区域201的第二透明导电层的厚度，从而增大了信号总线与第二透明导电层之间的间距，使得信号总线与第二透明导电层之间的电容变小，进而减小了信号源的损耗。
为了简化制程工艺，降低生产成本，所述第二区域202的第二透明导电层的厚度等于所述第三区域203的第二透明导电层的厚度。
请参照图11，图11为本发明实施例五的显示面板的结构示意图。
在另一实施例中，如图11所示，所述第一区域201的第二透明导电层的厚度、所述第二区域202的第二透明导电层的厚度均小于所述第三区域203的第二透明导电层的厚度。也即第一区域201的透明导电层和第二区域202的第二透明导电层的厚度都比较薄。由于在上一实施例的基础上，对所述第二区域202的第二透明导电层的厚度进行减薄，因此可以增大栅极驱动电路区中的金属层与第二透明导电层之间间距，以减小栅极驱动电路区中的金属层与第二透明导电层之间的电容，进而进一步减小了信号源的损耗。在一实施方式中，所述第一区域201的第二透明导电层的厚度等于所述第二区域202的第二透明导电层的厚度。
在另一实施方式中，所述第一区域201的第二透明导电层的厚度小于所述第二区域202的第二透明导电层的厚度，所述第二区域202的第二透明导电层的厚度小于所述第三区域203的第二透明导电层的厚度。
由于通过减小信号总线与第二透明导电层之间的电容，此外还可减小金属层与第二透明导电层之间的电容，从而减小了栅极驱动电路区以及信号总线区的信号源的损耗，避免信号源发生衰减，有利于栅极驱动电路（GOA电路）的输出信号更接近于方波信号，提高了扫描信号的稳定性，进而提高了显示效果。同时还可使GOA电路的设计空间减小，有利于形成窄边框的面板。
本发明还提供一种显示面板的制作方法，其包括：
S101、提供第一基板10；
如图2所示，其中所述第一基板10的截面结构包括第一衬底基板11，位于所述显示区101的第一衬底基板11上依次设置有开关阵列层12和第一透明导电层13，开关阵列层12和第一透明导电层13依次位于第一衬底基板11上，开关阵列层12包括开关元件，比如薄膜晶体管。其中所述第一透明导电层13为像素电极，其材料为ITO（氧化铟锡）。位于所述栅极驱动电路区102的第一衬底基板11上设置有驱动薄膜晶体管，驱动薄膜晶体管的截面结构包括金属层15，该金属层15包括源极和漏极金属层、栅极金属层。所述栅极驱动电路区102中的驱动薄膜晶体管通过信号总线14与信号源连接；其中信号源比如位时钟信号。位于所述信号总线区103的第一衬底基板11上设置有至少一信号总线14。
S102、提供第二衬底基板，在与所述信号总线区对应的第二衬底基板上未制作第二透明导电层。
在一实施方式中，步骤S102，也即所述在与所述信号总线区对应的第二衬底基板上未制作第二透明导电层包括：
S1021、在所述第二衬底基板21上制作第二透明导电层23；
也即在所述第二衬底基板21上制作整层第二透明导电层23。
S1022、采用激光将与所述信号总线区对应的第二透明导电层与其余的第二透明导电层进行分离；
如图12所示，采用激光将与所述信号总线区对应的第二透明导电层（也即第一区域201的第二透明导电层）与其余（第二区域202和第三区域203）的第二透明导电层进行分离。
S1023、通过洗边方式将与所述信号总线区对应的第二透明导电层去除。
返回图6，再通过洗边方式将与所述信号总线区对应的第二透明导电层去除，也即将第一区域201的第二透明导电层去除，使得第二区域202和第三区域203的第二透明导电层保留。
可以理解的，也可以将部分第一区域201的第二透明导电层去除。
在另一实施方式中，步骤S102包括：
S1025、在与所述信号总线区对应的第二衬底基板21上设置遮光板，在所述第二衬底基板上沉积第二透明导电层，以在与所述显示区和所述栅极驱动电路区对应的第二衬底基板上沉积第二透明导电层。
例如，如图6所示，在与所述信号总线区对应的第二衬底基板21上设置遮光板，并在所述遮光板的上方向第二衬底基板21沉积第二透明导电层，使得在与所述显示区和所述栅极驱动电路区对应的第二衬底基板21上沉积第二透明导电层23，在与所述信号总线区对应的第二衬底基板21未沉积第二透明导电层23。
在另一实施例中，步骤S102，也即所述在与所述信号总线区对应的第二衬底基板上未制作第二透明导电层的步骤包括：
S103、在与所述信号总线区和所述栅极驱动电路区对应的第二衬底基板上未制作第二透明导电层。
如图9所示，在与所述信号总线区和所述栅极驱动电路区对应的第二衬底基板21上未制作第二透明导电层23，也即在第一区域201和第二区域202均未设置第二透明导电层23。
比如制作整层第二透明导电层，再用激光将第一区域201和第二区域202的第二透明导电层与第三区域203的第二透明导电层切割，之后通过洗边方式将第一区域201和第二区域202的第二透明导电层去除；或者在第一区域201和第二区域202的上方设置遮光板，避免在第一区域201和第二区域202沉积第二透明导电层，以在第三区域203的第二衬底基板21上沉积第二透明导电层。具体的制作方法与上面的制作方法相同，在此不再赘述。
可以理解的，也可将部分第一区域和第二区域的第二透明导电层去除。
本发明还提供一种显示装置，其包括上述任意一种显示面板。
本发明的显示面板及其制作方法以及显示装置，通过对第二基板的第二透明导电层进行改进，减少了信号总线区与第二透明导电层之间的电容，降低了输入栅极驱动电路的信号源的损耗，从而提高了显示效果。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其包括：
    第一基板，其截面结构包括第一衬底基板；在俯视角下，所述第一衬底基板包括显示区、栅极驱动电路区以及信号总线区，位于所述显示区的第一衬底基板上设置有开关阵列层和第一透明导电层；位于所述栅极驱动电路区的第一衬底基板上设置有驱动薄膜晶体管，位于所述信号总线区的第一衬底基板上设置有至少一信号总线，所述驱动薄膜晶体管通过所述信号总线与信号源连接；
    第二基板，其截面结构包括第二透明导电层，所述信号总线与所述第二透明导电层之间的电容小于第一预设电容。
  2. 根据权利要求1所述的显示面板，其中
    所述驱动薄膜晶体管的截面结构包括金属层，所述金属层与所述第二透明导电层之间的电容小于第二预设电容。
  3. 根据权利要求2所述的显示面板，其中
    在俯视角下，所述第二基板包括第一区域和第二区域以及第三区域，所述第一区域的位置与所述信号总线区的位置对应，所述第二区域的位置与所述栅极驱动电路区的位置对应，所述第三区域的位置与所述显示区的位置对应；
    至少第三区域设置有第二透明导电层。
  4. 根据权利要求3所述的显示面板，其中
    部分所述第一区域覆盖有第二透明导电层，部分所述第二区域设置有第二透明导电层，所述第三区域设置有第二透明导电层。
  5. 根据权利要求4所述的显示面板，其中
    所述第一区域的第二透明导电层的面积小于或等于所述第二区域的第二透明导电层的面积。
  6. 根据权利要求3所述的显示面板，其中
    至少部分所述第二区域以及所述第三区域均设置有第二透明导电层。
  7. 根据权利要求1所述的显示面板，其中
    部分所述第一区域、所述第二区域以及所述第三区域均设置有第二透明导电层。
  8. 根据权利要求1所述的显示面板，其中
    所述第二区域以及所述第三区域均设置有第二透明导电层。
  9. 根据权利要求2所述的显示面板，其中
    所述第一区域的第二透明导电层的厚度、所述第二区域的第二透明导电层的厚度均小于所述第三区域的第二透明导电层的厚度。
  10. 根据权利要求9所述的显示面板，其中
    所述第一区域的第二透明导电层的厚度小于或等于所述第二区域的第二透明导电层的厚度。
  11. 根据权利要求1所述的显示面板，其中
    所述第一区域的第二透明导电层的厚度小于所述第二区域的第二透明导电层的厚度以及所述第三区域的第二透明导电层的厚度。
  12. 根据权利要求11所述的显示面板，其中
    所述第二区域的第二透明导电层的厚度等于所述第三区域的第二透明导电层的厚度。
  13. 一种显示装置，其包括显示面板，其包括：
    第一基板，其截面结构包括第一衬底基板；在俯视角下，所述第一衬底基板包括显示区、栅极驱动电路区以及信号总线区，位于所述显示区的第一衬底基板上设置有开关阵列层和第一透明导电层；位于所述栅极驱动电路区的第一衬底基板上设置有驱动薄膜晶体管，位于所述信号总线区的第一衬底基板上设置有至少一信号总线，所述驱动薄膜晶体管通过所述信号总线与信号源连接；
    第二基板，其截面结构包括第二透明导电层，所述信号总线与所述第二透明导电层之间的电容小于第一预设电容。
  14. 根据权利要求13所述的显示装置，其中
    所述驱动薄膜晶体管的截面结构包括金属层，所述金属层与所述第二透明导电层之间的电容小于第二预设电容。
  15. 根据权利要求14所述的显示装置，其中
    在俯视角下，所述第二基板包括第一区域和第二区域以及第三区域，所述第一区域的位置与所述信号总线区的位置对应，所述第二区域的位置与所述栅极驱动电路区的位置对应，所述第三区域的位置与所述显示区的位置对应；
    至少第三区域设置有第二透明导电层。
  16. 根据权利要求14所述的显示装置，其中
    所述第一区域的第二透明导电层的厚度、所述第二区域的第二透明导电层的厚度均小于所述第三区域的第二透明导电层的厚度。
  17. 一种显示面板的制作方法，其包括：
    提供第一基板，其中所述第一基板的截面结构包括第一衬底基板；在俯视角下，所述第一衬底基板包括显示区、栅极驱动电路区以及信号总线区，位于所述显示区的第一衬底基板上设置有开关阵列层和第一透明导电层；位于所述栅极驱动电路区的第一衬底基板上设置有驱动薄膜晶体管，位于所述信号总线区的第一衬底基板上设置有至少一信号总线，所述驱动薄膜晶体管通过所述信号总线与信号源连接；
    提供第二衬底基板，在与所述信号总线区对应的第二衬底基板上未制作第二透明导电层。
  18. 根据权利要求17所述的显示面板的制作方法，其中所述在与所述信号总线区对应的第二衬底基板上未制作第二透明导电层包括：
    在所述第二衬底基板上制作第二透明导电层；
    采用激光将与所述信号总线区对应的第二透明导电层与其余的第二透明导电层进行分离；
    通过洗边方式将与所述信号总线区对应的第二透明导电层去除。
  19. 根据权利要求17所述的显示面板的制作方法，其中
    在与所述信号总线区对应的第二衬底基板上设置遮光板；
    在所述第二衬底基板上沉积第二透明导电层，以在与所述显示区和所述栅极驱动电路区对应的第二衬底基板上沉积第二透明导电层。
  20. 根据权利要求17所述的显示面板的制作方法，其中所述在与所述信号总线区对应的第二衬底基板上未制作第二透明导电层的步骤包括：
    在与所述信号总线区和所述栅极驱动电路区对应的第二衬底基板上未制作第二透明导电层。
PCT/CN2019/075523 2019-01-07 2019-02-20 一种显示面板及其制作方法以及显示装置 WO2020143100A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060009749A (ko) * 2004-07-26 2006-02-01 삼성전자주식회사 표시장치
CN104090406A (zh) * 2014-07-17 2014-10-08 深圳市华星光电技术有限公司 显示面板及其彩色滤光片基板
CN105824157A (zh) * 2015-01-28 2016-08-03 群创光电股份有限公司 液晶显示面板
US20170146871A1 (en) * 2015-11-25 2017-05-25 Japan Display Inc. Liquid crystal display device
CN108445684A (zh) * 2018-02-27 2018-08-24 上海中航光电子有限公司 阵列基板、显示面板与显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4502806B2 (ja) * 2002-07-26 2010-07-14 サムスン エレクトロニクス カンパニー リミテッド 上部基板、これを有する液晶表示装置及びこれの製造方法
CN103472606B (zh) * 2013-09-27 2017-02-01 京东方科技集团股份有限公司 一种液晶显示面板及显示装置
CN106773227A (zh) * 2017-03-02 2017-05-31 上海天马微电子有限公司 一种液晶显示装置及液晶显示装置的制造方法
CN107065329A (zh) * 2017-06-05 2017-08-18 京东方科技集团股份有限公司 显示基板以及制备方法、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060009749A (ko) * 2004-07-26 2006-02-01 삼성전자주식회사 표시장치
CN104090406A (zh) * 2014-07-17 2014-10-08 深圳市华星光电技术有限公司 显示面板及其彩色滤光片基板
CN105824157A (zh) * 2015-01-28 2016-08-03 群创光电股份有限公司 液晶显示面板
US20170146871A1 (en) * 2015-11-25 2017-05-25 Japan Display Inc. Liquid crystal display device
CN108445684A (zh) * 2018-02-27 2018-08-24 上海中航光电子有限公司 阵列基板、显示面板与显示装置

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