WO2013091437A1 - 液晶显示装置、阵列基板及其制造方法 - Google Patents

液晶显示装置、阵列基板及其制造方法 Download PDF

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Publication number
WO2013091437A1
WO2013091437A1 PCT/CN2012/083330 CN2012083330W WO2013091437A1 WO 2013091437 A1 WO2013091437 A1 WO 2013091437A1 CN 2012083330 W CN2012083330 W CN 2012083330W WO 2013091437 A1 WO2013091437 A1 WO 2013091437A1
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WIPO (PCT)
Prior art keywords
array substrate
pixel
blocking structure
liquid crystal
electrode
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PCT/CN2012/083330
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English (en)
French (fr)
Inventor
宋省勋
马俊才
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北京京东方光电科技有限公司
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Priority to US13/704,811 priority Critical patent/US9348184B2/en
Publication of WO2013091437A1 publication Critical patent/WO2013091437A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes

Definitions

  • Liquid crystal display device array substrate, and manufacturing method thereof
  • Embodiments of the present invention relate to a liquid crystal display device, an array substrate, and a method of fabricating the same. Background technique
  • ADSDS Advanced Super Dimension Switch
  • ADvanced Super Dimension Switch ie
  • the ADS technology forms a multi-dimensional electric field by the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer, so that all the orientations between the slit electrodes in the liquid crystal cell and the slit electrode are directly above.
  • the liquid crystal molecules are capable of rotating, thereby improving the liquid crystal working efficiency and increasing the light transmittance.
  • ADS technology can improve the picture quality of thin film transistor liquid crystal display (TFT-LCD), which has high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no squeeze water ripple (push Mura) and other advantages.
  • TFT-LCD thin film transistor liquid crystal display
  • ADS technology overcomes the problem of low light transmittance in the IPS (In-Plane-Switching) technology and achieves high light transmittance with a wide viewing angle.
  • the ADS technology differs in that the common electrode and the pixel electrode of the liquid crystal panel (ADS liquid crystal panel) using the ADS technology are located in different layers, which are slit electrodes and plate electrodes, respectively, and ADS liquid crystal.
  • the common electrode and the pixel electrode of the panel are both formed of a transparent electrode, and high transmittance can be achieved.
  • the distance between the pixel electrodes of the ADS liquid crystal panel is much narrower than the distance between the pixel electrodes of the IPS liquid crystal panel, so that a stronger multi-dimensional electric field is generated, and the effective voltage applied to the liquid crystal will increase, thereby lowering the driving voltage. , can greatly improve the light transmittance.
  • the liquid crystal panel is generally formed by a pair of upper and lower substrates, and a liquid crystal layer is filled between the upper and lower substrates.
  • the upper substrate that is, the color filter substrate may include a transparent substrate (for example, a glass substrate) 19; a light blocking film or a black matrix (BM, 2) formed on the inner side of the transparent substrate 19, and a color resin 3 And an overcoat 4; and an antistatic conductive film (for example, an outer ITO film) formed on the outer side of the transparent substrate 19.
  • BM black matrix
  • the lower substrate that is, the array substrate may include a transparent substrate (for example, a glass substrate) 12; and a first conductive film (for example, a first ITO film) 11 formed on the transparent substrate 12, an insulating layer 10, and an amorphous silicon layer (a) -Si ) 9, data line 8, passivation layer 7 and second conductive film (for example, the second layer of ITO film) 6.
  • a liquid crystal (LC) layer 5 is filled between the upper substrate and the lower substrate.
  • the first conductive film 11 is a common electrode and is a plate electrode
  • the second conductive film 6 is a pixel electrode
  • the pixel electrode includes a slit which is a slit-shaped electrode.
  • FIG. 2 is a partial plan view showing a lower substrate of the liquid crystal panel of the prior art using the ADS technology, that is, an array substrate.
  • the array substrate of the ADS liquid crystal panel may include, for example, a data line 8, a common electrode 11, a pixel electrode 6, a contact hole 13, a source/drain 14 of the amorphous silicon thin film transistor 9, and a gate line. 15 and so on.
  • Figure 3 is a cross-sectional view of the area A in Figure 2. As shown in FIG.
  • the upper layer of the common electrode 11 is an insulating layer 10
  • the upper layer of the insulating layer 10 is an amorphous silicon thin film transistor 9
  • the upper layer of the amorphous silicon thin film transistor 9 is a data line 8
  • the upper layer of the data line 8 is passivated.
  • Layer 7, the upper layer of the passivation layer is the pixel electrode 6.
  • the common electrode of the liquid crystal panel is located at the lower portion of the pixel electrode, and the direction of the electric field applied to the liquid crystal in the vicinity of the data line is not uniform. Therefore, when a white screen is displayed (a voltage is required to be applied sufficiently), a liquid crystal alignment abnormality 16 (see Fig. 4) appears at the end of the pixel electrode, resulting in a partial black color and uneven brightness. As shown in FIG. 4, when the liquid crystal panel is touched, the liquid crystal alignment abnormality 16 of the pixel at the touch point will further extend to the inside, so that the uneven brightness area is further expanded, and cannot be restored immediately without touching. . Summary of the invention
  • An embodiment of the present invention provides an array substrate including a gate line, a data line, and a plurality of pixel units defined by a cross therebetween, each of the pixel units including a pixel electrode, wherein the data line or the gate A blocking structure is provided in both side regions of the line.
  • Another embodiment of the present invention provides a method of fabricating an array substrate, including: forming a gate line, an insulating layer, a thin film transistor, a data line, and a passivation layer; on both sides of the data line or the gate line
  • the locale blocks the structure and forms a pixel electrode.
  • a liquid crystal display device including a color filter substrate and an array substrate of a pair of boxes, the array substrate including a gate line, a data line, and a plurality of pixel units defined by a cross therebetween.
  • the pixel unit includes a pixel electrode, and a blocking structure is disposed in a side region of the data line or the gate line.
  • FIG. 1 is a cross-sectional view of a prior art liquid crystal panel using ADS technology
  • FIG. 2 is a partial plan view showing a lower substrate of the liquid crystal panel using the ADS technology of the prior art, that is, an array substrate;
  • Figure 3 is a cross-sectional view of the area A in Figure 2;
  • FIG. 4 is a schematic diagram of a liquid crystal alignment abnormality of a pixel at a touch point when a liquid crystal panel using ADS technology is touched by the prior art
  • FIG. 5 is a partial plan view of an array substrate according to an embodiment of the present invention, in which a blocking structure for preventing abnormal liquid crystal alignment is a convex structure;
  • Figure 6 is a cross-sectional view of the B region of Figure 5;
  • FIG. 7 is a partial plan view of an array substrate according to an embodiment of the present invention, in which a blocking structure for preventing abnormal liquid crystal alignment is a recessed structure;
  • Figure 8 is a cross-sectional view of the area C in Figure 7. detailed description
  • Embodiments of the present invention provide an array substrate capable of preventing an abnormality of liquid crystal alignment from extending to the inside by providing a blocking structure in both sides of a data line or a gate line, thereby preventing brightness from being generated when the liquid crystal panel is touched. The phenomenon of the average.
  • Embodiments of the present invention also provide a method of fabricating the above array substrate and a liquid crystal display device including the above array substrate.
  • the array substrate provided by the embodiment of the present invention may include a plurality of pixel units defined by a gate line, a data line, and a cross therebetween.
  • Each of the pixel units includes a pixel electrode, and a blocking is disposed in a side region of the data line or the gate line. Structure, the blocking structure can prevent abnormal liquid crystal alignment.
  • each of the pixel units may further include a common electrode, the common electrode covers the entire pixel area, the pixel electrode is in a slit shape, and the blocking structure is located between the pixel electrode and the common electrode, and the blocking structure may be A recessed structure, each recessed structure having a length greater than a width of the slit. This will improve the effect of unevenness of the screen or prevent the liquid crystal alignment from extending to the inside.
  • the array substrate may further include a passivation layer or an insulating layer, and the blocking structure may be formed on a portion of the passivation layer or the insulating layer corresponding to the non-display area of the pixel unit.
  • the material of the blocking structure may comprise, for example, silicon nitride, silicon dioxide or a resin material.
  • the blocking structure may be a raised structure or a recessed structure.
  • the passivation layer, the insulating layer, and the flat film are usually formed using, for example, silicon nitride or silicon dioxide, and the color film is usually formed of a resin material
  • the blocking structure is formed of silicon nitride, silicon dioxide, or a resin material. In this case, it is not necessary to separately prepare a material, and a passivation layer, an insulating layer, a flat film, or a color film material which can be directly used can be used, thereby reducing the cost.
  • the blocking structure may be a raised structure.
  • the array substrate may include a gate line 15 , a data line 8 , and a plurality of pixel units defined by a cross therebetween.
  • the pixel unit is provided with a common electrode 11 and a pixel electrode 6 .
  • a protruding structure 17 as a blocking structure is provided in the both side regions of the data line 8, and the long side of the convex structure 17 is not longer than the long side of the pixel electrode 6. This will improve the effect of unevenness of the screen or prevent the liquid crystal alignment from extending to the inside.
  • the thickness of the raised structure 17 is greater than the thickness of the pixel electrode 6, or the raised structure 17 may extend below one end of the pixel electrode 6, from one end of the pixel electrode 6. This will improve the effect of unevenness of the screen or prevent the liquid crystal alignment from extending to the inside. it is good.
  • the blocking structure may be a recessed structure. In this case, as shown
  • the array substrate may include a gate line 15 , a data line 8 , and a plurality of pixel units defined by a cross therebetween.
  • the pixel unit is provided with a common electrode 11 and a pixel electrode 6 on both sides of the data line 8 .
  • a recess structure 18 as a blocking structure is provided, and a recess structure 18 is formed on a portion of the passivation layer 7 corresponding to the non-display area of the pixel unit.
  • the recessed structure 18 is formed on the passivation layer 7, but the recessed structure 18 may be formed on the insulating layer 10 in other embodiments of the present invention.
  • the formation of the blocking structure may be performed by a deposition, photolithography, or etching process; or a printing, printing, or spraying process may be employed.
  • the blocking structure is disposed in both side regions of the data line
  • the blocking structure may be disposed in both side regions of the gate line, at this time blocking If the structure is a raised structure, the long side of the raised structure is shorter than the long side of the gate line.
  • the electric field can be controlled to prevent the liquid crystal alignment abnormality, thereby preventing unevenness of the image.
  • the phenomenon extends inside the pixel.
  • Embodiments of the present invention provide a method of fabricating an array substrate for fabricating the array substrate as shown in FIGS. 5-8.
  • the method of fabricating the array substrate provided by the embodiment of the present invention may include, for example, the following steps:
  • Step 101 forming a gate line, a common electrode, an insulating layer, a thin film transistor, a data line, and a passivation layer on the transparent substrate, wherein the gate line and the data line intersect to define a plurality of pixel units;
  • the above step S101 may employ, for example, a manufacturing process of the array substrate in the prior art, including: deposition, photolithography, etching process, etc., to form a gate line, a common electrode, an insulating layer, and a transparent substrate.
  • a thin film transistor, a data line, and a passivation layer wherein, as shown in FIG. 2, the thin film transistor may include a source/drain 14, an upper portion being a drain, a lower portion being a source, and a source between the source and the drain being a channel.
  • a via 13 is formed on the passivation layer.
  • the structure of the thin film transistor and the manufacturing process thereof are similar to those of the prior art, and are not described herein again.
  • Step 102 setting a blocking structure in the two sides of the data line, and forming a pixel electrode, the pixel electrode is slit-shaped, and the blocking structure is located between the pixel electrode and the common electrode;
  • the non-display of the corresponding pixel unit of the passivation layer or the insulating layer may be A portion of the region forms a blocking structure.
  • a blocking structure may be formed on a portion of the passivation layer or the insulating layer corresponding to the non-display area of the pixel unit by photolithography and etching, but Embodiments of the invention are not limited thereto.
  • a film layer for blocking only the structure may be performed in a portion of the non-display area of the corresponding pixel unit of the passivation layer or the insulating layer after the passivation layer or the insulating layer is formed. Deposition forms a blocking structure.
  • the material of the blocking structure may comprise, for example, silicon nitride, silicon dioxide or a resin material.
  • the blocking structure may be a raised structure or a recessed structure.
  • a non-display area corresponding to the pixel unit passing through the passivation layer, the insulating layer, the color film, or the flat film The portion is formed as a convex structure 17 as a blocking structure.
  • the long side of the convex structure is not longer than the long side of the pixel electrode, the thickness of the convex structure is larger than the thickness of the pixel electrode, or the convex structure may extend below one end of the pixel electrode, and the pixel electrode is padded One end.
  • a recess structure 18 is formed in a portion of the passivation layer 7 corresponding to the non-display area of the display unit.
  • the recess structure 18 may not be formed in the passivation layer 7, but in the insulating layer 10, and embodiments of the present invention are not limited thereto.
  • the recess structure 18 may be one or more; when the pixel electrode includes a hollow slit, the length of each recess structure 18 Greater than the width of the slit. This improves the effect of unevenness of the screen or prevents the liquid crystal alignment from being abnormally extended to the inside.
  • the protrusion structure 17 or the recess structure 18 as a barrier structure may be formed by a deposition, photolithography, or etching process; or a printing, printing, or spraying process may be employed.
  • the blocking structure for preventing the liquid crystal alignment abnormality is formed in both side regions of the data line, but the embodiment of the present invention is not limited thereto, and the blocking structure may be disposed in both side regions of the gate line.
  • the blocking structure may be a convex structure or a concave structure, and the long side of the blocking structure is shorter than the long side of the gate line.
  • the embodiment in which the blocking structures are formed in the side regions of the gate lines is substantially the same as the various embodiments formed in the side regions of the data lines, and will not be described herein.
  • Another embodiment of the present invention further provides another method for fabricating an array substrate, the array substrate
  • Each of the pixel units does not include a common electrode, and therefore the method is substantially the same as the above-described method of fabricating the array substrate, except that the step of forming the common electrode is correspondingly reduced in the step of forming the array substrate.
  • the pixel electrode may not be a slit shape but a whole sheet electrode.
  • a method of fabricating an array substrate provided by another embodiment of the present invention may include, for example, the following steps:
  • Step 201 forming a gate line, an insulating layer, a thin film transistor, a data line, and a passivation layer, wherein the gate line and the data line intersect to define a plurality of pixel units;
  • Step 202 A blocking structure is disposed in both side regions of the data line, and a pixel electrode is formed.
  • the method for fabricating all of the array substrates in the previous embodiment of the present invention is also applicable to the method of manufacturing such an array substrate, and can have an effect of improving the unevenness of the screen or preventing the liquid crystal alignment from being abnormally extended to the inside. I will not repeat them here.
  • the above array substrate and the manufacturing method thereof provided by the embodiments of the present invention are applicable not only to the ADS structure in which the common electrode is located under the pixel electrode, but also to the ADS structure in which the pixel electrode is located on the upper layer of the common electrode and the plane conversion (IPS, In-Plane Switching). ) Structure, also applicable to ordinary ⁇ structures.
  • Embodiments of the present invention also provide a liquid crystal display device including the above array substrate.
  • the liquid crystal display device includes liquid crystals filled between the upper substrate and the lower substrate of the cartridge and the upper and lower substrates, and the lower substrate is the array substrate described above.
  • the liquid crystal display device may include: a liquid crystal panel, a liquid crystal television, a liquid crystal display device, a digital photo frame, an electronic paper, a mobile phone, and the like.
  • the blocking structure in the data line or the two sides of the gate line By providing a blocking structure for preventing abnormality of the liquid crystal alignment in the both sides of the data line or the gate line, when the liquid crystal panel is subjected to pressure of external touch or squeezing, the blocking structure in the data line or the two sides of the gate line, In particular, the portion of the blocking structure that does not overlap with the data line can prevent the liquid crystal alignment from abnormally extending into the display region or the pixel region to prevent the occurrence of uneven brightness. This is because the film layer between the common electrode and the pixel electrode and the data line has a height difference, so that the electric field can be controlled to prevent the liquid crystal alignment from being abnormal, thereby preventing the image unevenness from extending into the inside of the pixel.

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Abstract

一种液晶显示装置、阵列基板及其制造方法。液晶显示装置包括对盒的彩膜基板和阵列基板。阵列基板包括栅线（15）、数据线（8）及二者交叉定义的多个像素单元，每个像素单元还包括像素电极（6），在阵列基板的数据线（8）或栅线（15）的两侧区域设置有阻断结构（17，18）。由于公共电极（11）和像素电极（6）以及数据线（8）之间的膜层存在高度差，可以控制电场，防止液晶配向异常。

Description

液晶显示装置、 阵列基板及其制造方法 技术领域
本发明的实施例涉及一种液晶显示装置、 阵列基板及其制造方法。 背景技术
高级超维场转换技术（ ADSDS, ADvanced Super Dimension Switch ), 即
ADS技术，通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板 状电极层之间产生的电场形成多维电场， 使液晶盒内狭缝电极间以及狭缝电 极正上方所有取向的液晶分子都能够产生旋转， 从而提高了液晶工作效率并 增大了透光率。 ADS技术可以提高薄膜晶体管液晶显示器（TFT-LCD )的画 面品质， 使其具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色 差、 无挤压水波紋（push Mura )等优点。 此外， ADS技术克服了平面方向 转换（IPS, In-Plane-Switching )技术存在的透光率低的问题， 并且可以在宽 视角的前提下实现高透光率。
与 IPS技术相比， ADS技术的不同之处在于， 釆用 ADS技术的液晶面 板（ADS液晶面板）的公共电极和像素电极位于不同层， 分别是狭缝状电极 和板状电极， 并且 ADS液晶面板的公共电极和像素电极都由透明电极形成， 可以实现高透光率。 另外， ADS液晶面板的像素电极之间的距离比 IPS液晶 面板的像素电极之间的距离窄很多， 因此会产生更强的多维电场， 作用于液 晶的实效电压将会增加， 进而使驱动电压降低， 可以大大提高透光率。
如图 1所示， 其为现有技术的釆用 ADS技术的液晶面板的剖面图， 该 液晶面板一般由上下基板对盒形成， 上下基板之间填充有液晶层。 通常， 上 基板、 即彩膜基板可以包括透明基板（例如， 玻璃基板） 19; 在透明基板 19 的内侧形成的阻光膜或黑矩阵（BM, Black Matrix ) 2、 彩膜（color resin ) 3 和平坦膜 ( overcoat ) 4; 以及在透明基板 19的外侧形成的防止静电的导电膜 (例如， 外层 ITO膜） 1。 下基板、 即阵列基板可以包括透明基板（例如， 玻璃基板） 12; 以及在透明基板 12上形成的第一导电膜（例如， 第一 ITO 膜） 11、 绝缘层 10、 非晶硅层 ( a-Si ) 9、 数据线 8、 钝化层 7和第二导电膜 (例如， 第二层 ITO膜） 6。 在上基板与下基板之间填充有液晶 （LC )层 5。 第一导电膜 11为公共电极， 为板状电极， 而第二导电膜 6为像素电极， 该像 素电极包括镂空的狭缝， 为狭缝状电极。 图 2为现有技术的釆用 ADS技术 的液晶面板的下基板、 即阵列基板的部分平面图。 如图 2所示， ADS液晶面 板的阵列基板可以包括例如数据线 8、公共电极 11、像素电极 6、过孔（ contact hole ) 13、 非晶硅薄膜晶体管 9的源 /漏极 14、 栅线 15等。 图 3为图 2中 A 区域的剖面图。 如图 3所示， 公共电极 11的上层为绝缘层 10, 绝缘层 10的 上层为非晶硅薄膜晶体管 9,非晶硅薄膜晶体管 9的上层为数据线 8,数据线 8的上层为钝化层 7, 钝化层的上层为像素电极 6。
但是， 釆用 ADS技术的液晶面板在驱动时， 液晶面板的公共电极位于 像素电极的下部， 导致数据线附近施加至液晶的电场方向不统一。 因此， 在 显示白色画面 （需要充分施加电压） 时， 在像素电极的末端会出现液晶配向 异常 16 (参照图 4 ), 从而导致局部呈黑色、 亮度不均的现象。 如图 4所示， 当液晶面板被触碰时， 触碰点处像素的液晶配向异常 16将进一步向内部延 伸， 使亮度不均面积更为扩展， 即使不触碰的情况下也不能立即还原。 发明内容
本发明的一个实施例提供了一种阵列基板， 其包括栅线、 数据线以及二 者交叉定义的多个像素单元， 每个像素单元包括像素电极， 其中， 在所述数 据线或所述栅线的两侧区域中设置有阻断结构。
本发明的另一个实施例提供了一种阵列基板的制造方法， 其包括： 形成 栅线、 绝缘层、 薄膜晶体管、 数据线和钝化层； 在所述数据线或所述栅线的 两侧区域设置阻断结构， 并形成像素电极。
本发明的另一个实施例提供了一种液晶显示装置， 其包括对盒的彩膜基 板和阵列基板， 所述阵列基板包括栅线、 数据线以及二者交叉定义的多个像 素单元， 每个像素单元包括像素电极， 其中， 在所述数据线或所述栅线的两 侧区域中设置有阻断结构。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术的釆用 ADS技术的液晶面板的剖面图；
图 2为现有技术的釆用 ADS技术的液晶面板的下基板、 即阵列基板的 部分平面图；
图 3为图 2中 A区域的剖面图；
图 4为现有技术的釆用 ADS技术的液晶面板被触碰时触碰点处像素的 液晶配向异常的示意图；
图 5为本发明实施例的阵列基板的部分平面图， 在该阵列基板中防止液 晶配向异常的阻断结构为凸起结构；
图 6为图 5中 B区域的剖面图；
图 7为本发明实施例的阵列基板的部分平面图， 在该阵列基板中防止液 晶配向异常的阻断结构为凹陷结构； 以及
图 8为图 7中 C区域的剖面图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" "第二" 以及类似的词语并不表示任何顺序、 数 量或者重要性， 而只是用来区分不同的组成部分。 同样， "一个"或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "包括" 或者 "包 含" 等类似的词语意指出现在 "包括" 或者 "包含" 前面的元件或者物件涵 盖出现在 "包括" 或者 "包含" 后面列举的元件或者物件及其等同， 并不排 除其他元件或者物件。 "连接" 或者 "相连" 等类似的词语并非限定于物理 的或者机械的连接， 而是可以包括电性的连接， 不管是直接的还是间接的。 本发明的实施例提供了一种阵列基板， 其通过在数据线或栅线的两侧区 域中设置有阻断结构而能够阻止液晶配向异常向内部延伸， 防止液晶面板被 触碰时产生亮度不均的现象。 本发明的实施例还提供了上述阵列基板的制造 方法以及包括上述阵列基板的液晶显示装置。
本发明的实施例提供的阵列基板可以包括栅线、 数据线及二者交叉定义 的多个像素单元， 每个像素单元包括像素电极， 在数据线或栅线的两侧区域 中设置有阻断结构， 该阻断结构可以防止液晶配向异常。
在本发明的实施例中， 每个像素单元还可以包括公共电极， 该公共电极 覆盖整个像素区， 像素电极为狭缝状， 阻断结构位于像素电极与公共电极之 间， 阻断结构可以为凹陷结构， 每个凹陷结构的长度大于狭缝的宽度。 这样 改善画面不均现象的效果或者防止液晶配向异常向内部延伸的效果会更好。
在本发明的实施例中， 阵列基板还可以包括钝化层或绝缘层， 阻断结构 可以形成在钝化层或绝缘层的对应于像素单元的非显示区的部分上。
在本发明的实施例中， 阻断结构的材料可以包括例如氮化硅、 二氧化硅 或树脂材料。
在本发明的实施例中， 阻断结构可以为凸起结构或凹陷结构。
因为钝化层、 绝缘层和平坦膜通常釆用例如氮化硅或二氧化硅形成， 而 彩膜通常釆用树脂材料形成， 所以阻断结构釆用氮化硅、 二氧化硅或树脂材 料形成时， 无需另外准备材料， 可以直接利用的钝化层、 绝缘层、 平坦膜或 彩膜的材料即可， 从而能够降低成本。
下面， 参照图 5至图 8说明本发明的实施例提供的阵列基板。
在本发明的实施例中， 阻断结构可以为凸起结构。 在这种情况下， 如图 5和图 6所示， 阵列基板可以包括栅线 15、 数据线 8及二者交叉定义的多个 像素单元， 像素单元内设置有公共电极 11和像素电极 6, 在数据线 8的两侧 区域中设置有作为阻断结构的突起结构 17 , 凸起结构 17的长边不长于像素 电极 6的长边。 这样改善画面不均现象的效果或者防止液晶配向异常向内部 延伸的效果会更好。
在本发明的实施例中， 凸起结构 17的厚度大于像素电极 6的厚度，或者 凸起结构 17可以延伸到像素电极 6的一端的下方， 藝起像素电极 6的一端。 这样改善画面不均现象的效果或者防止液晶配向异常向内部延伸的效果会更 好。
在本发明的实施例中， 阻断结构可以为凹陷结构。 在这种情况下， 如图
7和图 8所示， 阵列基板可以包括栅线 15、 数据线 8及二者交叉定义的多个 像素单元， 像素单元内设置有公共电极 11和像素电极 6, 在数据线 8的两侧 区域中设置有作为阻断结构的凹陷结构 18, 凹陷结构 18形成在钝化层 7的 对应于像素单元的非显示区的部分上。在本实施例中， 凹陷结构 18形成在钝 化层 7上， 但是在本发明的其它实施例中凹陷结构 18还可以形成在绝缘层 10上。
在本发明的实施例中， 阻断结构的形成可以釆用沉积、光刻、蚀刻工艺； 也可以釆用打印、 印刷、 喷涂工艺。
虽然在本发明的上述实施例中阻断结构设置在数据线的两侧区域中， 但 是在本发明的其它实施例中阻断结构还可以设置在栅线的两侧区域中， 此时 阻断结构如果为凸起结构， 则该凸起结构的长边短于栅线的长边。
在本发明的实施例提供的阵列基板中， 因为公共电极、 像素电极以及数 据线（或栅线）之间的膜层存在高度差， 所以可以控制电场， 防止液晶配向 异常， 从而防止画面不均现象延伸到像素内部。
本发明的实施例提供了一种阵列基板的制造方法， 用于制造如图 5至图 8 所示的阵列基板。 本发明的实施例提供的阵列基板的制造方法可以包括例 如以下几个步骤：
步骤 101 : 在透明基板上形成栅线、 公共电极、 绝缘层、 薄膜晶体管、 数据线和钝化层， 其中， 栅线和数据线交叉而定义出多个像素单元；
在本实施例中， 上述步骤 S101 可以釆用例如现有技术中的阵列基板的 制造工艺， 包括： 沉积、 光刻、 蚀刻工艺等， 以在透明基板上形成栅线、 公 共电极、 绝缘层、 薄膜晶体管、 数据线和钝化层， 其中， 如图 2所示， 薄膜 晶体管可以包括源 /漏极 14, 上部分是漏极， 下部分是源极， 源极和漏极之 间是沟道区， 钝化层上形成有过孔 13。 在本发明的实施例中， 薄膜晶体管的 结构及其制造工艺与现有技术类似， 这里不再赘述。
步骤 102: 在数据线的两侧区域中设置阻断结构， 并形成像素电极， 该 像素电极为狭缝状， 阻断结构位于像素电极和公共电极之间；
在本发明的实施例中， 可以在钝化层或绝缘层的对应像素单元的非显示 区的部分形成阻断结构。 在本发明的一些实施例中， 可以在形成钝化层或绝 缘层之后， 通过光刻和刻蚀， 在钝化层或绝缘层上对应像素单元的非显示区 的部分形成阻断结构， 但是本发明的实施例不限于此。 例如， 在本发明的一 些实施例中， 可以在形成钝化层或绝缘层之后， 再在钝化层或绝缘层的对应 像素单元的非显示区的部分进行只用于阻断结构的膜层沉积而形成阻断结 构。
在本发明的实施例中， 阻断结构的材料可以包括例如氮化硅、 二氧化硅 或树脂材料。
在本发明的实施例中， 阻断结构可以为凸起结构或凹陷结构。
在本发明的实施例中， 例如， 如图 5和图 6所示， 在数据线的两侧区域 中， 通过钝化层、 绝缘层、 彩膜或平坦膜的对应于像素单元的非显示区的部 分形成作为阻断结构的凸起结构 17。 在这种情况下， 凸起结构的长边不长于 像素电极的长边， 凸起结构的厚度大于像素电极的厚度， 或者凸起结构可以 延伸到像素电极的一端的下方， 垫起像素电极的一端。
在本发明的实施例中， 例如， 如图 7和图 8所示， 在数据线的两侧区域 中， 在钝化层 7的对应于显示单元的非显示区的部分形成凹陷结构 18。 在本 发明的一些实施例中， 凹陷结构 18也可以不形成在钝化层 7中，而是形成在 绝缘层 10中， 本发明的实施例不限于此。
在本发明的实施例中， 如图 7 所示， 在一个像素单元里， 凹陷结构 18 可以是一个， 也可以是多个； 当像素电极包括镂空的狭缝时， 每个凹陷结构 18的长度大于狭缝的宽度。这样改善画面不均现象的效果或者防止液晶配向 异常向内部延伸的效果会更好。
在本发明的实施例中， 作为阻挡结构的突起结构 17或凹陷结构 18的形 成可以釆用沉积、 光刻、 蚀刻工艺； 也可以釆用打印、 印刷、 喷涂工艺。
在本发明的上述实施例中， 防止液晶配向异常的阻断结构形成在数据线 的两侧区域中， 但是本发明的实施例不限于此， 阻挡结构还可以设置在栅线 的两侧区域中， 该阻断结构可以为凸起结构或凹陷结构， 该阻断结构的长边 短于栅线的长边。 阻挡结构形成在栅线的两侧区域中的实施例与形成在数据 线的两侧区域中的各种实施例大体相同， 在此不再赘述。
本发明的另一实施例还提供了另一种阵列基板的制造方法， 该阵列基板 的每个像素单元不包括公共电极， 因此该方法与上述阵列基板的制造方法基 本上相同，只是在形成阵列基板的步骤中相应地减少了形成公共电极的步骤。 此外， 在本发明的一些实施例中， 像素电极也可以不是狭缝状， 而是整片电 极。
本发明的另一实施例提供的阵列基板的制造方法可以包括例如以下几个 步骤：
步骤 201 : 形成栅线、 绝缘层、 薄膜晶体管、 数据线和钝化层， 其中， 栅线和数据线交叉而定义出多个像素单元；
步骤 202: 在数据线的两侧区域中设置阻断结构， 并形成像素电极。 本发明的前一个实施例中所有的阵列基板的制造方法在这种阵列基板的 制造方法上也同样适用， 并且能起到改善画面不均现象的效果或者防止液晶 配向异常向内部延伸的效果， 在此不再赘述。
本发明的实施例提供的上述阵列基板及其制造方法不仅适用于公共电极 位于像素电极下面的 ADS 结构， 同时也适用于像素电极位于公共电极上层 的 ADS结构以及平面转换 ( IPS, In-Plane Switching )结构， 对普通的 ΤΝ结 构也适用。
本发明的实施例还提供了包括上述阵列基板的液晶显示装置。 在本发明 的实施例中， 该液晶显示装置包括对盒的上基板和下基板以及上下基板间填 充的液晶， 该下基板为上述的阵列基板。
在本发明的实施例中， 液晶显示装置可以包括： 液晶面板、 液晶电视、 液晶显示器件、 数码相框、 电子纸、 手机等等终端产品。
通过在数据线或栅线的两侧区域中设置防止液晶配向异常的阻断结构， 当液晶面板受到外界触摸或挤压的压力时， 数据线或者栅线的两侧区域中的 阻断结构， 尤其是阻断结构中与数据线不重叠的部分能够阻止液晶配向异常 延伸到显示区域或像素区域中， 以防止产生亮度不均的现象。 这是因为公共 电极和像素电极以及数据线之间的膜层存在高度差， 所以可以控制电场， 防 止液晶配向异常， 从而防止画面不均现象延伸到像素内部。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、一种阵列基板，包括栅线、数据线以及二者交叉定义的多个像素单元， 每个像素单元包括像素电极， 其中， 在所述数据线或所述栅线的两侧区域中 设置有阻断结构。
2、根据权利要求 1所述的阵列基板， 其中， 每个像素单元还包括公共电 极， 所述公共电极覆盖整个像素区， 所述像素电极为狭缝状， 所述阻断结构 位于所述像素电极与所述公共电极之间。
3、根据权利要求 1所述的阵列基板， 其中， 所述阻断结构的材料包括氮 化硅、 二氧化硅或树脂材料。
4、根据权利要求 1所述的阵列基板，还包括钝化层或绝缘层， 所述阻断 结构形成在所述钝化层或所述绝缘层的对应于所述像素单元的非显示区的部 分。
5、根据权利要求 1所述的阵列基板，其中，所述阻断结构包括凸起结构。
6、根据权利要求 5所述的阵列基板， 其中， 所述阻断结构的长边不长于 所述像素电极的长边。
7、根据权利要求 5所述的阵列基板， 其中， 所述阻断结构延伸到所述像 素电极的一端的下方。
8、根据权利要求 5所述的阵列基板， 其中， 所述凸起结构的厚度大于所 述像素电极的厚度。
9、 根据权利要求 1所述的阵列基板， 其中， 所述阻断结构为凹陷结构。
10、 根据权利要求 9所述的阵列基板， 其中， 所述凹陷结构的长度大于 所述狭缝的宽度。
11、 一种阵列基板的制造方法， 包括：
形成栅线、 绝缘层、 薄膜晶体管、 数据线和钝化层；
在所述数据线或所述栅线的两侧区域中形成阻断结构 ,并形成像素电极。
12、根据权利要求 11所述的阵列基板的制造方法，还包括： 形成公共电 极， 所述公共电极覆盖整个像素区， 所述像素电极为狭缝状， 所述阻断结构 位于所述像素电极与所述公共电极之间。
13、根据权利要求 11所述的阵列基板的制造方法， 其中， 所述阻断结构 的形成包括：
形成钝化层或绝缘层后， 通过光刻和刻蚀在所述钝化层或绝缘层的对应 于所述像素单元的非显示区的部分形成所述阻断结构。
14、根据权利要求 11所述的阵列基板的制造方法， 其中， 所述阻断结构 的形成包括：
形成钝化层或绝缘层后， 再在所述钝化层或绝缘层的对应于所述像素单 元的非显示区的部分上进行只用于所述阻断结构的膜层沉积而形成所述阻断 结构。
15、根据权利要求 11所述的阵列基板的制造方法， 其中， 所述阻断结构 包括凸起结构或凹陷结构。
16、 一种液晶显示装置， 包括对盒的彩膜基板和阵列基板， 所述阵列基 板包括栅线、 数据线以及二者交叉定义的多个像素单元， 每个像素单元包括 像素电极， 其中， 在所述数据线或所述栅线的两侧区域中设置有阻断结构。
17、根据权利要求 16所述的液晶显示装置， 其中， 每个像素单元还包括 公共电极， 所述公共电极覆盖整个像素区， 所述像素电极为狭缝状， 所述阻 断结构位于所述像素电极与所述公共电极之间。
18、根据权利要求 16所述的液晶显示装置，还包括钝化层或绝缘层， 所 述阻断结构形成在所述钝化层或所述绝缘层的对应于所述像素单元的非显示 区的部分。
19、根据权利要求 16所述的液晶显示装置， 其中， 所述阻断结构包括凸 起结构或凹陷结构。
PCT/CN2012/083330 2011-12-22 2012-10-22 液晶显示装置、阵列基板及其制造方法 WO2013091437A1 (zh)

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