WO2019232906A1 - Goa电路的自举电容、goa电路及显示面板 - Google Patents

Goa电路的自举电容、goa电路及显示面板 Download PDF

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WO2019232906A1
WO2019232906A1 PCT/CN2018/098113 CN2018098113W WO2019232906A1 WO 2019232906 A1 WO2019232906 A1 WO 2019232906A1 CN 2018098113 W CN2018098113 W CN 2018098113W WO 2019232906 A1 WO2019232906 A1 WO 2019232906A1
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Prior art keywords
electrode plate
capacitor
branch
goa circuit
projection
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PCT/CN2018/098113
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English (en)
French (fr)
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奚苏萍
王添鸿
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/097,635 priority Critical patent/US20200365106A1/en
Publication of WO2019232906A1 publication Critical patent/WO2019232906A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • the present invention relates to the field of display technology, and in particular, to a bootstrap capacitor of a GOA circuit, a GOA circuit, and a display panel.
  • the liquid crystal display panel has become a display panel for mobile communication devices, PCs, TVs, etc. due to its advantages of high display quality, low price, and convenient portability.
  • the driving technology of liquid crystal display panels gradually adopts the GOA circuit.
  • the GOA circuit can simplify the manufacturing process of the flat panel display panel, eliminating the bonding process in the horizontal scanning line direction, which can increase productivity, reduce product costs, and improve the display panel.
  • the integration level makes it more suitable for making narrow border or borderless display products, and meets the visual pursuit of modern people.
  • the GOA circuit uses the existing liquid crystal display panel Array manufacturing process to fabricate the gate drive circuit on the substrate, and realizes the driving method of progressive scanning of the scanning lines.
  • the GOA circuit includes a plurality of thin film transistors, and the plurality of thin film transistors form a pull-up control circuit, a pull-up circuit, a pull-down sustain circuit, a pull-down circuit, a cascade circuit, and the like, and generally, for the function and stability of the GOA circuit, Design a bootstrap capacitor (C Boost), and the capacitance of the bootstrap capacitor needs a certain size to work stably.
  • the calculation formula for the capacitance C is as follows:
  • ⁇ is the dielectric constant of the medium between the electrode plates
  • S is the area facing the two electrode plates
  • d is the distance between the two electrode plates
  • k is the electrostatic force constant
  • the bootstrap capacitor needs to occupy a larger width W0 on the substrate of the display panel, which is not conducive to the realization of the narrow bezel of the display panel with the GOA circuit.
  • the technical problem to be solved by the embodiments of the present invention is to provide a bootstrap capacitor of a GOA circuit, a GOA circuit, and a display panel. Can reduce the width occupied by the bootstrap capacitor.
  • an embodiment of the first aspect of the present invention provides a bootstrap capacitor of a GOA circuit, including:
  • a second branch capacitor is located above the first branch capacitor, the second branch capacitor is connected in parallel with the first branch capacitor, and a projection of the second branch capacitor and the first branch capacitor on a horizontal plane is at least Partially overlap to reduce the width of the bootstrap capacitor.
  • the projection of the second branch capacitor on the horizontal plane is less than or equal to the projection of the first branch capacitor on the horizontal plane, and the projection of the second branch capacitor on the horizontal plane completely falls into the first branch.
  • the capacitance is within the range of the projection of the horizontal plane.
  • the first branch capacitor includes a first electrode plate and a second electrode plate
  • the second branch capacitor includes the second electrode plate and a third electrode plate. A projection of an electrode plate on the second electrode plate and a projection of the third electrode plate on the second electrode plate at least partially overlap.
  • the lengths and widths of the first electrode plate, the second electrode plate, and the third electrode plate are all the same, and the three electrodes are arranged exactly opposite to each other.
  • the distance between the first electrode plate and the second electrode plate is d1
  • the length of the overlapping area of the first electrode plate and the second electrode plate is L1
  • the first The dielectric coefficient of a branch capacitor is ⁇ 1
  • the distance between the third electrode plate and the second electrode plate is d2
  • the length of the overlapping area between the third electrode plate and the second electrode plate is L2
  • the second The dielectric coefficient of the branch capacitor is ⁇ 2
  • the bootstrap capacitor further includes a connection electrode, and the connection electrode is electrically connected to the first electrode plate and the third electrode plate respectively to realize the first branch capacitor and the second branch. Capacitors are connected in parallel.
  • a portion where the projection of the third electrode plate on the second electrode plate overlaps with the projection of the first electrode plate on the second electrode plate is connected to the connection electrode, and the second electrode Via holes are provided on the electrode plate, and the connection electrodes are electrically connected to the first electrode plate and the third electrode plate through the via holes, respectively.
  • a gate insulating layer is provided between the first electrode plate and the second electrode plate, and a second electrode plate is provided between the second electrode plate and the third electrode plate. Insulation.
  • An embodiment of the second aspect of the present invention provides a GOA circuit including the bootstrap capacitor of the GOA circuit described above.
  • An embodiment of the third aspect of the present invention provides a display panel including the GOA circuit described above.
  • the bootstrap capacitor includes: a first branch capacitor; and a second branch capacitor, which is located above the first branch capacitor, the second branch capacitor is connected in parallel with the first branch capacitor, and the second branch capacitor and The projection of the first branch capacitor on the horizontal plane at least partially overlaps to reduce the width of the bootstrap capacitor.
  • the width of the bootstrap capacitor can be reduced, which is beneficial to the realization of the narrow bezel of the display panel with the GOA circuit.
  • FIG. 1 (a) is a sectional view of a bootstrap capacitor of a GOA circuit in the prior art
  • FIG. 1 (b) is a top view of a bootstrap capacitor of a GOA circuit in the prior art
  • FIG. 2 (a) is a cross-sectional view of a bootstrap capacitor of a GOA circuit provided by the first embodiment of the present invention
  • FIG. 2 (b) is a top view of a bootstrap capacitor of a GOA circuit provided by the first embodiment of the present invention
  • 3 (a) is a sectional view of a bootstrap capacitor of a GOA circuit provided by a second embodiment of the present invention
  • 3 (b) is a top view of a bootstrap capacitor of a GOA circuit provided by a second embodiment of the present invention.
  • An embodiment of the present invention provides a bootstrap capacitor for a GOA circuit. See FIG. 2 (a) and FIG. 2 (b).
  • the bootstrap capacitor includes a first branch capacitor C1 and a second branch capacitor C2.
  • the branch capacitor C1 is in the same position on the display panel as the prior art bootstrap capacitor.
  • the second branch capacitor C2 is located above the first branch capacitor C1.
  • the second branch capacitor C2 is located
  • the first branch capacitor C1 is directly above, but the present invention is not limited thereto. In other embodiments of the present invention, the second branch capacitor may also be located diagonally above the first branch capacitor.
  • the parallel connection of the two branch capacitors C2 can reach the capacitance required by the bootstrap capacitor in the GOA circuit, and each of the capacitance of the first branch capacitor C1 and the capacitance of the second branch capacitor C2 is larger than that required by the bootstrap capacitor in the GOA circuit.
  • the electric capacity is small.
  • the projection of the second branch capacitor C2 and the first branch capacitor C1 on a horizontal plane at least partially overlaps to reduce the total width of the bootstrap capacitor.
  • the projection of the second branch capacitor C2 on the horizontal plane is smaller than or equal to the projection of the first branch capacitor C1 on the horizontal plane, and the projection of the second branch capacitor C2 on the horizontal plane completely falls into the first branch capacitor C1 on the horizontal plane.
  • the projection of the second branch capacitor C2 on the horizontal plane and the projection of the first branch capacitor C1 on the horizontal plane completely overlap.
  • the second branch capacitor C2 shares the capacitance of a part of the bootstrap capacitor, so that the first branch capacitor C1
  • the capacitance is smaller than the capacitance of the bootstrap capacitor in the GOA circuit in the prior art, so that the width of the display panel occupied by the first branch capacitor C1 can be reduced, because the projection of the second branch capacitor C2 on the horizontal plane completely falls into the first branch
  • the capacitor C1 is within the range of the projection of the horizontal plane, so that the width of the display panel occupied by the bootstrap capacitor can also be reduced, which is beneficial to the realization of the narrow bezel of the liquid crystal display panel with the GOA circuit.
  • the first branch capacitor C1 includes a first electrode plate 210 and a second electrode plate 220
  • the second branch capacitor C2 includes the second electrode plate 220 and a third electrode plate 230, that is,
  • the first branch capacitor C1 and the second branch capacitor C2 share a second electrode plate 220, and the projection of the first electrode plate 210 on the second electrode plate 220 and the third electrode plate 230 on the first
  • the projections on the two electrode plates 220 are at least partially overlapped to reduce the width of the bootstrap capacitor.
  • the lengths and widths of the first electrode plate 210, the second electrode plate 220, and the third electrode plate 230 are the same, and The two electrode plates are completely opposite to each other, that is, the projections of the three electrode plates on the horizontal plane completely overlap, so that the width of the display panel occupied by the bootstrap capacitor can be greatly reduced.
  • the position of the first branch capacitor C1 is the same as the position of the bootstrap capacitor in the prior art, ⁇ 1 is the same as ⁇ 0, and d1 is the same as d0. Because the first electrode plate 210, the second The length and width of the electrode plate 220 and the third electrode plate 230 are equal, so L1 and L2 are the same, and W1 and W2 are the same. In addition, generally speaking, the same as the prior art bootstrap capacitor design, in order to minimize the bootstrap capacitor The width of the bootstrap capacitor is designed to be as long as possible, so L1 and L2 are generally designed to be the same as L0. Substituting these parameters into the above formula for calculation can be obtained:
  • the bootstrap capacitor further includes a connection electrode 231, and the material of the connection electrode 231 is the same as that of the connection electrode 231.
  • the third electrode plate 230 is made of the same material, and the connection electrode 231 is electrically connected to the first electrode plate 210 and the third electrode plate 230 to realize the first branch capacitor C1 and the second branch capacitor C2 in parallel.
  • the second electrode plate 220 is provided with via holes 221, and the connection electrodes 231 pass through the via holes 221, respectively.
  • the via hole 221 is larger than the size of the connection electrode 231, and a gap exists between the hole wall of the via hole 221 and the connection electrode 231 to prevent the second electrode plate 220. It is electrically connected or short-circuited with the connection electrode 231.
  • a gate insulating layer is provided between the first electrode plate 210 and the second electrode plate 220, and a material of the gate insulating layer is, for example, a silicon nitride material.
  • a second insulating layer is provided between the two electrode plates 220 and the third electrode plate 230.
  • the material of the second insulating layer is, for example, a silicon nitride material, an organic insulating layer, or an inorganic insulating layer.
  • the material of the first electrode plate 210 may be a single metal material or a metal alloy.
  • the material of the first electrode plate 210 may be Al, Mo, Mo, and an Al alloy.
  • the material of the second electrode plate 220 may be a single metal material or a metal alloy, such as Mo / Al / Mo material, the material of the third electrode plate 230 is ITO, and the material of the connection electrode 231 is also ITO. .
  • An embodiment of the present invention further provides a GOA circuit.
  • the GOA circuit includes a plurality of interconnected units, each of which includes the bootstrap capacitor described above.
  • each of the units of the GOA circuit further includes a pull-up control. Circuit, pull-up circuit, pull-down sustain circuit, pull-down circuit, cascade circuit, etc.
  • An embodiment of the present invention further provides a display panel including the above-mentioned GOA circuit.
  • the display panel includes a substrate, a first metal layer, a second metal layer, and a third metal layer in order from bottom to top.
  • the first metal layer forms the first electrode plate 210 and the gate
  • the second metal layer forms the second electrode plate 220, the source and the drain
  • the third metal layer forms the first Three electrode plates 230 and pixel electrodes.
  • the display panel is a thin film transistor liquid crystal display panel.
  • the thin film transistor in the thin film transistor liquid crystal display panel may be an a-Si type thin film transistor, or an IGZO type thin film transistor.
  • FIG. 3 (a) is a schematic diagram of a bootstrap capacitor of a GOA circuit according to a second embodiment of the present invention.
  • the structure of FIG. 3 (a) is the same as that of FIG. 2 (a). Therefore, the same component symbols represent the same components.
  • the main difference between this example and the first embodiment is the structure of the first branch capacitor and the second branch capacitor.
  • the bootstrap capacitor includes a first branch capacitor C11 and a second branch capacitor C21, and the second branch capacitor C21 is located above the first branch capacitor C11.
  • the second branch capacitor C21 is located diagonally above the first branch capacitor C11, specifically diagonally above the left.
  • the second branch capacitor C11 may also be located on the first branch capacitor C11. Diagonal right of the branch capacitor, etc.
  • the second branch capacitor C21 and the first branch capacitor C11 are connected in parallel, and the projections of the second branch capacitor C21 and the first branch capacitor C11 on the horizontal plane at least partially overlap to reduce The width of the bootstrap capacitor.
  • the first branch capacitor C11 includes a first electrode plate 310 and a second electrode plate 320
  • the second branch capacitor C21 includes the second electrode plate 320 and a third electrode plate 330.
  • the width of the second electrode plate 320 is greater than the width of the first electrode plate 310 and the width of the third electrode plate 330.
  • the left end of the second electrode plate 320 and the third electrode The end of the left end of the plate 330 is flush, and the end of the right end of the second electrode plate 320 is flush with the end of the right end of the first electrode plate 310.
  • the projection of the first electrode plate 310 on the second electrode plate 320 and the projection of the third electrode plate 330 on the second electrode plate 320 at least partially overlap.
  • the distance between the first electrode plate 310 and the second electrode plate 320 is d1, and the area where the first electrode plate 310 and the second electrode plate 320 overlap
  • the length is L1
  • the dielectric coefficient of the first branch capacitor C11 is ⁇ 1
  • the distance between the third electrode plate 330 and the second electrode plate 320 is d2
  • the third electrode plate 330 and the second electrode is L2
  • the dielectric coefficient of the second branch capacitor C21 is ⁇ 2
  • the lifting capacitor occupies the width of the display panel.
  • the capacitance of the second branch capacitor C21 is larger than the reduced capacitance of the first branch capacitor C11. Therefore, the width of the second branch electrode can be set to be smaller than ⁇ W, and the width of the bootstrap capacitor will be smaller than W11 + ⁇ W. Therefore, the width occupied by the bootstrap capacitor can be reduced, and the width of the frame can be reduced.
  • the length of the bootstrap capacitor is generally designed. As long as possible, that is, the length of the bootstrap capacitor is generally designed to the maximum length, so that the length of the first branch capacitor C11 and the second branch capacitor C21 are generally designed to be the same. Therefore, the above formula can be further transformed into:
  • the projection of the third electrode plate 330 on the second electrode plate 320 and the first electrode plate 310 on the second electrode plate The overlapping part of the projection on 320 is connected to the connection electrode 331, where the connection electrode 331 is disposed on the right side of the third electrode plate 330, and both ends of the connection electrode 331 are respectively connected to the third electrode plate 330 and the first The electrode plate 310 is electrically connected.
  • the second electrode plate 320 is provided with a via hole 321, and the connection electrode 331 is electrically connected to the first electrode plate 310 from the third electrode plate 330 through the via hole 321, so A gap exists between the connection electrode 331 and a hole wall of the via hole 321.

Abstract

一种GOA电路的自举电容、GOA电路及显示面板，包括：第一分支电容（C1）；第二分支电容（C2），其位于第一分支电容上方。第二分支电容与第一分支电容并联连接，且第二分支电容与第一分支电容在水平面的投影至少部分重叠以减少自举电容的宽度，由此获得减少自举电容所占用的宽度的优点。

Description

GOA电路的自举电容、GOA电路及显示面板
本申请要求2018年6月6日提交中国专利局的，申请号为2018105721762，发明名称为“GOA电路的自举电容、GOA电路及显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，特别是涉及一种GOA电路的自举电容、GOA电路及显示面板。
背景技术
液晶显示面板以其显示品质高、价格低廉、携带方便等优点，成为移动通讯设备、PC、TV等的显示面板。目前液晶显示面板驱动技术逐渐趋向于采用GOA电路，GOA电路能简化平板显示面板的制作工序，省去水平扫描线方向的接合(bonding)工艺，可提升产能、降低产品成本，同时可以提升显示面板的集成度使之更适合制作窄边框或无边框显示产品，满足现代人们的视觉追求。
GOA电路，即Gate Driver on Array技术，也就是利用现有液晶显示面板Array制程将栅极驱动电路制作在衬底基板上，实现对扫描线逐行扫描的驱动方式。所述GOA电路包括多个薄膜晶体管，多个所述薄膜晶体管形成上拉控制电路、上拉电路、下拉维持电路、下拉电路、级传电路等，而且，为了GOA电路的功能及稳定性一般会设计自举电容(C Boost)，且自举电容的电容量需要有一定的大小才能稳定发挥作用，电容量C的计算公式如下：
Figure PCTCN2018098113-appb-000001
其中，ε为电极板间介质的介电常数，S为两电极板的正对面积，d为两电极板间的距离，k则是静电力常量。
请参见图1(a)和图1(b)，将图1(a)、图1(b)中的参数代入，得到现有技术的自举电容的电容量为：
Figure PCTCN2018098113-appb-000002
从上面式子可以看出，自举电容在显示面板的衬底基板上需要占用较大的宽度W0，这样不利于带GOA电路的显示面板窄边框的实现。
发明内容
本发明实施例所要解决的技术问题在于，提供一种GOA电路的自举电容、GOA电路及显示面板。可减少自举电容所占用的宽度。
为了解决上述技术问题，本发明第一方面实施例提供了一种GOA电路的自举电容，包括：
第一分支电容；
第二分支电容，其位于所述第一分支电容上方，所述第二分支电容与所述第一分支电容并联连接，且所述第二分支电容与所述第一分支电容在水平面的投影至少部分重叠以减少自举电容的宽度。
在本发明第一方面一实施例中，第二分支电容在水平面的投影小于或等于第一分支电容在水平面的投影，且所述第二分支电容在水平面的投影完全落入所述第一分支电容在水平面的投影的范围内。
在本发明第一方面一实施例中，所述第一分支电容包括第一电极板和第二电极板，所述第二分支电容包括所述第二电极板和第三电极板，所述第一电极板在所述第二电极板上的投影与所述第三电极板在所述第二电极板上的投影至少部分重叠。
在本发明第一方面一实施例中，所述第一电极板、所述第二电极板、所述第三电极板的长度、宽度均相等，三个电极完全正对设置。
在本发明第一方面一实施例中，所述第一电极板与第二电极板正对的距离为d1，所述第一电极板与第二电极板重叠区域的长度为L1，所述第一分支电容的介电系数为ε1，所述第三电极板与第二电极板正对的距离为d2，所述第三电极板与第二电极板重叠区域的长度为L2，所述第二分支电容的介电系数为ε2，则：
Figure PCTCN2018098113-appb-000003
在本发明第一方面一实施例中，所述自举电容还包括连接电极，所述连接电极分别与所述第一电极板、第三电极板电连接以实现第一分支电容和第二分支电容并联。
在本发明第一方面一实施例中，所述第三电极板在第二电极板上的投影与第一电极板在第二电极板上投影重叠的部分连接所述连接电极，所述第二电极板上设有过孔，所述连接电极穿过所述过孔分别与所述第一电极板、第三电极板电连接。
在本发明第一方面一实施例中，所述第一电极板和第二电极板之间设有栅极绝缘层，所述第二电极板与所述第三电极板之间设有第二绝缘层。
本发明第二方面实施例提供了一种GOA电路，包括上述的GOA电路的自举电容。
本发明第三方面实施例提供了一种显示面板，包括上述的GOA电路。
实施本发明实施例，具有如下有益效果：
由于自举电容包括：第一分支电容；第二分支电容，其位于所述第一分支电容上方，所述第二分支电容与所述第一分支电容并联连接，且所述第二分支电容与所述第一分支电容在水平面的投影至少部分重叠以减少自举电容的宽度。通过如此设置，可以减少自举电容的宽度，有利于带GOA电路的显示面板窄边框的实现。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1(a)是现有技术一种GOA电路的自举电容的剖视图；
图1(b)是现有技术一种GOA电路的自举电容的俯视图；
图2(a)是本发明第一实施例提供的一种GOA电路的自举电容的剖视图；
图2(b)是本发明第一实施例提供的一种GOA电路的自举电容的俯视图；
图3(a)是本发明第二实施例提供的一种GOA电路的自举电容的剖视图；
图3(b)是本发明第二实施例提供的一种GOA电路的自举电容的俯视图；
图示标号：
210、310-第一电极板；220、320-第二电极板；221、321-过孔；230、330-第三电极板；231、331-连接电极；C1、C11-第一分支电容；C2、C21-第二分支电容。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请说明书、权利要求书和附图中出现的术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。此外，术语“第一”、“第二”和“第三”等是用于区别不同的对象，而并非用于描述特定的顺序。
第一实施例
本发明实施例提供一种GOA电路的自举电容，请参见图2(a)和图2(b)，所述自举电容包括第一分支电容C1和第二分支电容C2，所述第一分支电容C1与现有技术的自举电容在显示面板上处于相同的位置，所述第二分支电容C2位于所述第一分支电容C1的上方，在这里，所述第二分支电容C2是位于所述第一分支电容C1的正上方，但本发明不限于此，在本发明的其他实施例中，所述第二分支电容还可以位于所述第一分支电容的斜上方。
在本实施例中，所述第二分支电容C2与所述第一分支电容C1并联连接，由于两电容并联连接后计算公式为：C 总＝C1+C2，也即，第一分支电容C1和第二分支电容C2并联后的总电容量为第一分支电容C1的电容量与第二分支电容C2的电容量的总和，从而即使减小自举电容的宽度，通过第一分支电容C1和第二分支电容C2的并联可以达到GOA电路中自举电容需要的电容量,而且第一分支电容C1的电容量和第二分支电容C2的电容量中的每一个均比GOA电路中自举电容需要的电容量小。
在本实施例中，所述第二分支电容C2与所述第一分支电容C1在水平面的投影至少部分重叠以减少自举电容的总宽度。在本实施例中，第二分支电容C2在水平面的投影小于或等于第一分支电容C1在水平面的投影，且第二分支电容C2在水平面的投影完全落入所述第一分支电容C1在水平面的投影的范围内，在此处，第二分支电容C2在水平面的投影与第一分支电容C1在水平面的投影完全重叠。在本实施例中，由于第一分支电容C1与现有技术中的自举电容所处的位置相同，从而通过第二分支电容C2分担部分自举电容的电容量，从而第一分支电容C1的电容量要小于现有技术中GOA电路中自举电容的电容量，从而可以减少第一分支电容C1占用显示面板的宽度，由于第二分支电容C2在水平面的投影完全落入所述第一分支电容C1在水平面的投影的范围内，从而自举电容占用显示面板的宽度也可以减小，从而有利于带GOA电路的液晶显示面板窄边框的实现。
在本实施例中，所述第一分支电容C1包括第一电极板210和第二电极板220，所述第二分支电容C2包括所述第二电极板220和第三电极板230，也即第一分支电容C1和所述第二分支电容C2共用第二电极板220，所述第一电极板210在所述第二电极板220上的投影与所述第三电极板230在所述第二电极板220上的投影至少部分重叠以减少自举电容的宽度，在此处，所述第一电极板210、第二电极板220、第三电极板230的长度、宽度均相同，且三个电极板完全正对设置，也即三个电极板在水平面的投影完全重叠，从而可以极大的减少自举电容占用的显示面板的宽度。
以下参照图2(a)、图2(b)来具体说明本实施例的技术方案是如何减小自举电容的宽 度的，为了达到跟现有技术同样的电容量，也即：
C 总＝C 现；
而C 总＝C1+C2；
将图2(a)、图2(b)中参数代入，得到：
Figure PCTCN2018098113-appb-000004
代入现有技术电容量的计算式和本实施例C1和C2的计算式，得到：
Figure PCTCN2018098113-appb-000005
由于第一分支电容C1所处的位置与现有技术的自举电容所处的位置一样，从而ε1与ε0相同，d1与d0相同；由于第一分支电容C1中第一电极板210、第二电极板220、第三电极板230的长度和宽度均相等，因此L1与L2相同，W1与W2相同，而且，一般说来，跟现有技术的自举电容设计一样，为了尽量减少自举电容的宽度，自举电容的长度设计的会尽可能长，从而L1、L2一般会设计与L0相同,将这些参数代入上面式子进行计算，可得：
Figure PCTCN2018098113-appb-000006
在上式中，由于
Figure PCTCN2018098113-appb-000007
必然大于0，从而
Figure PCTCN2018098113-appb-000008
的值必然大于1，也即W0必然大于W1，而W0是现有技术自举电容所需要占用的宽度，W1是本实施例自举电容所需要占用的宽度，从而相对现有技术可以减少自举电容占用显示面板的宽度，从而有利于带GOA电路的显示面板窄边框的实现。而且，在本实施例中，由于第一电极板210、第二电极板220、第三电极板230的长度、宽度均相等，从而可以尽可能的减少自举电容占用的宽度，可以尽量减少显示面板边框的宽度。
为了实现第一分支电容C1和第二分支电容C2并联，在本实施例中，请参见图2(a)，所述自举电容还包括连接电极231，所述连接电极231的材料与所述第三电极板230的材料相同，所述连接电极231分别与所述第一电极板210、第三电极板230电连接以实现第一分支电容C1和第二分支电容C2并联。为了减掉连接电极231向外绕而增加自举电容的宽度，在本实施例中，所述第二电极板220上设有过孔221，所述连接电极231穿过所述过孔221分别与所述第一电极板210、第三电极板230电连接。在本实施例中，所述过孔221要大于所述连接电极231的大小，且所述过孔221的孔壁与所述连接电极231之间存在间隙，以防止所述第二电极板220与所述连接电极231电连接或者短路。
另外，在本实施例中，所述第一电极板210和所述第二电极板220之间设有栅极绝缘层，所述栅极绝缘层的材料例如为氮化硅材料，所述第二电极板220与所述第三电极板230之间设有第二绝缘层，所述第二绝缘层的材料例如为氮化硅材料、有机绝缘层或者无机绝缘层等。
在本实施例中，所述第一电极板210的材料可以是单金属材料也可以是金属合金，例如所述第一电极板210的材料可以是Al、Mo、Mo和Al合金等，所述第二电极板220的材料可以是单金属材料也可以是金属合金，例如为Mo/Al/Mo材料等，所述第三电极板230的材料为ITO，所述连接电极231的材料也为ITO。
本发明实施例还提供一种GOA电路，所述GOA电路包括很多级互联的单元，每一级单元均包括上述的自举电容，另外，所述GOA电路的每一级单元还包括上拉控制电路、上拉电路、下拉维持电路、下拉电路、级传电路等。
本发明实施例还提供一种显示面板，所述显示面板包括上述的GOA电路，所述显示面板从下到上依次包括衬底、第一金属层、第二金属层和第三金属层，其中，所述第一金属层形成所述第一电极板210、栅极，所述第二金属层形成所述第二电极板220、源极和漏极，所述第三金属层形成所述第三电极板230、像素电极。在本实施例中，所述显示面板为薄膜晶体管液晶显示面板，所述薄膜晶体管液晶显示面板中的薄膜晶体管可以为a-Si型的薄膜晶体管，也可以是IGZO类型的薄膜晶体管等。
第二实施例
图3(a)是本发明第二实施例一种GOA电路的自举电容的示意图，图3(a)的结构与图2(a)相同，因此相同的元件符号代表相同的部件，本实施例与第一实施例的主要不同点为所述第一分支电容与所述第二分支电容的结构。
请参见图3(a)和图3(b)，所述自举电容包括第一分支电容C11和第二分支电容C21，所述第二分支电容C21位于所述第一分支电容C11上方，在此处所述第二分支电容C21位于所述第一分支电容C11斜上方，具体为左斜上方，当然，在本发明的其他实施例中，所述第二分支电容还可以位于所述第一分支电容的右斜上方等。在本实施例中，所述第二分支电容C21与所述第一分支电容C11并联连接，且所述第二分支电容C21与所述第一分支电容C11在水平面上的投影至少部分重叠以减少自举电容的宽度。
在本实施例中，所述第一分支电容C11包括第一电极板310和第二电极板320，所述第二分支电容C21包括所述第二电极板320和第三电极板330，所述第二电极板320的宽度既大于第一电极板310的宽度，也大于第三电极板330的宽度，在本实施例中，所述第二电极板320左端的端部与所述第三电极板330左端的端部平齐，所述第二电极板320右端的端部与所述第一电极板310右端的端部平齐。在本实施例中，所述第一电极板310在所述第二电极板320上的投影与所述第三电极板330在所述第二电极板320上投影至少部分重叠。
为了实现减少自举电容的宽度，在本实施例中，所述第一电极板310与第二电极板320 正对的距离为d1，所述第一电极板310与第二电极板320重叠区域的长度为L1，所述第一分支电容C11的介电系数为ε1，所述第三电极板330与第二电极板320正对的距离为d2，所述第三电极板330与第二电极板320重叠区域的长度为L2，所述第二分支电容C21的介电系数为ε2，则：
Figure PCTCN2018098113-appb-000009
由于满足上面公式，且所述第一电极板310在所述第二电极板320上的投影与所述第三电极板330在所述第二电极板320上投影至少部分重叠，可以实现减少自举电容占用显示面板的宽度。
以下参照图3(a)、图3(b)来具体说明本实施例的技术方案是如何减小自举电容的宽度的，假设第一分支电容C11相对现有技术的自举电容减少了△W的宽度，为了弥补第一分支电容C11减少的电容量，假定第二分支电容C21的宽度为△W，则第二分支电容C21为了弥补第一分支电容C11减少的的电容量而增加的电容量为：
Figure PCTCN2018098113-appb-000010
由于
Figure PCTCN2018098113-appb-000011
则：
Figure PCTCN2018098113-appb-000012
再由于所述第一电极板310在所述第二电极板320上的投影与所述第三电极板330在所述第二电极板320上投影至少部分重叠，从而：
Figure PCTCN2018098113-appb-000013
从而，第二分支电容C21的电容量的大于第一分支电容C11减小的电容量，从而，第二分支电极的宽度可以设置为小于△W，从而自举电容的宽度会小于W11+△W，从而可以减少自举电容占用的宽度，可以减少边框的宽度。
一般说来，显示面板上的自举电容的数量是很多个，为了尽可能减少自举电容占用的显示面板的宽度，也为了制程上的便利性，所述自举电容的长度一般会设计的尽量长，也即自举电容的长度一般会设计到最大长度，从而第一分支电容C11和第二分支电容C21的长度一般会设计为相同，从而，上面的式子可以进一步变形为：
Figure PCTCN2018098113-appb-000014
另外，在本实施例中，为了实现第一分支电容C11和第二分支电容C21并联，所述第三电极板330在第二电极板320上的投影与第一电极板310在第二电极板320上投影重叠的部 分连接连接电极331，在此处所述连接电极331设置在所述第三电极板330的右侧，所述连接电极331的两端分别与第三电极板330和第一电极板310电连接。在本实施例中，所述第二电极板320上设有过孔321，所述连接电极331从第三电极板330穿过所述过孔321与所述第一电极板310电连接，所述连接电极331与所述过孔321的孔壁之间存在间隙。
需要说明的是，本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。对于装置实施例而言，由于其与方法实施例基本相似，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
以上所揭露的仅为本发明较佳实施例而已，当然不能以此来限定本发明之权利范围，因此依本发明权利要求所作的等同变化，仍属本发明所涵盖的范围。

Claims (19)

  1. 一种GOA电路的自举电容，其中，包括：
    第一分支电容；
    第二分支电容，其位于所述第一分支电容上方，所述第二分支电容与所述第一分支电容并联连接，且所述第二分支电容与所述第一分支电容在水平面的投影至少部分重叠以减少自举电容的宽度。
  2. 如权利要求1所述的GOA电路的自举电容，其中，第二分支电容在水平面的投影小于或等于第一分支电容在水平面的投影，且所述第二分支电容在水平面的投影完全落入所述第一分支电容在水平面的投影的范围内。
  3. 如权利要求1所述的GOA电路的自举电容，其中，所述第一分支电容包括第一电极板和第二电极板，所述第二分支电容包括所述第二电极板和第三电极板，所述第一电极板在所述第二电极板上的投影与所述第三电极板在所述第二电极板上的投影至少部分重叠。
  4. 如权利要求3所述的GOA电路的自举电容，其中，所述第一电极板、所述第二电极板、所述第三电极板的长度、宽度均相等，三个电极完全正对设置。
  5. 如权利要求3所述的GOA电路的自举电容，其中，所述第一电极板与第二电极板正对的距离为d1，所述第一电极板与第二电极板重叠区域的长度为L1，所述第一分支电容的介电系数为ε1，所述第三电极板与第二电极板正对的距离为d2，所述第三电极板与第二电极板重叠区域的长度为L2，所述第二分支电容的介电系数为ε2，则：
    Figure PCTCN2018098113-appb-100001
  6. 如权利要求3所述的GOA电路的自举电容，其中，所述自举电容还包括连接电极，所述连接电极分别与所述第一电极板、第三电极板电连接以实现第一分支电容和第二分支电容并联。
  7. 如权利要求4所述的GOA电路的自举电容，其中，所述自举电容还包括连接电极，所述连接电极分别与所述第一电极板、第三电极板电连接以实现第一分支电容和第二分支电容并联。
  8. 如权利要求5所述的GOA电路的自举电容，其中，所述自举电容还包括连接电极，所述连接电极分别与所述第一电极板、第三电极板电连接以实现第一分支电容和第二分支电容并联。
  9. 如权利要求6所述的GOA电路的自举电容，其中，所述第三电极板在第二电极板上的 投影与第一电极板在第二电极板上投影重叠的部分连接所述连接电极，所述第二电极板上设有过孔，所述连接电极穿过所述过孔分别与所述第一电极板、第三电极板电连接。
  10. 如权利要求3所述的GOA电路的自举电容，其中，所述第一电极板和第二电极板之间设有栅极绝缘层，所述第二电极板与所述第三电极板之间设有第二绝缘层。
  11. 一种GOA电路，其中，包括自举电容，所述自举电容包括：
    第一分支电容；
    第二分支电容，其位于所述第一分支电容上方，所述第二分支电容与所述第一分支电容并联连接，且所述第二分支电容与所述第一分支电容在水平面的投影至少部分重叠以减少自举电容的宽度。
  12. 如权利要求11所述的GOA电路，其中，第二分支电容在水平面的投影小于或等于第一分支电容在水平面的投影，且所述第二分支电容在水平面的投影完全落入所述第一分支电容在水平面的投影的范围内。
  13. 如权利要求11所述的GOA电路，其中，所述第一分支电容包括第一电极板和第二电极板，所述第二分支电容包括所述第二电极板和第三电极板，所述第一电极板在所述第二电极板上的投影与所述第三电极板在所述第二电极板上的投影至少部分重叠。
  14. 如权利要求13所述的GOA电路，其中，所述第一电极板、所述第二电极板、所述第三电极板的长度、宽度均相等，三个电极完全正对设置。
  15. 如权利要求13所述的GOA电路，其中，所述第一电极板与第二电极板正对的距离为d1，所述第一电极板与第二电极板重叠区域的长度为L1，所述第一分支电容的介电系数为ε1，所述第三电极板与第二电极板正对的距离为d2，所述第三电极板与第二电极板重叠区域的长度为L2，所述第二分支电容的介电系数为ε2，则：
    Figure PCTCN2018098113-appb-100002
  16. 如权利要求13所述的GOA电路，其中，所述自举电容还包括连接电极，所述连接电极分别与所述第一电极板、第三电极板电连接以实现第一分支电容和第二分支电容并联。
  17. 如权利要求16所述的GOA电路，其中，所述第三电极板在第二电极板上的投影与第一电极板在第二电极板上投影重叠的部分连接所述连接电极，所述第二电极板上设有过孔，所述连接电极穿过所述过孔分别与所述第一电极板、第三电极板电连接。
  18. 如权利要求13所述的GOA电路，其中，所述第一电极板和第二电极板之间设有栅极绝缘层，所述第二电极板与所述第三电极板之间设有第二绝缘层。
  19. 一种显示面板，其中，包括如权利要求11所述的GOA电路。
PCT/CN2018/098113 2018-06-06 2018-08-01 Goa电路的自举电容、goa电路及显示面板 WO2019232906A1 (zh)

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