US11056035B1 - Gate on array circuit with capacitors connected in parallel - Google Patents

Gate on array circuit with capacitors connected in parallel Download PDF

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Publication number
US11056035B1
US11056035B1 US16/768,675 US202016768675A US11056035B1 US 11056035 B1 US11056035 B1 US 11056035B1 US 202016768675 A US202016768675 A US 202016768675A US 11056035 B1 US11056035 B1 US 11056035B1
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metal layer
thin film
film transistor
pull
circuit unit
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US16/768,675
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Leilei Deng
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present disclosure relates to display technologies, and more particularly, to a gate on array (GOA) circuit.
  • GAA gate on array
  • the capacitor is usually formed as a whole of a first metal layer (M1), a second metal layer (M2), and an insulating layer interposed between the first metal layer (M1) and the second metal layer (M2).
  • the present invention provides a GOA circuit to solve the problem that capacitors fail due to fine particles and film breakage during film formation.
  • the present disclosure provides a gate on array (GOA) circuit to provide a bootstrap capacitor divided into a plurality of first capacitors connected in parallel. After a function of the first capacitor is lost due to small foreign objects or the insulating layer damaged, a connecting line of at least one of the first capacitors being unable to store is cut off. An overall bootstrap capacitance function will not fail to avoid a loss of GOA circuit function due to a failure of the overall capacitor resulted from small foreign objects.
  • GOA gate on array
  • one embodiment of the disclosure provides a GOA circuit, including a plurality of cascading GOA units.
  • An n th GOA unit includes: a pull-up control circuit unit, a pull-up circuit unit, a pass-down circuit unit, a pull-down circuit unit 104 , a pull-down maintaining circuit unit, and a bootstrap capacitor. All the pull-up control circuit unit, the pull-up circuit unit, the pass-down circuit unit, the pull-down circuit unit 104 , the pull-down maintaining circuit unit, and the bootstrap capacitor are connected to a first node.
  • the pull-up control circuit unit 101 is configured to receive an (n ⁇ 1) th pass-down signal and an (n ⁇ 1) th scan driving signal to pre-charge the first node.
  • the pull-up circuit unit is configured to receive a clock signal to pull-up an electrical level of an n th scan driving signal.
  • the pass-down circuit unit is configured to output an n th pass-down signal to control a pull-up control circuit unit of a (n+1) th GOA unit to turn on or off.
  • the pull-down circuit unit is configured to receive an (n+1) th scan driving signal to pull-down the pre-charge electrical level of the first node Q(n) and an electrical level of the n th scan driving signal to a low power source.
  • the pull-down maintaining circuit unit is configured to maintain the pre-charge electrical level of the first node Q(n) and the electrical level of the n th scan driving signal G(n) at the low power source and to keep unchanged.
  • the bootstrap capacitor is configured to provide and to maintain the pre-charge electrical level of the first node, and the bootstrap capacitor includes a plurality of first capacitors connected in parallel, wherein a connecting line of at least one of the first capacitors being unable to store is cut off.
  • the bootstrap capacitor 106 includes: a first metal layer, an insulating layer disposed on the first metal layer, and a second metal layer disposed on the insulating layer.
  • patterns of the first metal layer and the second metal layer both are gridlike. Nodes of the grid of the first metal layer correspond to nodes of the grid of the second metal layer.
  • the first metal layer, the insulating layer, and the second metal layer form the first capacitor at the nodes.
  • patterns of the first metal layer and the second metal layer are both striplike.
  • a strip of the first metal layer is perpendicular to a strip of the second metal layer.
  • the first metal layer, the insulating layer, and the second metal layer form the first capacitor at a cross region at which a projection of the second metal layer projected on the first metal layer crosses the first metal layer.
  • a pattern of the first metal layer is striplike.
  • a pattern of the second metal layer includes a plurality of squares. The first metal layer, the insulating layer, and the second metal layer form the first capacitor at a cross region at which a projection of the second metal layer projected on the first metal layer crosses the striplike pattern.
  • a pattern of the first metal layer includes a plurality of squares.
  • a pattern of the second metal layer is striplike. The first metal layer, the insulating layer, and the second metal layer form the first capacitor at a cross region at which a projection of the striplike pattern projected on the first metal layer crosses the first metal layer.
  • the pull-up control circuit unit includes a first thin film transistor.
  • a gate of the first thin film transistor is configured to receive the (n ⁇ 1) th pass-down signal.
  • a source of the first thin film transistor connects with the first node Q(n).
  • a drain of the first thin film transistor is configured to receive the (n ⁇ 1) th scan driving signal.
  • the pull-up circuit unit includes a second thin film transistor.
  • a gate of the second thin film transistor connects with the first node.
  • a drain of the second thin film transistor is configured to receive the clock signal.
  • a source of the second thin film transistor is configured to receive the n th scan driving signal.
  • the pass-down circuit unit includes a third thin film transistor.
  • a gate of the third thin film transistor connects with the first node.
  • a source of the third thin film transistor is configured to output the n th pass-down signal ST(n).
  • a drain of the third thin film transistor is configured to receive the clock signal.
  • the pull-down circuit unit includes a fourth thin film transistor and a fifth thin film transistor.
  • a gate of the fourth thin film transistor is configured to receive the (n+1) th scan driving.
  • a source of the fourth thin film transistor is configured to receive the low power source.
  • a drain of the fourth thin film transistor is configured to receive the n th scan driving signal.
  • a gate of the fifth thin film transistor is configured to receive the (n+1) th scan driving signal.
  • a source of the fifth thin film transistor connects with the first node.
  • a drain of the fifth thin film transistor is configured to receive the low power source.
  • the pull-down maintaining circuit unit includes an inverter, a sixth thin film transistor, and a seventh thin film transistor.
  • One end of the inverter connects with the first node.
  • Another end of the inverter connects with a gate of the sixth thin film transistor and a gate of the seventh thin film transistor respectively.
  • a source of the sixth thin film transistor is configured to receive the low power source.
  • a drain of the sixth thin film transistor is configured to receive the n th scan driving signal.
  • a source of the seventh thin film transistor is configured to receive the low power source.
  • a drain of the seventh thin film transistor connects with the first node.
  • the gate on array (GOA) circuit provides the bootstrap capacitor divided into a plurality of the first capacitors connected in parallel. After a function of the first capacitor is lost due to small foreign objects or the insulating layer damaged, the connecting line of at least one of the first capacitors being unable to store is cut off. An overall bootstrap capacitance function will not fail to avoid a loss of GOA circuit function due to a failure of the overall capacitor resulted from small foreign objects.
  • FIG. 1 is a schematic view of a GOA circuit according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic view of a structure of a pattern of a bootstrap capacitor according to a first embodiment of the present disclosure.
  • FIG. 3 is a schematic cross-sectional view of a node of a grid according to FIG. 2 .
  • FIG. 4 is a schematic view of a structure of a pattern of a bootstrap capacitor according to a second embodiment of the present disclosure.
  • FIG. 5 is a schematic view of a structure of a pattern of a bootstrap capacitor according to a third embodiment of the present disclosure.
  • FIG. 6 is a schematic view of a structure of a pattern of a bootstrap capacitor according to the third embodiment of the present disclosure.
  • FIG. 7 is a schematic view of a structure of a pattern of a bootstrap capacitor according to a fourth embodiment of the present disclosure.
  • FIG. 8 is a schematic view of a structure of a pattern of a bootstrap capacitor according to the fourth embodiment of the present disclosure.
  • an n th GOA unit includes: a pull-up control circuit unit 101 , a pull-up circuit unit 102 , a pass-down circuit unit 103 , a pull-down circuit unit 104 , a pull-down maintaining circuit unit 105 , and a bootstrap capacitor 106 .
  • All the pull-up control circuit unit 101 , the pull-up circuit unit 102 , the pass-down circuit unit 103 , the pull-down circuit unit 104 , the pull-down maintaining circuit unit 105 , and the bootstrap capacitor 106 are connected to a first node Q(n).
  • the pull-up control circuit unit 101 is configured to receive an (n ⁇ 1) th pass-down signal ST(n ⁇ 1) and an (n ⁇ 1) th scan driving signal G(n ⁇ 1) to pre-charge the first node Q(n).
  • the pull-up control circuit unit 101 includes a first thin film transistor T 1 .
  • a gate of the first thin film transistor T 1 is configured to receive the (n ⁇ 1) th pass-down signal ST(n ⁇ 1).
  • a source of the first thin film transistor T 1 connects with the first node Q(n).
  • a drain of the first thin film transistor T 1 is configured to receive the (n ⁇ 1) th scan driving signal G(n ⁇ 1).
  • the pull-up circuit unit 102 is configured to receive a clock signal CK to pull-up an electrical level of an n th scan driving signal G(n).
  • the pull-up circuit unit 102 includes a second thin film transistor T 2 .
  • a gate of the second thin film transistor T 2 connects with the first node Q(n).
  • a drain of the second thin film transistor T 2 is configured to receive the clock signal CK.
  • a source of the second thin film transistor T 2 is configured to receive the n th scan driving signal G(n).
  • the pass-down circuit unit 103 is configured to output an n th pass-down signal ST(n) to control a pull-up control circuit unit of a (n+1) th GOA unit to turn on or off.
  • the pass-down circuit unit 103 includes a third thin film transistor T 3 .
  • a gate of the third thin film transistor T 3 connects with the first node Q(n).
  • a source of the third thin film transistor T 3 is configured to output the n th pass-down signal ST(n).
  • a drain of the third thin film transistor T 3 is configured to receive the clock signal CK.
  • the pull-down circuit unit 104 is configured to receive an (n+1) th scan driving signal G(n+1) to pull-down the pre-charge electrical level of the first node Q(n) and an electrical level of the n th scan driving signal G(n) to a low power source VSS.
  • the pull-down circuit unit 104 includes a fourth thin film transistor T 4 and a fifth thin film transistor T 5 .
  • a gate of the fourth thin film transistor T 4 is configured to receive the (n+1) th scan driving G(n+1).
  • a source of the fourth thin film transistor T 4 is configured to receive the low power source VSS.
  • a drain of the fourth thin film transistor T 4 is configured to receive the n th scan driving signal G(n).
  • a gate of the fifth thin film transistor T 5 is configured to receive the (n+1) th scan driving signal G(n+1).
  • a source of the fifth thin film transistor T 5 connects with the first node Q(n).
  • a drain of the fifth thin film transistor T 5 is configured to receive the low power source VSS.
  • the pull-down maintaining circuit unit 105 is configured to maintain the pre-charge electrical level of the first node Q(n) and the electrical level of the n th scan driving signal G(n) at the low power source VSS and to keep unchanged.
  • the pull-down maintaining circuit unit 105 includes an inverter, a sixth thin film transistor T 6 , and a seventh thin film transistor.
  • One end of the inverter connects with the first node Q(n). Another end of the inverter connects with a gate of the sixth thin film transistor T 6 and a gate of the seventh thin film transistor T 7 respectively.
  • a source of the sixth thin film transistor T 6 is configured to receive the low power source VSS.
  • a drain of the sixth thin film transistor T 6 is configured to receive the n th scan driving signal G(n).
  • a source of the seventh thin film transistor T 7 is configured to receive the low power source VSS.
  • a drain of the seventh thin film transistor T 7 connects with the first node Q(n).
  • the bootstrap capacitor 106 is configured to provide and to maintain the pre-charge electrical level of the first node Q(n), and the bootstrap capacitor 106 includes a plurality of first capacitors C connected in parallel, wherein a connecting line of at least one of the first capacitors C being unable to store is cut off.
  • the bootstrap capacitor 106 includes: a first metal layer, an insulating layer, and a second metal layer.
  • the insulating layer disposed on the first metal layer.
  • the second metal layer disposed on the insulating layer.
  • the disclosure provides four types of patterns of the bootstrap capacitor from a first embodiment to a fourth embodiment.
  • patterns of the first metal layer 201 and the second metal layer 202 both are gridlike. Nodes of the grid of the first metal layer 201 correspond to nodes of the grid of the second metal layer 202 .
  • the first metal layer 201 , the insulating layer 203 , and the second metal layer 202 form the first capacitor at the nodes 200 .
  • All fractions of the first metal layer 201 correspond to nodes of the grid.
  • a upper metal fraction, a lower metal fraction, and the insulating layer between them are formed the first capacitor C.
  • patterns of the first metal layer 201 and the second metal layer 202 are both striplike.
  • a strip of the first metal layer 201 is perpendicular to a strip of the second metal layer 202 .
  • the first metal layer 201 , the insulating layer, and the second metal layer 202 form the first capacitor at a cross region at which a projection of the second metal layer 202 projected on the first metal layer 201 crosses the first metal layer 201 .
  • one of the first capacitors C is failure, one can cut the strip of the first metal layer or the strip of the second metal layer at the cross region corresponding to the failure capacitor.
  • a pattern of the first metal layer 201 is striplike (shown as a dash line in FIG. 5 ).
  • a pattern of the second metal layer 202 includes a plurality of squares. The first metal layer 201 , the insulating layer, and the second metal layer 202 form the first capacitor at a cross region at which a projection of the second metal layer 202 projected on the first metal layer 201 crosses every one of the striplike patterns.
  • the second metal layer and the first metal layer need a staggered setting to preserve a cutting region of the strip.
  • the first metal layer includes a main trunk corresponding to an interval.
  • the main trunk is perpendicular to every strip of the first metal layer.
  • a pattern of the first metal layer 201 includes a plurality of squares.
  • a pattern of the second metal layer 202 is striplike.
  • the first metal layer 201 , the insulating layer, and the second metal layer 202 form the first capacitor at a cross region at which a projection of the striplike pattern projected on the first metal layer 201 crosses the first metal layer 201 .
  • the second metal layer 202 and the first metal layer 201 need a staggered setting to preserve a cutting region of the strip.
  • the second metal layer includes a main trunk corresponding to an interval.
  • the main trunk is perpendicular to every strip of the second metal layer.
  • the gate on array (GOA) circuit provides the bootstrap capacitor divided into a plurality of the first capacitors connected in parallel. After a function of the first capacitor is lost due to small foreign objects or the insulating layer damaged, the connecting line of at least one of the first capacitors being unable to store is cut off. An overall bootstrap capacitance function will not fail to avoid a loss of GOA circuit function due to a failure of the overall capacitor resulted from small foreign objects.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)

Abstract

A gate on array (GOA) circuit with capacitors connected in parallel includes a plurality of cascading GOA units. An nth GOA unit includes: a pull-up control circuit unit, a pull-up circuit unit, a pass-down circuit unit, a pull-down circuit unit, a pull-down maintaining circuit unit, and a bootstrap capacitor. The bootstrap capacitor is divided into a plurality of first capacitors connected in parallel. After a function of the first capacitor is lost due to small foreign objects or the insulating layer damaged, a connecting line of at least one of the first capacitors being unable to store is cut off.

Description

FIELD
The present disclosure relates to display technologies, and more particularly, to a gate on array (GOA) circuit.
BACKGROUND
In existing display panel technologies, Application of the gate on array (GOA) circuit is widespread and deep. In order to improve clock signal transmission efficiency, a designed capacitor is pre-charged and pulled up so as to quickly pull up the nth level signal potential. The capacitor is usually formed as a whole of a first metal layer (M1), a second metal layer (M2), and an insulating layer interposed between the first metal layer (M1) and the second metal layer (M2).
With development of a panel industry, cost is reduced to improve product competitiveness, and the insulating layer tends to be thinner. In addition, in an actual production process, fine particles and film breakage will be generated during the film formation process, which will cause the capacitor to fail and affect a GOA function to lead to product scrap.
Therefore, the present invention provides a GOA circuit to solve the problem that capacitors fail due to fine particles and film breakage during film formation.
SUMMARY
In view of the above, the present disclosure provides a gate on array (GOA) circuit to provide a bootstrap capacitor divided into a plurality of first capacitors connected in parallel. After a function of the first capacitor is lost due to small foreign objects or the insulating layer damaged, a connecting line of at least one of the first capacitors being unable to store is cut off. An overall bootstrap capacitance function will not fail to avoid a loss of GOA circuit function due to a failure of the overall capacitor resulted from small foreign objects.
In order to achieve above-mentioned object of the present disclosure, one embodiment of the disclosure provides a GOA circuit, including a plurality of cascading GOA units. An nth GOA unit includes: a pull-up control circuit unit, a pull-up circuit unit, a pass-down circuit unit, a pull-down circuit unit 104, a pull-down maintaining circuit unit, and a bootstrap capacitor. All the pull-up control circuit unit, the pull-up circuit unit, the pass-down circuit unit, the pull-down circuit unit 104, the pull-down maintaining circuit unit, and the bootstrap capacitor are connected to a first node. The pull-up control circuit unit 101 is configured to receive an (n−1)th pass-down signal and an (n−1)th scan driving signal to pre-charge the first node. The pull-up circuit unit is configured to receive a clock signal to pull-up an electrical level of an nth scan driving signal. The pass-down circuit unit is configured to output an nth pass-down signal to control a pull-up control circuit unit of a (n+1)th GOA unit to turn on or off. The pull-down circuit unit is configured to receive an (n+1)th scan driving signal to pull-down the pre-charge electrical level of the first node Q(n) and an electrical level of the nth scan driving signal to a low power source. The pull-down maintaining circuit unit is configured to maintain the pre-charge electrical level of the first node Q(n) and the electrical level of the nth scan driving signal G(n) at the low power source and to keep unchanged. The bootstrap capacitor is configured to provide and to maintain the pre-charge electrical level of the first node, and the bootstrap capacitor includes a plurality of first capacitors connected in parallel, wherein a connecting line of at least one of the first capacitors being unable to store is cut off.
In one embodiment of the GOA circuit, the bootstrap capacitor 106 includes: a first metal layer, an insulating layer disposed on the first metal layer, and a second metal layer disposed on the insulating layer.
In one embodiment of the GOA circuit, patterns of the first metal layer and the second metal layer both are gridlike. Nodes of the grid of the first metal layer correspond to nodes of the grid of the second metal layer. The first metal layer, the insulating layer, and the second metal layer form the first capacitor at the nodes.
In one embodiment of the GOA circuit, patterns of the first metal layer and the second metal layer are both striplike. A strip of the first metal layer is perpendicular to a strip of the second metal layer. The first metal layer, the insulating layer, and the second metal layer form the first capacitor at a cross region at which a projection of the second metal layer projected on the first metal layer crosses the first metal layer.
In one embodiment of the GOA circuit, a pattern of the first metal layer is striplike. A pattern of the second metal layer includes a plurality of squares. The first metal layer, the insulating layer, and the second metal layer form the first capacitor at a cross region at which a projection of the second metal layer projected on the first metal layer crosses the striplike pattern.
In one embodiment of the GOA circuit, a pattern of the first metal layer includes a plurality of squares. A pattern of the second metal layer is striplike. The first metal layer, the insulating layer, and the second metal layer form the first capacitor at a cross region at which a projection of the striplike pattern projected on the first metal layer crosses the first metal layer.
In one embodiment of the GOA circuit, the pull-up control circuit unit includes a first thin film transistor. A gate of the first thin film transistor is configured to receive the (n−1)th pass-down signal. A source of the first thin film transistor connects with the first node Q(n). A drain of the first thin film transistor is configured to receive the (n−1)th scan driving signal.
In one embodiment of the GOA circuit, the pull-up circuit unit includes a second thin film transistor. A gate of the second thin film transistor connects with the first node. A drain of the second thin film transistor is configured to receive the clock signal. A source of the second thin film transistor is configured to receive the nth scan driving signal.
In one embodiment of the GOA circuit, the pass-down circuit unit includes a third thin film transistor. A gate of the third thin film transistor connects with the first node. A source of the third thin film transistor is configured to output the nth pass-down signal ST(n). A drain of the third thin film transistor is configured to receive the clock signal.
In one embodiment of the GOA circuit, the pull-down circuit unit includes a fourth thin film transistor and a fifth thin film transistor. A gate of the fourth thin film transistor is configured to receive the (n+1)th scan driving. A source of the fourth thin film transistor is configured to receive the low power source. A drain of the fourth thin film transistor is configured to receive the nth scan driving signal. A gate of the fifth thin film transistor is configured to receive the (n+1)th scan driving signal. A source of the fifth thin film transistor connects with the first node. A drain of the fifth thin film transistor is configured to receive the low power source.
In one embodiment of the GOA circuit. The pull-down maintaining circuit unit includes an inverter, a sixth thin film transistor, and a seventh thin film transistor. One end of the inverter connects with the first node. Another end of the inverter connects with a gate of the sixth thin film transistor and a gate of the seventh thin film transistor respectively. A source of the sixth thin film transistor is configured to receive the low power source. A drain of the sixth thin film transistor is configured to receive the nth scan driving signal. A source of the seventh thin film transistor is configured to receive the low power source. A drain of the seventh thin film transistor connects with the first node.
In comparison with prior art, the gate on array (GOA) circuit provides the bootstrap capacitor divided into a plurality of the first capacitors connected in parallel. After a function of the first capacitor is lost due to small foreign objects or the insulating layer damaged, the connecting line of at least one of the first capacitors being unable to store is cut off. An overall bootstrap capacitance function will not fail to avoid a loss of GOA circuit function due to a failure of the overall capacitor resulted from small foreign objects.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a schematic view of a GOA circuit according to an embodiment of the present disclosure.
FIG. 2 is a schematic view of a structure of a pattern of a bootstrap capacitor according to a first embodiment of the present disclosure.
FIG. 3 is a schematic cross-sectional view of a node of a grid according to FIG. 2.
FIG. 4 is a schematic view of a structure of a pattern of a bootstrap capacitor according to a second embodiment of the present disclosure.
FIG. 5 is a schematic view of a structure of a pattern of a bootstrap capacitor according to a third embodiment of the present disclosure.
FIG. 6 is a schematic view of a structure of a pattern of a bootstrap capacitor according to the third embodiment of the present disclosure.
FIG. 7 is a schematic view of a structure of a pattern of a bootstrap capacitor according to a fourth embodiment of the present disclosure.
FIG. 8 is a schematic view of a structure of a pattern of a bootstrap capacitor according to the fourth embodiment of the present disclosure.
 DETAILED DESCRIPTION
The following description of the embodiments is provided by reference to the drawings and illustrates the specific embodiments of the present disclosure. Directional terms mentioned in the present disclosure, such as “up,” “down,” “top,” “bottom,” “forward,” “backward,” “left,” “right,” “inside,” “outside,” “side,” “peripheral,” “central,” “horizontal,” “peripheral,” “vertical,” “longitudinal,” “axial,” “radial,” “uppermost” or “lowermost,” etc., are merely indicated the direction of the drawings. Therefore, the directional terms are used for illustrating and understanding of the application rather than limiting thereof.
Referring to FIG. 1, one embodiment of the disclosure provides a GOA circuit, including a plurality of cascading GOA units. An nth GOA unit includes: a pull-up control circuit unit 101, a pull-up circuit unit 102, a pass-down circuit unit 103, a pull-down circuit unit 104, a pull-down maintaining circuit unit 105, and a bootstrap capacitor 106.
All the pull-up control circuit unit 101, the pull-up circuit unit 102, the pass-down circuit unit 103, the pull-down circuit unit 104, the pull-down maintaining circuit unit 105, and the bootstrap capacitor 106 are connected to a first node Q(n).
The pull-up control circuit unit 101 is configured to receive an (n−1)th pass-down signal ST(n−1) and an (n−1)th scan driving signal G(n−1) to pre-charge the first node Q(n).
The pull-up control circuit unit 101 includes a first thin film transistor T1. A gate of the first thin film transistor T1 is configured to receive the (n−1)th pass-down signal ST(n−1). A source of the first thin film transistor T1 connects with the first node Q(n). A drain of the first thin film transistor T1 is configured to receive the (n−1)th scan driving signal G(n−1).
The pull-up circuit unit 102 is configured to receive a clock signal CK to pull-up an electrical level of an nth scan driving signal G(n).
The pull-up circuit unit 102 includes a second thin film transistor T2. A gate of the second thin film transistor T2 connects with the first node Q(n). A drain of the second thin film transistor T2 is configured to receive the clock signal CK. A source of the second thin film transistor T2 is configured to receive the nth scan driving signal G(n).
The pass-down circuit unit 103 is configured to output an nth pass-down signal ST(n) to control a pull-up control circuit unit of a (n+1)th GOA unit to turn on or off.
The pass-down circuit unit 103 includes a third thin film transistor T3. A gate of the third thin film transistor T3 connects with the first node Q(n). A source of the third thin film transistor T3 is configured to output the nth pass-down signal ST(n). A drain of the third thin film transistor T3 is configured to receive the clock signal CK.
The pull-down circuit unit 104 is configured to receive an (n+1)th scan driving signal G(n+1) to pull-down the pre-charge electrical level of the first node Q(n) and an electrical level of the nth scan driving signal G(n) to a low power source VSS.
The pull-down circuit unit 104 includes a fourth thin film transistor T4 and a fifth thin film transistor T5.
A gate of the fourth thin film transistor T4 is configured to receive the (n+1)th scan driving G(n+1). A source of the fourth thin film transistor T4 is configured to receive the low power source VSS. A drain of the fourth thin film transistor T4 is configured to receive the nth scan driving signal G(n).
A gate of the fifth thin film transistor T5 is configured to receive the (n+1)th scan driving signal G(n+1). A source of the fifth thin film transistor T5 connects with the first node Q(n). A drain of the fifth thin film transistor T5 is configured to receive the low power source VSS.
The pull-down maintaining circuit unit 105 is configured to maintain the pre-charge electrical level of the first node Q(n) and the electrical level of the nth scan driving signal G(n) at the low power source VSS and to keep unchanged.
The pull-down maintaining circuit unit 105 includes an inverter, a sixth thin film transistor T6, and a seventh thin film transistor.
One end of the inverter connects with the first node Q(n). Another end of the inverter connects with a gate of the sixth thin film transistor T6 and a gate of the seventh thin film transistor T7 respectively.
A source of the sixth thin film transistor T6 is configured to receive the low power source VSS. A drain of the sixth thin film transistor T6 is configured to receive the nth scan driving signal G(n).
A source of the seventh thin film transistor T7 is configured to receive the low power source VSS. A drain of the seventh thin film transistor T7 connects with the first node Q(n).
The bootstrap capacitor 106 is configured to provide and to maintain the pre-charge electrical level of the first node Q(n), and the bootstrap capacitor 106 includes a plurality of first capacitors C connected in parallel, wherein a connecting line of at least one of the first capacitors C being unable to store is cut off.
The bootstrap capacitor 106 includes: a first metal layer, an insulating layer, and a second metal layer. The insulating layer disposed on the first metal layer. The second metal layer disposed on the insulating layer.
The disclosure provides four types of patterns of the bootstrap capacitor from a first embodiment to a fourth embodiment.
As shown in FIG. 2 and FIG. 3, in the first embodiment of the GOA circuit, patterns of the first metal layer 201 and the second metal layer 202 both are gridlike. Nodes of the grid of the first metal layer 201 correspond to nodes of the grid of the second metal layer 202. The first metal layer 201, the insulating layer 203, and the second metal layer 202 form the first capacitor at the nodes 200.
All fractions of the first metal layer 201 correspond to nodes of the grid. A upper metal fraction, a lower metal fraction, and the insulating layer between them are formed the first capacitor C.
If one of the first capacitors C is failure, one can cut the connecting line at the node corresponding to the failure capacitor.
As shown in FIG. 4, in the fourth embodiment of the GOA circuit, patterns of the first metal layer 201 and the second metal layer 202 are both striplike. A strip of the first metal layer 201 is perpendicular to a strip of the second metal layer 202.
The first metal layer 201, the insulating layer, and the second metal layer 202 form the first capacitor at a cross region at which a projection of the second metal layer 202 projected on the first metal layer 201 crosses the first metal layer 201.
If one of the first capacitors C is failure, one can cut the strip of the first metal layer or the strip of the second metal layer at the cross region corresponding to the failure capacitor.
In the third embodiment of the GOA circuit, a pattern of the first metal layer 201 is striplike (shown as a dash line in FIG. 5). A pattern of the second metal layer 202 includes a plurality of squares. The first metal layer 201, the insulating layer, and the second metal layer 202 form the first capacitor at a cross region at which a projection of the second metal layer 202 projected on the first metal layer 201 crosses every one of the striplike patterns.
As shown in FIG. 5, when the pattern of the second metal layer 202 is a whole square, the second metal layer and the first metal layer need a staggered setting to preserve a cutting region of the strip.
As shown in FIG. 6, when the pattern of the second metal layer 202 is at least two squares, the squares are staggered setting. The first metal layer includes a main trunk corresponding to an interval. The main trunk is perpendicular to every strip of the first metal layer.
In the fourth embodiment of the GOA circuit, a pattern of the first metal layer 201 includes a plurality of squares. A pattern of the second metal layer 202 is striplike. The first metal layer 201, the insulating layer, and the second metal layer 202 form the first capacitor at a cross region at which a projection of the striplike pattern projected on the first metal layer 201 crosses the first metal layer 201.
As shown in FIG. 7, when the pattern of the first metal layer 201 is a whole square, the second metal layer 202 and the first metal layer 201 need a staggered setting to preserve a cutting region of the strip.
As shown in FIG. 8, when the pattern of the first metal layer 201 is at least two squares, the squares are staggered setting. The second metal layer includes a main trunk corresponding to an interval. The main trunk is perpendicular to every strip of the second metal layer.
In comparison with prior art, the gate on array (GOA) circuit provides the bootstrap capacitor divided into a plurality of the first capacitors connected in parallel. After a function of the first capacitor is lost due to small foreign objects or the insulating layer damaged, the connecting line of at least one of the first capacitors being unable to store is cut off. An overall bootstrap capacitance function will not fail to avoid a loss of GOA circuit function due to a failure of the overall capacitor resulted from small foreign objects.
The present disclosure has been described by the above embodiments, but the embodiments are merely examples for implementing the present disclosure. It must be noted that the embodiments do not limit the scope of the invention. In contrast, modifications and equivalent arrangements are intended to be included within the scope of the invention.

Claims (9)

What is claimed is:
1. A gate on array (GOA) circuit, comprising a plurality of cascading GOA units, wherein an nth GOA unit comprises a pull-up control circuit unit, a pull-up circuit unit, a pass-down circuit unit, a pull-down circuit unit, a pull-down maintaining circuit unit, and a bootstrap capacitor,
wherein: all the pull-up control circuit unit, the pull-up circuit unit, the pass-down circuit unit, the pull-down circuit unit, the pull-down maintaining circuit unit, and the bootstrap capacitor are connected to a first node Q(n);
the pull-up control circuit unit is configured to receive an (n−1)th pass-down signal and an (n−1)th scan driving signal to pre-charge the first node;
the pull-up circuit unit is configured to receive a clock signal to pull-up an electrical level of an nth scan driving signal;
the pass-down circuit unit is configured to output an nth pass-down signal to control a pull-up control circuit unit of a (n+1)th GOA unit to turn on or off;
the pull-down circuit unit is configured to receive an (n+1)th scan driving signal to pull-down the pre-charge electrical level of the first node and an electrical level of the nth scan driving signal to a low power source;
the pull-down maintaining circuit unit is configured to maintain the pre-charge electrical level of the first node and the electrical level of the nth scan driving signal at the low power source and to keep unchanged; and
the bootstrap capacitor is configured to provide and to maintain the pre-charge electrical level of the first node, and the bootstrap capacitor comprises a plurality of first capacitors connected in parallel, wherein a connecting line of at least one of the first capacitors being unable to store is cut off, and
wherein: a pattern of a first metal layer is striplike, a pattern of a second metal layer comprises a plurality of squares, and the first metal layer, an insulating layer, and the second metal layer form the first capacitor at a cross region at which a projection of the second metal layer projected on the first metal layer crosses the striplike pattern; or
the pattern of the first metal layer comprises a plurality of squares, and the pattern of the second metal layer is striplike, and the first metal layer, the insulating layer, and the second metal layer form the first capacitor at a cross region at which a projection of the striplike pattern projected on the first metal layer crosses the first metal layer.
2. The GOA circuit according to claim 1, wherein the bootstrap capacitor comprises:
the first metal layer;
the insulating layer disposed on the first metal layer; and
the second metal layer disposed on the insulating layer.
3. The GOA circuit according to claim 2, wherein patterns of the first metal layer and the second metal layer both are gridlike, nodes of the grid of the first metal layer correspond to nodes of the grid of the second metal layer, and the first metal layer, the insulating layer, and the second metal layer form the first capacitor at the nodes.
4. The GOA circuit according to claim 2, wherein:
patterns of the first metal layer and the second metal layer are both striplike, and a strip of the first metal layer is perpendicular to a strip of the second metal layer; and
the first metal layer, the insulating layer, and the second metal layer form the first capacitor at a cross region at which a projection of the second metal layer projected on the first metal layer crosses the first metal layer.
5. The GOA circuit according to claim 1, wherein
the pull-up control circuit unit comprises a first thin film transistor, a gate of the first thin film transistor is configured to receive the (n−1)th pass-down signal, a source of the first thin film transistor connects with the first node, and a drain of the first thin film transistor is configured to receive the (n−1)th scan driving signal.
6. The GOA circuit according to claim 1, wherein
the pull-up circuit unit comprises a second thin film transistor, a gate of the second thin film transistor connects with the first node, a drain of the second thin film transistor is configured to receive the clock signal, and a source of the second thin film transistor is configured to receive the nth scan driving signal.
7. The GOA circuit according to claim 1, wherein:
the pass-down circuit unit comprises a third thin film transistor, a gate of the third thin film transistor connects with the first node, a source of the third thin film transistor is configured to output the nth pass-down signal, and a drain of the third thin film transistor is configured to receive the clock signal.
8. The GOA circuit according to claim 1, wherein:
the pull-down circuit unit comprises a fourth thin film transistor and a fifth thin film transistor;
a gate of the fourth thin film transistor is configured to receive the (n+1)th scan driving, a source of the fourth thin film transistor is configured to receive the low power source, and a drain of the fourth thin film transistor is configured to receive the nth scan driving signal; and
a gate of the fifth thin film transistor is configured to receive the (n+1)th scan driving signal, a source of the fifth thin film transistor connects with the first node, and a drain of the fifth thin film transistor is configured to receive the low power source.
9. The GOA circuit according to claim 1, wherein:
the pull-down maintaining circuit unit comprises an inverter, a sixth thin film transistor, and a seventh thin film transistor;
one end of the inverter connects with the first node, another end of the inverter connects with a gate of the sixth thin film transistor and a gate of the seventh thin film transistor respectively;
a source of the sixth thin film transistor is configured to receive the low power source, and a drain of the sixth thin film transistor is configured to receive the nth scan driving signal; and
a source of the seventh thin film transistor is configured to receive the low power source, and a drain of the seventh thin film transistor connects with the first node.
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