WO2017206646A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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Publication number
WO2017206646A1
WO2017206646A1 PCT/CN2017/082436 CN2017082436W WO2017206646A1 WO 2017206646 A1 WO2017206646 A1 WO 2017206646A1 CN 2017082436 W CN2017082436 W CN 2017082436W WO 2017206646 A1 WO2017206646 A1 WO 2017206646A1
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WIPO (PCT)
Prior art keywords
pixel electrode
plane
edge
orthographic projection
extension line
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PCT/CN2017/082436
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English (en)
French (fr)
Inventor
先建波
李盼
乔勇
吴新银
徐健
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/741,919 priority Critical patent/US10705389B2/en
Publication of WO2017206646A1 publication Critical patent/WO2017206646A1/zh
Priority to US16/882,948 priority patent/US11249351B2/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
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    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
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    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a display device.
  • liquid crystal display devices have gradually replaced traditional picture tube display devices, becoming the mainstream of today's display devices.
  • the liquid crystal display device is composed of an array substrate and a color filter substrate, and liquid crystal is injected therebetween.
  • the array substrate is provided with intersecting gate lines and data lines to cross define the pixel unit, and the liquid crystal display device comprises
  • the pixel electrode and the common electrode form an electric field between the pixel electrode and the common electrode, and the liquid crystal molecules are deflected by changing the voltage of the electric field, and the color filter layer is matched to realize image display.
  • the liquid crystal display device When the liquid crystal display device performs image display, since the electric field corresponding to the edge of the pixel electrode is weak, the liquid crystal molecules located in the region are difficult to deflect, which in turn affects the display quality of the display device.
  • the invention provides an array substrate and a display device, which can improve the display quality of the display device.
  • the present invention provides an array substrate including a plurality of gate lines and a plurality of data lines, the gate lines and the data lines intersecting to define pixel units, the pixel units including pixel electrodes and thin film transistors,
  • the thin film transistor includes a drain, and the array substrate further includes a common electrode line.
  • the drain includes an extension portion, the common electrode line and the extension portion together form a light shielding structure, and an orthographic projection of the light shielding structure on a plane where the pixel electrode is located is located at an edge of the pixel electrode.
  • the drain of the thin film transistor is extended to form an extension portion, and a common electrode line is disposed, and the extension portion and the common electrode line cooperate with each other to form a light shielding structure, and the light shielding structure is located at the pixel electrode.
  • the orthographic projection on the plane is at the edge of the pixel electrode.
  • embodiments of the present invention provide a display device including the above array substrate.
  • the display device provided by the embodiment of the present invention has at least the same advantageous effects as the above array substrate, and details are not described herein again.
  • FIG. 1 is a schematic view showing a structure of an array substrate according to an embodiment of the invention.
  • FIG. 2 is a schematic diagram of a structure of an array substrate according to an embodiment of the invention.
  • FIG. 3 is a schematic diagram of a structure of an array substrate according to an embodiment of the invention.
  • FIG. 4 is a schematic diagram of a structure of an array substrate according to an embodiment of the invention.
  • FIG. 5 is a schematic diagram of a structure of an array substrate according to an embodiment of the invention.
  • FIG. 6 is a schematic view showing a structure of an array substrate according to an embodiment of the invention.
  • FIG. 7 shows a schematic diagram of a structure of an array substrate according to an embodiment of the invention.
  • an embodiment of the present invention provides an array substrate including a plurality of gate lines 10 and a plurality of data lines 11 , wherein the data lines 11 and the gate lines 10 are disposed at intersection; the plurality of gate lines 10 and the plurality of data lines 11 are defined by intersection
  • the pixel unit 20 is out.
  • each two adjacent gate lines 10 and two adjacent data lines 11 define one pixel unit 20.
  • Each of the pixel units 20 includes a pixel electrode 30 including a gate, a source 41 and a drain 42, wherein the gate is connected to the gate line 10, the source 41 is connected to the data line 11, and the drain 42 is provided. It is connected to the pixel electrode 30.
  • the gate and the gate lines may also be a unitary structure.
  • the array substrate in this embodiment further includes a common electrode line 50.
  • the drain electrode 42 includes an extension portion 421.
  • the common electrode line 50 and the extension portion 421 cooperate to form a light shielding structure, and the light projection structure is orthographically projected on the plane of the pixel electrode 30.
  • a corresponding light-shielding structure projection is formed, that is, the orthographic projection of the common electrode line 50 on the plane of the pixel electrode 30 and the orthographic projection of the extension portion 421 on the plane of the pixel electrode 30 are surrounded by the pixel.
  • the edge of the electrode 30 forms a light-shielding structure projection.
  • the projection of the light-shielding structure may be closed or non-closed.
  • the drain electrode 42 of the thin film transistor on the array substrate is extended to form the extension portion 421 while the common electrode line 50 is disposed on the array substrate, and the extension portion 421 is orthographically projected and common on the plane of the pixel electrode 30.
  • An orthographic projection of the electrode line 50 on the plane of the pixel electrode 30 together forms a light shielding structure projected around the edge of the pixel electrode 30 so that the light shielding structure corresponding to the projection of the light shielding structure can shield the edge of the pixel electrode 30.
  • the display quality of the display device is improved.
  • the orthographic projection formed by the light-shielding structure perpendicularly projected on the plane of the pixel electrode 30 may be a closed light-shielding structure projecting around the edge of the pixel electrode 30, or may be surrounded by the edge of the pixel electrode 30.
  • Non-closed shading structure projection may be a closed light-shielding structure projecting around the edge of the pixel electrode 30, or may be surrounded by the edge of the pixel electrode 30.
  • Non-closed shading structure projection projection.
  • the specific shape of the light shielding structure is not limited in this embodiment, and the specific shape of the light shielding structure may be correspondingly set according to the shape of the actual pixel electrode 30 or other factors.
  • the light-shielding structure can take many forms, and the following four ways are listed in the present embodiment for reference.
  • the shape of the pixel electrode 30 is assumed to be a rectangle, but the pixel electrode 30 is not limited to this shape.
  • the rectangular edges of the pixel electrode 30 are a first edge 31, a second edge 32, a third edge 33 and a fourth edge 34, respectively, wherein the first edge 31 and the second edge 32 are a pair of opposite edges, which can be seen here.
  • the upper and lower edges of the rectangular shape of the pixel electrode 30, and the third edge 33 and the fourth edge 34 are a pair of opposite edges, where the left and right edges of the upper and lower edges of the rectangle with respect to the pixel electrode 30 can be seen. Therefore, it can be assumed that the light shielding structure also includes four sides, and correspondingly, the light shielding structure projection also includes four sides surrounding the pixel electrode edge 30.
  • the first form of light-shielding structure can be seen in FIG. 1.
  • the drain 42 extends from the extension portion 421.
  • the extension portion 421 is mainly the drain electrode 42 and includes a first extension line 4211 parallel to the first edge 31 of the pixel electrode 30.
  • the orthographic projection of the first extension line 4211 on the plane of the pixel electrode is located at the first edge 31 of the pixel electrode, such that the first extension line 4211 forms one side of the light shielding structure; the common electrode line 50 includes parallel to the pixel electrode 30.
  • the first portion 51 being on the plane of the pixel electrode 30
  • the orthographic projection is located at the second edge 32 of the pixel electrode 30, the orthographic projection of the second portion 52 on the plane of the pixel electrode 30 is located at the third edge 33 of the pixel electrode 30, and the orthographic projection of the third portion 53 on the plane of the pixel electrode 30 Located at the fourth edge 34 of the pixel electrode 30, the three portions of the common electrode line 50 form the other three sides of the light shielding structure.
  • the sum of the lengths of the light shielding structures of the at least one pixel unit is greater than or equal to 3/4 of the sum of the side lengths of the corresponding pixel electrodes to form a better light shielding effect.
  • the sum of the lengths of the light shielding structures of the at least one pixel unit is between 7/8 and 15/16 of the sum of the side lengths of the corresponding pixel electrodes.
  • the sum of the lengths of the light shielding structures is the sum of the lengths of the first portion 51, the second portion 52, the third portion 53 and the drain extension portion 421 of the common electrode line 50, and the sum of the side lengths of the corresponding pixel electrodes is a pixel.
  • the side lengths corresponding to the first edge 31, the second edge 32, the third edge 33, and the fourth edge 34 of the electrode 30 are summed.
  • the orthographic projection of the second portion 52 on the plane of the pixel electrode 30 and the orthographic projection of the third portion 53 on the plane of the pixel electrode 30 may be orthogonal to the projection of the first portion 51 on the plane of the pixel electrode 30.
  • the connection is such that the projection of the common electrode line 50 is a unitary structure on the plane, and there is no gap, and the light shielding property is good.
  • the orthographic projection of the second portion 52 on the plane of the pixel electrode 30 and the orthographic projection of the third portion 53 on the plane of the pixel electrode 30 may be perpendicular to the first portion 51 at the pixel electrode 30.
  • the drain 42 extends from the extension portion 421.
  • the extension portion 421 is mainly the drain electrode 42 and first includes a first extension line parallel to the first edge 31 of the pixel electrode 30. 4211, then, extending from the first extension line 4211, the second extension line 4212 and the third extension line 4213, the orthographic projection of the first extension line 4211 on the plane of the pixel electrode 30 is located at the first edge 31 of the pixel electrode, and second An orthographic projection of the extension line 4212 on the plane of the pixel electrode 30 is located at the third edge 33 of the pixel electrode, and an orthographic projection of the third extension line 4213 on the plane of the pixel electrode 30 is located at the fourth edge 34 of the pixel electrode, thereby extending the portion 421
  • Each of the portions form three sides of the light-shielding structure; the common electrode line 50 is parallel to the second edge 32 of the pixel electrode 30, and the orthographic projection of the common electrode line 50 on the plane of the pixel electrode 30 is located at the second edge 32 of the pixel
  • the second extension line 4212 and the third extension line 4213 are both perpendicular to the first extension line 4211 to form a rectangular light-shielding structure.
  • the light-shielding structure shown in FIGS. 3 and 4 can be regarded as a combination of the light-shielding structures in FIGS. 1 and 2, which can make the second portion 52 of the common electrode line 50 in FIG. 1 and the second extension in FIG.
  • the line 4212 is commonly located adjacent the third edge 33 of the pixel electrode 30 to provide a light blocking effect at the third edge 33; correspondingly, the third portion 53 of the common electrode line 50 of FIG. 1 and the third extension of FIG.
  • the line 4213 is commonly located adjacent the fourth edge 34 of the pixel electrode 30 to provide a light blocking effect at the fourth edge 34.
  • the drain 42 extends out of the extension portion 421
  • the extension portion 421 is mainly composed of the drain electrode 42 and first includes a first extension line 4211 parallel to the first edge 31 of the pixel electrode 30. Then, the second extension line 4212 and the third extension extend from the first extension line 4211.
  • the line 4213, the orthographic projection of the first extension line 4211 on the plane of the pixel electrode 30 is located at the first edge 31 of the pixel electrode, and the orthographic projection of the second extension line 4212 on the plane of the pixel electrode 30 is located at the third edge 33 of the pixel electrode.
  • the orthographic projection of the third extension line 4213 on the plane of the pixel electrode 30 is located at the fourth edge 34 of the pixel electrode;
  • the common electrode line 50 includes the first portion 51 parallel to the second edge 32 of the pixel electrode 30, at the third edge 33
  • the second portion 52 and the third portion 53 of the fourth edge 34, the orthographic projection of the first portion 51 on the plane of the pixel electrode 30 is located at the second edge 32 of the pixel electrode 30, and the second portion 52 is at the plane of the pixel electrode 30.
  • the upper orthographic projection is located at the third edge 33 of the pixel electrode 30, and the orthographic projection of the third portion 53 on the plane of the pixel electrode 30 is located at the fourth edge 34 of the pixel electrode 30, such that the first extension line 4211 and the first Points 51 are formed two sides of the light shielding structure, a second extension line 4212 and the second portion 52 together form one side of the light shielding structure, the third extension line 4213 and the third portion 53 together form one side of the light shielding structure.
  • the second extension line 4212 and the third extension line 4213 are both perpendicular to the first extension line 4211, and the orthographic projection of the second portion 52 on the plane of the pixel electrode 30 and The orthographic projection of the three portions 53 on the plane of the pixel electrode 30 is perpendicular to the orthographic projection of the first portion 51 on the plane of the pixel electrode 30 to form a projection of the light-shielding structure of a regular shape.
  • the orthographic projection of the second portion on the plane of the pixel electrode 30 and the orthographic projection of the third portion on the plane of the pixel electrode 30 are both connected to the orthographic projection of the first portion 51 on the plane of the pixel electrode 30, thereby
  • the projection of the common electrode line 50 is also an integral structure without the gap in the extension portion 421 itself, and there is no gap, and the light shielding property is further improved.
  • Figure 5 shows a form of light blocking structure.
  • the drain 42 extends out of the extension portion 421.
  • the extension portion 421 is mainly the drain electrode 42 and first includes a first extension line parallel to the first edge 31 of the pixel electrode 30. 4211.
  • a third extension line 4213 extends from the first extension line 4211.
  • the orthographic projection of the first extension line 4211 on the plane of the pixel electrode 30 is located at the first edge 31 of the pixel electrode, and the third extension line 4213 is at the pixel electrode.
  • An orthographic projection on the plane of 30 is located at the fourth edge 34 of the pixel electrode; the common electrode line 50 includes parallel to the pixel electrode 30 a first portion 51 of the second edge 32, a second portion 52 at the third edge 33, and a third portion 53 at the fourth edge 34.
  • the orthographic projection of the first portion 51 on the plane of the pixel electrode 30 is located at the pixel electrode 30.
  • the second edge 32, the orthographic projection of the second portion 52 on the plane of the pixel electrode 30 is located at the third edge 33 of the pixel electrode 30, and the orthographic projection of the third portion 53 on the plane of the pixel electrode 30 is located at the fourth of the pixel electrode 30.
  • the edge 34 such that the first extension line 4211 and the first portion 51 respectively form two sides of the light shielding structure, the second portion 52 forms one side of the light shielding structure, and the third extension line 4213 and the third portion 53 together form one side of the light shielding structure .
  • the third extension line 4213 is perpendicular to the first extension line 4211, the orthographic projection of the second portion 52 on the plane of the pixel electrode 30, and the third portion 53 is at the pixel electrode 30.
  • the orthographic projections on the plane are perpendicular to the orthographic projection of the first portion 51 on the plane of the pixel electrode 30 to form a light-shielding structure of a regular shape.
  • the orthographic projection of the second portion on the plane of the pixel electrode 30 and the orthographic projection of the third portion on the plane of the pixel electrode 30 are both connected to the orthographic projection of the first portion 51 on the plane of the pixel electrode 30, thereby
  • the projection of the common electrode line 50 is also an integral structure without the gap in the extension portion 421 itself, and there is no gap, and the light shielding property is further improved.
  • the first portion 51, the second portion 52, and the third portion 53 of the common electrode line 50 may be disposed on the same layer according to actual needs, for example, according to the need to form the storage capacitor, or Set on the same layer.
  • this solution is not only applicable to the above three modes, and correspondingly, the parts of the common electrode line 50 may be disposed on the same layer, or may not be disposed on the same layer.
  • the drain extension portion 421 and the common electrode line 50 may be disposed in the same layer or in different layers.
  • the first portion 51, the second portion 52, and the third portion 53 of the common electrode line are not disposed on the same layer, that is, the first portion 51, the second portion 52, and the third portion 53 are disposed in different layers, that is, at least a part of The other two parts are set in different layers.
  • the first portion 51, the second portion 52, and the third portion 53 may be disposed in different layers such that the second portion 52 and the second extension line 4212 Different layers, at the same time, the second extension line 4212 and the second portion 52 are at the pixel electrode 30 There is an overlap area in the projection on the plane.
  • the end of the second extension line 4212 on the plane of the pixel electrode 30 is overlapped with the end of the second portion 52 on the plane of the pixel electrode 30, such that the end of the second extension line 4212
  • the ends of the portion and the second portion 52 form a storage capacitor which facilitates driving the liquid crystal molecules at the edge of the pixel electrode 30, thereby improving the performance of the array substrate, and on the plane where the pixel electrode 30 is located, the third
  • the corresponding light-shielding structure at the edge 33 has no gap, and the light-shielding effect is good.
  • the third extension line 4213 and the third portion 53 may be disposed in different layers.
  • the projection of the third extension line 4213 and the third portion 53 on the plane of the pixel electrode 30 has an overlapping area, for example, The orthographic projection end of the third extension line 4213 on the plane of the pixel electrode 30 overlaps with the orthographic projection end of the third portion 53 on the plane of the pixel electrode 30, and also forms a storage capacitor.
  • the first portion 51, the second portion 52, and the third portion 53 may be disposed in different layers such that the third portion 53 and The third extension line 4213 has different layers, and at the same time, the projection of the third extension line 4213 and the third portion 53 on the plane of the pixel electrode 30 has an overlapping area, for example, the third extension line 4213 is positive on the plane of the pixel electrode 30.
  • the projected end overlaps the orthographic projection end of the third portion 53 on the plane of the pixel electrode 30 such that the end of the third extension line 4213 and the end of the third portion 53 form a storage capacitor.
  • the projection on the plane of the pixel electrode 30 since the second extension line 4212 is connected to the first extension line 4211, it can be understood that one end of the second extension line 4212 is connected to the first extension line 4211. The other end is the orthographic projection end of the second extension line 4212 on the plane of the pixel electrode 30.
  • the projection of the third extension line 4213 on the plane of the pixel electrode 30 is a projection of the third extension line 4213 away from the end of the first extension line 4211. Therefore, it is not difficult to imagine that the projection of the second portion 52 on the plane of the pixel electrode 30 is the projection of the second portion 52 away from the end of the first portion 51, and the orthographic projection of the third portion 53 on the plane of the pixel electrode 30.
  • the end portion is a projection of the third portion 53 away from the end of the first portion 51.
  • the storage capacitor may be formed at the edge of the pixel electrode 30 side, or the storage capacitor may be formed at the edges of the pixel electrode 30, respectively.
  • the performance of the array substrate is improved step by step; at the same time, the light-shielding structures corresponding to the edges of the pixel electrodes 30 have no gaps, thereby further improving the light-shielding property.
  • a plurality of closed light-shielding structures that are void-free between the orthographic projections of portions of the common electrode line 50 on the plane of the pixel electrode 30.
  • the orthographic projection of the second extension line 4212 on the plane of the pixel electrode 30 and the orthographic projection of the second portion 52 on the plane of the pixel electrode 30 may be parallel to each other, and the ends of the two projections intersect each other in the plane.
  • the orthogonal projections on the plane of the pixel electrode 30 are parallel to each other.
  • the specific manner of realizing this closed light-shielding structure may be as follows: referring to the first pixel unit 20 in FIG. 4, the orthographic projection of the second extension line 4212 on the plane of the pixel electrode 30 is compared with the second portion 52 at the pixel electrode 30.
  • the fourth edge 34 of 30, that is, the orthographic projection of the second extension line 4212 and the third extension line 4213 on the plane of the pixel electrode 30, extends into the plane of the second portion 52 and the third portion 53 at the pixel electrode 30. The inside of the area defined by the orthographic projection.
  • the closed light-shielding structure can also be implemented in an opposite manner, that is, the orthographic projection of the second portion 52 and the third portion 53 on the plane of the pixel electrode 30 extends into the second The extension line 4212 and the third extension line 4213 are on the plane of the pixel electrode 30
  • the inside of the region defined by the orthographic projection is specifically: an orthographic projection of the second extension line 4212 on the plane of the pixel electrode 30, and an orthographic projection of the second portion 52 on the plane of the pixel electrode 30 away from the third edge of the pixel electrode 30 33.
  • An orthographic projection of the third extension line 4213 on the plane of the pixel electrode 30 is closer to the fourth edge 34 of the pixel electrode 30 than the orthographic projection of the third portion 53 on the plane of the pixel electrode 30.
  • the “closed” means that the edges of the pixel electrode 30 are provided with a light-shielding structure, which is, in an image, no exposed gap with respect to the edge of the pixel electrode 30. It does not mean that the shading structure itself must be continuous and closed.
  • the common electrode line 50 includes the first portion 51, the second portion 52, and the third portion 53.
  • the vertical distance of each portion on the plane of the pixel electrode 30 to the corresponding edge has a plurality of cases.
  • the vertical distance between the orthographic projection of the second portion 52 on the plane of the pixel electrode 30 and the third edge 33 may be greater than between the orthographic projection of the third portion 53 on the plane of the pixel electrode 30 and the fourth edge 34.
  • the vertical distance referring to the first pixel unit 20 in FIG. 5, the vertical distance between the orthographic projection of the second portion 52 on the plane of the pixel electrode 30 and the third edge 33 is smaller than The vertical distance between the orthographic projection of the third portion 53 on the plane of the pixel electrode and the fourth edge 34.
  • the vertical distance of each portion of the extending portion 421 on the plane of the pixel electrode 30 to the corresponding edge is also various.
  • the second extension line 4212 is positive on the plane of the pixel electrode 30.
  • the vertical distance between the projection and the third edge 33 may be greater than the vertical distance between the orthographic projection of the third extension line 4213 on the plane of the pixel electrode 30 and the fourth edge 34.
  • the vertical distance between the orthographic projection of the second extension line 4212 on the plane of the pixel electrode 30 and the third edge 33 may be smaller than the third extension line 4213 at the pixel electrode 30.
  • the vertical distance between the orthographic projection on the plane and the fourth edge 34 may be smaller than the third extension line 4213 at the pixel electrode 30.
  • the orthographic projection of the common electrode line 50 on the plane of the pixel electrode 30 may overlap with the pixel electrode 30, thereby forming a storage between the common electrode line 50 and the pixel electrode 30. Capacitance to improve the performance of the array substrate.
  • the extension portion 421 of the drain electrode 42 can also be made at the pixel electrode 30.
  • the orthographic projection on the plane overlaps with the pixel electrode 30, so that a storage capacitor is formed between the extending portion 421 and the pixel electrode 30 to improve the performance of the array substrate.
  • the two structures that form the storage capacitor must be set to a different layer. Of course, the above two cases are no exception.
  • at least one of the extending portions 421 and the common electrode line 50 may be disposed in different layers. Therefore, there can be at least one storage capacitor to improve the performance of the array substrate.
  • the array substrate can include a non-closed light blocking structure.
  • the extension portion 421 and the common electrode line 50 are disposed in the same layer, and a portion of the extension portion 421 is orthographically projected on the plane of the pixel electrode 30, and the common electrode
  • the orthographic projection of the line 50 on the plane of the pixel electrode 30 is on the same straight line, the projection between the two portions is voided, which is one of the non-closed light-shielding structures.
  • the drain electrode 42 and the pixel electrode 30 are connected through the via 60.
  • the extension portion 421 of the drain electrode 42 and the pixel electrode 30 can be connected through the via hole 60.
  • the via hole 60 can be disposed at a position away from the thin film transistor, thereby avoiding the influence of the etching solution etching the thin film transistor or the residual process process when the via hole 60 is in the vicinity of the thin film transistor when the via hole 60 is etched. The phenomenon of the performance of thin film transistors.
  • a groove 101 may be disposed on the gate line 10 away from the thin film transistor, and the groove 101 corresponds to a region where the via 60 is located, so that the region of the via 60 is located. In the groove 101, this saves layout space. For example, when the thin film transistor of the pixel unit 20 is located at the end of the gate line 10 corresponding to the pixel unit 20, the recess 101 may be disposed at a position other than the end of the gate line 10, that is, at both ends of the gate line 10. Any position between to achieve via 60 away from the thin film transistor.
  • the embodiment provides an array substrate including a plurality of gate lines 10 and a plurality of data lines 11, wherein the data lines 11 and the gate lines 10 are disposed at intersection; the plurality of gate lines 10 and the plurality of data lines 11 are defined by intersection.
  • the pixel unit 20 is out.
  • Each of the pixel units 20 includes a pixel electrode 30 including a gate, a source 41 and a drain 42, and a thin film transistor, wherein the gate is connected to the gate line 10, and the source 41 is The data lines 11 are connected, and the drain 42 is connected to the pixel electrodes 30.
  • the gate and the gate lines may also be a unitary structure.
  • the array substrate in this embodiment further includes a common electrode line 50, and a common electrode line 50 is shared by two adjacent pixel units in the vertical direction of the drawing, that is, the direction in which the data lines extend, so that the number of common electrode lines can be reduced, for example,
  • the first portion 51 of the common electrode line 50 in the drawing is shared by adjacent pixel units (upper and lower pixel units in Fig. 6).
  • the drain electrode 42 includes an extension portion 421.
  • the common electrode line 50 and the extension portion 421 cooperate to form a light shielding structure, and an orthographic projection of the light shielding structure on the plane of the pixel electrode 30 is located at an edge of the pixel electrode 30 to form a corresponding light shielding structure projection.
  • the orthographic projection of the common electrode line 50 on the plane of the pixel electrode 30 and the orthographic projection of the extension portion 421 on the plane of the pixel electrode 30 surround the edge of the pixel electrode 30 to form a light-shielding structure projection.
  • the projection of the light-shielding structure may be closed or non-closed.
  • the common electrode line 50 includes a first portion 51, a second portion 52, and a third portion 53.
  • the first portion 51 is substantially parallel to the gate lines, and the second portion 52 and the third portion 53 are substantially parallel to the data lines.
  • the orthographic projection of the second portion 52 and the third portion 53 on the plane of the pixel electrode 30 may be perpendicular to the first portion 51.
  • an auxiliary connecting line 60 is further included, and the auxiliary connecting line 60 may extend in a direction in which the gate line extends (ie, a horizontal direction of the drawing), and electrically connect the second portion 52 and the second portion of the common electrode line 50 of the same pixel unit 20 Three parts 53.
  • the auxiliary connection line 60 may be electrically connected to the common electrode line of the adjacent pixel unit 20.
  • the auxiliary connection line 60 extends in the horizontal direction, and the second and third portions of the adjacent pixel unit 20 intersect and are electrically connected to the auxiliary connection line. Due to the auxiliary connection line 60, the second portion and the third portion of the common connection line are connected in parallel to reduce the resistance.
  • FIG. 7 shows a case where the auxiliary connection line 60 electrically connects the second portion and the third portion of the adjacent pixel unit 20. It should be understood that FIG. 7 shows only two pixel units 20, which may be electrically connected to a plurality of adjacent pixel units 20 in practical use.
  • the drain electrode 42 of the thin film transistor on the array substrate is extended to form the extension portion 421 while the common electrode line 50 is disposed on the array substrate, and the extension portion 421 is orthographically projected and common on the plane of the pixel electrode 30.
  • Orthotropic projection of the electrode line 50 on the plane of the pixel electrode 30, Forming a light-shielding structure to project around the edge of the pixel electrode 30 so that the light-shielding structure corresponding to the light-shielding structure projection can shield the edge of the pixel electrode 30 to minimize the amount of light leakage in the edge region of the pixel electrode 30, thereby The display quality of the display device is improved.
  • Step S1 forming a gate metal layer on the base substrate, and patterning the gate metal layer to form a gate line, a gate, and a pattern of a common electrode line required.
  • the gate metal layer may be deposited by a sputtering process, and the material of the gate metal layer may be a metal such as copper, aluminum, molybdenum, titanium, chromium, tungsten, or an alloy of these metals.
  • a gate line of a single-layer structure or a gate line of a multi-layer structure such as a multilayer structure of molybdenum, aluminum, and molybdenum superposition, and a stacked structure of titanium, copper, and titanium, may be formed.
  • a multi-layered structure of molybdenum, titanium, and copper may be formed.
  • Step S2 forming a gate protection layer on the substrate having the gate lines, the gate electrodes, and the common electrode lines.
  • the gate protection layer may be formed by plasma enhanced chemical vapor deposition.
  • the material for forming the gate protection layer may be silicon nitride or silicon oxide, and the gate insulating layer formed may be a single layer structure or may be A multilayer structure such as a stacked structure of silicon nitride and silicon oxide.
  • Step S3 forming a semiconductor layer on the gate protection layer, and patterning the semiconductor layer to form an active layer.
  • amorphous silicon may be deposited by plasma enhanced chemical vapor deposition to form a semiconductor layer, or an oxide semiconductor (eg, indium gallium zinc oxide) may be deposited by a sputtering process to form a semiconductor layer.
  • an oxide semiconductor eg, indium gallium zinc oxide
  • Step S4 forming a source/drain metal layer on the active layer, and patterning the source/drain metal layer to form a pattern of data lines, sources, and drains.
  • the pattern of drains herein includes a pattern of extensions that cooperate with the common electrode lines.
  • the source/drain metal layer may be deposited by a sputtering process, and the source/drain metal layer may be made of a metal material such as copper, aluminum, molybdenum, titanium, chromium, tungsten or the like or an alloy of these metals.
  • Step S5 forming a passivation layer on the substrate having the data line, the source and the drain, and forming a pattern of via holes by a patterning process, the via holes being above the drain.
  • the vias may be located above the extension of the drain, and further, the vias may be remote from the corresponding thin film transistor.
  • a passivation layer such as silicon nitride may be formed by using an inorganic material, and correspondingly, silicon nitride may be deposited by plasma enhanced chemical vapor deposition on the substrate having the data line, the source and the drain to form a blunt
  • the passivation layer may also be formed by using an organic material, such as a resin.
  • a resin layer may be coated on the substrate having the data line, the source, and the drain to form a passivation layer.
  • Step S6 forming a transparent conductive film on the passivation layer, forming a pattern of the pixel electrode by a patterning process, and the pixel electrode is electrically connected to the drain through the via hole.
  • the pixel electrode can be electrically connected to the extension of the drain.
  • a transparent conductive film may be formed by a sputtering process, and the material for forming the transparent conductive film may be some transparent metal oxide such as indium tin oxide or indium zinc oxide.
  • the patterning process may include a process of coating photoresist, exposure development, etching, and the like.
  • the array substrate in the present embodiment can be formed, and the array substrate includes the light shielding structure in the above content.
  • One embodiment of the present invention provides a display device including the above array substrate.
  • the extension portion extending through the drain and the common electrode line are disposed together to form a light-shielding structure, and the light-shielding structure is vertically projected on the plane of the pixel electrode to form an orthographic projection at the edge of the pixel electrode.
  • the display device may be any product or component having a display function, such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a liquid crystal panel, an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种阵列基板及显示装置。所述阵列基板包括多条栅线（10）和多条数据线（11），所述栅线（10）和所述数据线（11）交叉界定出像素单元（20），所述像素单元（20）包括像素电极（30）和薄膜晶体管，所述薄膜晶体管包括漏极（42），所述阵列基板还包括公共电极线（50），所述漏极（42）包括延伸部（421），所述公共电极线（50）和所述延伸部（421）共同形成遮光结构，且所述遮光结构在所述像素电极（30）所在的平面上的正投影位于所述像素电极（20）的边缘附近。本发明提供的阵列基板应用于显示装置。

Description

阵列基板及显示装置
交叉引用
本申请要求于2016年5月31日提交的、名称为“一种阵列基板及显示装置”的中国专利申请NO.201620520143.X的优先权，该专利申请的公开内容通过引用方式整体并入本文。
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及显示装置。
背景技术
随着显示技术的发展，液晶显示装置已经逐渐取代了传统的显像管显示装置，成为当今显示装置的主流。
液晶显示装置是由阵列基板和彩膜基板对盒，并在二者之间注入液晶而成，阵列基板上设置有相互交叉的栅线和数据线，以交叉界定出像素单元，液晶显示装置包括像素电极和公共电极，像素电极与公共电极之间形成电场，通过改变电场的电压使液晶分子产生偏转，并配合彩色滤光层，从而实现图像的显示。
在液晶显示装置进行图像显示时，由于像素电极边缘对应的电场较弱，所以位于该区域范围内的液晶分子偏转难度相对较大，进而影响显示装置的显示质量。
发明内容
本发明提供一种阵列基板及显示装置，可以提高显示装置的显示质量。
本发明的实施例提供如下技术方案：
一方面，本发明提供了一种阵列基板，包括多条栅线和多条数据线，所述栅线和所述数据线交叉界定出像素单元，所述像素单元包括像素电极和薄膜晶体管，所述薄膜晶体管包括漏极，所述阵列基板还包括公共电极线，所 述漏极包括延伸部，所述公共电极线和所述延伸部共同形成遮光结构，且所述遮光结构在所述像素电极所在的平面上的正投影位于所述像素电极的边缘。
在本发明实施例提供的阵列基板中，将薄膜晶体管的漏极延伸以形成延伸部，同时设置公共电极线，延伸部和公共电极线相互配合，形成遮光结构，且遮光结构在像素电极所在的平面上的正投影位于像素电极的边缘。
另一方面，本发明的实施例提供了一种显示装置，所述显示装置包括上述阵列基板。
本发明实施例所提供的显示装置的至少具有与上述阵列基板相同的有益效果，在此不再赘述。
附图说明
此处所说明的附图用来提供对本发明的进一步理解，构成本发明的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1为根据发明一个实施例的阵列基板的一种结构的示意图；
图2为根据发明一个实施例的阵列基板的一种结构的示意图；
图3为根据发明一个实施例的阵列基板的一种结构的示意图；
图4为根据发明一个实施例的阵列基板的一种结构的示意图；
图5为根据发明一个实施例的阵列基板的一种结构的示意图。
图6示出根据发明一个实施例的阵列基板的一种结构的示意图；
图7示出根据发明一个实施例的阵列基板的一种结构的示意图。
具体实施方式
为使本发明所提出的技术方案的目的、特征和优点能够更加明显易懂，下面将结合附图，对本发明所提出的技术方案的实施例进行清楚、完整地描述。显然，所描述的实施例仅仅是所提出的技术方案的一部分实施例，而不 是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本发明保护的范围。
参见图1，本实施例提供了一种阵列基板，包括多条栅线10和多条数据线11，数据线11与栅线10交叉设置；多条栅线10和多条数据线11交叉界定出像素单元20。例如，每两条相邻的栅线10和两条相邻的数据线11界定出一个像素单元20。每个像素单元20中包括像素电极30和薄膜晶体管，薄膜晶体管包括栅极、源极41和漏极42，其中，栅极与栅线10相连，源极41与数据线11相连，漏极42与像素电极30相连。当然，在一种实施例中，栅极与栅线也可以为一体结构。本实施例中的阵列基板还包括公共电极线50，漏极42包括延伸部421，公共电极线50和延伸部421共同配合形成遮光结构，且该遮光结构在像素电极30所在平面上的正投影位于像素电极30的边缘，形成对应的遮光结构投影，也就是说，公共电极线50在像素电极30所在平面上的正投影与延伸部421在像素电极30所在平面上的正投影共同环绕在像素电极30的边缘，形成遮光结构投影。当然，该遮光结构投影可以是闭合的，也可以是非闭合的。
在本实施例中，将阵列基板上薄膜晶体管的漏极42延伸以形成延伸部421，同时在阵列基板上设置公共电极线50，使延伸部421在像素电极30所在平面上的正投影和公共电极线50在像素电极30所在平面上的正投影，共同形成一遮光结构投影围绕在像素电极30的边缘，以便与该遮光结构投影对应的遮光结构能够在像素电极30的边缘起到遮光作用，以尽量减少像素电极30的边缘区域的漏光量，从而提高了显示装置的显示质量。
在本实施例中，遮光结构垂直投射在像素电极30所在平面上所形成的正投影可以为一个环绕在像素电极30的边缘的闭合的遮光结构投影，也可以为环绕在像素电极30的边缘的非闭合的遮光结构投影。同时，本实施例中并不局限遮光结构的具体形状，可根据实际像素电极30的形状或者其它因素来相应地设定遮光结构的具体形状。
遮光结构可有多种形式，本实施例中列举以下四种方式，以供参考。
需要说明的是，在以下方式中，为了便于理解，将像素电极30的形状假设为矩形，但像素电极30不局限于该形状。像素电极30的矩形边缘分别为第一边缘31、第二边缘32、第三边缘33和第四边缘34，其中，第一边缘31与第二边缘32为一组相对的边缘，这里可以看到是像素电极30矩形的上边缘和下边缘，第三边缘33与第四边缘34为一组相对的边缘，这里可以看到相对于像素电极30矩形的上下边缘的左侧边缘和右侧边缘，因此，可以假设遮光结构对应的也包括四条边，相应的，遮光结构投影也包括环绕在像素电极边缘30的四条边。
第一种形式的遮光结构可以参见图1，漏极42延伸出延伸部421，该延伸部421以漏极42为主干，包括一条平行于像素电极30的第一边缘31的第一延伸线4211，同时，第一延伸线4211在像素电极所在平面上的正投影位于像素电极的第一边缘31，从而第一延伸线4211形成遮光结构的一条边；公共电极线50包括平行于像素电极30的第二边缘32的第一部分51、位于像素电极30的第三边缘33的第二部分52和位于像素电极30的第四边缘34的第三部分53，第一部分51在像素电极30所在平面上的正投影位于像素电极30的第二边缘32，第二部分52在像素电极30所在平面上的正投影位于像素电极30的第三边缘33，第三部分53在像素电极30所在平面上的正投影位于像素电极30的第四边缘34，从而公共电极线50的三部分形成遮光结构的其它三条边。
在方式一中，至少一像素单元的所述遮光结构的长度之和大于等于对应像素电极的边长之和的3/4，以形成较好的遮光效果。
可选的，在方式一中，至少一像素单元的所述遮光结构的长度之和在对应像素电极的边长之和的7/8-15/16之间。
例如：所述遮光结构的长度之和为公共电极线50的第一部分51、第二部分52、第三部分53以及漏极延伸部421的长度加和，对应像素电极的边长之和为像素电极30的第一边缘31、第二边缘32、第三边缘33、第四边缘34所对应的边长加和。
在方式一中，第二部分52在像素电极30所在平面上的正投影和第三部分53在像素电极30所在平面上的正投影，可与第一部分51在像素电极30所在平面上的正投影连接，从而在该平面上，公共电极线50的投影为一个整体结构，没有空隙，遮光性较好。
进一步的，基于像素电极30为矩形，第二部分52在像素电极30所在平面上的正投影和第三部分53在像素电极30所在平面上的正投影，可以垂直于第一部分51在像素电极30所在平面上的正投影，以形成一个矩形形状的遮光结构。
第二种形式的遮光结构可以参见图2，漏极42延伸出延伸部421，该延伸部421以漏极42为主干，首先包括一条平行于像素电极30的第一边缘31的第一延伸线4211，接着，从第一延伸线4211延伸出第二延伸线4212和第三延伸线4213，第一延伸线4211在像素电极30所在平面上的正投影位于像素电极的第一边缘31，第二延伸线4212在像素电极30所在平面上的正投影位于像素电极的第三边缘33，第三延伸线4213在像素电极30所在平面上的正投影位于像素电极的第四边缘34，从而延伸部421的各部分形成遮光结构的三条边；公共电极线50与像素电极30的第二边缘32相平行，且公共电极线50在像素电极30所在平面上的正投影位于像素电极的第二边缘32；从而公共电极线50的形成遮光结构的另外一条边。
在第二种形式的遮光结构中，基于像素电极30为矩形，第二延伸线4212和第三延伸线4213均垂直于第一延伸线4211，以形成一个矩形的遮光结构。
参见图3和图4示出一种形式的遮光结构。图3和图4中示出的遮光结构可以看作是图1和图2中的遮光结构的结合，可使图1中的公共电极线50的第二部分52与图2中的第二延伸线4212共同位于像素电极30的第三边缘33附近，以在第三边缘33处起到遮光作用；相应的，使图1中公共电极线50的第三部分53与图2中的第三延伸线4213共同位于像素电极30的第四边缘34附近，以在第四边缘34处起到遮光作用。
参见图3和图4，基于上述思路，可选地，漏极42延伸出延伸部421， 该延伸部421以漏极42为主干，首先包括一条平行于像素电极30的第一边缘31的第一延伸线4211，接着，从第一延伸线4211延伸出第二延伸线4212和第三延伸线4213，第一延伸线4211在像素电极30所在平面上的正投影位于像素电极的第一边缘31，第二延伸线4212在像素电极30所在平面上的正投影位于像素电极的第三边缘33，第三延伸线4213在像素电极30所在平面上的正投影位于像素电极的第四边缘34；公共电极线50包括平行于像素电极30的第二边缘32的第一部分51、位于第三边缘33的第二部分52和位于第四边缘34的第三部分53，第一部分51在像素电极30所在平面上的正投影位于像素电极30的第二边缘32，第二部分52在像素电极30所在平面上的正投影位于像素电极30的第三边缘33，第三部分53在像素电极30所在平面上的正投影位于像素电极30的第四边缘34，从而第一延伸线4211和第一部分51分别形成遮光结构的两条边，第二延伸线4212和第二部分52共同形成遮光结构的一条边，第三延伸线4213和第三部分53共同形成遮光结构的一条边。
对应的，基于像素电极30为矩形，可选地，第二延伸线4212和第三延伸线4213均垂直于第一延伸线4211，第二部分52在像素电极30所在平面上的正投影和第三部分53在像素电极30所在平面上的正投影，均垂直于第一部分51在像素电极30所在平面上的正投影，以形成一个规整形状的遮光结构投影。进一步的，第二部分在像素电极30所在平面上的正投影和第三部分在像素电极30所在平面上的正投影，均连接于第一部分51在像素电极30所在平面上的正投影，从而在该平面上，在延伸部421本身没有空隙的前提下，公共电极线50的投影也为一个整体结构，没有空隙，进一步提高了遮光性。
图5示出一种形式的遮光结构。参见图5中的第一个像素单元20，漏极42延伸出延伸部421，该延伸部421以漏极42为主干，首先包括一条平行于像素电极30的第一边缘31的第一延伸线4211，接着，从第一延伸线4211延伸出第三延伸线4213，第一延伸线4211在像素电极30所在平面上的正投影位于像素电极的第一边缘31，第三延伸线4213在像素电极30所在平面上的正投影位于像素电极的第四边缘34；公共电极线50包括平行于像素电极30 的第二边缘32的第一部分51、位于第三边缘33的第二部分52和位于第四边缘34的第三部分53，第一部分51在像素电极30所在平面上的正投影位于像素电极30的第二边缘32，第二部分52在像素电极30所在平面上的正投影位于像素电极30的第三边缘33，第三部分53在像素电极30所在平面上的正投影位于像素电极30的第四边缘34，从而第一延伸线4211和第一部分51分别形成遮光结构的两条边，第二部分52形成遮光结构的一条边，第三延伸线4213和第三部分53共同形成遮光结构的一条边。
对应的，基于像素电极30为矩形，可选地，第三延伸线4213垂直于第一延伸线4211，第二部分52在像素电极30所在平面上的正投影和第三部分53在像素电极30所在平面上的正投影，均垂直于第一部分51在像素电极30所在平面上的正投影，以形成一个规整形状的遮光结构。进一步的，第二部分在像素电极30所在平面上的正投影和第三部分在像素电极30所在平面上的正投影，均连接于第一部分51在像素电极30所在平面上的正投影，从而在该平面上，在延伸部421本身没有空隙的前提下，公共电极线50的投影也为一个整体结构，没有空隙，进一步提高了遮光性。
在上述多种示例方式中，可根据实际需要，例如，根据形成存储电容的需要，将公共电极线50的第一部分51、第二部分52和第三部分53设置在同一层上，或者，不设置在同一层上。当然了，此方案不仅仅适用于以上三种方式，相应的，公共电极线50的各部分可设置在同一层上，或者，不设置在同一层上。
可选的，漏极延伸部421与公共电极线50可以同层或异层设置。例如，公共电极线的第一部分51、第二部分52和第三部分53不设置在同一层上，即第一部分51、第二部分52和第三部分53异层设置，也就是至少有一部分与其它两部分是异层设置的。
参见图3的第一个像素单元20，例如，为了进一步完善遮光结构，可将第一部分51、第二部分52和第三部分53异层设置，以使第二部分52和第二延伸线4212不同层，同时，第二延伸线4212与第二部分52在像素电极30 所在平面上的投影存在交叠区域。比如，第二延伸线4212在像素电极30所在平面上的正投影的端部，与第二部分52在像素电极30所在平面上的正投影的端部重叠，这样，第二延伸线4212的端部和第二部分52的端部就会形成存储电容，该存储电容有利于驱动像素电极30的边缘的液晶分子，从而了提高阵列基板的性能，而且在像素电极30所在的平面上，第三边缘33处对应的遮光结构是没有空隙的，遮光效果好。
在另一实施例中，还可使第三延伸线4213与第三部分53异层设置，第三延伸线4213与第三部分53在像素电极30所在平面上的投影存在交叠区域，比如，第三延伸线4213在像素电极30所在平面上的正投影的端部，与第三部分53在像素电极30所在平面上的正投影的端部重叠，也形成存储电容。
参见图5中的第一个像素单元20，在一个实施例中，为了进一步完善遮光结构，可将第一部分51、第二部分52和第三部分53异层设置，以使第三部分53和第三延伸线4213不同层，同时，第三延伸线4213与第三部分53在像素电极30所在平面上的投影存在交叠区域，比如，第三延伸线4213在像素电极30所在平面上的正投影的端部，与第三部分53在像素电极30所在平面上的正投影的端部重叠，这样，第三延伸线4213的端部和第三部分53的端部就会形成存储电容。
说明的是，对于像素电极30所在平面上的投影来说，因第二延伸线4212与第一延伸线4211连接，因此，可以理解为第二延伸线4212的一端与第一延伸线4211连接，另一端即为上述第二延伸线4212在像素电极30所在平面上的正投影的端部。同理，上述第三延伸线4213在像素电极30所在平面上的正投影的端部为第三延伸线4213远离第一延伸线4211一端的投影。因此，不难想到，第二部分52在像素电极30所在平面上的正投影的端部为第二部分52远离第一部分51一端的投影，第三部分53在像素电极30所在平面上的正投影的端部为第三部分53远离第一部分51一端的投影。
在上述形成存储电容的方案中，可以是在像素电极30一侧的边缘形成存储电容，还可以是在像素电极30的两侧的边缘分别形成存储电容，这样进一 步地提高阵列基板的性能；同时像素电极30的两侧的边缘对应的遮光结构均没有空隙，也就进一步提高了遮光性。在一个实施例中，在公共电极线50的各部分在像素电极30所在平面上的正投影之间为无空隙的情况，对应的遮光结构为闭合的，从而达到更佳的遮光效果。
参见图4，根据本发明的其他实施例，还有多种闭合的遮光结构在公共电极线50的各部分在像素电极30所在平面上的正投影之间为无空隙的情形。例如，可使第二延伸线4212在像素电极30所在平面上的正投影和第二部分52在像素电极30所在平面上的正投影相互平行，且二者正投影的端部在平面内相互交叠，这样，遮光结构在第三边缘33对应的部分是没有空隙的，而且在二者端部位置为双重遮光；同时，第三延伸线4213在像素电极30所在平面上的正投影和第三部分53在像素电极30所在平面上的正投影相互平行，且二者正投影的端部在平面内相互交叠，这样，遮光结构在第四边缘34对应的部分也是没有空隙的，而且在二者端部位置也为双重遮光，像素电极30边缘的遮光结构为闭合的。在另一实施例中，基于上述第二延伸线4212和第三延伸线4213均垂直于第一延伸线4211的方案，此方案中的第二延伸线4212、第三延伸线4213、第二部分52和第三部分53，在像素电极30所在平面上的正投影相互平行。
实现这一闭合的遮光结构具体方式可以是：参见图4中第一个像素单元20，使第二延伸线4212在像素电极30所在平面上的正投影，较第二部分52在像素电极30所在平面上的正投影，靠近像素电极30的第三边缘33，第三延伸线4213在像素电极30所在平面上的正投影，较第三部分53在像素电极30所在平面上的正投影靠近像素电极30的第四边缘34，也就是说，第二延伸线4212和第三延伸线4213在像素电极30所在平面上的正投影，伸入第二部分52和第三部分53在像素电极30所在平面上的正投影限定的区域内部。
参见图4中第二个像素单元20，上述闭合的遮光结构还可以采取相反的方式实现，也就是第二部分52和第三部分53在像素电极30所在平面上的正投影，伸入第二延伸线4212和第三延伸线4213在像素电极30所在平面上的 正投影限定的区域内部，具体为：使第二延伸线4212在像素电极30所在平面上的正投影，较第二部分52在像素电极30所在平面上的正投影远离像素电极30的第三边缘33，第三延伸线4213在像素电极30所在平面上的正投影，较第三部分53在像素电极30所在平面上的正投影远离像素电极30的第四边缘34。
需要补充的是，在本实施例中，所述“闭合”是指像素电极30的边缘均设有遮光结构，形象的说，就是相对于像素电极30的边缘而言，没有暴露的缝隙，而并不是指遮光结构本身必须是连续的且封闭的。
在本实施例，公共电极线50包括第一部分51、第二部分52和第三部分53的方案中，各部分在像素电极30所在平面上的正投影到对应边缘的垂直距离有多种情况，例如：第二部分52在像素电极30所在平面上的正投影与第三边缘33之间的垂直距离，可以大于第三部分53在像素电极30所在平面上的正投影与第四边缘34之间的垂直距离。在本发明的实施例中，也可以是，参见图5中的第一个像素单元20，第二部分52在像素电极30所在平面上的正投影与第三边缘33之间的垂直距离，小于第三部分53在像素电极所在平面上的正投影与第四边缘34之间的垂直距离。
根据本发明的实施例，延伸部421的各部分在像素电极30所在平面上的正投影到对应边缘的垂直距离也有多种情况，例如：第二延伸线4212在像素电极30所在平面上的正投影与第三边缘33之间的垂直距离，可以大于第三延伸线4213在像素电极30所在平面上的正投影与第四边缘34之间的垂直距离。或者，根据本发明的实施例，也可以是，第二延伸线4212在像素电极30所在平面上的正投影与第三边缘33之间的垂直距离，小于第三延伸线4213在像素电极30所在平面上的正投影与第四边缘34之间的垂直距离。
进一步，在本发明的另一实施例中，还可使公共电极线50在像素电极30所在平面上的正投影与像素电极30存在重叠，从而使公共电极线50与像素电极30之间形成存储电容，以提高阵列基板的性能。
在本发明的另一实施例中，还可使漏极42的延伸部421在像素电极30 所在平面上的正投影与像素电极30存在重叠，从而使延伸部421与像素电极30之间形成存储电容，以提高阵列基板的性能。
形成存储电容的两个结构必须保证异层设置，当然以上两种情况也不例外。而在本实施例中的遮光结构中，漏极42的延伸部421的各部分与公共电极线50的各部分之间，可至少有一组延伸部421和公共电极线50是异层设置的，因此，可至少有一个存储电容，以提高阵列基板的性能。
上述内容具体说明了根据本发明的多个实施例的闭合的遮光结构。在根据本发明的其他实施例中，阵列基板可以包括非闭合的遮光结构。参见图3中第二个像素单元，例如：当延伸部421与公共电极线50之间为同层设置，且延伸部421中的某部分在像素电极30所在平面上的正投影，与公共电极线50在像素电极30所在平面上的正投影处于同一条直线时，这时，这两部分之间的投影是有空隙的，这就是其中一种非闭合遮光结构。
参见图5，值得一提的是，漏极42与像素电极30通过过孔60连接，在本实施例中，可使漏极42的延伸部421与像素电极30通过过孔60连接，这样，可将过孔60设置在远离薄膜晶体管的位置处，从而避免了在刻蚀过孔60时，若过孔60在薄膜晶体管附近，出现因刻蚀液腐蚀薄膜晶体管，或者工艺过程的残留等影响薄膜晶体管的性能的现象。
进一步的，在根据本发明的实施例中，可在栅线10上远离薄膜晶体管处设置有凹槽101，该凹槽101与过孔60所在区域相对应，从而可使过孔60所在区域位于该凹槽101内，这样就节省了布局空间。例如，当像素单元20的薄膜晶体管位于该像素单元20所对应的栅线10的端部时，可将凹槽101设置在栅线10非端部的位置处，也就是栅线10两端之间的任意位置，以实现过孔60远离薄膜晶体管。
参见图6，本实施例提供了一种阵列基板，包括多条栅线10和多条数据线11，数据线11与栅线10交叉设置；多条栅线10和多条数据线11交叉界定出像素单元20。每个像素单元20中包括像素电极30和薄膜晶体管，薄膜晶体管包括栅极、源极41和漏极42，其中，栅极与栅线10相连，源极41与 数据线11相连，漏极42与像素电极30相连。当然，在一种实施例中，栅极与栅线也可以为一体结构。本实施例中的阵列基板还包括公共电极线50，沿图的竖直方向即数据线延伸的方向上的相邻两个像素单元共用一条公共电极线50，如此可以减少公共电极线数量，例如图中公共电极线50的第一部分51被相邻的像素单元(图6中上下两个像素单元)共用。漏极42包括延伸部421，公共电极线50和延伸部421共同配合形成遮光结构，且该遮光结构在像素电极30所在平面上的正投影位于像素电极30的边缘，形成对应的遮光结构投影，也就是说，公共电极线50在像素电极30所在平面上的正投影与延伸部421在像素电极30所在平面上的正投影共同环绕在像素电极30的边缘，形成遮光结构投影。当然，该遮光结构投影可以是闭合的，也可以是非闭合的。
可选的，公共电极线50包括第一部分51，第二部分52和第三部分53。第一部分51大致平行栅线，第二部分52和第三部分53大致平行于数据线。优选的，第二部分52和第三部分53在像素电极30所在平面上的正投影可以垂直于第一部分51。
可选的，还包括辅助连接线60，辅助连接线60可以沿栅线延伸的方向(即图的水平方向)延伸，并且电性连接同一像素单元20公共电极线50的第二部分52和第三部分53。
可选的，辅助连接线60可以电性连接相邻像素单元20的公共电极线。具体地，辅助连接线60沿水平方向延伸，相邻像素单元20的第二部分和第三部分与辅助连接线相交并电连接。由于辅助连接线60，公共连接线的第二部分和第三部分被并联连接从而减小电阻。图7示出辅助连接线60电连接相邻像素单元20的第二部分和第三部分的情形。应该知道，图7仅示出两个像素单元20，实际应用中辅助连接线60可以电连接多个相邻像素单元20。
在本实施例中，将阵列基板上薄膜晶体管的漏极42延伸以形成延伸部421，同时在阵列基板上设置公共电极线50，使延伸部421在像素电极30所在平面上的正投影和公共电极线50在像素电极30所在平面上的正投影，共 同形成一遮光结构投影围绕在像素电极30的边缘，以便与该遮光结构投影对应的遮光结构能够在像素电极30的边缘起到遮光作用，以尽量减少像素电极30的边缘区域的漏光量，从而提高了显示装置的显示质量。
以下对应的提供一种上述阵列基板的制备方法：
步骤S1：在衬底基板上形成栅极金属层，对栅极金属层进行构图工艺，形成栅线、栅极，以及所需要的公共电极线的图形。
可选的，可采用溅射工艺沉积栅极金属层，形成栅极金属层的材料可为铜、铝、钼、钛、铬、钨等金属，也可为这些金属的合金。
其中，在步骤S1中，可形成单层结构的栅线，或者多层结构的栅线，如：钼、铝、钼叠加式的多层结构，钛、铜、钛叠加式的多层结构，或者，钼、钛、铜叠加式的多层结构。
步骤S2：在具有栅线、栅极和公共电极线的基板上形成栅极保护层。
可选的，可通过等离子体增强化学气相沉积法形成栅极保护层，形成栅极保护层的材料可为氮化硅或者氧化硅，形成的栅极绝缘层可以是单层结构，也可以是多层结构，例如氮化硅和氧化硅叠加式的多层结构。
步骤S3：在栅极保护层上形成半导体层，对半导体层进行构图工艺，形成有源层。
可选的，可通过等离子体增强化学气相沉积法沉积非晶硅来形成半导电体层，或者可通过溅射工艺沉积氧化物半导体来(如：氧化铟镓锌)形成半导电体层。
步骤S4：在有源层上形成源漏金属层，对源漏金属层进行构图工艺，形成数据线、源极、漏极的图形。
可选地，这里的漏极的图形包括与公共电极线相互配合的延伸部的图形。
可选地，可采用溅射工艺沉积源漏金属层，源漏金属层可由铜、铝、钼、钛、铬、钨等金属材料或者这些金属的合金制备而成。
步骤S5：在具有数据线、源极、漏极的基板上形成钝化层，通过构图工艺形成过孔的图形，过孔位于漏极上方。
可选地，过孔可位于漏极的延伸部的上方，进一步的，过孔可远离相应的薄膜晶体管。
可选地，可采用无机物形成钝化层，如氮化硅，对应的，可在具有数据线、源极、漏极的基板上采用等离子体增强化学气相沉积法沉积氮化硅来形成钝化层；也可采用有机物形成钝化层，如树脂，对应的，可在具有数据线、源极、漏极的基板上涂覆树脂层来形成钝化层。
步骤S6：在钝化层上形成透明导电薄膜，通过构图工艺形成像素电极的图形，像素电极通过过孔与漏极电连接。
可选地，像素电极可与漏极的延长部电连接。
可选地，可采用溅射工艺形成透明导电薄膜，形成透明导电薄膜的材料可为氧化铟锡、氧化铟锌等一些透明金属氧化物。
以上步骤中，构图工艺可包括涂覆光刻胶、曝光显影、刻蚀等过程。
通过这一制备方法，可形成本实施例中的阵列基板，该阵列基板包括上述内容中的遮光结构。
本本发明的一个实施例提供了一种显示装置，该显示装置包括上述阵列基板。
在上述阵列基板的像素电极的边缘，通过漏极延伸的延伸部与公共电极线的设置，共同形成遮光结构，且遮光结构垂直投射在像素电极所在平面上形成的正投影，在像素电极的边缘形成闭合或者非闭合的遮光结构投影，从而使遮光结构在像素电极的边缘能够起到遮光作用，进而减少了像素电极边缘的漏光量，显示装置的显示质量得以提高。
需要说明的是，本实施例所提供的显示装置可以为液晶面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护 范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种阵列基板，包括多条栅线和多条数据线，所述栅线和所述数据线交叉界定出像素单元，所述像素单元每个包括像素电极和薄膜晶体管，所述薄膜晶体管包括漏极，其中，所述阵列基板还包括公共电极线，所述漏极包括延伸部，所述公共电极线和所述延伸部共同形成遮光结构，且所述遮光结构在所述像素电极所在的平面上的正投影位于所述像素电极的边缘。
  2. 根据权利要求1所述的阵列基板，其中，所述延伸部包括第一延伸线，所述第一延伸线与所述像素电极的第一边缘相平行，且所述第一延伸线在所述像素电极所在平面上的正投影位于所述像素电极的第一边缘；
    所述公共电极线包括第一部分、第二部分和第三部分，所述第一部分与所述像素电极的第二边缘相平行，且所述第一部分在所述像素电极所在平面上的正投影位于所述像素电极的第二边缘；所述第二部分和所述第三部分分别在所述像素电极所在平面上的正投影均与所述第一部分在所述像素电极所在平面上的正投影连接，且所述第二部分在所述像素电极所在平面上的正投影位于所述像素电极的第三边缘，所述第三部分在所述像素电极所在平面上的正投影位于所述像素电极的第四边缘；
    其中，所述像素电极的第一边缘与所述像素电极的第二边缘相对，所述像素电极的第三边缘与所述像素电极第四边缘相对。
  3. 根据权利要求1所述的阵列基板，其中，所述延伸部包括第一延伸线、第二延伸线和第三延伸线，所述第一延伸线与所述像素电极的第一边缘相平行，且所述第一延伸线在所述像素电极所在平面上的正投影位于所述像素电极的第一边缘；所述第二延伸线和所述第三延伸线均与所述第一延伸线连接，所述第二延伸线在所述像素电极所在平面上的正投影位于所述像素电极的第三边缘，所述第三延伸线在所述像素电极所在平面上的正投影位于所述像素电极的第四边缘；
    所述公共电极线与所述像素电极的第二边缘相平行，且所述公共电极线 在所述像素电极所在平面上的正投影位于所述像素电极的第二边缘；
    其中，所述像素电极的第一边缘与所述像素电极的第二边缘相对，所述像素电极的第三边缘与所述像素电极第四边缘相对。
  4. 根据权利要求1所述的阵列基板，其中，所述延伸部包括第一延伸线、第二延伸线和第三延伸线，所述第一延伸线与所述像素电极的第一边缘相平行，且所述第一延伸线在所述像素电极所在平面上的正投影位于所述像素电极的第一边缘；所述第二延伸线和所述第三延伸线均与所述第一延伸线连接，所述第二延伸线在所述像素电极所在平面上的正投影位于所述像素电极的第三边缘，所述第三延伸线在所述像素电极所在平面上的正投影位于所述像素电极的第四边缘；
    所述公共电极线包括第一部分、第二部分和第三部分，所述第一部分与所述像素电极的第二边缘相平行，且所述第一部分在所述像素电极所在平面上的正投影位于所述像素电极的第二边缘；所述第二部分在所述像素电极所在平面上的正投影连接于所述第一部分在所述像素电极所在平面上的正投影，所述第二部分在所述像素电极所在平面上的正投影位于所述像素电极的第三边缘；所述第三部分在所述像素电极所在平面上的正投影连接于所述第一部分在所述像素电极所在平面上的正投影，所述第三部分在所述像素电极所在平面上的正投影位于所述像素电极的第四边缘；
    其中，所述像素电极的第一边缘与所述像素电极的第二边缘相对，所述像素电极的第三边缘与所述像素电极第四边缘相对。
  5. 根据权利要求4所述的阵列基板，其中，所述第二延伸线与所述第二部分异层设置，所述第二延伸线与所述第二部分在所述像素电极所在平面上的投影存在交叠区域；和/或，
    所述第三延伸线与所述第三部分异层设置，所述第三延伸线与所述第三部分在所述像素电极所在平面上的投影存在交叠区域。
  6. 根据权利要求4所述的阵列基板，其中，所述第二延伸线、所述第三延伸线、所述第二部分和所述第三部分，在所述像素电极所在平面上的正投 影相互平行，且所述第二延伸线在所述像素电极所在平面上的正投影的端部与所述第二部分在所述像素电极所在平面上的正投影的端部相互交叠，所述第三延伸线在所述像素电极所在平面上的正投影的端部与所述第三部分在所述像素电极所在平面上的正投影的端部相互交叠。
  7. 根据权利要求6所述的阵列基板，其中，所述第二延伸线在所述像素电极所在平面上的正投影，较所述第二部分在所述像素电极所在平面上的正投影远离所述像素电极的第三边缘，所述第三延伸线在所述像素电极所在平面上的正投影，较所述第三部分在所述像素电极所在平面上的正投影远离所述像素电极的第四边缘；或者，
    所述第二延伸线在所述像素电极所在平面上的正投影，较所述第二部分在所述像素电极所在平面上的正投影靠近对应的所述像素电极的第三边缘，所述第三延伸线在所述像素电极所在平面上的正投影，较所述第三部分在所述像素电极所在平面上的正投影靠近所述像素电极的第四边缘。
  8. 根据权利要求1所述的阵列基板，其中，所述延伸部包括第一延伸线和第三延伸线，所述第一延伸线与所述像素电极的第一边缘相平行，且所述第一延伸线在所述像素电极所在平面上的正投影位于所述像素电极的第一边缘；所述第三延伸线与所述第一延伸线连接，所述第三延伸线在所述像素电极所在平面上的正投影位于所述像素电极的第四边缘；
    所述公共电极线包括第一部分、第二部分和第三部分，所述第一部分与所述像素电极的第二边缘相平行，且所述第一部分在所述像素电极所在平面上的正投影位于所述像素电极的第二边缘；所述第二部分在所述像素电极所在平面上的正投影连接于所述第一部分在所述像素电极所在平面上的正投影，所述第二部分在所述像素电极所在平面上的正投影位于所述像素电极的第三边缘；所述第三部分在所述像素电极所在平面上的正投影连接于所述第一部分在所述像素电极所在平面上的正投影，所述第三部分在所述像素电极所在平面上的正投影位于所述像素电极的第四边缘；
    其中，所述像素电极的第一边缘与所述像素电极的第二边缘相对，所述 像素电极的第三边缘与所述像素电极第四边缘相对。
  9. 根据权利要求8所述的阵列基板，其中，所述第三延伸线与所述第三部分异层设置，所述第三延伸线与所述第三部分在所述像素电极所在平面上的投影存在交叠区域。
  10. 根据权利要求2、4、8任一项所述的阵列基板，其中，所述第二部分在所述像素电极所在平面上的正投影与所述第三边缘之间的垂直距离，大于所述第三部分在所述像素电极所在平面上的正投影与所述第四边缘之间的垂直距离；或者，
    所述第二部分在所述像素电极所在平面上的正投影与所述第三边缘之间的垂直距离，小于所述第三部分在所述像素电极所在平面上的正投影与所述第四边缘之间的垂直距离。
  11. 根据权利要求3或4所述的阵列基板，其中，所述第二延伸线在所述像素电极所在平面上的正投影与所述第三边缘之间的垂直距离，大于所述第三延伸线在所述像素电极所在平面上的正投影与所述第四边缘之间的垂直距离；或者，
    所述第二延伸线在所述像素电极所在平面上的正投影与所述第三边缘之间的垂直距离，小于所述第三延伸线在所述像素电极所在平面上的正投影与所述第四边缘之间的垂直距离。
  12. 根据权利要求2、4、8任一项所述的阵列基板，其中，所述公共电极线的第一部分、第二部分和第三部分为同层设置，或者，所述公共电极线的第一部分、第二部分和第三部分的至少一部分与其它两个部分为异层设置。
  13. 根据权利要求1～9任一项所述的阵列基板，其中，所述公共电极线在所述像素电极所在平面上的正投影与所述像素电极存在重叠。
  14. 根据权利要求1～9任一项所述的阵列基板，其中，所述漏极的延伸部在所述像素电极所在平面上的正投影与所述像素电极存在重叠。
  15. 根据权利要求1～9任一项所述的阵列基板，其中，所述漏极的延伸部与所述像素电极通过过孔连接，所述薄膜晶体管位于所述像素单元对应栅 线的端部，在所述像素单元对应栅线的非端部的位置处设置有凹槽，所述过孔所在区域位于所述凹槽内。
  16. 根据权利要求1～9任一项所述的阵列基板，其中，所述相邻像素单元共用一条公共电极线。
  17. 根据权利要求1～9任一项所述的阵列基板，其中，所述延伸部包括第一延伸线，所述第一延伸线与所述像素电极的第一边缘相平行，且所述第一延伸线在所述像素电极所在平面上的正投影位于所述像素电极的第一边缘；
    至少一像素单元的所述公共电极线包括相互平行的第二部分和第三部分，还包括一辅助连接线，所述辅助连接线电性连接所述第二部分和第三部分。
  18. 根据权利要求2-4和17任一项所述的阵列基板，还包括一辅助连接线，所述辅助连接线平行于栅线延伸方向延伸并且电性连接相邻像素单元的公共电极线的所述第二部分和第三部分。
  19. 根据权利要求1～9任一项所述的阵列基板，其中，至少一像素单元的所述遮光结构的长度之和大于等于对应像素电极的边长之和的四分之三。
  20. 一种显示装置，其中，所述显示装置包括权利要求1～19任一项所述的阵列基板。
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CN110660836A (zh) * 2019-09-30 2020-01-07 上海天马有机发光显示技术有限公司 一种显示面板及显示装置
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