WO2021239091A1 - 薄膜晶体管及其制备方法、阵列基板和显示面板 - Google Patents

薄膜晶体管及其制备方法、阵列基板和显示面板 Download PDF

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WO2021239091A1
WO2021239091A1 PCT/CN2021/096622 CN2021096622W WO2021239091A1 WO 2021239091 A1 WO2021239091 A1 WO 2021239091A1 CN 2021096622 W CN2021096622 W CN 2021096622W WO 2021239091 A1 WO2021239091 A1 WO 2021239091A1
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substrate
gate
end surface
oxide nanowire
layer
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PCT/CN2021/096622
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English (en)
French (fr)
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王利忠
周天民
胡合合
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京东方科技集团股份有限公司
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Priority to US17/921,322 priority Critical patent/US20230178560A1/en
Publication of WO2021239091A1 publication Critical patent/WO2021239091A1/zh

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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a thin film transistor and a preparation method thereof, an array substrate and a display panel.
  • the present disclosure provides a thin film transistor and a preparation method thereof, an array substrate and a display panel.
  • the present disclosure provides a thin film transistor including:
  • An oxide nanowire extending in a direction perpendicular to the substrate, including a first end surface facing the substrate, a second end surface facing away from the substrate, and connecting the first end surface And the side surface of the second end surface;
  • a gate insulation layer surrounds the side surface of the oxide nanowire and exposes the second end surface;
  • the gate insulation layer has a gate insulation layer side surface surrounding the side surface, And an end surface of the gate insulating layer that is far from the substrate and connected to the side surface of the gate insulating layer;
  • a gate surrounds the side surface of the gate insulation layer and exposes the second end surface;
  • the gate has a gate side surface surrounding the side surface of the gate insulation layer, and is away from the The gate end surface of the substrate and connected to the side surface of the gate;
  • a passivation layer surrounds the gate side surface, the gate end surface and the gate insulating layer end surface, and exposes the second end surface; having a passivation surrounding the gate side surface A side surface of the layer, and an end surface of the passivation layer covering the end surface of the gate electrode and the end surface of the gate insulating layer;
  • a source electrode, the source electrode and the oxide nanowire are located on the same side of the substrate, and the orthographic projection on the substrate and the orthographic projection of the passivation layer on the substrate do not overlap each other, And electrically connected to the first end surface of the oxide nanowire;
  • the drain electrode is located on the second end surface of the oxide nanowire and is in contact with the second end surface.
  • the thickness of the oxide nanowire is greater than or equal to And less than or equal to
  • the maximum width of the oxide nanowire is greater than or equal to 40 nm and less than or equal to 60 nm.
  • the thickness of the oxide nanowire is greater than the width of the oxide nanowire.
  • the thin film transistor further includes: an extension portion that extends on the substrate from a side of the first end surface away from the oxide nanowire;
  • the source electrode is electrically connected to the extension part in contact.
  • the orthographic projection of the gate on the substrate and the orthographic projection of the extension portion on the substrate do not overlap each other.
  • the passivation layer has a hollow that exposes the second end surface, and the drain is electrically connected to the second end surface through the hollow.
  • the orthographic projection of the hollow on the substrate roughly coincides with the orthographic projection of the oxide nanowire on the substrate.
  • the orthographic projection of the drain on the substrate covers the orthographic projection of the hollow on the substrate.
  • the end surface of the gate insulating layer and the end surface of the gate are substantially on the same plane.
  • the end surface of the passivation layer and the second end surface are substantially located on the same plane.
  • the cross-sectional pattern of the oxide nanowire is circular, elliptical, square, rectangular or triangular.
  • the oxide nanowires are crystalline oxide nanowires.
  • the crystalline direction of the oxide nanowire is perpendicular to the substrate.
  • the embodiment of the present disclosure also provides a method for manufacturing a thin film transistor for preparing the thin film transistor provided in the embodiment of the present disclosure, which includes:
  • An oxide film layer is formed on a substrate, and an oxide nanowire extending in a direction perpendicular to the substrate is formed through a patterning process.
  • the oxide film layer includes a first end surface facing the substrate and away from the substrate. A second end surface of the substrate, and a side surface connecting the first end surface and the second end surface;
  • a gate insulating layer is formed on the oxide nanowire, the gate insulating layer has a gate insulating layer side surface surrounding the side surface, and a gate insulating layer that is away from the substrate and connected to the gate insulating layer side surface Gate insulating layer end face;
  • a gate layer is formed on the gate insulating layer, and the gate layer is patterned to form a gate surrounding the side surface of the gate insulating layer and exposing the second end surface.
  • the gate The electrode has a gate side surface surrounding the side surface of the gate insulating layer, and a gate end surface far away from the substrate and connected to the gate side surface;
  • a passivation layer is formed on the gate, and the passivation layer is patterned so as to surround the gate side surface, the gate end surface and the gate insulating layer end surface, and expose all of them In the second end surface, the passivation layer has a side surface of the passivation layer surrounding the side surface of the gate, and an end surface of the passivation layer covering the end surface of the gate and the end surface of the gate insulating layer;
  • a metal layer is formed on the passivation layer and the oxide nanowire, and the metal layer is patterned to form a source electrode that is electrically connected to the first end surface of the oxide nanowire, And a drain electrically connected to the second end surface.
  • the forming an oxide film layer on a substrate and forming an oxide nanowire extending in a direction perpendicular to the substrate through a patterning process specifically includes:
  • the oxide film layer is patterned by exposure and development technology to form oxide nanowires, and the end of the oxide nanowires facing the substrate is formed from the first end facing away from the oxide nanowires.
  • a passivation layer is formed on the gate, and the passivation layer is patterned so that the end of the oxide nanowire away from the substrate is exposed, so that the passivation layer and the passivation layer A portion corresponding to the extension portion forms a through hole to expose the extension portion, and the passivation layer covers the gate.
  • the forming a metal layer on the passivation layer and the oxide nanowire specifically includes:
  • Metal is deposited on the passivation layer and the oxide nanowire, and the metal deposited on the passivation layer and the oxide nanowire is subjected to plasma bombardment during the metal deposition process, so that the The end portion of the oxide nanowire on the side away from the substrate is made conductive, and the extension portion is made conductive.
  • the embodiment of the present disclosure further provides an array substrate, which includes the thin film transistor provided in the embodiment of the present disclosure.
  • the substrate is a flexible substrate.
  • the embodiment of the present disclosure further provides a display panel, which includes the array substrate provided in the embodiment of the present disclosure.
  • 1 to 5 are schematic diagrams of film structure changes during the manufacturing process of a thin film transistor provided by the embodiments of the present disclosure
  • FIG. 6 is a schematic flowchart of a method for manufacturing a thin film transistor according to an embodiment of the disclosure
  • Icon 1-substrate; 2-oxide nanowire; 3-gate insulating layer; 4-gate; 5-passivation layer; 6-source; 7-drain; 21-extension.
  • FIG. 5 is a schematic structural diagram of a thin film transistor provided by an embodiment of the disclosure.
  • the embodiments of the present disclosure provide a thin film transistor including:
  • the oxide nanowires 2, which extend in a direction perpendicular to the substrate 1, include a first end surface 21 facing the substrate 1, a second end surface 22 facing away from the substrate 1, and a connection between the first end surface 21 and the second end surface.
  • the gate insulating layer 3 surrounds the side surface 23 of the oxide nanowire 2 and exposes the second end surface 22; the gate insulating layer 3 has a gate insulating layer side surface 33 surrounding the side surface 23, and is away from the substrate 1 and the end face 32 of the gate insulating layer connected to the side surface 33 of the gate insulating layer;
  • the gate 4 surrounds the gate insulating layer side surface 33, and exposes the second end surface 22; the gate 4 has a gate side surface 43 surrounding the gate insulating layer side surface 33, and is away from the substrate 1 and is in contact with The gate end surface 42 connected to the gate side surface 33;
  • the passivation layer 5 surrounds the gate side surface 43, the gate end surface 42 and the gate insulating layer end surface 32, and exposes the second end surface 22; has a passivation layer side surface 53 surrounding the gate side surface 43, And the passivation layer end surface 52 covering the gate end surface 42 and the gate insulating layer end surface 32;
  • the source electrode 6, the source electrode 6 and the oxide nanowire 2 are located on the same side of the substrate 1, and the orthographic projection on the substrate 1 and the orthographic projection of the passivation layer 5 on the substrate 1 do not overlap each other, and are with the oxide nanowires.
  • the first end surface 21 of the line 2 is electrically connected;
  • the drain 7 and the drain 7 are located on the second end surface 22 of the oxide nanowire 2 and are in contact with the second end surface 22.
  • the thin film transistor in the present disclosure is an oxide thin film transistor, and includes an oxide nanowire 2 disposed on a substrate 1.
  • the oxide nanowire 2 is a crystal and is the active layer of the thin film transistor, and the oxide nanowire 2 It extends along the thickness direction (ie the vertical direction) of the substrate 1 to form a crystalline nanowire.
  • the oxide nanowire 2 is surrounded by a gate insulating layer 3 on the peripheral side, and a gate 4 is provided on the outer peripheral side of the gate insulating layer 3,
  • the gate 4 is arranged around the oxide nanowire 2, and the gate 4 can be arranged all around the oxide nanowire 2, or the gate 4 can be arranged locally on the peripheral side of the oxide nanowire 2.
  • the gate 4 may be provided on the circumference of the nanowire 2 so that the gate 4 can provide a voltage signal to the oxide nanowire 2.
  • a passivation layer 5 is provided on the gate 4, and the passivation layer 5 covers the gate 4, In addition, an opening can be provided at the position corresponding to the top of the oxide nanowire 2 in the passivation layer 5 to expose the top of the oxide nanowire 2, and a source 6 is provided on the side of the circumference of the oxide nanowire 2. It is connected to the end of the oxide nanowire 2 facing the substrate 1, that is, to the bottom of the oxide nanowire 2 to form an electrical connection relationship.
  • a drain 7 is provided on the side of the oxide nanowire 2 away from the substrate 1. The pole 7 is arranged on the top of the oxide nanowire 2 and connected to the oxide nanowire 2 to form an electrical connection relationship.
  • the channel length of the thin film transistor is formed by extending in the direction perpendicular to the substrate 1.
  • the thin film transistor Formed as a vertical TFT the active layer of the above-mentioned thin film transistor is oxide nanowire 2, which can greatly reduce the defect state of the active layer, effectively improve the mobility and stability of the thin film transistor, and when applied to a display panel, The structure size of the thin film transistor can be made smaller, which is conducive to further improving the transmittance of the display panel.
  • the above thin film transistor is a vertical TFT structure, and the active layer of the thin film transistor extends in a direction perpendicular to the substrate 1.
  • the channel length of the above-mentioned thin film transistor extends in the direction perpendicular to the substrate 1
  • the channel layer is less affected, which helps to ensure the stability of the thin film transistor.
  • the active layer of the above-mentioned thin film transistor is an oxide nanowire and extends along the direction perpendicular to the substrate to form a vertical TFT structure, which effectively improves the mobility and stability of the thin film transistor.
  • the structure size effectively improves the transmittance of the display screen.
  • the thickness D of the oxide nanowire 2 is greater than or equal to And less than or equal to That is, the thickness D of the oxide nanowire 2 in the direction perpendicular to the substrate 1 is greater than or equal to And less than or equal to
  • the size of the oxide nanowire 2 in the direction perpendicular to the substrate 1 can be in Choosing a suitable thickness within the range can make the above-mentioned thin film transistor perform better and have a more suitable size.
  • the thickness of the oxide nanowire 2 in the direction perpendicular to the substrate 1 can be set to or The thickness can also be other numerical values, and can be set according to actual needs, and this embodiment is not limited.
  • the shape of the oxide nanowire 2 may be a bar-shaped column, and its length direction is perpendicular to the substrate 1.
  • the clean oxide semiconductor may be a cylinder with a vertical center axis.
  • the oxide nanowires 2 can also be rectangular parallelepiped or other shapes. This embodiment is not limited. In the cross section of the oxide nanowires 2 perpendicular to the substrate 1, the cross section is parallel to the substrate 1.
  • the dimension B in the direction of 1 is greater than or equal to 40 nm or less than or equal to 60 nm, that is, the maximum width of the oxide nanowire 2 is greater than or equal to 40 nm and less than or equal to 60 nm, preferably 45 nm, 48 nm, 50 nm, 52 nm or 55 nm, Or other size values are not limited in this embodiment.
  • the thickness D of the oxide nanowire 2 is greater than the width B of the oxide nanowire 2, that is, the thickness D of the oxide nanowire 2 in the direction perpendicular to the substrate 1 is greater than that of the oxide nanowire 2 in parallel to the substrate 1 The thickness B in the bottom 1 direction.
  • the material of the gate insulating layer may be silicon oxide, and the thickness of the gate insulating layer may be set to
  • the gate 4 may be a laminated structure of copper, molybdenum or copper and molybdenum, and the gate 4 is arranged on the 2nd side of the oxide nanowire and attached to the 2nd side of the oxide nanowire.
  • the thickness dimension C of the gate electrode 4 in the direction parallel to the substrate 1 is Preferably, it can be set to or It can also be other size values, and this embodiment is not limited.
  • the passivation layer may be silicon oxide, silicon nitride, or a stacked structure of silicon oxide and silicon nitride, and the thickness of the passivation layer may be set to
  • the oxide nanowire 2 further includes an extension portion 20, which extends on the substrate 1 from the first end surface 21 to a side away from the oxide nanowire 2
  • the source electrode 6 is electrically connected to the extension portion 20, and the source electrode 6 is provided on the extension portion 20 and is electrically connected to the extension portion 20.
  • the extension portion 20 can be an integral structure with the oxide nanowire 2 and formed in the same manufacturing process , To facilitate the electrical connection between the source electrode 6 and the oxide nanowire 2.
  • the gate 4 is arranged around the oxide nanowire 2 and is surrounded by the outer peripheral side of the gate insulating layer 3, and the gate 4 is completely surrounded on the peripheral side of the oxide nanowire 2.
  • the passivation layer 5 has a hollow 50 exposing the main body portion 20, and the drain 7 is electrically connected to the second end surface 22 of the oxide nanowire 2 through the hollow 50.
  • the orthographic projection of the hollow 50 on the substrate 1 and the orthographic projection of the oxide nanowire 2 on the substrate 1 roughly coincide.
  • the orthographic projection of the drain 7 on the substrate 1 covers the orthographic projection of the hollow 50 on the substrate 1.
  • the end face 32 of the gate insulating layer and the end face 42 of the gate electrode are substantially on the same plane.
  • the end surface 52 of the passivation layer and the second end surface 22 are substantially on the same plane.
  • the cross-sectional pattern of the oxide nanowire 2 is a circle, an ellipse, a square, a rectangle, or a triangle. Specifically, its cross-section can be understood as being parallel to the plane of the substrate 1.
  • the oxide nanowire 2 is a crystalline oxide nanowire. Specifically, the crystalline direction of the oxide nanowire 2 is perpendicular to the substrate 1.
  • an insulating dielectric layer and an ITO layer are formed on the source electrode and the drain electrode, so that the thin film transistor is electrically connected with other devices to perform corresponding functions.
  • the present disclosure also provides a method for manufacturing a thin film transistor for preparing any of the thin film transistors provided in the above technical solutions, including:
  • Step S101 as shown in FIG. 1, an oxide film layer is formed on the substrate 1, and an oxide nanowire 2 extending in a direction perpendicular to the substrate 1 is formed through a patterning process;
  • Step S102 as shown in FIG. 2, a gate insulating layer 3 is formed on the oxide nanowire 2;
  • Step S103 as shown in FIG. 3, a gate 4 layer is formed on the gate insulating layer 3, and the gate 4 layer is patterned to surround the side surface 33 of the gate insulating layer and expose the second end surface 22
  • the gate 4, that is, the gate 4 arranged around the crystalline oxide and located on the outer peripheral side of the gate insulating layer 3 is formed;
  • Step S104 as shown in FIG. 4, a passivation layer 5 is formed on the gate 4, and the passivation layer 5 is patterned, so that the top of the oxide nanowire 2 is exposed, and the passivation layer 5 covers the gate 4 ;
  • Step S105 as shown in FIG. 5, a metal layer is formed on the passivation layer 5 and the oxide nanowire 2, and the metal layer is patterned to form a metal layer located on the side of the oxide nanowire 2 and interacting with the oxide nanowire 2 2
  • a source 6 electrically connected to one end of the substrate 1 and a drain 7 located on the side of the crystalline oxide semiconductor away from the substrate 1 and electrically connected to the oxide nanowire 2.
  • the active layer of the thin film transistor prepared according to the above preparation method is an oxide nanowire and extends along the direction perpendicular to the substrate to form a vertical TFT structure, which effectively improves the mobility and stability of the thin film transistor.
  • the structure size can be reduced, and the transmittance of the display screen can be effectively improved.
  • step S101 a patterning process is performed to form oxide nanowires 2 extending in a direction perpendicular to the substrate 1, which specifically includes: patterning the oxide film layer by exposure and development technology Processing to form an oxide nanowire 2, and an end of the oxide nanowire 2 facing the substrate 1 is formed with an extension portion 20 extending to the peripheral side; and in the subsequent step S104, as shown in FIG.
  • the passivation layer 5 is formed on the electrode 4, and the passivation layer 5 is patterned.
  • the passivation layer 5 is formed on the gate 4, and the passivation layer 5 is patterned to make the oxide nano The top of the line 2 is exposed, so that a portion of the passivation layer 5 corresponding to the extension 20 forms a through hole to expose the extension 20, and the passivation layer 5 covers the gate 4.
  • forming a metal layer on the passivation layer 5 and the oxide nanowire 2 specifically includes: depositing metal on the passivation layer 5 and the oxide nanowire 2, and During the metal deposition process, plasma bombards the metal deposited on the passivation layer 5 and the oxide nanowire 2 to make the end of the oxide nanowire 2 away from the substrate 1 conductive, and to make the extension 20 Conduction; wherein, when the metal used to prepare the source 6 and the drain 7 is deposited, plasma bombardment is performed at the same time, so that the oxide nanowire 2 can be conductive away from the exposed top of the substrate 1 and the extension 20 is made into a conductor, so that a channel is formed between the source 6 and the drain 7 in the oxide nanowire 2.
  • the present disclosure also provides an array substrate, including a thin film transistor as provided in the above embodiment, and the display area of the array substrate is provided with the thin film transistor, and the thin film transistor in the display area is located in each sub-pixel unit, which can effectively Increase the light transmittance of the display area; in addition, the thin film transistor can also be provided in the non-display area of the array substrate, such as the wiring area, which can effectively reduce the frame width and realize a narrow frame design.
  • the substrate of the array substrate may be a flexible substrate, and the above-mentioned array substrate may be used to form a flexible display panel, to ensure the stability of the thin film transistor, to ensure that the flexible display panel displays normally when bent, and to extend the flexibility. The life span of the display panel.
  • the present disclosure also provides a display panel, including any one of the array substrates provided in the above-mentioned embodiments.

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Abstract

本公开涉及显示技术领域，公开了一种薄膜晶体管及其制备方法、阵列基板和显示面板。所述薄膜晶体管，包括: 衬底; 氧化物纳米线，所述氧化物纳米线沿垂直于所述衬底的方向延伸，包括面向所述衬底的第一端面，背离所述衬底的第二端面，以及连接所述第一端面和所述第二端面的侧表面; 栅绝缘层; 栅极; 钝化层; 源极，所述源极与所述氧化物纳米线位于所述衬底的相同侧，且在所述衬底的正投影与所述钝化层在所述衬底的正投影互不重叠，并与所述氧化物纳米线的所述第一端面电连接; 漏极，所述漏极位于所述氧化物纳米线的所述第二端面，与所述第二端面接触。

Description

薄膜晶体管及其制备方法、阵列基板和显示面板
相关申请的交叉引用
本申请要求在2020年05月29日提交中国专利局、申请号为202010471830.8、申请名称为“一种薄膜晶体管及其制备方法、阵列基板和显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及一种薄膜晶体管及其制备方法、阵列基板和显示面板。
背景技术
随着人们对显示效果的要求不断提高，传统的a-Si LCD产品已经满足不了窄边框、高清、高刷新频率的性能要求，相对a-Si薄膜晶体管，氧化物薄膜晶体管具有更高迁移率，满足高端大尺寸TV产品的要求，但是目前高透过滤是制约显示效果进一步提升的关键，因此，如何进一步提高显示屏的透过率、提高显示效果是目前亟需研究解决的问题。
发明内容
本公开提供了一种薄膜晶体管及其制备方法、阵列基板和显示面板。本公开提供一种薄膜晶体管，包括：
衬底；
氧化物纳米线，所述氧化物纳米线沿垂直于所述衬底的方向延伸，包括面向所述衬底的第一端面，背离所述衬底的第二端面，以及连接所述第一端面和所述第二端面的侧表面；
栅绝缘层，所述栅绝缘层包围于所述氧化物纳米线的所述侧表面，并暴露所述第二端面；所述栅绝缘层具有包围所述侧表面的栅极绝缘层侧表面， 以及远离所述衬底且与所述栅极绝缘层侧表面连接的栅绝缘层端面；
栅极，所述栅极包围于所述栅极绝缘层侧表面，并暴露所述第二端面；所述栅极具有包围所述栅极绝缘层侧表面的栅极侧表面，以及远离所述衬底且与所述栅极侧表面连接的栅极端面；
钝化层，所述钝化层包围于所述栅极侧表面，所述栅极端面以及所述栅绝缘层端面，并暴露所述第二端面；具有包围所述栅极侧表面的钝化层侧表面，以及覆盖栅极端面、所述栅绝缘层端面的钝化层端面；
源极，所述源极与所述氧化物纳米线位于所述衬底的相同侧，且在所述衬底的正投影与所述钝化层在所述衬底的正投影互不重叠，并与所述氧化物纳米线的所述第一端面电连接；
漏极，所述漏极位于所述氧化物纳米线的所述第二端面，与所述第二端面接触。
在一种可能的实施方式中，所述氧化物纳米线的厚度为大于或等于
Figure PCTCN2021096622-appb-000001
且小于或等于
Figure PCTCN2021096622-appb-000002
在一种可能的实施方式中，所述氧化物纳米线的最大宽度大于或等于40nm且小于或等于60nm。
在一种可能的实施方式中，所述氧化物纳米线厚度，大于所述氧化物纳米线的宽度。
在一种可能的实施方式中，所述薄膜晶体管还包括：延伸部，所述延伸部由所述第一端面向远离所述氧化物纳米线的一侧在所述衬底上延伸；所述源极与所述延伸部接触电连接。
在一种可能的实施方式中，所述栅极在所述衬底的正投影与所述延伸部在所述衬底的正投影互不重叠。
在一种可能的实施方式中，所述钝化层具有暴露所述第二端面的镂空，所述漏极通过所述镂空与第二端面接触电连接。
在一种可能的实施方式中，所述镂空在所述衬底的正投影与所述氧化物纳米线在所述衬底的正投影大致重合。
在一种可能的实施方式中，所述漏极在所述衬底的正投影覆盖所述镂空在所述衬底的正投影。
在一种可能的实施方式中，所述栅绝缘层端面与所述栅极端面大致位于同一平面。
在一种可能的实施方式中，所述钝化层端面与所述第二端面大致位于同一平面。
在一种可能的实施方式中，所述氧化物纳米线的截面图案为圆形、椭圆形、正方形、长方形或三角形。
在一种可能的实施方式中，所述氧化物纳米线为结晶氧化物纳米线。
在一种可能的实施方式中，所述氧化物纳米线的结晶方向与所述衬底垂直。
本公开实施例还提供一种薄膜晶体管的制备方法，用于制备如本公开实施例提供的所述薄膜晶体管，其中，包括：
在衬底上形成氧化物膜层，并通过图案化处理形成沿垂直于所述衬底的方向延伸的氧化物纳米线，所述氧化物膜层包括面向所述衬底的第一端面，背离所述衬底的第二端面，以及连接所述第一端面和所述第二端面的侧表面；
在所述氧化物纳米线上形成栅绝缘层，所述栅绝缘层具有包围所述侧表面的栅极绝缘层侧表面，以及远离所述衬底且与所述栅极绝缘层侧表面连接的栅绝缘层端面；
在所述栅绝缘层上形成栅极层，并对所述栅极层进行图案化处理，以形成包围于所栅极绝缘层侧表面，并暴露所述第二端面的栅极，所述栅极具有包围所述栅极绝缘层侧表面的栅极侧表面，以及远离所述衬底且与所述栅极侧表面连接的栅极端面；
在所述栅极上形成钝化层，并对所述钝化层进行图案化处理，以使包围于所述栅极侧表面，所述栅极端面以及所述栅绝缘层端面，并暴露所述第二端面，所述钝化层具有包围所述栅极侧表面的钝化层侧表面，以及覆盖栅极端面、所述栅绝缘层端面的钝化层端面；
在所述钝化层和所述氧化物纳米线上形成金属层，并对所述金属层进行图案化处理，以形成与所述氧化物纳米线的所述第一端面电连接的源极、以及与所述第二端面电连接的漏极。
在一种可能的实施方式中，所述在衬底上形成氧化物膜层，并通过图案化处理形成沿垂直于所述衬底的方向延伸的氧化物纳米线，具体包括：
采用曝光显影技术对所述氧化物膜层进行图案化处理，形成氧化物纳米线，且所述氧化物纳米线朝向所述衬底的一端形成由所述第一端面向远离所述氧化物纳米线的一侧在所述衬底上延伸的延伸部；
在所述栅极上形成钝化层，并且对所述钝化层进行图案化处理，以使所述氧化物纳米线远离所述衬底的一端裸露，使所述钝化层中与所述延伸部对应的部位形成通孔裸露所述延伸部，且所述钝化层覆盖所述栅极。
在一种可能的实施方式中，所述在所述钝化层和所述氧化物纳米线上形成金属层，具体包括：
在所述钝化层和所述氧化物纳米线上沉积金属，且在金属的沉积过程中对沉积在所述钝化层和所述氧化物纳米线上的金属进行等离子体轰击，以使所述氧化物纳米线远离所述衬底一侧的端部导体化，以及使所述延伸部导体化。
本公开实施例还提供一种阵列基板，其中，包括如本公开实施例提供的所述薄膜晶体管。
在一种可能的实施方式中，所述衬底为柔性衬底。
本公开实施例还提供一种显示面板，其中，包括如本公开实施例提供的所述阵列基板。
附图说明
图1至图5为本公开实施例提供的一种薄膜晶体管的制备过程中膜层结构变化示意图；
图6为本公开实施例提供的一种薄膜晶体管的制备方法的流程示意图；
图标：1-衬底；2-氧化物纳米线；3-栅绝缘层；4-栅极；5-钝化层；6-源极；7-漏极；21-延伸部。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
如图5所示，图5为本公开实施例提供的一种薄膜晶体管的结构示意图。本公开实施例提供了一种薄膜晶体管，包括：
衬底1；
氧化物纳米线2，氧化物纳米线2沿垂直于衬底1的方向延伸，包括面向衬底1的第一端面21，背离衬底1的第二端面22，以及连接第一端面21和第二端面22的侧表面23；
栅绝缘层3，栅绝缘层3包围于氧化物纳米线2的侧表面23，并暴露第二端面22；栅绝缘层3具有包围侧表面23的栅极绝缘层侧表面33，以及远离衬底1且与栅极绝缘层侧表面33连接的栅绝缘层端面32；
栅极4，栅极4包围于栅极绝缘层侧表面33，并暴露第二端面22；栅极4具有包围栅极绝缘层侧表面33的栅极侧表面43，以及远离衬底1且与栅极侧表面33连接的栅极端面42；
钝化层5，钝化层5包围于栅极侧表面43，栅极端面42以及栅绝缘层端面32，并暴露第二端面22；具有包围栅极侧表面43的钝化层侧表面53，以及覆盖栅极端面42、栅绝缘层端面32的钝化层端面52；
源极6，源极6与氧化物纳米线2位于衬底1的相同侧，且在衬底1的正投影与钝化层5在衬底1的正投影互不重叠，并与氧化物纳米线2的第一端面21电连接；
漏极7，漏极7位于氧化物纳米线2的第二端面22，与第二端面22接触。
上述薄膜晶体管中，为便于说明，以垂直于衬底1的方向为竖直方向，以平行于所述衬底1表面的方向为水平方向。本公开中的薄膜晶体管为氧化物薄膜晶体管，包括设置在衬底1上的氧化物纳米线2，该氧化物纳米线2为晶体，是薄膜晶体管的有源层，且该氧化物纳米线2沿衬底1的厚度方向(即竖直方向)延伸设置，形成结晶纳米线，该氧化物纳米线2周侧包围有栅绝缘层3，在栅绝缘层3的外周侧设置有栅极4，栅极4绕氧化物纳米线2设置，且，氧化物纳米线2的周围可以全部设置有栅极4，也可以在氧化物纳米线2的周侧的局部设置栅极4，只要在氧化物纳米线2的周侧设置有栅极4即可，以便于栅极4提供电压信号给氧化物纳米线2，在栅极4上设置有钝化层5，钝化层5覆盖栅极4，且可以在钝化层5与氧化物纳米线2顶部对应的部位设置开孔裸露出氧化物纳米线2的顶部，在氧化物纳米线2的周侧的一侧设置源极6，源极6与氧化物纳米线2朝向衬底1的一端连接，也就是与氧化物纳米线2的底部连接，形成电连接关系，在氧化物纳米线2远离衬底1的一侧设置漏极7，漏极7设置在氧化物纳米线2的顶部与氧化物纳米线2连接，形成电连接关系，则也就是上述薄膜晶体管的沟道长度是沿垂直于衬底1的方向延伸形成的，上述薄膜晶体管形成为垂直TFT，上述薄膜晶体管中有源层为氧化物纳米线2，可以使有源层缺陷态大幅度降低，有效提升薄膜晶体管的迁移率和稳定性，进而在应用于显示面板中时，可以将薄膜晶体管的结构尺寸做的更小，有利于进一步提高显示面板的透过率，且上述薄膜晶体管为一垂直TFT结构，薄膜晶体管的有源层沿垂直于衬底1的方向延伸布置，可以在柔性屏、弯曲屏或折叠屏的设计应用中有效避免有源层在衬底1水平方向太长导致折叠断裂的现象，且上述薄膜晶体管的沟道长度沿垂直于衬底1的方向延伸，当显示屏弯折时，沟道层受影响较小，有利于保证薄膜晶体管的稳定性。
因此，上述薄膜晶体管的有源层为氧化物纳米线且沿垂直于衬底方向延伸设置，形成垂直TFT结构，有效提高了薄膜晶体管的迁移率和稳定性，应用于显示屏时，可以减小结构尺寸，有效提升显示屏的透过率。
具体地，如图1所示，上述薄膜晶体管中，氧化物纳米线2的厚度D为大于或等于
Figure PCTCN2021096622-appb-000003
且小于或等于
Figure PCTCN2021096622-appb-000004
即，氧化物纳米线2沿垂直于衬底1的方向上的厚度D为大于或等于
Figure PCTCN2021096622-appb-000005
且小于或等于
Figure PCTCN2021096622-appb-000006
氧化物纳米线2在垂直于衬底1的方向的尺寸可以在
Figure PCTCN2021096622-appb-000007
范围内选择合适的厚度，可以使上述薄膜晶体管性能更好，且尺寸更合适，优选地，可以设置氧化物纳米线2在垂直衬底1的方向的厚度为
Figure PCTCN2021096622-appb-000008
Figure PCTCN2021096622-appb-000009
或者
Figure PCTCN2021096622-appb-000010
也可以其它数值厚度，可以根据实际需求进行设置，本实施例不做局限。
如图1所示，上述薄膜晶体管中，氧化物纳米线2的形状可以为条形柱体，其长度方向垂直于衬底1，具体地，洁净氧化物半导体可以为圆柱体型，其中心轴线垂直于衬底1，氧化物纳米线2也可以是长方体型，或者其它形状，本实施例不做局限，且上述氧化物纳米线2的垂直于衬底1的截面中，截面沿平行于衬底1的方向的尺寸B为大于或等于40nm或小于等于60nm，即，氧化物纳米线2的最大宽度大于或等于40nm且小于或等于60nm，优选地可以为45nm、48nm、50nm、52nm或者55nm，或者其它尺寸数值，本实施例不做局限。
具体地，氧化物纳米线2厚度D，大于氧化物纳米线2的宽度B，即，氧化物纳米线2在垂直于衬底1方向上的厚度D，大于氧化物纳米线2在平行于衬底1方向上的厚度B。
具体地，栅绝缘层的材料可以为氧化硅，且栅绝缘层的厚度可以设置为
Figure PCTCN2021096622-appb-000011
具体地，如图3所示，栅极4可以为铜、钼或者铜与钼的叠层结构，且栅极4设置在氧化物纳米线2周侧，贴附在氧化物纳米线2周侧的栅绝缘层3外表面，栅极4在平行于衬底1的方向的厚度尺寸C为
Figure PCTCN2021096622-appb-000012
优选地，可以设置为
Figure PCTCN2021096622-appb-000013
或者
Figure PCTCN2021096622-appb-000014
也可以为其它尺寸数值，本实施例不做局限。
其中，钝化层可以为氧化硅、氮化硅或者氧化硅和氮化硅的叠层结构， 且钝化层的厚度可以设置为
Figure PCTCN2021096622-appb-000015
具体地，如图5所示，上述薄膜晶体管中，氧化物纳米线2还包括：延伸部20，延伸部20由第一端面21向远离氧化物纳米线2的一侧在衬底1上延伸；源极6与延伸部20接触电连接，源极6设于延伸部20上并与延伸部20电连接，延伸部20可以与氧化物纳米线2为一体式结构，在同一制备工艺中形成，便于源极6与氧化物纳米线2电连接。
具体地，如图3所示，上述薄膜晶体管中，栅极4绕氧化物纳米线2设置且包围于栅绝缘层3外周侧，栅极4完全包围在氧化物纳米线2的周侧，可以更好的给有源层施加电信号，有利于提高薄膜晶体管的灵敏性。
具体地，结合图5所示，钝化层5具有暴露主体部20的镂空50，漏极7通过镂空50与氧化物纳米线2的第二端面22接触电连接。具体地，镂空50在衬底1的正投影与氧化物纳米线2在衬底1的正投影大致重合。
具体地，结合图5所示，漏极7在衬底1的正投影覆盖镂空50在衬底1的正投影。
具体地，结合图5所示，栅绝缘层端面32与栅极端面42大致位于同一平面。
具体地，结合图5所示，钝化层端面52与第二端面22大致位于同一平面。
具体地，结合图5所示，氧化物纳米线2的截面图案为圆形、椭圆形、正方形、长方形或三角形。具体的，其截面可以理解为平行于衬底1的平面。
具体地，氧化物纳米线2为结晶氧化物纳米线。具体地，氧化物纳米线2的结晶方向与衬底1垂直。
具体地，在源极、漏极之上形成有绝缘介质层，以及ITO层，以使薄膜晶体管与其它器件电连接完成相应的功能。
基于相同的公开构思，结合图6，如图1至图5所示，本公开还提供了一种薄膜晶体管的制备方法，用于制备如上述技术方案提供的任意一种薄膜晶体管，包括：
步骤S101，如图1所示，在衬底1上形成氧化物膜层，并通过图案化处理形成沿垂直于衬底1的方向延伸的氧化物纳米线2；
步骤S102，如图2所示，在氧化物纳米线2上形成栅绝缘层3；
步骤S103，如图3所示，在栅绝缘层3上形成栅极4层，并对栅极4层进行图案化处理，以包围于栅极绝缘层侧表面33，并暴露第二端面22的栅极4，即，形成绕结晶氧化物设置且位于栅绝缘层3的外周侧的栅极4；
步骤S104，如图4所示，在栅极4上形成钝化层5，并对钝化层5进行图案化处理，以使氧化物纳米线2顶部裸露，且钝化层5覆盖栅极4；
步骤S105，如图5所示，在钝化层5和氧化物纳米线2上形成金属层，并对金属层进行图案化处理，以形成位于氧化物纳米线2一侧且与氧化物纳米线2朝向衬底1的一端电连接的源极6、以及位于结晶氧化物半导远离衬底1一侧且与氧化物纳米线2电连接的漏极7。
依据上述制备方法制备的薄膜晶体管的有源层为氧化物纳米线且沿垂直于衬底方向延伸设置，形成垂直TFT结构，有效提高了薄膜晶体管的迁移率和稳定性，应用于显示屏时，可以减小结构尺寸，有效提升显示屏的透过率。
具体地，在步骤S101中，如图1所示，通过图案化处理形成沿垂直于衬底1的方向延伸的氧化物纳米线2，具体包括：采用曝光显影技术对氧化物膜层进行图案化处理，形成氧化物纳米线2，且氧化物纳米线2朝向衬底1的一端形成有向周侧的一侧延伸的延伸部20；并且在后续步骤S104中，如图4所示，在栅极4上形成钝化层5，并对钝化层5进行图案化处理，具体包括：在栅极4上形成钝化层5，并且对钝化层5进行图案化处理，以使氧化物纳米线2顶部裸露，使钝化层5中与延伸部20对应的部位形成通孔裸露延伸部20，且钝化层5覆盖栅极4。
具体地，在步骤S105中，如图5所示，在钝化层5和氧化物纳米线2上形成金属层，具体包括：在钝化层5和氧化物纳米线2上沉积金属，且在金属的沉积过程中对沉积在钝化层5和氧化物纳米线2上的金属进行等离子体轰击，以使氧化物纳米线2远离衬底1一侧的端部导体化，以及使延伸部20 导体化；其中，在用于制备源极6、漏极7的金属进行沉积时，同时进行等离子体轰击，可以使氧化物纳米线2远离衬底1的裸露的顶部导体化，且使延伸部20导体化，使氧化物纳米线2中在位于源极6和漏极7之间的部位形成沟道。
本公开还提供了一种阵列基板，包括如上述实施例提供的一种薄膜晶体管，且阵列基板的显示区域设置有该薄膜晶体管，且显示区域内的薄膜晶体管位于各子像素单元内，可以有效增加显示区域的光透过率；另外，在阵列基板的非显示区域，如布线区，也可以设置有该薄膜晶体管，可以有效减少边框宽度，实现窄边框设计。
具体地，上述阵列基板中，阵列基板的衬底可以为柔性衬底，则上述阵列基板可以用于形成柔性显示面板，保证薄膜晶体管的稳定性，保证柔性显示面板在弯曲时正常显示，延长柔性显示面板的使用寿命。
本公开还提供了一种显示面板，包括如上述实施例提供的任意一种阵列基板。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (20)

  1. 一种薄膜晶体管，其中，包括：
    衬底；
    氧化物纳米线，所述氧化物纳米线沿垂直于所述衬底的方向延伸，包括面向所述衬底的第一端面，背离所述衬底的第二端面，以及连接所述第一端面和所述第二端面的侧表面；
    栅绝缘层，所述栅绝缘层包围于所述氧化物纳米线的所述侧表面，并暴露所述第二端面；所述栅绝缘层具有包围所述侧表面的栅极绝缘层侧表面，以及远离所述衬底且与所述栅极绝缘层侧表面连接的栅绝缘层端面；
    栅极，所述栅极包围于所述栅极绝缘层侧表面，并暴露所述第二端面；所述栅极具有包围所述栅极绝缘层侧表面的栅极侧表面，以及远离所述衬底且与所述栅极侧表面连接的栅极端面；
    钝化层，所述钝化层包围于所述栅极侧表面，所述栅极端面以及所述栅绝缘层端面，并暴露所述第二端面；具有包围所述栅极侧表面的钝化层侧表面，以及覆盖栅极端面、所述栅绝缘层端面的钝化层端面；
    源极，所述源极与所述氧化物纳米线位于所述衬底的相同侧，且在所述衬底的正投影与所述钝化层在所述衬底的正投影互不重叠，并与所述氧化物纳米线的所述第一端面电连接；
    漏极，所述漏极位于所述氧化物纳米线的所述第二端面，与所述第二端面接触。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述氧化物纳米线的厚度为大于或等于
    Figure PCTCN2021096622-appb-100001
    且小于或等于
    Figure PCTCN2021096622-appb-100002
  3. 根据权利要求1所述的薄膜晶体管，其中，所述氧化物纳米线的最大宽度大于或等于40nm且小于或等于60nm。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述氧化物纳米线厚度，大于所述氧化物纳米线的宽度。
  5. 根据权利要求1所述的薄膜晶体管，其中，所述薄膜晶体管还包括：延伸部，所述延伸部由所述第一端面向远离所述氧化物纳米线的一侧在所述衬底上延伸；所述源极与所述延伸部接触电连接。
  6. 根据权利要求5所述的薄膜晶体管，其中，所述栅极在所述衬底的正投影与所述延伸部在所述衬底的正投影互不重叠。
  7. 根据权利要求1所述的薄膜晶体管，其中，所述钝化层具有暴露所述第二端面的镂空，所述漏极通过所述镂空与第二端面接触电连接。
  8. 根据权利要求7所述的薄膜晶体管，其中，所述镂空在所述衬底的正投影与所述氧化物纳米线在所述衬底的正投影大致重合。
  9. 根据权利要求8所述的薄膜晶体管，其中，所述漏极在所述衬底的正投影覆盖所述镂空在所述衬底的正投影。
  10. 根据权利要求1所述的薄膜晶体管，其中，所述栅绝缘层端面与所述栅极端面大致位于同一平面。
  11. 根据权利要求10所述的薄膜晶体管，其中，所述钝化层端面与所述第二端面大致位于同一平面。
  12. 根据权利要求1所述的薄膜晶体管，其中，所述氧化物纳米线的截面图案为圆形、椭圆形、正方形、长方形或三角形。
  13. 根据权利要求1所述的薄膜晶体管，其中，所述氧化物纳米线为结晶氧化物纳米线。
  14. 根据权利要求13所述的薄膜晶体管，其中，所述氧化物纳米线的结晶方向与所述衬底垂直。
  15. 一种薄膜晶体管的制备方法，用于制备如权利要求1-14任一项所述的薄膜晶体管，其中，包括：
    在衬底上形成氧化物膜层，并通过图案化处理形成沿垂直于所述衬底的方向延伸的氧化物纳米线，所述氧化物膜层包括面向所述衬底的第一端面，背离所述衬底的第二端面，以及连接所述第一端面和所述第二端面的侧表面；
    在所述氧化物纳米线上形成栅绝缘层，所述栅绝缘层具有包围所述侧表 面的栅极绝缘层侧表面，以及远离所述衬底且与所述栅极绝缘层侧表面连接的栅绝缘层端面；
    在所述栅绝缘层上形成栅极层，并对所述栅极层进行图案化处理，以形成包围于所述栅极绝缘层侧表面，并暴露所述第二端面的栅极，所述栅极具有包围所述栅极绝缘层侧表面的栅极侧表面，以及远离所述衬底且与所述栅极侧表面连接的栅极端面；
    在所述栅极上形成钝化层，并对所述钝化层进行图案化处理，以使包围于所述栅极侧表面，所述栅极端面以及所述栅绝缘层端面，并暴露所述第二端面，所述钝化层具有包围所述栅极侧表面的钝化层侧表面，以及覆盖栅极端面、所述栅绝缘层端面的钝化层端面；
    在所述钝化层和所述氧化物纳米线上形成金属层，并对所述金属层进行图案化处理，以形成与所述氧化物纳米线的所述第一端面电连接的源极、以及与所述第二端面电连接的漏极。
  16. 根据权利要求15所述的制备方法，其中，所述在衬底上形成氧化物膜层，并通过图案化处理形成沿垂直于所述衬底的方向延伸的氧化物纳米线，具体包括：
    采用曝光显影技术对所述氧化物膜层进行图案化处理，形成氧化物纳米线，且所述氧化物纳米线朝向所述衬底的一端形成由所述第一端面向远离所述氧化物纳米线的一侧在所述衬底上延伸的延伸部；
    在所述栅极上形成钝化层，并且对所述钝化层进行图案化处理，以使所述氧化物纳米线远离所述衬底的一端裸露，使所述钝化层中与所述延伸部对应的部位形成通孔裸露所述延伸部，且所述钝化层覆盖所述栅极。
  17. 根据权利要求15所述的制备方法，其中，所述在所述钝化层和所述氧化物纳米线上形成金属层，具体包括：
    在所述钝化层和所述氧化物纳米线上沉积金属，且在金属的沉积过程中对沉积在所述钝化层和所述氧化物纳米线上的金属进行等离子体轰击，以使所述氧化物纳米线远离所述衬底一侧的端部导体化，以及使所述延伸部导体 化。
  18. 一种阵列基板，其中，包括如权利要求1-14任一项所述的薄膜晶体管。
  19. 根据权利要求18所述的阵列基板，其中，所述衬底为柔性衬底。
  20. 一种显示面板，其中，包括如权利要求18或19所述的阵列基板。
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CN115220274B (zh) * 2022-07-27 2023-10-03 京东方科技集团股份有限公司 显示背板及其制备方法、显示装置

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