WO2020140782A1 - 模数转换器及其时钟产生电路 - Google Patents

模数转换器及其时钟产生电路 Download PDF

Info

Publication number
WO2020140782A1
WO2020140782A1 PCT/CN2019/127385 CN2019127385W WO2020140782A1 WO 2020140782 A1 WO2020140782 A1 WO 2020140782A1 CN 2019127385 W CN2019127385 W CN 2019127385W WO 2020140782 A1 WO2020140782 A1 WO 2020140782A1
Authority
WO
WIPO (PCT)
Prior art keywords
module
clock
delay
stage
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/127385
Other languages
English (en)
French (fr)
Inventor
李琛
王浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSMC Technologies Fab2 Co Ltd
Original Assignee
CSMC Technologies Fab2 Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSMC Technologies Fab2 Co Ltd filed Critical CSMC Technologies Fab2 Co Ltd
Priority to US17/419,548 priority Critical patent/US11711088B2/en
Publication of WO2020140782A1 publication Critical patent/WO2020140782A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the technical field of microelectronics, in particular to an analog-to-digital converter and its clock generation circuit.
  • Successive approximation analog-to-digital converters occupy most of the market for medium-to-high-resolution analog-to-digital converters.
  • the successive approximation analog-to-digital converter is a binary search algorithm.
  • the N-bit successive approximation analog-to-digital converter requires N+2 or N+3 comparison cycles, and the next conversion must not be entered before the conversion of the previous bit is completed. Due to the successive approximation algorithm, the actual working clock of the successive approximation ADC is much larger than its sampling rate.
  • the successive approximation analog-to-digital converter needs to provide a high-speed and high-precision clock signal in high-speed applications.
  • the clock speed exceeds the 100-megabit level, the complex clock circuit will have a greater impact on the system and increase the system power consumption. .
  • a clock generation circuit includes a cascaded clock generation module.
  • the clock generation module of each stage is used to generate a corresponding internal clock signal.
  • the clock generation module of each stage includes a delay module and a logic gate module;
  • the output terminal of the Nth stage delay module is connected to the input terminal of the N+1th stage delay module, wherein the input terminal of the first stage delay module is used to input an external clock signal, and the frequency of the external clock signal is lower than the internal clock The frequency of the signal;
  • Each of the logic gate modules includes a first input terminal, a second input terminal, and an output terminal.
  • the first input terminal of the Nth-level logic gate module is connected to the output terminal of the Nth-level delay module, and the Nth-level logic
  • the second input terminal of the gate module is connected to the output terminal of the logic gate module of level N-1, and the output terminal of the logic gate module of level N is used to output the Nth internal clock signal, where N is greater than or equal to 2;
  • the first input terminal of the first-stage logic gate module is used to input the external clock signal, and the second input terminal is connected to the output terminal of the first-stage delay module.
  • An analog-to-digital converter includes the aforementioned clock generation circuit.
  • the above clock generation circuit can be applied to an analog-to-digital converter or other electronic circuits. Since the frequency of the external clock signal is lower than the frequency of the internal clock signal, the external low-frequency clock signal can be converted into an internal high-frequency clock signal. When the user needs to use a high-frequency clock signal, there is no need to generate a high-frequency signal externally, and only a low-frequency clock signal needs to be connected externally. After being processed by the clock generation circuit of this application, multiple internal high-frequency clock signals are obtained, which reduces the Application difficulty and system complexity. This application uses the logic gate module to cooperate with the delay module.
  • the first-level clock generation module can generate an internal clock signal
  • the internal clock N can be calculated from the internal clock N-1 and the delay time of the delay module in the current-level clock generation module.
  • 2-N One internal clock signal, the user can choose one of the clocks for the analog-to-digital converter according to the demand, the principle is simple, the circuit structure is simple and easy to implement, the system power consumption is reduced, and the analog-to-digital converter will not be generated after being applied to the analog-to-digital converter influences.
  • FIG. 1 is a schematic diagram of a clock generation circuit module provided by an embodiment of this application.
  • FIG. 2 is a schematic diagram of a clock generation circuit module provided by another embodiment of this application.
  • FIG. 3 is a schematic structural diagram of a delay unit provided by an embodiment of this application.
  • FIG. 4 is a timing diagram generated by a clock generation circuit provided by an embodiment of the present application.
  • successive approximation analog-to-digital converters are common structures for medium to high resolution applications with sampling rates below 5Msps.
  • the sampling rate is higher than 5Msps
  • the clock is too high
  • the approximation register type of the conventional structure is difficult to meet the requirements.
  • a combination of other structures is used to implement the high-speed successive approximation type analog-to-digital converter.
  • the mainstream practices in the industry are: 1. Built-in high-performance phase-locked loop to provide high-precision clock, but the performance of the phase-locked loop will seriously affect the characteristics of the analog-to-digital converter. In addition, the phase-locked loop will significantly increase the chip area and power. Consume. 2.
  • a pipelined successive approximation analog-to-digital converter is used.
  • the analog-to-digital converter of this structure is composed of multiple sub-analog-to-digital converters, which can significantly improve the conversion speed of the successive approximation register, but the circuit complexity is also obvious increase.
  • Adopt parallel operation successive approximation type analog-to-digital converter. Multiple analog-to-digital converters work in parallel. Different phase clocks are allocated to different registers through auxiliary circuits such as phase-locked loops. Multiple registers collect conversion data at different phases according to this theory. On the other hand, the conversion rate of the analog-to-digital converter can be greatly improved, but in practical applications, there are factors such as offset and gain error between the registers of different channels, which will seriously restrict the performance of the analog-to-digital converter.
  • an embodiment of the present application provides a clock generation circuit.
  • the clock generation circuit includes a plurality of cascaded clock generation modules 100, and each stage of the clock generation module 100 is used to generate an internal clock signal.
  • Each level of clock generation module 100 includes a delay module 110 and a logic gate module 120.
  • the delay module 110 includes multiple stages. As shown in FIG. 1, the first stage delay module is a delay module 1, the second pole delay module is a delay module 2, the Nth pole delay module is a delay module N, and so on.
  • the delay modules 110 of each stage are cascaded with each other, and the output terminal of the delay module N is connected to the input terminal of the delay module N+1.
  • the input terminal of the delay module 1 is used to input an external clock signal. By controlling the delay time of the delay module 110, the clock period of the output internal clock signal can be controlled.
  • the multi-level logic gate modules 120 are cascaded with each other, and each level of the logic gate module 120 is connected to the corresponding delay module 110.
  • the first-level logic gate module is logic gate module 1
  • the second-pole logic gate module is logic gate module 2
  • the N-th logic gate module is logic gate module N, and so on.
  • Each logic gate module 120 includes a first input terminal, a second input terminal, and an output terminal.
  • the first input terminal of the logic gate module N is connected to the output terminal of the delay module N
  • the second input terminal of the logic gate module N is connected to the output terminal of the logic gate module N-1
  • the output terminal of the logic gate module N is used to output the Nth Internal clock signal, where N is greater than or equal to 2.
  • the first input terminal of the logic gate module 1 is used to input an external clock signal
  • the second input terminal is connected to the output terminal of the delay module 1.
  • the frequency of the external clock signal is lower than the frequency of the internal clock signal.
  • the clock generation circuit provided in this embodiment can convert an external low-frequency clock signal into an internal high-frequency clock signal.
  • the user needs to use a high-frequency clock signal, there is no need to generate a high-frequency signal externally, and only a low-frequency clock signal needs to be connected externally.
  • multiple internal high-frequency clock signals are obtained, which reduces the Application difficulty and system complexity.
  • each stage clock generation module 100 can generate an internal clock signal.
  • the first stage clock generation module is used to generate the internal clock I
  • the second stage clock generation module is used to generate the internal clock II
  • the Nth stage clock generation module is used to generate the internal clock N.
  • the internal clock N is calculated from the internal clock N-1 and the delay time of the delay module 110 in the clock generation module 100 of the current stage.
  • an external clock signal can be used to generate 2-N internal clock signals.
  • the user can select one of the clocks for the analog-to-digital converter according to the needs.
  • the principle is simple and the circuit structure It is simple and easy to implement and reduces system power consumption. It will not affect the electronic circuit when it is used in analog-to-digital converters or other electronic circuits.
  • the user can also adjust the cycle length of the output clock signal by adjusting the delay time of the delay module, which is convenient for adjustment.
  • the delay module 110 includes multiple delay units 111.
  • the output terminal of the delay unit 111 is connected to the input terminal of the next delay unit 111.
  • the clock generation circuit provided in this embodiment includes 2N-1 delay units, wherein the delay module 1 includes a delay unit 111, and the delay module 2 to the delay module N each include 2 delay units, that is, the delay module 1 includes the first delay Unit, the delay module N includes the 2N-2th delay unit and the 2N-1th delay unit, and N is greater than or equal to 2.
  • each delay unit 111 is used to control the clock cycle of the generated internal clock signal.
  • each delay unit 111 includes at least one inverter 112, and the inverters 112 of a plurality of delay units 111 are cascaded with each other. The user can adjust the corresponding number by adjusting the number of the inverters 112. The delay time of the delay unit 110.
  • each delay unit 110 further includes at least one adjustable capacitor 113.
  • One end of the adjustable capacitor 113 is connected to the output end of the inverter 112, and the other end is grounded.
  • the user can adjust the delay time of the corresponding delay unit 110 by adjusting the capacity of the adjustable capacitor 113.
  • the user can adjust the number of the inverter 112 alone, the capacity of the capacitor 113 alone, or both to adjust the delay time of the delay unit 110.
  • the pulse width of the internal clock signal generated by each clock generation module 100 depends on the delay time of the delay unit 110, and the delay time of each delay unit 110 can be adjusted by adjusting the number of inverters 112 or the adjustable capacitor 113 The capacity is adjusted, so the pulse width of each stage of the internal clock generated by the clock generation circuit provided in this embodiment can be adjusted. Furthermore, the user can adjust the pulse width of each stage to the same according to the demand to generate a synchronized clock. Or the user can adjust the pulse width of each stage to make it different according to the demand to generate asynchronous clock.
  • the clock generation circuit includes a multi-level logic gate module 120, the logic gate module 1 includes an XOR gate 121, and the logic gate module 2 to the logic gate module N include an XOR gate 121 and an OR gate 122.
  • the XOR gate 121 includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the first XOR gate 121 is connected to the input terminal of the first delay unit 111, and the second input terminal is connected to the first The output terminal of each delay unit 111, the output terminal of the first XOR gate 121 is used to output the first internal clock signal.
  • the logic gate module N includes an Nth XOR gate 121 and an N-1 OR gate 122, wherein the output terminal of the N-1 OR gate 122 is the output terminal of the logic module N, which is used to output the Nth gate Internal clock signal.
  • the first input terminal of the Nth XOR gate 121 is connected to the output terminal of the 2N-2th delay unit 111, and the second input terminal is connected to the output terminal of the 2N-1th delay unit 111.
  • the first input terminal of the N-th OR gate 122 is connected to the output terminal of the N-th XOR gate 121, and the second input terminal is connected to the output terminal of the previous-stage logic module 120, where N is greater than or equal to 2.
  • the input terminal of the first delay unit 1 is used to receive an external clock signal. If the external clock signal is a high-level signal, it is processed by the first delay unit 1 to output a low-level signal.
  • the external clock signal and the processed The low level signal of enters the first XOR gate 1, after the operation of the first XOR gate 1, the high level of the internal clock I can be obtained, whose pulse width is equal to the delay time of the first delay unit 1, and The low time of the internal height clock I depends on the delay time of the second delay unit 2.
  • the low-level signal After the first delay unit 1 outputs a low-level signal, the low-level signal enters the second delay unit 2 in the second clock generation module, and the second delay unit 2 processes the low-level signal and outputs a high power
  • the flat signal is transmitted to the first input terminal of the second XOR gate 2 and the high-level signal is transmitted to the third delay unit 3.
  • the third delay unit 3 processes the high-level signal and outputs a low-level signal To the second input terminal of the second XOR gate 2, the second XOR gate 2 outputs a high level.
  • the width depends on the delay time of the third delay unit 3
  • the low-level signal pulse width of the internal clock II depends on the delay time of the fourth delay unit 4, the previous clock cycle of the internal clock II and the clock of the internal high-speed clock I The cycle is the same.
  • Fig. 4 is an internal clock timing diagram.
  • the first N-1 clock cycles of the internal clock N are the same as the internal clock N-1.
  • the N-th clock high-level pulse width of the internal clock N depends on the delay time of the 2N-1th delay unit.
  • the clock cycles of the internal 2-N clocks plus their corresponding redundancy time are equal to 1 external clock cycle.
  • the analog-to-digital converter needs a start signal before sampling, the sample conversion can be performed.
  • the first high-speed clock signal can also be used as the start signal of the analog-to-digital converter. Therefore, the clock circuit can generate not only the internal clock signal but also the start signal, which simplifies the circuit module of the analog-to-digital converter.
  • the clock generation circuit further includes a trigger module 130, the input terminal of the trigger module 130 is used to input an external clock signal, and the output terminal is respectively connected to the input terminal of the first delay unit 1 and the first The first input of XOR gate 1.
  • the trigger module may be a T flip-flop, and the T flip-flop may divide the external clock signal to eliminate unnecessary falling or rising edges.
  • An embodiment of the present application provides an analog-to-digital converter, including the aforementioned clock generation circuit.
  • the clock generation circuit of the analog-to-digital converter uses an external clock signal to generate 2-N internal clock signals through the operation of the logic gate module and the delay module.
  • the user can select one of the clocks for the analog-to-digital converter according to the needs.
  • the principle is simple, the circuit structure is simple and easy to implement, reducing the system power consumption, and will not affect the analog-to-digital converter.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

一种模数转换器及其时钟产生电路，包括级联的时钟产生模组(100)，每一级所述时钟产生模组(100)用于产生对应的内部时钟信号，每一级所述时钟产生模组(100)包括延迟模块(110)和逻辑门模块(120)，第N级逻辑门模块(120)的第二输入端连接前一级逻辑门模块(120)的输出端，而逻辑门模块(120)的输出端用于输出内部时钟，因此每一级时钟产生模组(100)均可产生一个内部时钟信号，且内部时钟N可由内部时钟N-1和本级时钟产生模组(100)中延迟模块(110)的延迟时间运算得到，利用一个外部时钟信号可产生2-N个内部时钟信号。用户可根据需求选择其中一路时钟用于模数转换器，原理简单，电路结构简单易实现，降低了系统功耗，应用于模数转换器后不会对模数转换器产生影响。

Description

模数转换器及其时钟产生电路
技术领域：本发明涉及微电子技术领域，特别是涉及模数转换器及其时钟产生电路。
背景技术
逐次逼近型模数转换器占据着大部分的中等至高分辨率模数转换器的市场。逐次逼近型模数转换器是一种二进制搜索算法。通常，N位逐次逼近型模数转换器需要N+2或N+3个比较周期，在前一位转换完成之前不得进入下一次转换。由于逐次逼近算法的缘故，逐次逼近ADC的实际工作时钟远远大于其采样速率。
逐次逼近型模数转换器在高速应用时，需要提供一路高速高精度的时钟信号，当时钟速度超过百兆级别以后，时钟电路复杂会对系统带来较大影响，且会增大系统功耗。
申请内容
基于此，有必要针对逐次逼近型模数转换器在高速应用时时钟电路复杂影响工作系统的问题，提供一种模数转换器及其时钟产生电路。
一种时钟产生电路，包括级联的时钟产生模组，每一级所述时钟产生模组用于产生对应的内部时钟信号，每一级所述时钟产生模组包括延迟模块和逻辑门模块；
第N级延迟模块的输出端连接第N+1级延迟模块的输入端，其中，第一级延迟模块的输入端用于输入外部时钟信号，所述外部时钟信号的频率低于所述内部时钟信号的频率；
各所述逻辑门模块均包括第一输入端、第二输入端和输出端，第N级逻辑门模块的第一输入端连接所述第N级延迟模块的输出端，所述第N级逻辑门模块的第二输入端连接第N-1级逻辑门模块的输出端，所述第N级逻辑门模块的输出端用于输出第N个内部时钟信号，其中N大于等于2；
第一级逻辑门模块的第一输入端用于输入所述外部时钟信号，第二输入端连接所述第一级延迟模块的输出端。
一种模数转换器，包括前述时钟产生电路。
上述时钟产生电路可应用于模数转换器或其他电子电路中，由于外部时钟信号的频率低于内部时钟信号的频率，因此可将外部的低频时钟信号转换成内部的高频时钟信号。当用户需要使用高频时钟信号时，无需外部产生高频信号，只需在外部连接一个低频时钟信号，经过本申请的时钟产生电路处理后得到多个内部高频时钟信号，降低了电子电路的应用难度和系统复杂度。本申请通过采用逻辑门模块与延迟模块配合，由于第N级逻辑门模块的第二输入端连接前一级逻辑门模块的输出端，而逻辑门模块的输出端用于输出内部时钟，因此每一级时钟产生模组均可产生一个内部时钟信号，且内部时钟N可由内部时钟N-1和本级时钟产生模组中延迟模块的延迟时间运算得到，利用一个外部时钟信号可产生2-N个内部时钟信号，用户可根据需求选择其中一路时钟用于模数转换器，原理简单，电路结构简单易实现，降低了系统功耗，应用于模数转换器后不会对模数转换器产生影响。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1为本申请的一个实施例提供的时钟产生电路模块示意图；
图2为本申请的又一实施例提供的时钟产生电路模块示意图；
图3为本申请的一个实施例提供的延迟单元结构示意图；
图4为本申请的一个实施例提供的时钟产生电路产生的时序图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似改进，因此本发明不受下面公开的具体实施例的限制。
需要说明的是，当元件被称为“设置于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“垂直的”、“水平的”、“左”、“右”以及类似的表述只是为了说明的目的，并不表示是唯一的实施方式。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是在于限制本发明。
如背景技术所述，逐次逼近型模数转换器是采样速率低于5Msps的中等 至高分辨率应用的常见结构。在采样速率高于5Msps的高速应用中，因为时钟过高，常规结构的逼近寄存器型很难满足要求，通常会采用与其它结构结合的方式来实现高速逐次逼近型模数转换器。通常，业界主流的做法有：1、内置高性能锁相环提供高精度时钟，但锁相环性能好坏会严重影响模数转换器的特性，此外，锁相环会显著增加芯片面积和功耗。2、采用流水线型逐次逼近型模数转换器，这种结构的模数转换器采用多级子模数转换器组合而成，可以显著提升逐次逼近型寄存器的转换速度，但电路复杂程度也明显增加。3、采用并行运算逐次逼近型模数转换器，多个模数转换器并行工作，通过锁相环等辅助电路为不同寄存器分配不同相位时钟，多个寄存器在不同相位依此采集转换数据，理论上可以大幅提高模数转换器的转换速率，但实际应用中，不同通道的寄存器之间存在失调、增益误差等因素，会严重制约模数转换器的性能。
因此，为解决上述问题，请参见图1，本申请的一个实施例提供一种时钟产生电路。需要说明的是，本实施例提供的时钟产生电路不仅可应用于逐次逼近型模数转换器，也可用于其他类型的模数转换器以及任何需要高速时钟的电路。该时钟产生电路包括多个级联的时钟产生模组100，每一级时钟产生模组100均用于产生内部时钟信号。每一级时钟产生模组100均包括延迟模块110和逻辑门模块120。
延迟模块110包括多级，如图1所示，第一级延迟模块为延迟模块1，第二极延迟模块为延迟模块2，第N极延迟模块为延迟模块N，以此类推。每一级延迟模块110之间相互级联，延迟模块N的输出端连接延迟模块N+1的输入端。延迟模块1的输入端用于输入外部时钟信号。通过控制延迟模块110的延迟时间可控制输出的内部时钟信号的时钟周期。
多级逻辑门模块120互相级联，且每级逻辑门模块120与对应的延迟模块110连接。本实施例中，第一级逻辑门模块为逻辑门模块1，第二极逻辑门模块为逻辑门模块2，第N极逻辑门模块为逻辑门模块N，以此类推。各逻辑门模块120均包括第一输入端、第二输入端和输出端。逻辑门模块N的第一输入端连接延迟模块N的输出端，逻辑门模块N的第二输入端连接逻辑门模块N-1的输出端，逻辑门模块N的输出端用于输出第N个内部时钟信号，其中N大于等于2。逻辑门模块1的第一输入端用于输入外部时钟信号，第二输入端连接延迟模块1的输出端。本实施例中，外部时钟信号的频率低于内部时钟信号的频率。
本实施例提供的时钟产生电路，可将外部的低频时钟信号转换成内部的高频时钟信号。当用户需要使用高频时钟信号时，无需外部产生高频信号，只需在外部连接一个低频时钟信号，经过本申请的时钟产生电路处理后得到多个内部高频时钟信号，降低了电子电路的应用难度和系统复杂度。该时钟产生电路中每一级时钟产生模组100均可产生一个内部时钟信号，例如，第一级时钟产生模组用于产生内部时钟I，第二级时钟产生模组用于产生内部时钟II，第N级时钟产生模组用于产生内部时钟N。内部时钟N由内部时钟N-1和本级时钟产生模组100中延迟模块110的延迟时间运算得到。本实施例通过采用逻辑门模块120与延迟模块110配合，利用一个外部时钟信号可产生2-N个内部时钟信号，用户可根据需求选择其中一路时钟用于模数转换器，原理简单，电路结构简单易实现，降低了系统功耗，应用于模数转换器或其他电子电路中不会对电子电路产生影响。用户还可通过调节延迟模块的延迟时间调节输出的时钟信号的周期长度，调节方便。
请参见图2，在其中一个实施例中，延迟模块110包括多个延迟单元111。 延迟单元111的输出端连接下一个延迟单元111的输入端。本实施例提供的时钟产生电路包括2N-1个延迟单元，其中，延迟模块1包括一个延迟单元111，延迟模块2至延迟模块N均包括2个延迟单元，即延迟模块1包括第一个延迟单元，延迟模块N包括第2N-2个延迟单元和第2N-1个延迟单元，且N大于等于2。
具体的，本实施例中，延迟单元111用于控制产生的内部时钟信号的时钟周期。请参见图3，每个延迟单元111包括至少一个反相器112，多个延迟单元111的反相器112之间相互级联，用户可通过调节所述反相器112的个数调节对应的延迟单元110的延迟时间。
进一步的，每个延迟单元110还包括至少一个可调电容113。可调电容113的一端连接反相器112的输出端，另一端接地，用户可通过调节可调电容113的容量调节对应的延迟单元110的延迟时间。本实施例中，用户既可单独调节所述反相器112的个数，也可单独调电容113的容量，或同时调节两者以调节延迟单元110的延迟时间。由于每个时钟产生模组100产生的内部时钟信号的脉冲宽度取决于延迟单元110的延迟时间，而每一个延迟单元110的延迟时间均可通过调节反相器112的数量或可调电容113的容量调节，因此本实施例提供的时钟产生电路产生的内部时钟每一级脉宽均可调节。进而，用户可根据需求将每一级脉宽调节至相同，以产生同步时钟。或用户也可根据需求调节每一级脉宽使其不同，以产生异步时钟。
请继续参见图2，时钟产生电路包括多级逻辑门模块120，逻辑门模块1包括一个异或门121，逻辑门模块2至逻辑门模块N均包括一个异或门121和一个或门122。异或门121包括第一输入端、第二输入端和输出端，其中，第一个异或门121的第一输入端连接第一个延迟单元111的输入端，第二输 入端连接第一个延迟单元111输出端，第一个异或门121的输出端用于输出第一个内部时钟信号。
逻辑门模块N包括第N个异或门121和第N-1个或门122，其中，第N-1个或门122的输出端即为逻辑模块N的输出端，用于输出第N个内部时钟信号。
第N个异或门121的第一输入端连接第2N-2个延迟单元111的输出端，第二输入端连接第2N-1个延迟单元111的输出端。第N-1个或门122的第一输入端连接第N个异或门121的输出端，第二输入端连接前一级逻辑模块120的输出端，其中，N大于等于2。
具体的，第一个延迟单元1的输入端用于接收外部时钟信号，若外部时钟信号为高电平信号，经第一个延迟单元1处理后输出低电平信号，外部时钟信号和处理后的低电平信号进入第一个异或门1，经第一个异或门1运算后即可得到内部时钟I的高电平，其脉宽等于第一个延迟单元1的延迟时间，而内部高度时钟I的低电平时间取决于第二个延迟单元2的延迟时间。第一个延迟单元1输出低电平信号后，低电平信号进入第二个时钟产生模组中的第二个延迟单元2，第二个延迟单元2对低电平信号进行处理输出高电平信号并传输至第二个异或门2的第一输入端，同时高电平信号传输至第三个延迟单元3，第三个延迟单元3对高电平信号处理后输出低电平信号至第二个异或门2的第二输入端，因此第二个异或门2输出高电平。第一个异或门1输出的高电平和第二个异或门2输出的高电平进入第一个或门1，第一个或门1输出内部时钟II的高电平信号，其脉冲宽度取决于第三个延迟单元3的延迟时间，内部时钟II的低电平信号脉冲宽度取决于第四个延迟单元4的延迟时间，内部时钟II的前一个时钟周期与内部高速时钟I的时钟周期相同。
以此类推，可产生第III个至第N个内部时钟，请参见图4，图4为内部时钟时序图。内部时钟N的前N-1个时钟周期和内部时钟N-1相同，内部时钟N的第N个时钟高电平脉宽取决于第2N-1个延迟单元的延迟时间。内部2-N个时钟的时钟周期分别加上其对应的冗余时间等于1个外部时钟周期。
由于模数转换器进行采样之前需要一个启动信号方可进行采样转换，本实施例中，第一个高速时钟信号还可作为所述模数转换器的启动信号。因此时钟电路不仅可产生内部时钟信号，也可产生启动信号，简化了模数转换器的电路模块。
在其中一个实施例中，请继续参见图2，时钟产生电路还包括触发模块130，触发模块130输入端用于输入外部时钟信号，输出端分别连接第一个延迟单元1的输入端和第一个异或门1的第一输入端。本实施例中，触发模块可以是T触发器，T触发器可以对外部时钟信号进行分频处理，以消除不需要的下降沿或上升沿。
本申请的一个实施例提供一种模数转换器，包括前述时钟产生电路。
本申请提供的模数转换器，其时钟产生电路利用一个外部时钟信号通过逻辑门模块与延迟模块的运算产生2-N个内部时钟信号，用户可根据需求选择其中一路时钟用于模数转换器，原理简单，电路结构简单易实现，降低了系统功耗，且不会对模数转换器产生影响。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本 领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种时钟产生电路，包括级联的时钟产生模组，每一级所述时钟产生模组用于产生对应的内部时钟信号，每一级所述时钟产生模组包括延迟模块和逻辑门模块；
    第N级延迟模块的输出端连接第N+1级延迟模块的输入端，其中，第一级延迟模块的输入端用于输入外部时钟信号，所述外部时钟信号的频率低于所述内部时钟信号的频率；
    各所述逻辑门模块均包括第一输入端、第二输入端和输出端，第N级逻辑门模块的第一输入端连接所述第N级延迟模块的输出端，所述第N级逻辑门模块的第二输入端连接第N-1级逻辑门模块的输出端，所述第N级逻辑门模块的输出端用于输出第N个内部时钟信号，其中N大于等于2；
    第一级逻辑门模块的第一输入端用于输入所述外部时钟信号，第二输入端连接所述第一级延迟模块的输出端。
  2. 根据权利要求1所述的时钟产生电路，其特征在于，各所述延迟模块均包括延迟单元，其中，
    第一级延迟模块包括第一个延迟单元；
    第N级延迟模块包括第2N-2个延迟单元和第2N-1个延迟单元，且N大于等于2；
    各所述延迟单元的输出端连接下一个延迟单元的输入端，所述第一个延迟单元的输入端用于输入所述外部时钟信号。
  3. 根据权利要求2所述的时钟产生电路，其特征在于，第一级逻辑门模块包括第一个异或门，所述第一个异或门的第一输入端连接所述第一个延迟单元的输入端，所述第一个异或门的第二输入端连接所述第一个延迟单元的 输出端，所述第一个异或门的输出端用于输出第一个内部时钟信号。
  4. 根据权利要求3所述的时钟产生电路，其特征在于，第N级逻辑门模块包括第N个异或门和第N-1个或门，所述第N-1个或门的输出端即为所述第N级逻辑模块的输出端，用于输出第N个内部时钟信号；
    所述第N个异或门的第一输入端连接所述第2N-2个延迟单元的输出端，所述第N个异或门的第二输入端连接所述第2N-1个延迟单元的输出端，所述第N-1个或门的第一输入端连接所述第N个异或门的输出端，所述第N-1个或门的第二输入端连接前一级所述逻辑模块的输出端，其中，N大于等于2。
  5. 根据权利要求2-4中任一项所述的时钟产生电路，其特征在于，各所述延迟单元均包括至少一个反相器。
  6. 根据权利要求5所述的时钟产生电路，其特征在于，通过配置所述反相器的数量调节所述延迟单元的延迟时间。
  7. 根据权利要求5所述的时钟产生电路，其特征在于，所述延迟单元还包括至少一个可调电容，所述可调电容的一端连接所述反相器的输出端，另一端接地。
  8. 根据权利要求6或7所述的时钟产生电路，其特征在于，通过配置所述可调电容的容量调节所述延迟单元的延迟时间。
  9. 根据权利要求8所述的时钟产生电路，其特征在于，内部时钟N的第N个时钟高电平脉宽等于第2N-1个延迟单元的延迟时间。
  10. 根据权利妖求9所述的时钟产生电路，其特征在于，第2个内部时钟至第N个内部时钟的时钟周期分别加上其对应的冗余时间等于一个外部时钟的时钟周期。
  11. 根据权利要求8所述的时钟产生电路，其特征在于，配置所述内部 时钟的每一级脉冲宽度相同以产生同步时钟；
    配置每一级所述内部时钟每一级的脉冲宽度不同以产生异步时钟。
  12. 根据权利要求11所述的时钟产生电路，其特征在于，第一个内部时钟信号还作为所述模数转换器的启动信号。
  13. 根据权利要求12所述的时钟产生电路，其特征在于，还包括触发模块，所述触发模块的输入端用于输入所述外部时钟信号，输出端分别连接所述第一个延迟单元的输入端和所述第一个异或门的第一输入端。
  14. 根据权利要求13所述的时钟产生电路，其特征在于，所述触发模块包括T触发器。
  15. 一种模数转换器，包括权利要求1-14中任一项所述的时钟产生电路。
PCT/CN2019/127385 2019-01-03 2019-12-23 模数转换器及其时钟产生电路 Ceased WO2020140782A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/419,548 US11711088B2 (en) 2019-01-03 2019-12-23 Analog-to-digital converter and clock generation circuit thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910003174.6 2019-01-03
CN201910003174.6A CN111404550B (zh) 2019-01-03 2019-01-03 模数转换器及其时钟产生电路

Publications (1)

Publication Number Publication Date
WO2020140782A1 true WO2020140782A1 (zh) 2020-07-09

Family

ID=71407148

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/127385 Ceased WO2020140782A1 (zh) 2019-01-03 2019-12-23 模数转换器及其时钟产生电路

Country Status (3)

Country Link
US (1) US11711088B2 (zh)
CN (1) CN111404550B (zh)
WO (1) WO2020140782A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115334264A (zh) * 2022-08-17 2022-11-11 中国电子科技集团公司第四十四研究所 Cmos图像传感器片上时钟产生电路、模块及方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111651402B (zh) * 2020-07-16 2025-03-11 深圳比特微电子科技有限公司 时钟树、用于执行哈希算法的电路、计算芯片、算力板和计算设备
CN113608575B (zh) * 2021-10-09 2022-02-08 深圳比特微电子科技有限公司 流水线时钟驱动电路、计算芯片、算力板和计算设备
CA3165378A1 (en) 2021-10-09 2023-04-09 Nan Li Pipeline clock driving circuit, computing chip, hashboard and computing device
CN114839405B (zh) * 2022-07-04 2022-09-09 苏州锴威特半导体股份有限公司 单引脚烧录装置
CN118353459B (zh) * 2024-04-25 2025-07-29 成都士模微电子有限责任公司 多通道逐次逼近型模数转换器系统、集成电路、芯片与设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101562440A (zh) * 2009-05-12 2009-10-21 华为技术有限公司 延迟模块和方法、时钟检测装置及数字锁相环
US20100090876A1 (en) * 2008-10-13 2010-04-15 National Semiconductor Corporation Continuous synchronization for multiple adcs
CN102427368A (zh) * 2011-11-30 2012-04-25 香港应用科技研究院有限公司 一种高速的逐次逼近寄存器模数转换器
CN103684465A (zh) * 2013-12-20 2014-03-26 清华大学 用于异步逐步逼近模数转换器的多相时钟产生电路
CN103986461A (zh) * 2014-05-30 2014-08-13 华为技术有限公司 时间数字转换方法及时间数字转换器

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3561792B2 (ja) * 1995-09-06 2004-09-02 株式会社ルネサステクノロジ クロック発生回路
US5963071A (en) * 1998-01-22 1999-10-05 Nanoamp Solutions, Inc. Frequency doubler with adjustable duty cycle
TW200427224A (en) * 2003-05-21 2004-12-01 Myson Century Inc Clock multiplier
CN102419417B (zh) * 2011-08-17 2014-02-26 北京时代民芯科技有限公司 一种现场可编程逻辑门阵列触发器传播延迟的测试电路
CN102664623B (zh) * 2012-05-09 2015-02-18 龙芯中科技术有限公司 数字延迟装置
CN104617957B (zh) * 2015-01-30 2017-08-15 中国电子科技集团公司第二十四研究所 异步逐次逼近型模数转换器
US9973178B1 (en) * 2017-02-16 2018-05-15 Nuvoton Technology Corporation Method and apparatus for clock frequency multiplier
CN106898319B (zh) * 2017-02-20 2019-02-26 武汉华星光电技术有限公司 一种goa电路及液晶显示面板
JP6899287B2 (ja) * 2017-09-01 2021-07-07 株式会社日立製作所 逐次比較型アナログデジタル変換器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100090876A1 (en) * 2008-10-13 2010-04-15 National Semiconductor Corporation Continuous synchronization for multiple adcs
CN101562440A (zh) * 2009-05-12 2009-10-21 华为技术有限公司 延迟模块和方法、时钟检测装置及数字锁相环
CN102427368A (zh) * 2011-11-30 2012-04-25 香港应用科技研究院有限公司 一种高速的逐次逼近寄存器模数转换器
CN103684465A (zh) * 2013-12-20 2014-03-26 清华大学 用于异步逐步逼近模数转换器的多相时钟产生电路
CN103986461A (zh) * 2014-05-30 2014-08-13 华为技术有限公司 时间数字转换方法及时间数字转换器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115334264A (zh) * 2022-08-17 2022-11-11 中国电子科技集团公司第四十四研究所 Cmos图像传感器片上时钟产生电路、模块及方法
CN115334264B (zh) * 2022-08-17 2024-04-09 中国电子科技集团公司第四十四研究所 Cmos图像传感器片上时钟产生电路、模块及方法

Also Published As

Publication number Publication date
CN111404550B (zh) 2022-09-09
US11711088B2 (en) 2023-07-25
US20220077865A1 (en) 2022-03-10
CN111404550A (zh) 2020-07-10

Similar Documents

Publication Publication Date Title
WO2020140782A1 (zh) 模数转换器及其时钟产生电路
CN105718404B (zh) 一种基于fpga的方波发生器及方法
JP5561010B2 (ja) 逐次比較型ａｄ変換器及び逐次比較型ａｄ変換器の動作クロック調整方法
CN110661513B (zh) 一种数字脉宽调制电路及工作方法
US7573409B2 (en) Variable sized aperture window of an analog-to-digital converter
CN106941345B (zh) D触发器和异步逐次逼近型模数转换器
CN110120798B (zh) 一种双沿触发混合结构的dpwm电路及其控制方法
CN110649922B (zh) 一种数字时钟倍频器
CN104579320B (zh) 时钟延迟方法、装置、延迟锁相环及数字时钟管理单元
WO2017197946A1 (zh) 一种基于pvtm的宽电压时钟拉伸电路
WO2017124219A1 (zh) 一种基于fpga的方波发生器及方法
CN111884631A (zh) 一种采用混合结构的数字脉冲宽度调制模块
CN103262423A (zh) 时间差数字转换电路以及包括它的时间差数字转换器
JP2005033392A (ja) 半導体集積回路装置
EP4037192B1 (en) Coarse-fine counting architecture for a vco-adc based on interlocked binary asynchronous counters
CN109088619B (zh) 一种使能信号产生方法及电路
JP4517891B2 (ja) シリアル／パラレル変換回路及びパラレル／シリアル変換回路
US6265996B1 (en) Low latency, low power deserializer
US6535527B1 (en) Low latency, low power deserializer
CN109905128B (zh) 一种自适应的高速sar-adc转换时间完全利用电路及方法
CN119696548A (zh) 一种无毛刺数控环形振荡器
CN117478130B (zh) 一种时间交织adc的多相采样时钟产生电路
KR100321732B1 (ko) 디지털 링 동기식 미러 딜레이를 이용한 지연고정루프
CN204517790U (zh) 一种改进型全数字逐次逼近寄存器延时锁定环系统
CN117353737A (zh) 延迟自适应校准方法及装置、校准电路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19907882

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19907882

Country of ref document: EP

Kind code of ref document: A1