WO2020140751A1 - 阵列基板及其制备方法、显示面板和显示装置 - Google Patents

阵列基板及其制备方法、显示面板和显示装置 Download PDF

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WO2020140751A1
WO2020140751A1 PCT/CN2019/126106 CN2019126106W WO2020140751A1 WO 2020140751 A1 WO2020140751 A1 WO 2020140751A1 CN 2019126106 W CN2019126106 W CN 2019126106W WO 2020140751 A1 WO2020140751 A1 WO 2020140751A1
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thin film
film transistor
display panel
array substrate
layer
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PCT/CN2019/126106
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English (en)
French (fr)
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王国英
宋振
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京东方科技集团股份有限公司
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Priority to US16/910,590 priority Critical patent/US11257874B2/en
Publication of WO2020140751A1 publication Critical patent/WO2020140751A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
    • H01L31/14—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the light source or sources being controlled by the semiconductor device sensitive to radiation, e.g. image converters, image amplifiers or image storage devices
    • H01L31/147—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the light source or sources being controlled by the semiconductor device sensitive to radiation, e.g. image converters, image amplifiers or image storage devices the light sources and the devices sensitive to radiation all being semiconductor devices characterised by potential barriers
    • H01L31/153—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto the light source or sources being controlled by the semiconductor device sensitive to radiation, e.g. image converters, image amplifiers or image storage devices the light sources and the devices sensitive to radiation all being semiconductor devices characterised by potential barriers formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1884—Manufacture of transparent electrodes, e.g. TCO, ITO
    • H01L31/1888—Manufacture of transparent electrodes, e.g. TCO, ITO methods for etching transparent electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/13—Active-matrix OLED [AMOLED] displays comprising photosensors that control luminance

Definitions

  • the present disclosure relates to the technical field of displays, and in particular, to an array substrate and a preparation method thereof, a display panel, and a display device.
  • an embodiment of the present disclosure provides an array substrate including a base substrate, a first thin film transistor on the base substrate, and a photosensitive sensor connected to the first thin film transistor; wherein ,
  • the photosensitive sensor is located above the drain of the first thin film transistor and is electrically connected to the drain;
  • the conductive channel of the first thin film transistor has an insulating dielectric portion formed of metal by anodizing treatment.
  • the metal forming the insulating dielectric portion and the drain of the first thin film transistor are the same metal layer.
  • a display panel including the array substrate according to any one of the first aspect; the photosensitive sensor and the first thin film transistor are located in a non-display area of the display panel .
  • the display panel is an OLED display panel;
  • the array substrate further includes: a light emitting device located in the display area, and a second thin film transistor connected to the light emitting device, and the first thin film The transistor and the second thin film transistor are on the same film layer.
  • the display panel is an LCD display panel;
  • the array substrate further includes: a third thin film transistor located in the display area, and the first thin film transistor and the third thin film transistor are located in the same film Floor.
  • an embodiment of the present disclosure provides a display device including the display panel according to any one of the second aspects.
  • an embodiment of the present disclosure provides a method for manufacturing an array substrate.
  • the manufacturing method includes:
  • the metal layer pattern including a source electrode, a drain electrode, and a region covering the conductive channel;
  • a photosensitive sensor is formed on the drain.
  • the anodizing the region covering the conductive channel in the metal layer pattern to form an insulating dielectric part specifically includes:
  • an area of the metal layer pattern covering the conductive channel is anodized to form an insulating dielectric portion.
  • the patterned photoresist layer is used as a shield, and an area of the metal layer pattern covering the conductive channel is anodized to form an insulating dielectric portion, specifically include:
  • a citric acid solution is used, and a metal oxide film is formed on the surface of the region of the metal layer pattern covering the conductive channel by electrolysis in a constant current and constant pressure mode.
  • the forming a photosensitive sensor on the drain electrode specifically includes:
  • the transparent conductive oxide layer is patterned by wet etching, and the phosphorus or arsenic-doped semiconductor layer, intrinsic semiconductor layer and boron-doped semiconductor layer are dry-etched to form the pattern Photo sensor.
  • FIG. 1 is a schematic flow chart of a method for manufacturing an array substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure
  • FIG. 3 is another schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 4 is another schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is another schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is another schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • the main methods for screen brightness compensation are internal compensation and external compensation.
  • the internal compensation method refers to using the capacitance inside the display panel to compensate for the threshold voltage and mobility of the TFT (Thin Film Transistor, thin film transistor) before the organic light emitting diode emits light, but the compensation range of this compensation method is small.
  • the external compensation method refers to adding a compensation circuit outside the TFT to monitor the threshold voltage of the driving TFT in real time, and realize the compensation by rewriting the voltage. Compared with the internal compensation method, the external compensation method can achieve a larger range of compensation.
  • the above two compensation methods can only compensate for uneven display brightness caused by TFT threshold voltage and mobility changes, but cannot compensate for brightness changes caused by aging of display devices.
  • the more uniform the brightness of the screen of the display device the better.
  • the brightness of the display device such as the OLED display panel
  • the methods for screen brightness compensation are mainly the above-mentioned internal compensation methods and external compensation methods, but the above two compensation methods cannot compensate for the brightness change caused by the aging of the display device.
  • a photosensitive sensor connected to the first thin film transistor is provided in the array substrate to detect the actual light emission brightness of the pixels of the display panel provided with the array substrate through the photosensitive sensor in real time, thereby realizing the display panel in real time Brightness compensation to improve the uniformity of display panel brightness.
  • the first thin film transistor has an insulating dielectric part formed by anodizing on the conductive channel of the metal, the insulating dielectric part can prevent the photosensitive sensor which is located above the drain of the first thin film transistor and is electrically connected to the drain The introduced hydrogen gas penetrates into the area under the conductive channel and adversely affects the array substrate.
  • an embodiment of the present disclosure provides a method for manufacturing an array substrate. As shown in FIG. 1, the specific flow of the manufacturing method is as follows:
  • Step S101, a gate 201, a gate insulating layer 202, and an active layer 204 are sequentially formed on the base substrate 20.
  • the first thin film transistor when fabricating the array substrate, the first thin film transistor is first fabricated.
  • the gate 201, the gate insulating layer 202 and the active layer 204 may be sequentially formed on the base substrate 20.
  • a metal layer may be deposited on the glass, and then a photoresist layer is coated on the metal layer, and the photoresist layer is imaged to form a gate 201 pattern.
  • the material of the metal layer may be common metals such as Mo, Al, Ti, Au, Cu, Hf, Ta, or Cu alloys, such as the MoNd/Cu/MoNd metal layer formed by the Cu process.
  • a gate insulating layer 202 (GI layer) and an Act layer are sequentially deposited on the gate 201, and then the wet layer is patterned to form an active island, that is, an active layer 204.
  • the GI layer material may be insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride
  • the Act layer material may be a metal oxide material, such as IGZO material.
  • Step S102 forming a metal layer pattern on the active layer 204.
  • the metal layer pattern includes a source electrode 205, a drain electrode 206, and a region covering the conductive channel.
  • a metal layer may be deposited on the active layer 204, and the material of the metal layer may be Mo, Al, Ti, Au, Hf, Ta, or other metals Part of the metal alloy.
  • a metal layer pattern is formed on the metal layer.
  • the formed metal layer pattern includes a source electrode 205, a drain electrode 206, and a region covering the conductive channel.
  • Step S103 anodizing the region covering the conductive channel in the metal layer pattern to form an insulating dielectric portion 207.
  • a photoresist layer 207 may be formed on the metal layer pattern, and the photoresist layer 207 may be patterned to expose the area of the metal layer pattern covering the conductive channel, and then patterned.
  • the processed photoresist layer 207 serves as a shield, and anodizes the area of the metal layer pattern covering the conductive channel to form an insulating dielectric portion 208, as shown in FIG. 3 of the first thin film transistor.
  • the method of anodizing the region covering the conductive channel in the metal layer pattern may be a constant current and constant pressure mode using a citric acid solution under the conditions of normal pressure and room temperature
  • a metal oxide thin film is formed on the surface of the area of the metal layer pattern covering the conductive channel, such as a metal oxide thin film of high-K dielectrics such as aluminum oxide, hafnium oxide, tantalum oxide, and zirconium oxide, etc. to obtain an insulating dielectric portion 208 .
  • the insulating dielectric portion 208 is a metal oxide thin film, it has high density and can block gas and the like from invading the lower portion of the first thin film transistor through the conductive channel, thereby adversely affecting the array substrate.
  • Step S104 forming a photosensitive sensor on the drain 206.
  • a photosensitive sensor 209 may be formed on the drain 206 of the first thin film transistor, specifically, a phosphor or arsenic doped semiconductor layer
  • the semiconductor layer, the intrinsic semiconductor layer, and the boron-doped semiconductor layer are subjected to dry etching patterning to form a photosensitive sensor 209 as shown in FIG. 4 to obtain an array substrate provided by an embodiment of the present disclosure.
  • the first thin film transistor when fabricating the array substrate, the first thin film transistor is fabricated, and then the photosensitive sensor 209 is fabricated. Since the first thin film transistor has an insulating dielectric portion 208 formed by anodizing on the conductive channel of the metal, the insulating dielectric portion 208 has a high density, which can block the transmission of hydrogen introduced in the subsequent process of manufacturing the photosensitive sensor 209 The conductive channel enters the lower portion of the first thin film transistor to affect the array substrate.
  • the photosensitive sensor 209 is fabricated after the first thin film transistor is fabricated as a whole, which can avoid the influence on the sidewall of the photosensitive sensor during the wet etch patterning process of the first thin film transistor, so as to reduce the device Leakage current.
  • a PVX protective layer 211 may be deposited, and the patterned PVX protective layer 211 forms a Via hole, wherein the material of the PVX protective layer 211 may be silicon oxide, silicon nitride, silicon oxynitride, etc. Material, the projection of each Via hole on the base substrate 20 is the projection of the pixel definition layer of the base substrate 20 on the base substrate 20.
  • An ITO electrode 212 is deposited and patterned on the side of the photosensitive sensor 209 away from the base substrate 20 to form the structure shown in FIG. 5.
  • the array substrate provided by the embodiment of the present disclosure may be applied to the top emission cover glass or the bottom emission cover glass.
  • the following uses the array substrate provided by the embodiment of the present disclosure to be applied to the top emission cover glass as an example to introduce the production of the array substrate Subsequent process steps.
  • the black matrix BM213 may be continuously deposited and patterned on the PVX protective layer 211 so that the BM213 covers the active matrix TFT.
  • a color film CF layer 214 is deposited on the ITO layer 212 on the photosensitive sensor. Specifically, when forming the CF layer 214, R, G, and B color films are successively deposited, and the color films are provided to cover the BM213 to a certain extent.
  • the OC layer 215 and the auxiliary electrode 216 can be deposited and patterned on the upper surface of the array substrate obtained after making the BM213 and the CF layer 214, and the auxiliary electrode 216 can be commonly used in Mo, Al, Ti, Au, Cu, Hf, Ta, etc.
  • the metal may also be an alloy such as AlNd, MoNb, etc., or a multilayer metal such as a metal layer composed of MoNb/Cu/MoNb, AlNd/Mo/AlNd, etc.
  • a support PS (Photo Spacer) layer material can be deposited and a support 217 is formed, and then a layer of transparent conductive oxide TCO film 218 is deposited as a transparent cathode, wherein the material of the transparent conductive oxide film 218 can be AZO, IZO, AZTO Such as commonly used materials, or a combination of these materials, etc., to complete the production of the cover part, to obtain the structure shown in Figure 6.
  • an embodiment of the present disclosure also provides an array substrate manufactured by the above manufacturing method.
  • the array substrate includes a base substrate 20, a first thin film transistor on the base substrate 20, and A photosensitive sensor 209 connected to the first thin film transistor; wherein the photosensitive sensor 209 is located on and electrically connected to the drain 206 of the first thin film transistor, and the conductive channel of the first thin film transistor has a metal through anodizing treatment The insulating dielectric portion 208 formed.
  • the metal forming the insulating dielectric portion 208 and the drain 206 of the first thin film transistor may be the same metal layer.
  • the array substrate further includes a gate 201, a gate insulating layer 202 and an active layer 204 on the base substrate 20, a metal layer on the side of the active layer 204 away from the base substrate 20, the
  • the metal layer may include a source electrode 205, a drain electrode 206, and a region covering the conductive channel, and the region covering the conductive channel in the metal layer pattern is anodized to form an insulating dielectric portion 208, that is, the metal forming the insulating dielectric portion 208 and
  • the drain 206 of the first thin film transistor is the same metal layer.
  • the photosensitive sensor 209 is formed by sequentially forming a phosphorus or arsenic doped semiconductor layer, an intrinsic semiconductor layer, and a boron doped semiconductor layer on the drain 206.
  • an embodiment of the present disclosure also provides a display panel including the array substrate formed as described above, wherein the photosensitive sensor 209 and the first thin film transistor are located in a non-display area of the display panel.
  • the array substrate provided by the embodiments of the present disclosure can be applied to the display field, for example, it can be made into an OLED display panel or an LCD display panel.
  • the display panel is an OLED display panel
  • the array substrate may further include a light emitting device located in the display area, and a second thin film transistor connected to the light emitting device, the first thin film transistor and the second thin film transistor are located The same film.
  • the display panel is an LCD display panel
  • the array substrate may further include a third thin film transistor located in the display area, and the first thin film transistor and the third thin film transistor are located in the same film layer.
  • the array substrate provided by the embodiments of the present disclosure is applied to the field of touch panels, the array substrate also includes components necessary for the touch panel, which will not be repeated here.
  • an embodiment of the present disclosure also provides a display device, including any one of the above-mentioned display panels provided by the embodiment of the present disclosure. If the display device needs to display a color effect, a color filter may be provided on any layer or multiple layers of any panel of the display panel, or other color devices such as quantum dot films may be provided.
  • the display device may be any product or component with display and touch functions, such as mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, and navigators. For the implementation of the display device, reference may be made to the foregoing embodiments of the array substrate, and repeated descriptions are not repeated.

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Abstract

一种阵列基板及其制备方法、显示面板和显示装置，所述阵列基板内置了感光传感器（209），实时检测像素的实际发光亮度，从而实时地对设置阵列基板的显示面板进行亮度补偿，以提高显示面板亮度的均一性。该阵列基板包括衬底基板（20），位于所述衬底基板（20）上的第一薄膜晶体管，以及与所述第一薄膜晶体管连接的感光传感器（209）；其中，所述感光传感器（209）位于所述第一薄膜晶体管的漏极（206）之上且与所述漏极（206）电连接；所述第一薄膜晶体管的导电沟道之上具有金属通过阳极氧化处理形成的绝缘介质部（208）。

Description

阵列基板及其制备方法、显示面板和显示装置
相关申请的交叉引用
本公开要求在2019年01月02日提交中国专利局、申请号为201910002593.8、申请名称为“一种阵列基板及其制备方法、显示面板和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示器技术领域，特别涉及一种阵列基板及其制备方法、显示面板和显示装置。
背景技术
随着AMOLED近些年的需求不断增加，市场对其参数的要求也越来越高，而亮度就是其中的一项重要指标，它关系着良好的用户体验，所以客户往往不断对亮度均一性提出更高要求，如果整个屏幕的亮度不均一，则对整个屏幕的亮度进行补偿。
发明内容
第一方面，本公开实施例提供了一种阵列基板，该阵列基板包括衬底基板，位于所述衬底基板上的第一薄膜晶体管，以及与所述第一薄膜晶体管连接的感光传感器；其中，
所述感光传感器位于所述第一薄膜晶体管的漏极之上且与所述漏极电连接；
所述第一薄膜晶体管的导电沟道之上具有金属通过阳极氧化处理形成的绝缘介质部。
在一种可能的实施方式中，形成所述绝缘介质部的金属与所述第一薄膜晶体管的漏极为同一金属层。
第二方面，提供了一种显示面板，该显示面板包括如第一方面提供的任一项所述的阵列基板；所述感光传感器和所述第一薄膜晶体管位于所述显示面板的非显示区域。
在一种可能的实施方式中，所述显示面板为OLED显示面板；所述阵列基板还包括：位于显示区域的发光器件，以及与所述发光器件连接的第二薄膜晶体管，所述第一薄膜晶体管与所述第二薄膜晶体管位于相同膜层。
在一种可能的实施方式中，所述显示面板为LCD显示面板；所述阵列基板还包括：位于显示区域的第三薄膜晶体管，所述第一薄膜晶体管与所述第三薄膜晶体管位于相同膜层。
第三方面，本公开实施例提供了一种显示装置，该显示装置包括如第二方面提供的任一项所述的显示面板。
第四方面，本公开实施例提供了一种阵列基板的制作方法，该制作方法包括：
在衬底基板上依次形成栅极、栅绝缘层和有源层；
在所述有源层上形成金属层图形，所述金属层图形包括源极、漏极以及覆盖导电沟道的区域；
对所述金属层图形中覆盖所述导电沟道的区域进行阳极氧化处理，形成绝缘介质部；
在所述漏极上形成感光传感器。
在一种可能的实施方式中，所述对所述金属层图形中覆盖所述导电沟道的区域进行阳极氧化处理，形成绝缘介质部，具体包括：
在所述金属层图形上形成光刻胶层；
对所述光刻胶层进行图形化处理，露出所述金属层图形中覆盖导电沟道的区域；
以图形化处理后的光刻胶层作为遮挡，对所述金属层图形中覆盖所述导电沟道的区域进行阳极氧化处理，形成绝缘介质部。
在一种可能的实施方式中，所述以图形化处理后的光刻胶层作为遮挡， 对所述金属层图形中覆盖所述导电沟道的区域进行阳极氧化处理，形成绝缘介质部，具体包括：
在常压和室温的条件下，采用柠檬酸溶液，在恒流恒压的模式的下利用电解方式，使所述金属层图形中覆盖所述导电沟道的区域表面形成金属氧化物薄膜。
在一种可能的实施方式中，所述在所述漏极上形成感光传感器，具体包括：
在所述漏极上依次形成磷或砷掺杂半导体层、本征半导体层、硼掺杂半导体层以及透明导电氧化物层；
采用同一掩模板进行构图后，对透明导电氧化物层进行湿刻图形化，对所述磷或砷掺杂半导体层、本征半导体层和硼掺杂半导体层进行干刻图形化，形成所述感光传感器。
附图说明
图1是本公开实施例提供的阵列基板的制作方法的流程示意图；
图2为本公开实施例提供的阵列基板的一种结构示意图；
图3为本公开实施例提供的阵列基板的另一种结构示意图；
图4为本公开实施例提供的阵列基板的另一种结构示意图；
图5为本公开实施例提供的阵列基板的另一种结构示意图；
图6为本公开实施例提供的阵列基板的另一种结构示意图。
具体实施方式
目前针对屏幕亮度补偿的方式主要内部补偿方式和外部补偿方式。内部补偿方式指的是在有机发光二极管发光前，利用显示面板内部的电容补偿TFT(Thin Film Transistor，薄膜晶体管)的阈值电压和迁移率，但是这种补偿方式的补偿范围较小。外部补偿方式指的是在TFT外部增设一个补偿电路，实时监控驱动TFT的阈值电压，通过重新写入电压实现补偿，相较于内部补偿 方式，外部补偿方式可以实现较大范围补偿。
但是如上两种补偿方式只能对TFT阈值电压和迁移率变化造成的显示亮度不均匀进行补偿，而无法针对显示器件老化引起的亮度变化进行补偿。
可见相关技术中，存在因显示器件老化导致整个屏幕的亮度均一性变差的技术问题。
为使本公开的目的、技术方案和优点更加清楚明白，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。
通常，显示装置的屏幕的亮度越均一越好，然而实际上显示装置例如OLED显示面板的亮度并不均一，因此需要对整个屏幕的亮度进行补偿。目前针对屏幕亮度补偿的方式主要如上述的内部补偿方式和外部补偿方式，但是如上两种补偿方式无法针对显示器件老化引起的亮度变化进行补偿。
鉴于此，本公开实施例中，在阵列基板中设置与第一薄膜晶体管连接的感光传感器，以通过感光传感器实时检测设置阵列基板的显示面板的像素的实际发光亮度，从而实时地对显示面板进行亮度补偿，以提高显示面板亮度的均一性。且第一薄膜晶体管的导电沟道之上具有金属通过阳极氧化处理形成的绝缘介质部，该绝缘介质部可以防止位于第一薄膜晶体管的漏极之上且与漏极电连接的感光传感器在制作时引入的氢气渗透到导电沟道下方的区域而对阵列基板产生不良影响。
下面结合附图，对本公开实施例提供的阵列基板及其制备方法和显示装置的具体实施方式进行详细地说明。
附图中各膜层的厚度和形状不反映真实比例，目的只是示意说明本公开内容。
参见图1，结合图2-图5，本公开实施例提供了一种阵列基板的制作方法，如图1所示，该制作方法的具体流程如下：
步骤S101、在衬底基板20上依次形成栅极201、栅绝缘层202和有源层204。
本公开实施例在制作阵列基板时，首先制作第一薄膜晶体管，具体地， 请参见图2，可以在衬底基板20上依次形成栅极201、栅绝缘层202和有源层204。可能的实施方式中，可以在玻璃上沉积金属层，再在金属层上涂覆光刻胶层，对光刻胶层进行图像化处理，形成栅极201图形。其中，金属层的材料可为Mo、Al、Ti、Au、Cu、Hf、Ta等常用金属，也可为Cu合金，例如采用Cu工艺制作形成的MoNd/Cu/MoNd金属层。
在栅极201上依次沉积栅绝缘层202(GI层)、Act层，然后湿刻图形化Act层形成有源岛，即有源层204。其中，GI层材料可为氧化硅、氮化硅、氮氧化硅等绝缘材料，Act层材料可为金属氧化物材料，例如IGZO材料。
步骤S102、在有源层204上形成金属层图形，金属层图形包括源极205、漏极206以及覆盖导电沟道的区域。
本公开实施例在制作完有源层204之后，可以在有源层204上沉积金属层，该金属层的材料可以是Mo、Al、Ti、Au、Hf、Ta等金属或这几种金属中的部分金属的合金。在金属层上形成金属层图形，所形成的金属层图形包括源极205、漏极206以及覆盖导电沟道的区域。
步骤S103、对金属层图形中覆盖导电沟道的区域进行阳极氧化处理，形成绝缘介质部207。
如图2所示，本公开实施例可以在金属层图形上形成光刻胶层207，对光刻胶层207进行图形化处理，露出金属层图形中覆盖导电沟道的区域，再以图形化处理后的光刻胶层207作为遮挡，对金属层图形中覆盖导电沟道的区域进行阳极氧化处理，形成绝缘介质部208，如图3所示的第一薄膜晶体管。
在一种可能的实施方式中，对金属层图形中覆盖导电沟道的区域进行阳极氧化处理的方式可以是在常压和室温的条件下，采用柠檬酸溶液，在恒流恒压的模式的下利用电解方式，使金属层图形中覆盖导电沟道的区域表面形成金属氧化物薄膜，例如氧化铝、氧化铪、氧化钽、氧化锆等高K介质的金属氧化物薄膜，获得绝缘介质部208。由于绝缘介质部208是金属氧化物薄膜，所以致密性较高，可以阻挡气体等通过导电沟道侵入第一薄膜晶体管的下部，从而对阵列基板造成不良影响。
步骤S104、在漏极206上形成感光传感器。
本公开实施例在制作完第一薄膜晶体管的之后，可以在第一薄膜晶体管的在漏极206上形成感光传感器209，具体地可以在漏极206上依次形成磷或砷掺杂半导体层、本征半导体层、硼掺杂半导体层，以及透明导电氧化物层210，例如ITO层，在采用同一掩模板进行构图后，对透明导电氧化物层210进行湿刻图形化，对磷或砷掺杂半导体层、本征半导体层和硼掺杂半导体层进行干刻图形化，形成如图4所示的感光传感器209，获得本公开实施例提供的阵列基板。
本公开实施例在制作阵列基板时，先制作第一薄膜晶体管，再制作感光传感器209。由于第一薄膜晶体管的导电沟道之上具有金属通过阳极氧化处理形成的绝缘介质部208，绝缘介质部208的致密性较高，从而可以阻挡后续制作感光传感器209的工艺中引入的氢气透过导电沟道进入第一薄膜晶体管的下部对阵列基板造成影响。再者，本公开实施例整体将第一薄膜晶体管制作完成后再制作感光传感器209，可以避免在制作第一薄膜晶体管湿刻图形化过程中对感光传感器侧壁的影响，以致于降低了器件的漏电流。
本公开实施例在制作感光传感器209之后，可以沉积PVX保护层211，图形化PVX保护层211形成Via孔，其中，PVX保护层211的材料可为氧化硅、氮化硅、氮氧化硅等绝缘材料，每个Via孔在衬底基板20上的投影位于衬底基板20的像素定义层在衬底基板20上的投影。在感光传感器209远离衬底基板20的一侧沉积一层ITO电极212并图形化，形成如图5所示的结构。
本公开实施例提供的阵列基板可以应用在顶发射盖板玻璃，也可以应用在底发射盖板玻璃，下面以本公开实施例提供的阵列基板应用在顶发射盖板玻璃为例介绍制作阵列基板后续的流程步骤。
可能的实施方式中，本公开实施例获得如图5所示的阵列基板之后，可以继续在PVX保护层211上沉积黑矩阵BM213并图形化，使得BM213覆盖有源矩阵TFT。在感光传感器上的ITO层212上沉积彩膜CF层214。具体地，在制作CF层214时，先后沉积R、G、B各彩膜，并使彩膜对BM213有一定 的覆盖。之后可以在制作BM213和CF层214之后所得的阵列基板的上表面沉积OC层215和辅助电极216并图形化，辅助电极216材料可以为Mo、Al、Ti、Au、Cu、Hf、Ta等常用金属，或者也可以是合金例如AlNd、MoNb等，或者还可以为多层金属，例如MoNb/Cu/MoNb、AlNd/Mo/AlNd等组成的金属层。之后可以沉积支撑体PS(Photo Spacer)层材料并形成支撑体217，再淀积一层透明导电氧化物TCO薄膜218作为透明阴极，其中透明导电氧化物薄膜218的材料可为AZO、IZO、AZTO等常用材料，或这几种材料的组合等，完成盖板部分的制作，获得如图6所示的结构。
请继续参见图4，基于同一发明构思，本公开实施例还提供了通过上述制作方法制作的阵列基板，该阵列基板包括衬底基板20、位于衬底基板20上的第一薄膜晶体管、以及与第一薄膜晶体管连接的感光传感器209；其中，感光传感器209位于第一薄膜晶体管的漏极206之上且与漏极206电连接，第一薄膜晶体管的导电沟道之上具有金属通过阳极氧化处理形成的绝缘介质部208。
本公开实施例提供的上述阵列基板在具体实施时，形成绝缘介质部208的金属与第一薄膜晶体管的漏极206可以为同一金属层。
具体地，请继续参见图4，阵列基板还包括位于衬底基板20上的栅极201、栅绝缘层202和有源层204，位于有源层204远离衬底基板20一侧金属层，该金属层可以包括源极205、漏极206以及覆盖导电沟道的区域，而金属层图形中覆盖导电沟道的区域进行阳极氧化处理，形成绝缘介质部208，即形成绝缘介质部208的金属与第一薄膜晶体管的漏极206为同一金属层。感光传感器209为在漏极206上依次形成磷或砷掺杂半导体层、本征半导体层、硼掺杂半导体层。
基于同一发明思想，本公开实施例还提供了一种显示面板，该显示面板包括如上述制作方法形成的阵列基板，其中，感光传感器209和第一薄膜晶体管位于显示面板的非显示区域。
本公开实施例提供的阵列基板可以应用于显示领域，例如可以制成OLED 显示面板，也可以制成LCD显示面板。在一种可能的实施方式中，显示面板为OLED显示面板，那么阵列基板还可以包括位于显示区域的发光器件，以及与发光器件连接的第二薄膜晶体管，第一薄膜晶体管与第二薄膜晶体管位于相同膜层。在一种可能的实施方式中，显示面板为LCD显示面板，那么阵列基板还可以包括位于显示区域的第三薄膜晶体管，第一薄膜晶体管与第三薄膜晶体管位于相同膜层。
当然如果本公开实施例提供的阵列基板应用于触控面板领域，阵列基板还包括触控面板必备的组件，这里不再赘述。
基于同一发明思想，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述任一种的显示面板。如果显示装置需要显示彩色效果，则可以在显示面板的任一面板的任一层或者多层设置彩色滤光片，或者设置量子点膜等其他彩色器件。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示和触控功能的产品或部件。该显示装置的实施可以参见上述阵列基板的实施例，重复之处不再赘述。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (10)

  1. 一种阵列基板，其中，包括衬底基板，位于所述衬底基板上的第一薄膜晶体管，以及与所述第一薄膜晶体管连接的感光传感器；其中，
    所述感光传感器位于所述第一薄膜晶体管的漏极之上且与所述漏极电连接；
    所述第一薄膜晶体管的导电沟道之上具有金属通过阳极氧化处理形成的绝缘介质部。
  2. 如权利要求1所述的阵列基板，其中，形成所述绝缘介质部的金属与所述第一薄膜晶体管的漏极为同一金属层。
  3. 一种显示面板，其中，包括如权利要求1或2所述的阵列基板；所述感光传感器和所述第一薄膜晶体管位于所述显示面板的非显示区域。
  4. 如权利要求3所述的显示面板，其中，所述显示面板为OLED显示面板；所述阵列基板还包括：位于显示区域的发光器件，以及与所述发光器件连接的第二薄膜晶体管，所述第一薄膜晶体管与所述第二薄膜晶体管位于相同膜层。
  5. 如权利要求3所述的显示面板，其中，所述显示面板为LCD显示面板；所述阵列基板还包括：位于显示区域的第三薄膜晶体管，所述第一薄膜晶体管与所述第三薄膜晶体管位于相同膜层。
  6. 一种显示装置，其中，包括如权利要求3-5任一项所述的显示面板。
  7. 一种阵列基板的制作方法，其中，包括：
    在衬底基板上依次形成栅极、栅绝缘层和有源层；
    在所述有源层上形成金属层图形，所述金属层图形包括源极、漏极以及覆盖导电沟道的区域；
    对所述金属层图形中覆盖所述导电沟道的区域进行阳极氧化处理，形成绝缘介质部；
    在所述漏极上形成感光传感器。
  8. 如权利要求7所述的制作方法，其中，所述对所述金属层图形中覆盖所述导电沟道的区域进行阳极氧化处理，形成绝缘介质部，具体包括：
    在所述金属层图形上形成光刻胶层；
    对所述光刻胶层进行图形化处理，露出所述金属层图形中覆盖导电沟道的区域；
    以图形化处理后的光刻胶层作为遮挡，对所述金属层图形中覆盖所述导电沟道的区域进行阳极氧化处理，形成绝缘介质部。
  9. 如权利要求7所述的制作方法，其中，所述以图形化处理后的光刻胶层作为遮挡，对所述金属层图形中覆盖所述导电沟道的区域进行阳极氧化处理，形成绝缘介质部，具体包括：
    在常压和室温的条件下，采用柠檬酸溶液，在恒流恒压的模式的下利用电解方式，使所述金属层图形中覆盖所述导电沟道的区域表面形成金属氧化物薄膜。
  10. 如权利要求7所述的制作方法，其中，所述在所述漏极上形成感光传感器，具体包括：
    在所述漏极上依次形成磷或砷掺杂半导体层、本征半导体层、硼掺杂半导体层以及透明导电氧化物层；
    采用同一掩模板进行构图后，对透明导电氧化物层进行湿刻图形化，对所述磷或砷掺杂半导体层、本征半导体层和硼掺杂半导体层进行干刻图形化，形成所述感光传感器。
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