WO2020132909A1 - 一种芯片的封装结构 - Google Patents

一种芯片的封装结构 Download PDF

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Publication number
WO2020132909A1
WO2020132909A1 PCT/CN2018/123686 CN2018123686W WO2020132909A1 WO 2020132909 A1 WO2020132909 A1 WO 2020132909A1 CN 2018123686 W CN2018123686 W CN 2018123686W WO 2020132909 A1 WO2020132909 A1 WO 2020132909A1
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WIPO (PCT)
Prior art keywords
wiring board
metal
chip
wiring
board
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PCT/CN2018/123686
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English (en)
French (fr)
Inventor
符会利
郭茂
张晓东
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2018/123686 priority Critical patent/WO2020132909A1/zh
Priority to CN201880099876.2A priority patent/CN113169153B/zh
Publication of WO2020132909A1 publication Critical patent/WO2020132909A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Definitions

  • the invention relates to the technical field of semiconductors, in particular to a chip packaging structure.
  • Chips are already standing devices in electronic equipment.
  • the functional devices of the electronic equipment can be modularized, thereby reducing the design and manufacturing costs of the electronic equipment; on the other hand, by integrating a large number of The circuit can reduce the volume of electronic equipment, especially for electronic equipment (such as mobile phones) in the consumer field.
  • Smartphones are currently the most popular consumer electronic devices. As a consumer-oriented media terminal device, whether it is easy to carry and operate is an important indicator to measure the pros and cons of smart phones. In order to easily put the smartphone in the trouser pocket or allow consumers to operate it with one hand, the plane area of the smartphone cannot be made too large, and reducing the plane area of the smartphone can be achieved by reducing the plane area occupied by the chip .
  • POP packaging is usually used for packaging smartphone chips. In smartphones, it is usually necessary to equip multiple types of chips, such as processor chips and memory chips.
  • POP packaging proposes to stack a variety of chip packages up and down to form a new chip entity.
  • the packaging structure shown in FIG. 1 includes a memory chip package and a processor chip package.
  • the memory chip package is disposed above the processor chip package.
  • the memory chip 2 is fixed on the substrate 6.
  • the processor chip 1 is also called a system chip (System on Chip, SOC for short), and is fixed on the substrate 7.
  • the substrate 6 and the substrate 7 are provided with metal wiring, and the memory chip 2 and the processor chip 1 are communicatively connected to the respective substrates through jumpers (Wired Bonding) or pads provided on the bottom thereof.
  • a redistribution layer 3 is also provided between the processor chip 1 and the memory chip 2. Pads (not shown) are provided on both the upper and lower surfaces of the redistribution layer 3, and metal wiring is provided inside the redistribution layer 3.
  • the substrate 6 is in contact with the redistribution layer 3 via solder balls 8, and the redistribution layer 3 is in contact with the substrate 7 via solder balls 4.
  • the processor chip 1 when the processor chip 1 is to read data from the memory chip 2, the read data sequentially passes through the substrate 6, the solder ball 8, the redistribution layer 3, the solder ball 4 and the substrate 7 is transferred to the processor chip 1.
  • POP packaging is not only used for this combination of processor chips and memory chips.
  • Various chips in electronic devices can be stacked and sealed into a chip entity by POP packaging.
  • POP packaging is equivalent to using the space in the thickness direction to reduce the occupation of the plane space of the electronic device by the chip.
  • one of the most intuitive results of using POP packaging is that the plane size of smart phones becomes smaller, and even high-performance smart phones equipped with multiple functional chips can be controlled by one hand.
  • an embodiment of the present invention provides a packaging structure.
  • the packaging structure includes a first chip and a second chip.
  • the second chip is disposed on the top of the second wiring board, and the corresponding first chip is fixed on the bottom of the second wiring board.
  • the first chip is directly fixed on the bottom of the wiring board of the second chip, and a solder ball is additionally provided between the two to save space in the thickness direction of the packaging structure.
  • the first chip may be fixed to the bottom of the second wiring board through a chip bonding film.
  • the packaging structure further includes a first wiring board.
  • the first chip is provided on the first wiring board.
  • Both the first wiring board and the second wiring board are provided with metal wiring, and the surfaces of the first wiring board and the second wiring board are provided with interfaces communicating with the respective internal metal wiring for The metal wiring is electrically connected to the first chip or the second chip, or other circuit devices.
  • the interface between the surfaces of the first wiring board and the second wiring board may have various forms, such as pads, or may be exposed on the surfaces of the first wiring board and the second wiring board.
  • a piece of metal wiring may have various forms, such as pads, or may be exposed on the surfaces of the first wiring board and the second wiring board.
  • the first chip may be electrically connected to the interface on the surface of the first wiring board in various ways.
  • the first chip may be electrically connected to the pad on the top surface of the first wiring board through a wire (Wired Bonding); for another example, the first chip may be exposed to the first pad through the bottom pad
  • the metal wiring on the top surface of a wiring board is in direct contact.
  • the second chip may also be electrically connected to the metal wiring in the second wiring board by various methods.
  • an interconnection structure may be provided between the first wiring board and the second wiring board for connecting the metal wiring in the first wiring board and the second wiring board.
  • the interconnection structure may be a metal post provided between the first wiring board and the second wiring board; or, it may be a plastic package penetrating between the first wiring board and the second wiring board The material is plated with metal perforations.
  • the top of the first wiring board and the bottom of the second wiring board are provided with interfaces corresponding to the interconnection structure.
  • the interface may be a pad, or a metal wiring exposed on the surface, and communicate with the interconnection structure through soldering or direct contact.
  • the arrangement of the interconnect structure needs to avoid the first chip. Then, if the interconnection structure is realized by metal pillars, the metal pillars are arranged in a ring shape around the first chip.
  • This arrangement can increase the stability of the packaging structure, and can make the stress distribution in the thickness direction of the packaging structure more uniform, and avoid cracking.
  • the ring shape is not limited to a ring shape, and may be various shapes such as a triangular ring, a rectangular ring, or even an irregular shape surrounding the first chip. In a preferred embodiment, the ring shape may be a regular pattern centered on the first chip.
  • the second chip and the first chip are a structure stacked on top of each other.
  • the second chip above the first chip needs to communicate with the first chip, and also needs to communicate with the outside of the packaging structure. Therefore, the metal pillars for connecting the first wiring board and the second wiring board can be divided into two categories: the first metal pillar and the second metal pillar.
  • the metal wiring in the first wiring board is also divided into three categories: first metal wiring, second metal wiring and third metal wiring.
  • the second metal wiring is connected to the second metal pillar, the second metal wiring is also in communication with the one chip, and the second metal wiring and the second metal pillar constitute the first Part of the signal path between the chip and the second chip;
  • the third metal wiring is connected to the first metal post, the third metal wiring is also connected to the pad at the bottom of the first wiring board, the first The three-metal wiring and the first metal pillar form a part of the signal path that the second chip communicates with the outside of the packaging structure;
  • the first metal wiring is not connected to the metal pillar, and the first metal wiring Since the first chip is connected to the pad at the bottom of the first wiring board, the first metal wiring constitutes a part of a signal path that communicates between the first chip and the outside of the packaging structure.
  • the packaging structure provided by the embodiment of the present invention is mounted as a chip entity obtained after packaging on a carrier board of the electronic device.
  • the carrier board is usually a printed circuit board.
  • FIG. 1 is a schematic diagram of POP packaging in the prior art
  • FIG. 2 is a schematic diagram of a packaging structure according to an embodiment of the invention.
  • FIG. 3 is a schematic diagram of a packaging structure provided by another embodiment of the present invention.
  • FIG. 5 is a schematic diagram of an electronic device loaded with a packaging structure of an embodiment of the present invention.
  • An embodiment of the present invention provides a packaging structure.
  • the packaging structure two or more chips are packaged together.
  • these chips are packaged one above the other, that is, at least one chip is packaged on top of another chip.
  • top and bottom are involved. It should be noted that the top and bottom here are determined according to the position of the chip in the packaging structure.
  • a chip refers to an entity obtained by packaging a die.
  • the package structure provided by the embodiment of the present invention includes a first chip 10 and a second chip 20.
  • the first chip 10 is provided on the first wiring board 12.
  • the second chip 20 is provided on the second wiring board 22.
  • the second wiring board 22 is provided on top of the first chip 10.
  • the first chip 10, the second chip 20, the first wiring board 12 and the second wiring board 22 constitute a layered structure.
  • the first wiring board 12 and the second wiring board 22 may be a multilayer structure composed of an insulating medium. On the surfaces of the first wiring board 12 and the second wiring board 22, or on one or more layers, conductive sheets made of metal materials are arranged. Vias are provided between different layers of the first wiring board 12 and the second wiring board 22, and these through holes pass through different layers or even surfaces of the first wiring board 12 and the second wiring board 22.
  • the perforation is filled or coated with metal.
  • the metal in the perforation communicates with the conductive sheet on the layer.
  • the metal in the through-hole and the conductive sheet on the layer are collectively referred to as metal wiring.
  • the metal wiring forms a signal path in the first wiring board 12 and the second wiring board 22.
  • the metal pillar, metal sheet, conductive sheet and metal wiring involved in the embodiments of the present invention may be made of various metals such as metallic copper.
  • the first wiring board 12 and the second wiring board 22 may be substrates (Substrate) or heavy wiring boards (ReDistribution Layer (RDL for short). Both the substrate and the redistribution board are multi-layer structures, but in comparison, the substrate contains glass fiber, and the line width and line spacing of the metal wiring are more than 10um (including the horizontal distance and vertical distance); while the redistribution board does not Glass fiber, the width and spacing of metal wiring can be 5um. Therefore, if considering the saving of the thickness of the entire chip, the first wiring board 12 and the second wiring board 22 can select the rewiring board at the same time.
  • substrate Substrate
  • RDL Resource Layer
  • the chip stack packaging structure is usually used in the field of mobile phone chips.
  • the second chip 20 above is usually a memory chip.
  • the memory chip For mobile phone chip manufacturers, it is common for the memory chip to be purchased from a third party, and the purchased memory chip is usually packaged with the substrate.
  • a packaging entity, this packaging entity is also known as Qualified Device Packaging (Known-Good Package, referred to as KGP) in the industry. Since the KGP has already provided a substrate for the memory chip, and a pad is reserved at the bottom of the substrate as a signal interface, if the package is removed at this time and the substrate is replaced with a rewiring board, it will bring a lot of additional costs.
  • KGP Qualified Device Packaging
  • the second wiring board 22 may be a substrate, and the first wiring board 12 is a heavy wiring board.
  • the first wiring board 12 and the second wiring board 22 may adopt various process combinations, for example, it may even be considered to use a semiconductor substrate (Interposer), which should not constitute the present invention Implementation limits.
  • the first chip 10 and the second chip 20 are coupled to the metal wiring in the first wiring board 12 and the second wiring board 22 through pads 14 and 24 on the bottoms, respectively.
  • a metal post 25 is also arranged between the first wiring board 12 and the second wiring board 22. Both ends of the metal pillar 25 are respectively coupled to the signal paths in the first wiring board 12 and the second wiring board 22.
  • a plurality of pads 125 are provided on the bottom of the first wiring board 12, and the pads 125 are used as external interfaces of the packaging structure provided by the embodiment of the present invention.
  • the packaging structure provided in the embodiment of the present invention is installed in an electronic device, and the pad 125 is fixedly connected to a PCB (Printed Circuit Board) of the electronic device through solder balls.
  • PCB Print Circuit Board
  • the metal wiring in the first wiring board 12 includes a first metal wiring 122, a second metal wiring 124, and a third metal wiring 126.
  • the metal pillar 25 includes a first metal pillar 252 and a second metal pillar 254.
  • the first metal wiring 122 communicates with the pad 14 at the bottom of the first chip 10 and the pad 125 at the bottom of the first wiring board 125 for implementing the first chip 10 and the package structure provided by the embodiment of the present invention Signals of the circuit.
  • the second metal wiring 124 communicates with the second metal post 254 and the pad 14 at the bottom of the first chip 10 for implementing signal communication between the first chip 10 and the second chip 10.
  • the third metal wiring 126 communicates with the first metal post 252 and the pad at the bottom of the first wiring board 12 for implementing signal communication between the second chip 20 and a circuit outside the packaging structure .
  • the metal posts 25 are arranged in a ring shape around the first chip 10, and the first metal posts 252 and the second metal posts 254 are on different rings.
  • the ring formed by the metal posts 25 may be a circular ring, a rectangular ring, or even a ring with irregular patterns.
  • the first chip 10 is to be affixed to the bottom of the second wiring board 22, so the pad or pin arrangement at the bottom of the second wiring board 22 must reserve space for the first chip 10 Therefore, the metal posts 25 corresponding to the pads or pins on the bottom of the second wiring board 22 also need to be arranged around the first chip 10.
  • the second metal post 254 communicating with the first chip 10 is required, as opposed to only communicating with the pad at the bottom of the first wiring board 12
  • the first metal pillars 252 may be arranged closer to the first chip.
  • the first metal pillar 252 and the second metal pillar 254 are arranged in two rings of different sizes, and the ring arrangement of the first metal pillar 252 surrounds the first chip 10 and all The second metal pillars 254 are arranged in a ring shape.
  • both the first chip 10 and the second chip 20 are coupled to the metal wiring in the wiring board through pads provided at the bottom.
  • the chip may be coupled to the metal wiring on the wiring board through a jumper (Wired Bonding) on the top or side.
  • a jumper 23 is connected to the pad 24.
  • the jumper 23 is connected to the first metal post 252 or the second metal post 254 through the metal wiring on the second wiring board 22.
  • the second chip 20 is connected to the metal wiring in the second wiring board 22 by a jumper, which will increase the space requirement above the second chip 20, that is, increase the chip thickness.
  • the second chip 20 may be a purchased KGP. If the purchased KGP uses the jumper connection method, if the KGP is disassembled and the connection method of the second chip and the second wiring board 22 is changed, this will bring additional process and design costs, so it is not necessary To change the chip connection in KGP.
  • the first chip 10 is directly mounted on the bottom of the second wiring board 20, but is not disposed between the first chip 10 and the second chip 20 A layer of solder balls, or carrying an additional wiring board, no matter how the chip connection method in KGP, this has reduced the thickness of the entire package structure.
  • the first chip 10 may be fixed on the bottom of the second wiring board 20 by adhesive.
  • the adhesive here may be a die attach film (Die Attach Film, DAF for short) that is usually used to fix the bare chip in the chip.
  • the first wiring board 12 and the second wiring board 22 communicate with each other through a metal post 25.
  • the gap between the first wiring board 12 and the second wiring board 22 may be filled with an insulating medium (such as silicon dioxide, etc.).
  • a through hole (Via) connecting the first wiring board 12 and the second wiring board 22 may be formed in the insulating medium by plating in the through hole or Fill the metal to form the signal path between the first wiring board 12 and the second wiring board 22.
  • the use of metal pillars will make the process simpler and cheaper. For details, refer to the method for generating a package structure provided in the embodiments of the present invention provided in FIGS. 4a to 4h.
  • Step a Please refer to FIG. 4a to fix the KGP on the carrier board 30 with adhesive.
  • KGP is a packaged entity that includes the second chip 20 and the second wiring board 22 that is purchased.
  • the second chip 20 and the second wiring board 22 are filled with plastic encapsulation material.
  • the top of the KGP is in contact with the surface of the carrier board, and the side where the second wiring board 22 is located faces upward.
  • Step b Referring to FIG. 4b, fix the first chip 10 on the second wiring board 22.
  • the top of the first chip 10 is bonded to the second wiring board 22 by adhesive, such as DAF.
  • adhesive such as DAF.
  • the bottom of the first chip 10, that is, the side with the pads 14 is upward, or away from the second chip 20.
  • Step c Please refer to Figure 4c to fabricate a metal pillar array
  • the metal pillar array includes a base 29, and a plurality of metal pillars protruding from one side of the base.
  • the metal array may be made of the same metal, such as copper, and formed in one piece.
  • Various methods can be used to prepare the metal pillar array, but if the cost is considered, the existing equipment and processes in the packaging factory can be considered. For example, an etching process can be used to etch a whole metal plate by etching Come out of the metal column. It is easy to understand that the metal column array can be pre-made or purchased from a third party, and does not need to be produced at the current moment.
  • Step d Referring to FIG. 4d, buckle the metal column array on the KGP.
  • the metal array is fastened on the KGP, the metal post 25 surrounds the first chip in the center, and the substrate 29 is bridged above the first chip 10.
  • the metal post 25 is aligned with the metal wiring exposed on the surface of the second wiring board 22.
  • the surface of the second wiring board 22 may also be formed with a metal structure similar to a pad, and the metal post 25 and the metal wiring may be fixedly coupled by solder balls.
  • the metal pillars 25 are on the two sides of the first chip 10. However, in actual products, a plurality of metal pillars 25 may be arranged in a ring shape to surround the first chip 10 in the center.
  • Step e Please refer to Figure 4e for plastic packaging.
  • Step f Referring to FIG. 4f, the structure shown in FIG. 4e is ground to expose the pads on the bottom of the first chip 10.
  • the base 29 of the metal pillar array, the molding compound between the base 29 and the first chip 10, and the metal pillar 25 above the bottom surface of the first chip 10 are polished until the first A pad 14 at the bottom of the chip 10.
  • Step g Referring to FIG. 4g, the first wiring board 12 is prepared.
  • the second wiring board 12 generally includes metal wiring, and an insulating material (for example) surrounding the metal wiring. Therefore, an insulating material can be produced layer by layer on the surface of the first chip 10 and the surface of the plastic encapsulation material that wraps the first chip 10 by coating or growth.
  • Metal wiring is arranged on one or more layers of insulating material, and multiple layers of insulating material are perforated, and the perforations are filled or plated with metal to form metal wiring connecting different layers.
  • each metal post 25 is integrally formed, and its predecessor is a pre-formed array of metal posts.
  • the metal post can be simply fixed in the packaging structure through the grinding process, and Connect and support two chips. Compared with the electrochemical method for generating metal signal lines, the process cost is lower and the structure is more stable.
  • the entire package structure is equivalent to being divided into two layers: the first layer includes the first chip and the first wiring board; the second layer includes the second chip and the second wiring board.
  • the first layer may also include multiple first chips, the multiple first chips may be arranged in parallel on the first wiring board, or may be superimposed, one or more first chips Superimposed on another one or more first chips.
  • the plurality of first chips may directly communicate with each other, or communicate with each other through the first wiring board.
  • the second layer may include multiple second chips, and the multiple second chips may be arranged in parallel on the second wiring board, or may be superimposed.
  • the plurality of second chips may directly communicate with each other, or may communicate with each other through the second wiring board.
  • FIG. 5 is a schematic diagram of the packaging structure provided on the carrier board in the electronic device provided by the embodiment of the present invention.
  • the pad 125 at the bottom of the first wiring board 12 is fixedly connected to the carrier board of the electronic device through solder balls, and performs data communication with other chips or devices on the carrier board through the circuit on the carrier board.
  • the most common carrier board is a printed circuit board (Printed Circuit Board).

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种封装结构，包括布线板（22），以及贴附于所述布线板（22）上下两面的两个芯片（10、20）。由于上下两个芯片（10、20）直接贴附于所述布线板（22）上，从而减小了芯片封装的厚度。

Description

一种芯片的封装结构 技术领域
本发明涉及半导体技术领域，特别涉及一种芯片的封装结构。
背景技术
芯片，已经是电子设备中的常备器件。通过将电子设备运行中需要的功能电路集成在小小的芯片中，一方面可以使得电子设备的功能器件模块化，从而降低了电子设备的设计和制造成本；另一方面通过在芯片中集成大量的电路，能够缩减电子设备的体积，尤其是对消费者领域的电子设备(比如手机)有重大的意义。
智能手机是当前最为普及的消费者电子设备。作为面向消费者的媒体终端设备，是否便于携带和操作是衡量智能手机优劣的一个重要指标。为了能轻松的将智能手机放入裤兜，或者允许消费者单手操作，智能手机的平面面积就不能做的过大，而削减智能手机的平面面积是可以通过削减芯片占用的平面面积来实现的。
为了降低芯片占用的平面面积，在芯片领域有一种叫做POP(Package on Package，堆叠封装)的封装技术。POP封装通常用于智能手机芯片的封装。在智能手机中通常需要装备多种类型的芯片，比如处理器芯片，存储器芯片等。POP封装提出的就是将多种类型芯片的封装体上下堆叠在一起，组成一个新的芯片实体。比如，图1所示的封装结构中包括存储器芯片封装体和处理器芯片封装体。所述存储器芯片封装体被设置于处理器芯片封装体的上方。存储器芯片2被固定在基板6上。所述处理器芯片1又被称为系统芯片(System on Chip,简称SOC)，固定在基板7上。基板6和基板7中设置有金属布线，存储器芯片2和处理器芯片1通过跳线(Wired Bonding)或者设置在其底部的接垫(Pad)与各自的基板通信连接。在所述处理器芯片1和存储器芯片2之间还设置有重布线层3。所述重布线层3的上下表面均设有接垫(图中未显示)，所述重布线层3的内部设置有金属布线。所述基板6通过焊球8与所述重布线层3相接，所述重布线层3通过焊球4与所述基板7相接。在图1所示的POP封装结构中，当处理器芯片1要从存储器芯片2中读取数据时，读取的数据依次经过基板6，焊球8，重布线层3，焊球4和基板7被传递至处理器芯片1中。
POP封装并不是只能用于处理器芯片和存储器芯片的这一组合，在电子设备中的各种芯片都可以通过POP封装的这种方式堆叠封成成一个芯片实体。使用POP封装就相当于利用厚度方向的空间来减少芯片对电子设备平面空间的占用。在智能手机领域，使用POP封装的最直观的一个结果就是智能手机的平面尺寸变小，即使是搭载有多种功能芯片的高性能智能手机也变得能够一手掌控。
不过，POP封装的缺点也十分明显，那就是会带来电子设备的厚度的提升。在智能手机领域，厚度的提升会影响美观，这也很不利于销售。因此，如何进一步的减小POP封装的厚度，也是业界关注的重点。
发明内容
为了解决现有技术存在的问题，本发明实施例提供了一种封装结构。在所述封装结构中，至少两块芯片被上下叠加着封装在一起。所述封装结构包括第一芯片和第二芯片。所述第二芯片被设置在第二布线板的顶部，而对应的所述第一芯片被固定在所述第二布线板的底部。在本发明实施例提供的封装结构中，所述第一芯片被直接固定在第二芯片的布线板的底部，二者之间额外设置焊球，节省了封装结构在厚度方向上的空间。
在可选择的实施例中，所述第一芯片可以通过芯片粘结膜固定在所述第二布线板的底部。
在可选择的实施例中，所述封装结构还包括第一布线板。所述第一芯片被设置在所述第一布线板上。所述第一布线板和所述第二布线板中均设置有金属布线，所述第一布线板和所述第二布线板的表面设置有与各自内部的金属布线相通的接口，用于将所述金属布线与所述第一芯片或第二芯片，或者其他电路器件电性连接。
所述第一布线板和所述第二布线板的表面的接口可以有多种形式，比如可以为接垫，又比如可以为暴露于所述第一布线板和所述第二布线板表面的一段金属布线。
在可选择的实施例中，所述第一芯片可以通过多种方式与所述第一布线板表面的接口电性连接。比如，所述第一芯片可以通过跳线(Wired Bonding)与处于第一布线板顶部表面的接垫电性连接；又比如，所述第一芯片可以通过底部的接垫与暴露于所述第一布线板顶部表面的金属布线直接接触。与所述第一芯片和所述第一布线板的电性连接的方式类似，第二芯片也可以采用多种方法与所述第二布线板内的金属布线电性连接。
在可选择的实施例中，所述第一布线板和第二布线板之间可以设置有互联结构，用于连通所述第一布线板和所述第二布线板内的金属布线。所述互联结构可以为设置于所述第一布线板和所述第二布线板之间的金属柱；或者，也可以是贯穿所述第一布线板和所述第二布线板之间的塑封材料的镀有金属的穿孔。对应的，所述第一布线板的顶部，和所述第二布线板的底部设置有与所述互联结构对应的接口。所述接口可以为接垫，或者暴露于表面的金属布线，通过焊锡或者直接接触的方式连通所述互联结构。
从工艺成本的角度来说，采用金属柱作为互联结构的加工成本较低。
由于第一芯片贴在所述第二布线板的底部表面，因此互联结构的设置需要避开所述第一芯片。然后，如果互联结构是通过金属柱实现的，那么所述金属柱围绕所述第一芯片排列成环形。这样设置可以增加所述封装结构的稳定程度，能够使得封装结构的厚度方向的应力分布的更均匀，避免开裂。所述环形不限于圆环，可以为三角形环，矩形环等各种形状，甚至可以为围绕所述第一芯片的不规则形状。在较佳的实施例中，所述环形可以为以所述第一芯片为中心的规则图形。
在本发明实施例提供的封装结构中，所述第二芯片和第一芯片是一种上下叠加的结构。处于所述第一芯片上方的所述第二芯片需要与所述第一芯片进行信号互通，而且还需要与所述封装结构的外部进行信号互通。因此，用于连通第一布线板和第二布线板的金属柱可以分成两类：第一金属柱和第二金属柱。对应的，第一布线板中的金属布线也分成了三类：第一金属布线，第二金属布线和第三金属布线。其中，所述第二金属布线与所述第二金属柱相连，所述第二金属布线还与所述一芯片相通，所述第二金属布线和所述第二金属柱构成了所述第一芯片和所述第二芯片之间的信号通路的一部分；第三金属布线则与第一金属 柱相连，所述第三金属布线还与所述第一布线板底部的接垫相连，所述第三金属布线和所述第一金属柱构成了所述第二芯片与所述封装结构外部相通的信号路径的一部分；所述第一金属布线并不与金属柱相连，所述第一金属布线用于将所述第一芯片和所述第一布线板底部的接垫相连，因此，所述第一金属布线构成了所述第一芯片与所述封装结构外部相通的信号路径的一部分。
在电子设备中，本发明实施例提供的封装结构作为一个封装后得到的芯片实体，被安装在电子设备的载板上。所述载板通常是印刷电路板。当所述封装结构被安装在电子设备中时，所述第一布线板底部的接垫通过焊球与所述载板上的电路器件固定连接。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中的POP封装的示意图；
图2是本发明实施例的封装结构的示意图；
图3是本发明又一实施例提供的封装结构的示意图；
图4a～4g是本发明实施例提供的封装结构的加工流程图；
图5是装载了本发明实施例的封装结构的电子设备的示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
本发明实施例提供一种封装结构。在所述封装结构中，两个或两个以上的芯片封装在一起。并且，这些芯片采用的是一种上下叠加的封装方式，即至少一个芯片被封装至另一个芯片的上方。
在本发明实施例中，涉及有关“顶部”和“底部”的描述。需要注意的是，这里的顶部和底部是依照芯片在封装结构所处的位置来进行判定的。
在本发明实施例中，芯片是指将裸片(Die)封装后得到的实体。
参照图2，本发明实施例提供的封装结构包括第一芯片10和第二芯片20。所述第一芯片10被设置在第一布线板12上。所述第二芯片20被设置在第二布线板22上。所述第二布线板22被设置在所述第一芯片10的顶部。从而，所述第一芯片10、第二芯片20、第一布线板12和第二布线板22构成了一种上下层叠的结构。
所述第一布线板12和第二布线板22可以是由绝缘介质为主体构成的多层结构。在所述第一布线板12和所述第二布线板22的表面，或者一个或多个层上布设有金属材质构成的导电片。所述第一布线板12和第二布线板22的不同层间设置有穿孔(Via)，这些穿孔穿过所述第一布线板12和第二布线板22的不同的层，甚至表面。穿孔中填充或涂镀有金属。穿孔中的金属与层上的导电片连通。在本发明实施例中，穿孔中的金属与层上的导电片统 称为金属布线。所述金属布线在所述第一布线板12和所述第二布线板22内构成信号路径。
本发明实施例中涉及的金属柱、金属片、导电片和金属布线可以由金属铜等各种金属制成。
从工艺实现的角度来说，所述第一布线板12和第二布线板22可以是基板(Substrate)，也可以是重布线板(ReDistribution Layer，简称RDL)。基板和重布线板都是多层结构，但是相比较来说，基板含有玻璃纤维，其中的金属布线的线宽和线距在10um以上(包括水平距离和垂直距离)；而重布线板则没有玻璃纤维，其中的金属布线的线宽和线距能够做到5um。所以，如果从节省芯片整体的厚度来考虑，所述第一布线板12和第二布线板22可以同时选择重布线板。
但是从工业成本的角度来考量，芯片堆叠的封装结构通常用于手机芯片领域。而在手机芯片中，处于上方的第二芯片20通常为存储器芯片，对于手机芯片厂商来说，普遍存在着存储器芯片从第三方采购的情况，而采购的存储器芯片通常就已经与基板封装成了一个封装实体，这个封装实体在业界又被称为合格器件封装(Known-Good Package，简称KGP)。由于KGP中已经为存储器芯片设置了基板，并且在基板底部预留了接垫来作为信号接口，如果这时候拆除封装，并将基板替换成重布线板，会带来大量的额外成本。因此，从节省成本的角度考量，所述第二布线板22可以是基板，而第一布线板12则是重布线板。当然，未来面对半导体工艺中的各种需求，第一布线板12和第二布线板22可以采用各种工艺组合，比如，甚至可以考虑使用半导体基板(Interposer)，这些都不应构成本发明实施的限定。
继续参照图2，第一芯片10和第二芯片20通过各自底部的接垫(Pad)14和24，分别与第一布线板12和第二布线板22中的金属布线耦合。在所述第一布线板12和第二布线板22之间还布设有金属柱25。所述金属柱25的两端分别被耦合至所述第一布线板12和第二布线板22中的信号路径。
所述第一布线板12的底部设有多个接垫125，所述接垫125用于作为本发明实施例提供的封装结构的对外接口。具体的，在把本发明实施例提供的封装结构装设于电子设备中施，通过焊锡球将所述接垫125固定连接至电子设备的PCB板(Printed Circuit Board，印刷电路板)上。
可选择的，在本发明实施例中，所述第一布线板12中的金属布线包括第一金属布线122，第二金属布线124和第三金属布线126。所述金属柱25包括第一金属柱252和第二金属柱254。所述第一金属布线122连通第一芯片10底部的接垫14和所述第一布线板125底部的接垫125，用于实现所述第一芯片10与本发明实施例提供的封装结构外部的电路的信号互通。所述第二金属布线124连通所述第二金属柱254和所述第一芯片10底部的接垫14，用于实现所述第一芯片10和第二芯片10之间的信号互通。所述第三金属布线126连通所述第一金属柱252和所述第一布线板12底部的接垫，用于实现所述第二芯片20与所述封装结构外部的电路之间的信号互通。
在可选择的实施例中，金属柱25围绕第一芯片10排列成环形，第一金属柱252和第二金属柱254处于不同的环上。在可选择的实施例中，金属柱25排列成的环形可以为圆形环、矩形环甚至是不规则图形的环形。在本发明实施例中，第一芯片10要贴在第二布线板22的底部，因此第二布线板22底部的接垫或者引脚排布必须要给所述第一芯片10预留出空间，从而导致与第二布线板22底部的接垫或引脚对应的金属柱25也需要绕着第一芯片 10排布。当然，由于需要考虑到第一布线板12内的金属布线的排布空间，需要与第一芯片10连通的第二金属柱254，相对于仅需要与第一布线板12底部的接垫连通的第一金属柱252，可以排布的更靠近所述第一芯片。比如，在可选择的实施例中，所述第一金属柱252和第二金属柱254排列成大小不同的两个环形，第一金属柱252排列成的环形环绕所述第一芯片10和所述第二金属柱254排列成的环形。
图2中的封装结构中，第一芯片10和第二芯片20均是通过设置在底部的接垫与布线板中的金属布线耦合。但在可选择的实施方式中，芯片可以通过顶部或者侧部的跳线(Wired Bonding)来与布线板上的金属布线耦合。具体如图3所示，第二芯片20的顶部设有接垫24，接垫24上接有跳线23。所述跳线23通过第二布线板22上的金属布线，连接至第一金属柱252或第二金属柱254。
通常来说，第二芯片20采用跳线的方式连接第二布线板22中的金属布线，这会增加第二芯片20上方的空间需求，也就是提高了芯片厚度。但是正如前文所述，由于第二芯片20可能是采购来的KGP。如果，采购来的KGP中使用的是跳线连接的方式，如果将KGP拆解后改变第二芯片与第二布线板22的连接方法，这会带来额外的工艺和设计成本，因此可以不去改变KGP内的芯片连接方式。
在本发明实施例提供的图2和图3的封装结构中，第一芯片10直接贴装在第二布线板20的底部，而并没有在第一芯片10和第二芯片20之间再设置一层焊球，或者搭载额外的布线板，无论KGP中芯片连接方式是怎么样的，这都已经降低了整个封装结构的厚度。
可选择的，所述第一芯片10可以通过粘胶固定在第二布线板20的底部。这里的粘胶可以是通常用来固定芯片中的裸片的芯片粘结膜(Die Attach Film，简称DAF)。
在图2和图3提供的封装结构中，第一布线板12和第二布线板22之间通过金属柱25进行连通。在实际产品中，第一布线板12和第二布线板22之间的空隙有可能会填充绝缘介质(比如二氧化硅等)。就此，在可选择的实施例中，可以不使用金属柱25，而是在所述绝缘介质中形成连通第一布线板12和第二布线板22的穿孔(Via)，通过在穿孔中渡镀或者填充金属，来构成第一布线板12和第二布线板22之间的信号路径。不过，使用金属柱的话，在工艺上会更简单，成本低廉。具体的情参照图4a～图4h中提供的本发明实施例的封装结构的生成方法。
本发明实施例提供的封装方法，包括：
步骤a:请参照图4a，将KGP通过粘胶固定在载板30上。
KGP即采购来的包含第二芯片20和第二布线板22的封装实体。所述第二芯片20和第二布线板22周围填充有塑封材料。将所述KGP翻转过来，所述KGP的顶部与所述载板的表面接触，而所述第二布线板22所处的一侧朝上。
步骤b:请参照图4b，将第一芯片10固定在所述第二布线板22上。
通过黏胶，比如DAF将第一芯片10的顶部粘结在所述第二布线板22上。所述第一芯片10的底部，也就是有接垫14的一侧向上，或者说，背离所述第二芯片20。
步骤c:请参照图4c，制作金属柱阵列；
所述金属柱阵列包括基底29，以及突出于所述基底一侧的复数个金属柱。所述金属阵列可以采用同一种金属，比如铜，一体成型得到。金属柱阵列的制备可以用各种方法，但是如果考虑到成本，可以考虑利用封装工厂中已有的设备和工艺，比如，可以采用蚀刻的 工艺，在一整块金属板上通过蚀刻的方法蚀刻出金属柱来。容易理解的是，金属柱阵列可以预先制作完成，或者采购自第三方，而不需要在当前时刻才制作。
步骤d：请参照图4d，将金属柱阵列扣装在所述KGP上。
将金属阵列扣装在KGP上，所述金属柱25将第一芯片环绕在中心，基底29跨接在第一芯片10的上方。使得金属柱25对准暴露于第二布线板22的表面的金属布线。具体的，可以使得第二布线板22的表面也形成类似于接垫的金属结构，通过焊球来固定耦合金属柱25和金属布线。在本发明实施例中，金属柱25表现为处于第一芯片10两侧的形态。但是在实际产品中，复数个金属柱25可以排列成环形，将第一芯片10环绕在中心。
步骤e：请参照图4e，进行塑封。
将塑封材料35填满所述金属柱阵列和所述第一芯片10之间的间隙。
步骤f：参照图4f，对图4e中所示的结构进行研磨，露出第一芯片10的底部上的接垫。
在本发明实施例中，研磨掉金属柱阵列的基底29，基底29与第一芯片10之间的塑封材料，以及高出所述第一芯片10的底部表面的金属柱25，直到露住第一芯片10的底部的接垫14。
步骤g：参照图4g，制备第一布线板12。
第二布线板12通常包括金属布线，以及包裹所述金属布线的绝缘材料(比如)。因此可以通过涂覆或生长的方式在第一芯片10的表面，以及包裹所述第一芯片10的塑封材料的表面逐层生成绝缘材料。在绝缘材料的一个或多个层上排布金属布线，以及，在绝缘材料的多个层间穿孔，在穿孔中填充或者涂镀金属来形成连接不同的层的金属布线。
根据以上提供的封装方法可以看到，每一根金属柱25都是一体成型的，其前身为预先成型的金属柱阵列，通过研磨的工艺就可以简单的将金属柱固定于封装结构中，并连通和支撑两个芯片。相比用电化学的方法生成金属的信号线路，工艺成本更低，结构更稳固。
在本发明实施例中，整个封装结构相当于被分成了两层：第一层包括所述第一芯片和第一布线板；第二层包括所述第二芯片和第二布线板。在上文描述中，仅是以第一层包括了一个第一芯片、第二层包括了一个第二芯片为例进行说明。在实际产品中，第一层还可以包括多个第一芯片，所述多个第一芯片可以并行设置在所述第一布线板上，也可以采用叠加的方式，一个或多个第一芯片叠加在另一个或多个第一芯片上。多个第一芯片可以直接彼此连通，或者通过所述第一布线板相通。类似的，第二层可以包括多个第二芯片，多个第二芯片可以并行设置在所述第二布线板上，也可以采用叠加的方式。多个第二芯片之间可以直接互通，也可以通过第二布线板互通。
图5所示的是本发明实施例提供的封装结构装配于电子设备中的载板上的示意图。如图所示，第一布线板12底部的接垫125通过焊锡球与电子设备的载板固定连接，并通过所述载板上的电路与载板上的其它芯片或者设备进行数据通信。所述载板最常见的为印刷电路板(Printed Circuit Board)。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (13)

  1. 一种封装结构，其特征在于，包括第一芯片，第二芯片和第二布线板，所述第二芯片被布设于所述第二布线板上，所述第一芯片贴附于所述第二布线板的底部。
  2. 如权利要求1所述的封装结构，其特征在于，
    还包括第一布线板，所述第一布线板被设置在所述第二布线板下方，所述第一芯片被设置在所述第一布线板上，
    所述第一布线板和所述第二布线板内均设置有金属布线，
    所述第一芯片与所述第一布线板内的金属布线相通，所述第二芯片与所述第二布线板内的金属布线相通。
  3. 如权利要求2所述的封装结构，其特征在于，还包括金属柱，所述金属柱两端分别连接至所述第二布线板和所述第一布线板，所述金属柱的两端分别与所述第一布线板和所述第二布线板内的金属布线相通。
  4. 如权利要求3所述的封装结构，其特征在于，所述第二布线板的底部设置有与所述第二布线板内的金属布线相通的接垫，所述金属柱与所述第二布线板的接垫固定连接。
  5. 如权利要求4所述的封装结构，其特征在于，所述金属柱通过焊锡与所述第二布线板的接垫固定连接。
  6. 如权利要求3-5任一项所述的封装结构，其特征在于，所述第一布线板内的金属布线的一部分暴露于所述第一布线板的表面，所述金属柱与暴露于所述第一布线板表面的金属布线接触。
  7. 如权利要求3所述的封装结构，其特征在于，所述金属柱围绕所述第一芯片排列成环形。
  8. 如权利要求3所述的封装结构，其特征在于，所述第一布线板中包括第一金属布线，第二金属布线和第三金属布线，所述第一布线板的底部设置有接垫，所述金属柱包括第一金属柱和第二金属柱，所述第一金属布线连通所述第一芯片和所述第一布线板底部的接垫，所述第二金属布线连通所述第二金属柱和所述第一芯片，所述第三金属布线连通所述第一金属柱和第一布线板底部的接垫。
  9. 如权利要求8所述的封装结构，其特征在于，所述第一金属柱和第二金属柱分别围绕所述第一芯片排列成两个大小不同的环形，并且所述第一金属柱排列成的环形环绕所述第一金属柱排列成的环形。
  10. 如权利要求2所述的封装结构，其特征在于，所述第二布线板和第一布线板之间设置有互联结构，所述互联结构连通所述第二布线板和所述第一布线板。
  11. 如权利要求1所述的封装结构，其特征在于，所述第一芯片被芯片粘结膜固定在所述第二布线板的底部。
  12. 一种电子设备，其包括载板，和承载在所述载板上的如权利要求1-11任一项所述封装结构。
  13. 如权利要求12所述的电子设备，其特征在于，所述封装结构通过焊球被固定在所述载板上，并且所述封装结构通过所述焊球与所述载板上的电路或者器件相通。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220375809A1 (en) * 2019-09-16 2022-11-24 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140210099A1 (en) * 2013-01-30 2014-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged Semiconductor Devices and Packaging Methods
CN105118823A (zh) * 2015-09-24 2015-12-02 中芯长电半导体（江阴）有限公司 一种堆叠型芯片封装结构及封装方法
CN106558574A (zh) * 2016-11-18 2017-04-05 华为技术有限公司 芯片封装结构和方法
CN107808855A (zh) * 2016-09-09 2018-03-16 力成科技股份有限公司 芯片封装结构及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9601353B2 (en) * 2014-07-30 2017-03-21 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with molding structures and methods of forming the same
CN105047617B (zh) * 2015-06-09 2018-01-16 华进半导体封装先导技术研发中心有限公司 一种整体堆叠封装结构及其制作方法
CN106876363A (zh) * 2017-03-13 2017-06-20 江苏长电科技股份有限公司 3d连接的扇出型封装结构及其工艺方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140210099A1 (en) * 2013-01-30 2014-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged Semiconductor Devices and Packaging Methods
CN105118823A (zh) * 2015-09-24 2015-12-02 中芯长电半导体（江阴）有限公司 一种堆叠型芯片封装结构及封装方法
CN107808855A (zh) * 2016-09-09 2018-03-16 力成科技股份有限公司 芯片封装结构及其制造方法
CN106558574A (zh) * 2016-11-18 2017-04-05 华为技术有限公司 芯片封装结构和方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220375809A1 (en) * 2019-09-16 2022-11-24 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US11901252B2 (en) * 2019-09-16 2024-02-13 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same

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