WO2020113797A1 - 柔性阵列基板及其制作方法、显示面板 - Google Patents

柔性阵列基板及其制作方法、显示面板 Download PDF

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Publication number
WO2020113797A1
WO2020113797A1 PCT/CN2019/072492 CN2019072492W WO2020113797A1 WO 2020113797 A1 WO2020113797 A1 WO 2020113797A1 CN 2019072492 W CN2019072492 W CN 2019072492W WO 2020113797 A1 WO2020113797 A1 WO 2020113797A1
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Prior art keywords
substrate
flexible
layer
array substrate
bending
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English (en)
French (fr)
Inventor
柯霖波
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/331,975 priority Critical patent/US10833106B2/en
Publication of WO2020113797A1 publication Critical patent/WO2020113797A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/80—Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7426—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/744—Details of chemical or physical process used for separating the auxiliary support from a device or a wafer
    • H10P72/7442—Separation by peeling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to the field of display technology, in particular to a flexible array substrate, a manufacturing method thereof, and a display panel.
  • the traditional glass substrate is difficult to meet the requirements of future flexible display technology due to its own hardness and brittleness.
  • the polymer film substrate has the characteristics of light weight, flexibility and excellent comprehensive performance, which can well meet the flexibility requirements of the display technology. Therefore, flexible polymer substrate materials are the first choice for flexible display technologies in the future.
  • Polyimide Polyimide
  • PI polyimide
  • TFT Film Transistor
  • An object of the present invention is to provide a flexible array substrate, a manufacturing method thereof, and a display panel.
  • the flexible array substrate uses a patterned filling layer to reduce the thickness of the flexible substrate in the bending area, and uses a peeling layer to separate the flexible substrate and the filling layer, so that the metal trace layer in the bending area tends to the stress neutral plane, Thus, a flexible array substrate with excellent bending performance is realized. While maintaining the excellent performance of the polyimide material, the flexible substrate thinning in the bending area is used to improve the bending performance of the flexible array substrate in the bending area, thereby avoiding the possible increase of internal stress and metal walking in the bending area Bending and breaking problems.
  • the present invention provides a flexible array substrate, which includes: a flexible substrate; the flexible array substrate is divided into a non-bending area and a bending area, and the flexible substrate is self-owned The non-bending area extends to the bending area, and the flexible substrate in the bending area has a patterned structure.
  • the thickness of the flexible substrate in the bending region is smaller than the thickness of the flexible substrate in the non-bending region.
  • the flexible substrate includes: a first flexible sub-substrate, an inorganic layer and a second flexible sub-substrate stacked in a stack; the first in the bending region
  • the flexible sub-substrate has a groove facing the inorganic layer so that the thickness of the flexible substrate in the bending region is smaller than the thickness of the flexible substrate in the non-bending region.
  • the opening of the groove is rectangular, or inverted trapezoid, or semi-cylindrical.
  • the present invention provides a method for manufacturing a flexible array substrate as described above.
  • the method includes the following steps: (1) providing a supporting substrate, and coating an organic material on the supporting substrate, Forming a filling layer; (2) depositing a peeling layer on the filling layer, and patterning the filling layer and the peeling layer located in the bending region; (3) on the supporting substrate and A first flexible sub-substrate is covered on the peeling layer; (4) an inorganic layer is deposited on the first flexible sub-substrate, and a second flexible sub-substrate is provided on the inorganic layer; (5) A thin film transistor layer is provided on the second flexible sub-substrate; (6) The support substrate and the first flexible sub-substrate are separated using laser lift-off technology.
  • the organic material is one of polyethylene terephthalate and polycarbonate.
  • the viscosity of the organic material used in the filling layer is 1000-3000 mPa ⁇ s, and the thermal decomposition temperature is higher than 450 degrees.
  • the material used for the peeling layer is one of silicon dioxide and silicon nitride.
  • the inorganic layer is a silicon dioxide structure or a stacked structure of silicon dioxide and silicon nitride.
  • the present invention provides a display panel including the flexible array substrate as described above.
  • the advantage of the present invention is that the flexible array substrate, its manufacturing method, and display panel.
  • the flexible array substrate uses a patterned filling layer to reduce the thickness of the flexible substrate in the bending area, and uses a peeling layer to separate the flexible substrate and the filling layer, so that the metal trace layer in the bending area tends to the stress neutral plane,
  • a flexible array substrate with excellent bending performance is realized.
  • the flexible substrate thinning in the bending area is used to improve the bending performance of the flexible array substrate in the bending area, thereby avoiding the possible increase of internal stress and metal walking in the bending area Bending and breaking problems.
  • the structure of the flexible array substrate meets the requirements of high flexibility, heat resistance, high water and oxygen resistance, and has broad development prospects.
  • FIG. 1 is a schematic structural diagram of a flexible array substrate in an embodiment of the invention.
  • FIGS. 2A to 2C are schematic diagrams of the patterned structure of the first flexible sub-substrate of the flexible array substrate in the embodiment of the present invention.
  • FIG. 3 is a flowchart of steps of a method for manufacturing a flexible array substrate in an embodiment of the invention.
  • 4A to 4I are schematic process diagrams of the method for manufacturing the flexible array substrate in the embodiment of the present invention.
  • Embodiments of the present invention provide a flexible array substrate, a manufacturing method thereof, and a display panel. Each will be described in detail below.
  • FIG. 1 is a schematic structural diagram of a flexible array substrate in an embodiment of the present invention.
  • 2A to 2C are schematic diagrams of the patterned structure of the first flexible sub-substrate of the flexible array substrate in the embodiment of the present invention.
  • the present invention provides a flexible array substrate, which includes: a flexible substrate 200.
  • the flexible array substrate is divided into a non-bending area A and a bending area B, the flexible substrate 200 extends from the non-bending area A to the bending area B, and the bending area B
  • the flexible substrate 200 has a patterned structure.
  • the flexible substrate 200 includes a first flexible sub-substrate 110, an inorganic layer 101, and a second flexible sub-substrate 120 that are stacked.
  • the flexible substrate 200 is a double-layer flexible sub-substrate.
  • the flexible substrate 200 may also include a multilayer flexible sub-substrate.
  • Both the first flexible sub-substrate 110 and the second flexible sub-substrate 120 use organic materials, for example, one of polyethylene terephthalate and polycarbonate.
  • organic materials for example, one of polyethylene terephthalate and polycarbonate.
  • polyimide (PI) material is used, which has the characteristics of high temperature resistance, wide use temperature range, no obvious melting point, high insulation performance, and stable dielectric constant.
  • the inorganic layer 101 may be a water-oxygen barrier layer to prevent external moisture or oxygen from entering the flexible array substrate, thereby affecting the service life of the flexible array substrate.
  • the inorganic layer 101 is a silicon dioxide structure or a stacked structure of silicon dioxide and silicon nitride.
  • the first flexible sub-substrate 110 in the bending region B has a groove 103 facing the inorganic layer 101, so that the thickness of the flexible substrate 200 in the bending region B is smaller than that of the non- The thickness of the flexible substrate 200 in the bending region A.
  • the opening of the groove 103 has a rectangular shape, an inverted trapezoid shape, or a semi-cylindrical shape, as shown in FIGS. 2A to 2C.
  • the first flexible sub-substrate 110 of the bending region B has a patterned structure, a height difference is formed with the flexible substrate 200 of the non-bending region A, that is, the flexible substrate of the bending region B
  • the thickness of the bottom 200 is smaller than the thickness of the flexible substrate 200 in the non-bending area A, therefore, the flexible substrate 200 in the bending area B is thinned.
  • FIG. 3 is a flowchart of steps of a method for manufacturing a flexible array substrate in an embodiment of the present invention.
  • 4A to 4I are schematic process diagrams of the method for manufacturing the flexible array substrate in the embodiment of the present invention.
  • the present invention provides a method for manufacturing a flexible array substrate as described above.
  • the method includes the following steps:
  • Step S310 providing a supporting substrate, coating an organic material on the supporting substrate to form a filling layer.
  • the material used for the supporting substrate 100 is one of glass, metal, and non-metal.
  • the organic material is uniformly coated on the clean and smooth support substrate, and a film is formed by baking to obtain the filling layer 111.
  • the organic material is one of polyethylene terephthalate and polycarbonate.
  • the viscosity of the organic material used for the filling layer 111 is 1000-3000 mPa ⁇ s, and the thermal decomposition temperature is higher than 450 degrees.
  • the organic material is applied to form a wet film with a thickness of 30 microns to 100 microns, a film formation temperature of 200 degrees to 400 degrees, and a film formation time of 0.1 hours to 1 hour. After the wet film is baked, the filling layer 111 is formed.
  • Step S320 deposit a peeling layer on the filling layer 111, and pattern the filling layer 111 and the peeling layer 112 in the bending region B.
  • the material used for the peeling layer 112 is one of silicon dioxide and silicon nitride.
  • the thickness of the peeling layer 112 is 1000 angstroms to 3000 angstroms.
  • dry etching technology is used.
  • the width of the remaining filling layer 111 and the peeling layer 112 after patterning is 0.1 mm to 1 mm.
  • Step S330 covering a first flexible sub-substrate 110 on the supporting substrate 100 and the peeling layer 112.
  • this step further includes: uniformly coating the polyamic acid solution on the support substrate 100 and the peeling layer 112, forming a film by baking at a low temperature, and removing the organic solvent; heating and dehydrating the film in a high purity nitrogen atmosphere A high-temperature thermal imidization reaction occurs to produce the first flexible sub-substrate 110, that is, the first polyimide film layer.
  • the thickness of the wet film formed by coating is 50 microns to 300 microns
  • the baking temperature is 20 degrees to 80 degrees
  • the baking time is 1 minute to 20 minutes
  • the heating rate is 5 to 20 per minute when heating and dehydrating.
  • the curing temperature is 350 degrees to 550 degrees
  • the curing time is 0.1 hours to 1 hour, and then cooled to room temperature.
  • Step S340 deposit an inorganic layer 101 on the first flexible sub-substrate 110, and set a second flexible sub-substrate 120 on the inorganic layer 101.
  • the inorganic layer 101 is a first barrier layer
  • the first barrier layer is a silicon dioxide structure or a stacked structure of silicon dioxide and silicon nitride.
  • the thickness of the first barrier layer is 1000-6000 angstroms.
  • a second flexible sub-substrate 120 is provided on the first barrier layer.
  • the method for forming the second flexible sub-substrate 120 is the same as the method in step S330, wherein the wet film thickness, baking temperature, and baking time are the same as the parameters in the embodiment in step S330.
  • Step S350 A thin film transistor layer 130 is provided on the second flexible sub-substrate 120.
  • a second barrier layer 102 may be further formed on the second flexible sub-substrate 120 (ie, the second polyimide film layer).
  • the method for forming the second barrier layer 102 is the same as the method for forming the inorganic layer 101 (that is, the first barrier layer) in step S340, including the heating rate, the curing temperature, and the curing time.
  • Step S360 separating the supporting substrate 100 and the first flexible sub-substrate 110 using laser lift-off technology.
  • the laser lift-off technique is used to separate the supporting substrate 100 and the first flexible sub-substrate 110 from each other. Further, the filling layer 111 on the supporting substrate 100 is separated from the first flexible sub-substrate 110. Since the peeling layer 112 has van der Waals force and hydrogen bonding effect, the temporarily bonded first flexible sub-substrate 110 and the filling layer 111 are separated by heating at high temperature, and the thinning effect of the flexible substrate 200 in the bending zone B is achieved. When the flexible substrate 200 in the bending region B is thinned, the metal trace layer (not shown) in the bending region B can be oriented toward the stress neutral plane, thereby improving the thin film transistor layer 130 in the bending region B performance.
  • the thickness of the flexible substrate 200 of the bending region B can be reduced.
  • the material of the filling layer 111 is usually a high-temperature-resistant low-viscosity organic material, which is advantageous for controlling the thickness of the filling layer 111 by coating, so as to realize the controllability of the thickness reduction of the flexible substrate 200 in the bending zone B.
  • the technique of patterning the filling layer 111 and the peeling layer 112 is dry etching, and the thickness of the flexible substrate 200 in the bending region B is controlled by the etching depth and the etching speed.
  • the method includes the following steps:
  • the polycarbonate with a viscosity of 3000 mPa ⁇ s is evenly coated on a clean and smooth glass substrate with a wet film thickness of 60 ⁇ m and baked at 350 degrees for 10 minutes to form a film to produce an organic filling layer.
  • the dry etching process is performed on the filling layer and the peeling layer to form a 0.5 mm rectangular parallelepiped multi-pattern structure.
  • the patterned structure may be trapezoidal or semi-cylindrical. Therefore, the groove opening of the first flexible sub-substrate formed in the following steps is a rectangular parallelepiped, an inverted trapezoid, or a semi-cylindrical shape.
  • the wet film thickness is 200 microns, and bake at 40 degrees for 10 minutes to remove the organic solvent.
  • the barrier layer is made of silicon dioxide.
  • a thin film transistor layer and an organic light-emitting diode layer are prepared on the barrier layer.
  • a patterning process is performed in the bending region B.
  • a polyimide material is coated thereon and cured to form the first flexible sub-substrate 110, and then deposited to form a barrier layer.
  • a double-layer or multi-layer flexible array substrate structure is completed, and a complete thin film transistor layer 130 structure is prepared.
  • the first flexible sub-substrate 110 and the filling layer 111 are separated by the peeling layer 112 to achieve the thinning of the flexible substrate 200 in the bending region B.
  • the present invention provides a display panel including the flexible array substrate as described above.
  • the specific structure of the flexible array substrate is not repeated here.
  • the advantage of the present invention is that the flexible array substrate thins the thickness of the flexible substrate 200 in the bending region B through the patterned filling layer 111, and uses the peeling layer 112 to separate the flexible substrate 200 and the filling layer 111 so that the bending The metal wiring layer in the region B tends to a stress-neutral plane, thereby achieving a flexible array substrate with excellent bending performance.
  • the flexible substrate 200 in the bending area B is thinned to improve the bending performance of the flexible array substrate in the bending area B, thereby avoiding possible internal stress in the bending area B Increased, metal wiring bending and breaking problems.
  • the structure of the flexible array substrate meets the requirements of high flexibility, heat resistance, high water and oxygen resistance, and has broad development prospects.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种柔性阵列基板及其制作方法、显示面板。所述柔性阵列基板通过图案化的填充层(111)减薄弯折区(B)的柔性衬底(200)的厚度，并且使用剥离层(112)分离柔性衬底(200)和填充层(111)，使得弯折区(B)的金属走线层趋向应力中性面，从而实现弯折性能优异的柔性阵列基板。在保持聚酰亚胺材料优异性能的同时，利用弯折区(B)的柔性衬底(200)减薄来改善柔性阵列基板在弯折区(B)的弯折性能，从而避免弯折区(B)可能出现的内应力增加、金属走线弯折断裂等问题。

Description

柔性阵列基板及其制作方法、显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种柔性阵列基板及其制作方法、显示面板。
 背景技术
随着现代显示技术的快速发展，显示技术领域正朝着更轻、更薄、更柔、更透明的方向发展。传统的玻璃基板由于自身硬和脆等特性，难以满足未来柔性显示技术的要求；而高分子薄膜基板具有质轻、柔性、综合性能优异等特点，可以很好地满足显示技术对柔性的要求。因此，柔性高分子基板材料是未来柔性显示技术的首选材料。
 技术问题
目前用作柔性基板最具发展前景的高分子材料是聚酰亚胺（Polyimide，PI）。聚酰亚胺具有优异的耐热性、耐辐射性能、耐化学性、电绝缘性、机械性能等，但在柔性基板上制备薄膜晶体管（Thin Film Transistor，TFT）后，应力中性层与金属走线区不统一，使得弯折区域容易出现应力集中、金属走线弯折断裂等问题。
 技术解决方案
本发明的目的在于，提供一种柔性阵列基板及其制作方法、显示面板。所述柔性阵列基板通过图案化的填充层减薄弯折区的柔性衬底的厚度，并且使用剥离层分离柔性衬底和填充层，使得弯折区的金属走线层趋向应力中性面，从而实现弯折性能优异的柔性阵列基板。在保持聚酰亚胺材料优异性能的同时，利用弯折区的柔性衬底减薄来改善柔性阵列基板在弯折区的弯折性能，从而避免弯折区可能出现的内应力增加、金属走线弯折断裂等问题。
根据本发明的一方面，本发明提供了一种柔性阵列基板，其包括：一柔性衬底；所述柔性阵列基板划分为一非弯折区及一弯折区，所述柔性衬底自所述非弯折区延伸至所述弯折区，在所述弯折区的柔性衬底具有一图案化结构。
在本发明的一实施例中，所述弯折区的所述柔性衬底的厚度小于所述非弯折区的所述柔性衬底的厚度。
在本发明的一实施例中，所述柔性衬底包括：层叠设置的一第一柔性子衬底、一无机层和一第二柔性子衬底；在所述弯折区的所述第一柔性子衬底具有朝向所述无机层的凹槽，以使所述弯折区的所述柔性衬底的厚度小于所述非弯折区的所述柔性衬底的厚度。
在本发明的一实施例中，所述凹槽的开口呈长方形、或倒梯形、或半圆柱形。
根据本发明的另一方面，本发明提供一种如上述柔性阵列基板的制作方法，所述方法包括以下步骤：（1）提供一支撑衬底，在所述支撑衬底上涂覆有机材料，形成一填充层；（2）在所述填充层上沉积一剥离层，并且对位于弯折区的所述填充层和所述剥离层进行图案化；（3）在所述支撑衬底和所述剥离层上覆盖一第一柔性子衬底；（4）在所述第一柔性子衬底上沉积一无机层，并且在所述无机层上设置一第二柔性子衬底；（5）在所述第二柔性子衬底上设置一薄膜晶体管层；（6）使用激光剥离技术分离所述支撑衬底和所述第一柔性子衬底。
在本发明的一实施例中，在步骤（1）中，所述有机材料为聚对苯二甲酸乙二醇、聚碳酸酯中的一种。
在本发明的一实施例中，在步骤（1）中，所述填充层所用的有机材料的粘度为1000～3000毫帕·秒，热分解温度高于450度。
在本发明的一实施例中，在步骤（2）中，所述剥离层所用的材料为二氧化硅、氮化硅中的一种。
在本发明的一实施例中，在步骤（4）中，所述无机层为二氧化硅结构或二氧化硅与氮化硅的堆叠结构。
根据本发明的又一方面，本发明提供一种显示面板，所述显示面板包括如上述柔性阵列基板。
 有益效果
本发明的优点在于，所述柔性阵列基板及其制作方法、显示面板。所述柔性阵列基板通过图案化的填充层减薄弯折区的柔性衬底的厚度，并且使用剥离层分离柔性衬底和填充层，使得弯折区的金属走线层趋向应力中性面，从而实现弯折性能优异的柔性阵列基板。在保持聚酰亚胺材料优异性能的同时，利用弯折区的柔性衬底减薄来改善柔性阵列基板在弯折区的弯折性能，从而避免弯折区可能出现的内应力增加、金属走线弯折断裂等问题。另外，所述柔性阵列基板的结构满足高柔性、耐热、高阻水阻氧等要求，具有广阔的发展前景。
 附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明一实施例中的柔性阵列基板的结构示意图。
图2A至图2C是本发明所述实施例中柔性阵列基板的第一柔性子衬底的图案化结构的示意图。
图3是本发明一实施例中的柔性阵列基板的制作方法的步骤流程图。
图4A至图4I是本发明所述实施例中的柔性阵列基板的制作方法的工艺示意图。
 本发明的实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的说明书和权利要求书以及上述附图中的术语“第一”、“第二”、“第三”等（如果存在）是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应当理解，这样描述的对象在适当情况下可以互换。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含。
在本专利文档中，下文论述的附图以及用来描述本发明公开的原理的各实施例仅用于说明，而不应解释为限制本发明公开的范围。所属领域的技术人员将理解，本发明的原理可在任何适当布置的系统中实施。将详细说明示例性实施方式，在附图中示出了这些实施方式的实例。此外，将参考附图详细描述根据示例性实施例的终端。附图中的相同附图标号指代相同的元件。
本发明说明书中使用的术语仅用来描述特定实施方式，而并不意图显示本发明的概念。除非上下文中有明确不同的意义，否则，以单数形式使用的表达涵盖复数形式的表达。在本发明说明书中，应理解，诸如“包括”、“具有”以及“含有”等术语意图说明存在本发明说明书中揭示的特征、数字、步骤、动作或其组合的可能性，而并不意图排除可存在或可添加一个或多个其他特征、数字、步骤、动作或其组合的可能性。附图中的相同参考标号指代相同部分。
本发明实施例提供一种柔性阵列基板及其制作方法、显示面板。以下将分别进行详细说明。
参阅图1，图1是本发明一实施例中的柔性阵列基板的结构示意图。图2A至图2C是本发明所述实施例中柔性阵列基板的第一柔性子衬底的图案化结构的示意图。
本发明提供了一种柔性阵列基板，其包括：一柔性衬底200。所述柔性阵列基板划分为一非弯折区A及一弯折区B，所述柔性衬底200自所述非弯折区A延伸至所述弯折区B，在所述弯折区B的柔性衬底200具有图案化结构。
在本实施例中，所述柔性衬底200包括层叠设置第一柔性子衬底110、无机层101和第二柔性子衬底120。在本实施例中，所述柔性衬底200为双层柔性子衬底，在其他部分实施例中，所述柔性衬底200也可以包括多层柔性子衬底。
所述第一柔性子衬底110和所述第二柔性子衬底120均采用有机材料，例如为聚对苯二甲酸乙二醇、聚碳酸酯中的一种。在本实施例中，采用聚酰亚胺（PI）材料，其具有耐高温，使用温度范围广，无明显熔点，高绝缘性能，以及介电常数稳定等特点。
所述无机层101可以为水氧阻隔层，用于防止外界的水分或氧气进入所述柔性阵列基板，进而影响柔性阵列基板的使用寿命。所述无机层101为二氧化硅结构或二氧化硅与氮化硅的堆叠结构。
在所述弯折区B的所述第一柔性子衬底110具有朝向所述无机层101的凹槽103，以使所述弯折区B的所述柔性衬底200的厚度小于所述非弯折区A的所述柔性衬底200的厚度。所述凹槽103的开口呈长方形、或倒梯形、或半圆柱形，如图2A至图2C。
由于所述弯折区B的第一柔性子衬底110具有图形化结构，与所述非弯折区A的柔性衬底200形成一高度差，亦即，所述弯折区B的柔性衬底200的厚度小于所述非弯折区A的柔性衬底200的厚度，因此，所述弯折区B的柔性衬底200减薄。
参阅图3、图4A至图4I，图3是本发明一实施例中的柔性阵列基板的制作方法的步骤流程图。图4A至图4I是本发明所述实施例中的柔性阵列基板的制作方法的工艺示意图。
本发明提供一种如上述柔性阵列基板的制作方法，所述方法包括以下步骤：
步骤S310：提供一支撑衬底，在所述支撑衬底上涂覆有机材料，形成一填充层。
所述支撑衬底100所使用的材料为玻璃、金属、非金属中的一种。在此步骤中，将有机材料均匀涂覆于洁净光滑的支持衬底上，经烘烤成膜，制得填充层111。其中所述有机材料为聚对苯二甲酸乙二醇、聚碳酸酯中的一种。所述填充层111所用的有机材料的粘度为1000～3000毫帕·秒，热分解温度高于450度。另外，在涂覆有机材料，形成湿膜膜厚为30微米～100微米，成膜温度为200度至400度，成膜时间为0.1小时至1小时。湿膜经烘烤后形成填充层111。
步骤S320：在所述填充层111上沉积一剥离层，并且对位于弯折区B的所述填充层111和所述剥离层112进行图案化。
所述剥离层112采用的材料为二氧化硅、氮化硅中的一种。所述剥离层112的沉积厚度为1000埃至3000埃。在进行图案化时采用干刻蚀技术。图案化后的保留的填充层111和剥离层112的宽度为0.1毫米至1毫米。
步骤S330：在所述支撑衬底100和所述剥离层112上覆盖一第一柔性子衬底110。
在此步骤中，进一步包括：将聚酰胺酸溶液均匀涂覆在支撑衬底100和剥离层112上，经低温烘烤成膜，去除有机溶剂；在高纯氮气气氛中，将薄膜升温脱水，发生高温热酰亚胺化反应，制得第一柔性子衬底110，即第一聚酰亚胺膜层。在涂覆形成湿膜的膜厚为50微米至300微米，烘烤温度为20度至80度，烘烤时间为1分钟至20分钟，在进行升温脱水时，升温速率为每分钟5～20度，固化温度为350度至550度，固化时间为0.1小时至1小时，再冷却至室温。
步骤S340：在所述第一柔性子衬底110上沉积一无机层101，并且在所述无机层101上设置一第二柔性子衬底120。
在此步骤中，所述无机层101为第一阻隔层，所述第一阻隔层为二氧化硅结构或二氧化硅与氮化硅的堆叠结构。所述第一阻隔层的厚度为1000～6000埃。当形成第一阻隔层之后，在第一阻隔层上设置一第二柔性子衬底120。形成第二柔性子衬底120的方式与步骤S330中的方式相同，其中的湿膜厚度、烘烤温度、烘烤时间与步骤S330中实施方式的参数相同。
步骤S350：在所述第二柔性子衬底120上设置薄膜晶体管层130。
在形成所述第二柔性子衬底120之后，可以进一步在所述第二柔性子衬底120（即第二聚酰亚胺膜层）上形成一第二阻隔层102。形成第二阻隔层102的方式与步骤S340中形成无机层101（即第一阻隔层）的方式相同，包括升温速度、固化温度和固化时间。
步骤S360：使用激光剥离技术分离所述支撑衬底100和所述第一柔性子衬底110。
采用激光剥离技术使得所述支撑衬底100和所述第一柔性子衬底110彼此分离。进一步而言，将所述支撑衬底100上填充层111与所述第一柔性子衬底110分离。由于剥离层112具有范德华力与氢键作用，使得暂时粘贴的第一柔性子衬底110与填充层111经高温受热进行分离，实现对弯折区B的柔性衬底200的减薄效果。当减薄的弯折区B的柔性衬底200后，使得弯折区B的金属走线层(图中未示)能够趋向应力中性面，从而改善薄膜晶体管层130在弯折区B的性能。另外，通过对填充层111图案化，亦即，第一柔性子衬底110图案化，可以减薄所述弯折区B的柔性衬底200的厚度。通过填充层111的图案化，形成高度差，从而实现弯折区B的柔性衬底200变薄。填充层111的材料通常为耐高温的低粘度的有机材料，有利于通过涂覆方式控制填充层111的厚度，从而实现弯折区B的柔性衬底200的减薄厚度的可控性。需说明的是，图案化填充层111和剥离层112的技术为干刻蚀发，通过刻蚀深度和刻蚀速度来实现对弯折区B的柔性衬底200的厚度的控制。
以下将一实施例来进一步说明柔性阵列基板的制作方法，所述方法包括以下步骤：
1) 将粘度为3000毫帕·秒的聚碳酸酯均匀涂覆于洁净光滑的玻璃衬底上，湿膜厚度60微米，经350度且10分钟烘烤成膜，制得有机填充层。
2) 在填充层上沉积2000埃的剥离层；剥离层为二氧化硅制成。
3) 将填充层与剥离层经干刻蚀工艺，形成0.5毫米的长方体多图案结构。当然，在其他部分实施例中，图案化结构可以为梯形或半圆柱形。因此，在以下步骤中所形成的第一柔性子衬底具有的凹槽开口为长方体形、倒梯形或半圆柱形。
4) 将聚酰胺酸溶液均匀涂覆于填充层与剥离层上，湿膜厚度200微米，经40度烘烤10分钟，去除有机溶剂。
5) 在高纯氢气气氛中，以每分钟5度速率，升温至450度保持0.5小时，发生热酰亚胺化反应，制得第一聚酰亚胺膜层，即第一柔性子衬底110。
6) 在第一聚酰亚胺膜层上沉积厚度为5000埃的阻隔层。所述阻隔层为二氧化硅制成。
7) 将聚酰胺酸溶液均匀涂覆于阻隔层上，湿膜厚度200微米，经40度烘烤20分钟，去除有机溶剂。
8) 在高纯氢气气氛中，以每分钟5度的速率，升温至450度保持0.5小时，发生热酰亚胺化反应，制得第二聚酰亚胺膜层，即第二柔性子衬底120。
9) 在第二聚酰亚胺膜层上沉积第二阻隔层。
10) 在阻隔层上制备薄膜晶体管层和有机致电发光二极管层。
11) 使用LLO技术（激光剥离）剥离支撑层与第一聚酰亚胺膜层。
因此，通过涂布一定厚度的填充层111与剥离层112，并在弯折区B进行图案化处理。在其上涂布聚酰亚胺材料并固化以形成第一柔性子衬底110，然后再沉积形成一阻隔层。经二次或多次涂覆聚酰亚胺与沉积阻隔层工艺，完成双层或多层的柔性阵列基板结构，并制备完整薄膜晶体管层130结构。另外，通过剥离层112分离第一柔性子衬底110与填充层111，以实现弯折区B的柔性衬底200的变薄。
根据本发明的又一方面，本发明提供一种显示面板，所述显示面板包括如上述柔性阵列基板。所述柔性阵列基板的具体结构在此不再一一赘述。
本发明的优点在于，所述柔性阵列基板通过图案化的填充层111减薄弯折区B的柔性衬底200的厚度，并且使用剥离层112分离柔性衬底200和填充层111，使得弯折区B的金属走线层趋向应力中性面，从而实现弯折性能优异的柔性阵列基板。在保持聚酰亚胺材料优异性能的同时，利用弯折区B的柔性衬底200减薄来改善柔性阵列基板在弯折区B的弯折性能，从而避免弯折区B可能出现的内应力增加、金属走线弯折断裂等问题。另外，所述柔性阵列基板的结构满足高柔性、耐热、高阻水阻氧等要求，具有广阔的发展前景。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。
 工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (10)

  1. 一种柔性阵列基板，其包括：一柔性衬底；所述柔性阵列基板划分为一非弯折区及一弯折区，所述柔性衬底自所述非弯折区延伸至所述弯折区，在所述弯折区的柔性衬底具有一图案化结构。
  2. 根据权利要求1所述的柔性阵列基板，其中所述弯折区的所述柔性衬底的厚度小于所述非弯折区的所述柔性衬底的厚度。
  3. 根据权利要求1所述的柔性阵列基板，其中所述柔性衬底包括：层叠设置的一第一柔性子衬底、一无机层和一第二柔性子衬底；在所述弯折区的所述第一柔性子衬底具有朝向所述无机层的凹槽，以使所述弯折区的所述柔性衬底的厚度小于所述非弯折区的所述柔性衬底的厚度。
  4. 根据权利要求3所述的柔性阵列基板，其中所述凹槽的开口呈长方形、或倒梯形、或半圆柱形。
  5. 一种如权利要求1所述的柔性阵列基板的制作方法，其中所述方法包括以下步骤：
    （1）提供一支撑衬底，在所述支撑衬底上涂覆有机材料，形成一填充层；
    （2）在所述填充层上沉积一剥离层，并且对位于弯折区的所述填充层和所述剥离层进行图案化；
    （3）在所述支撑衬底和所述剥离层上覆盖一第一柔性子衬底；
    （4）在所述第一柔性子衬底上沉积一无机层，并且在所述无机层上设置一第二柔性子衬底；
    （5）在所述第二柔性子衬底上设置一薄膜晶体管层；
    （6）使用激光剥离技术分离所述支撑衬底和所述第一柔性子衬底。
  6. 根据权利要求5所述的制作方法，其中在步骤（1）中，所述有机材料为聚对苯二甲酸乙二醇、聚碳酸酯中的一种。
  7. 根据权利要求5所述的制作方法，其中在步骤（1）中，所述填充层所用的有机材料的粘度为1000～3000毫帕·秒，热分解温度高于450度。
  8. 根据权利要求5所述的制作方法，其中在步骤（2）中，所述剥离层所用的材料为二氧化硅、氮化硅中的一种。
  9. 根据权利要求5所述的制作方法，其中在步骤（4）中，所述无机层为二氧化硅结构或二氧化硅与氮化硅的堆叠结构。
  10. 一种显示面板，其中所述显示面板包括如权利要求1所述的柔性阵列基板。
PCT/CN2019/072492 2018-12-06 2019-01-21 柔性阵列基板及其制作方法、显示面板 Ceased WO2020113797A1 (zh)

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