WO2020113663A1 - 常关型氧化镓场效应晶体管结构及制备方法 - Google Patents

常关型氧化镓场效应晶体管结构及制备方法 Download PDF

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WO2020113663A1
WO2020113663A1 PCT/CN2018/121422 CN2018121422W WO2020113663A1 WO 2020113663 A1 WO2020113663 A1 WO 2020113663A1 CN 2018121422 W CN2018121422 W CN 2018121422W WO 2020113663 A1 WO2020113663 A1 WO 2020113663A1
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gallium oxide
normally
effect transistor
transistor structure
layer
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PCT/CN2018/121422
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French (fr)
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吕元杰
王元刚
周幸叶
谭鑫
宋旭波
梁士雄
冯志红
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中国电子科技集团公司第十三研究所
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Publication of WO2020113663A1 publication Critical patent/WO2020113663A1/zh
Priority to US17/061,261 priority Critical patent/US11456387B2/en

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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
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    • H01L29/1025—Channel region of field-effect devices
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
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    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the technical field of semiconductor devices of the present application more specifically, relates to a normally-off type gallium oxide field effect transistor structure and preparation method.
  • normally-off gallium oxide field effect transistors are usually implemented using deep groove technology under the gate, and the grooves are generally realized by dry etching.
  • the deep-groove under-gate technology is used to realize normally-off gallium oxide field effect transistor devices.
  • the etching depth is uncontrollable and the threshold is unstable; gallium oxide has strong resistance to etching, and dry etching will cause the surface of the groove under the gate Roughness and unevenness can cause a spiked electric field in the area under the gate when the device is in operation, affecting the breakdown characteristics of the device.
  • etching will introduce material damage problems, which will seriously affect the saturation current and breakdown voltage of the device.
  • the purpose of this application is to provide a normally-off gallium oxide field effect transistor structure to solve the uncontrollable etching depth, the existence of etching damage, the surface roughness, the unstable threshold, and the serious impact of the existing deep groove technology under the gate Technical issues such as saturation current and breakdown voltage.
  • the technical solution adopted in this application is to provide a normally-off gallium oxide field effect transistor structure, which includes a substrate layer and an n-type doped gallium oxide channel layer from bottom to top, the n-type doped oxide
  • the gallium channel layer is provided with a source, a drain and a gate, the gate is located between the source and the drain, and the n-type doped gallium oxide channel layer under the gate There is no electron channel area inside.
  • the length of the electron-free channel region is less than or equal to the length of the gate.
  • the number of the electron-free channel regions is an integer greater than or equal to 1
  • the number of the gate is an integer greater than or equal to 1
  • the electron-free channel regions are all located below the gate.
  • the substrate layer is at least one layer of semiconductor material, metal material or insulating medium, wherein the substrate layer connected to the n-type doped gallium oxide channel layer is an insulating dielectric layer.
  • the substrate layer includes a sapphire substrate layer and a gallium oxide channel layer from bottom to top.
  • the n-type doped gallium oxide channel layer includes a first n-type doped gallium oxide channel layer and a second n-type doped gallium oxide channel layer from bottom to top, the first n-type doped The doping concentrations of the gallium oxide channel layer and the second n-type doped gallium oxide channel layer are not equal.
  • the source electrode and the drain electrode form an ohmic contact by ion implantation and high-temperature annealing, or an ohmic contact by a high-temperature alloy.
  • At least one of the source electrode and the n-type doped gallium oxide channel layer, the drain electrode and the n-type doped gallium oxide channel layer is in Schottky contact.
  • the normally-off gallium oxide field effect transistor structure further includes a field plate, the field plate is a source field plate, a gate field plate and a drain field plate, or any one of them, or any two of them Pcs.
  • the source field plate, the gate field plate and the drain field plate all have at least one layer.
  • a gate dielectric layer is provided between the n-type doped gallium oxide channel layer and the gate.
  • a passivation layer is provided between the source and the gate, and between the drain and the gate.
  • the passivation layer is a layer of insulating medium or multiple layers of insulating medium.
  • Another object of the present application is to provide a method for preparing a normally-off gallium oxide field effect transistor structure, including:
  • Annealing at high temperature in an oxygen atmosphere forms an electron-free channel region.
  • the high-temperature annealing temperature is 300°C-1300°C, and the high-temperature annealing time ⁇ 30s.
  • This application does not require a dry etching process, which avoids the problems of surface roughness, material damage, and uneven etching caused by etching, which is beneficial to reduce the leakage characteristics of the device, improve the voltage resistance and switching characteristics of the device, and can also improve The uniformity of the device threshold voltage is conducive to mass production.
  • high-temperature annealing can repair defects in the material in the mask area, and is expected to further improve device performance.
  • FIG. 1 is a schematic structural diagram of a normally-off gallium oxide field effect transistor structure provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a normally-off gallium oxide field effect transistor structure with a gate field plate provided by an embodiment of the present application.
  • the normally-off gallium oxide field effect transistor structure includes, from bottom to top, 1 and an n-type doped gallium oxide channel layer 2, and the n-type doped gallium oxide channel layer 2 is provided with a source 3 and a drain 5 and a gate 4, the gate 4 is located between the source 3 and the drain 5, and there is no electron in the n-type doped gallium oxide channel layer 2 under the gate 4 Channel region 6.
  • the normally-off gallium oxide field-effect transistor structure provided by this application does not require a dry etching process to avoid the surface roughness caused by etching. Problems such as material damage and uneven etching are conducive to reducing the leakage characteristics of the device, improving the voltage resistance and switching characteristics of the device, and at the same time can improve the uniformity of the threshold voltage of the device and facilitate mass production.
  • the length of the electron-free channel region 6 is less than or equal to the length of the gate 4.
  • the number of the electron-free channel regions 6 is an integer greater than or equal to 1, and the number of the gates 4 It is an integer greater than or equal to 1, and the electron-free channel regions 6 are all located below the gate 4.
  • said 1 is at least one layer of semiconductor material, metal material or insulating medium, wherein, it is doped with the n-type
  • the 1 connected by the gallium oxide channel layer 2 is an insulating dielectric layer.
  • the semiconductor material is Ga 2 O 3 , GaN, AlN, etc.
  • the metal material is nickel, titanium, platinum, tungsten, etc.
  • the insulating medium is SiO 2 , SiN, Al 2 O 3, etc.
  • the substrate layer 1 includes a substrate layer 11 and a gallium oxide channel layer 12 from bottom to top.
  • the n-type doped gallium oxide channel layer 2 includes a first n-type doped gallium oxide from bottom to top
  • the channel layer 21 and the second n-type doped gallium oxide channel layer 22 the doping concentration of the first n-type doped gallium oxide channel layer and the second n-type doped gallium oxide channel layer is not equal.
  • the different concentration of the two layers is helpful to improve the transconductance of the device and improve the voltage resistance of the device.
  • the source electrode 3 and the drain electrode 5 form an ohmic contact through ion implantation and high temperature annealing, or through high temperature The alloy forms an ohmic contact.
  • the source 3 and the n-type doped gallium oxide channel layer, the drain 5 and At least one of the n-type doped gallium oxide channel layers is a Schottky contact.
  • the normally-off gallium oxide field effect transistor structure further includes a field plate, and the field plate is a source field plate , The grid field plate 9 and the drain field plate, either one of them, or any two of them.
  • the source field plate, the gate field plate 9 and the drain field plate all have at least one layer.
  • the field plate structure is beneficial to suppress the peak electric field of the device channel and improve the voltage resistance of the device.
  • a gate dielectric layer 7 is provided between the n-type doped gallium oxide channel layer and the gate 4 .
  • the passivation layer 8 is a layer of insulating medium or multiple layers of insulating medium.
  • the present application also provides a method for preparing a normally-off gallium oxide field effect transistor structure, including:
  • High-temperature annealing is performed in an oxygen atmosphere to form an electron-free channel region 6.
  • the high-temperature annealing temperature is 300°C-1300°C, and the high-temperature annealing time ⁇ 30s.
  • the beneficial effect of the preparation method of the present application is that it does not require a dry etching process, which avoids the problems of surface roughness, material damage and uneven etching caused by etching, which is beneficial to reduce the leakage characteristics of the device and improve the voltage resistance of the device And switching characteristics, at the same time can improve the uniformity of the threshold voltage of the device, which is conducive to mass production.
  • high-temperature annealing can repair defects in the material in the mask area, and is expected to further improve device performance.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种常关型氧化镓场效应晶体管结构及制备方法，自下至上包括衬底层（1,11）和n型掺杂氧化镓沟道层（2,21,22），所述n型掺杂氧化镓沟道层（2,21,22）上设有源极（3）、漏极（5）和栅极（4），所述栅极（4）位于所述源极（3）和所述漏极（5）之间，所述栅极（4）下方的所述n型掺杂氧化镓沟道层（2,21,22）内设有无电子沟道区（6）。所述的常关型氧化镓场效应晶体管结构，无需在栅极（4）下制备凹槽，而是通过高温氧化形成无电子沟道区（6），在无电子沟道区（6）上形成栅极（4），避免了刻蚀损伤和刻蚀深度不可控的问题，提高了饱和电流和击穿电压。

Description

常关型氧化镓场效应晶体管结构及制备方法 技术领域
本申请半导体器件技术领域，更具体地说，是涉及一种常关型氧化镓场效应晶体管结构及制备方法。
 背景技术
由于缺乏有效的P型掺杂和注入技术，常关型氧化镓场效应晶体管通常采用栅下深凹槽技术实现，凹槽一般通过干法刻蚀实现。利用栅下深凹槽技术实现常关型氧化镓场效应晶体管器件，刻蚀深度不可控，阈值不稳定；氧化镓具有较强的抗刻蚀性，干法刻蚀会导致栅下凹槽表面粗糙不平整，从而会导致器件工作时栅下区域出现尖峰电场，影响器件的击穿特性，同时，刻蚀会引入材料损伤问题，会严重影响器件饱和电流和击穿电压。
 技术问题
本申请的目的在于提供一种常关型氧化镓场效应晶体管结构，以解决现有栅下深凹槽技术存在的刻蚀深度不可控、存在刻蚀损伤、表面粗糙、阈值不稳定、严重影响饱和电流和击穿电压等技术问题。
 技术解决方案
为实现上述目的，本申请采用的技术方案是：提供一种常关型氧化镓场效应晶体管结构，自下至上包括衬底层和n型掺杂氧化镓沟道层，所述n型掺杂氧化镓沟道层上设有源极、漏极和栅极，所述栅极位于所述源极和所述漏极之间，所述栅极下方的所述n型掺杂氧化镓沟道层内设有无电子沟道区。
进一步地，所述无电子沟道区的长度小于等于所述栅极的长度。
进一步地，所述无电子沟道区的数量为大于等于1的整数，所述栅极的数量为大于等于1的整数，且所述无电子沟道区均位于所述栅极的下方。
进一步地，所述衬底层为至少一层半导体材料、金属材料或者绝缘介质，其中，与所述n型掺杂氧化镓沟道层相连接的所述衬底层为绝缘介质层。
进一步地，所述衬底层自下至上包括蓝宝石衬底层和氧化镓沟道层。
进一步地，所述n型掺杂氧化镓沟道层自下至上包括第一n型掺杂氧化镓沟道层和第二n型掺杂氧化镓沟道层，所述第一n型掺杂氧化镓沟道层和所述第二n型掺杂氧化镓沟道层的掺杂浓度不相等。
进一步地，所述源极和所述漏极通过离子注入和高温退火形成欧姆接触，或者通过高温合金形成欧姆接触。
进一步地，所述源极与所述n型掺杂氧化镓沟道层、所述漏极与所述n型掺杂氧化镓沟道层，至少有一个为肖特基接触。
进一步地，所述的常关型氧化镓场效应晶体管结构还包括场板，所述场板为源场板、栅场板和漏场板，或者为其中的任意一个，或者为其中的任意两个。
进一步地，所述源场板、所述栅场板和所述漏场板均至少具有一层。
进一步地，所述n型掺杂氧化镓沟道层与所述栅极之间设有栅介质层。
进一步地，所述源极和所述栅极之间、所述漏极和所述栅极之间具有钝化层。
进一步地，所述钝化层为一层绝缘介质或者多层绝缘介质。
本申请另一目的在于提供一种常关型氧化镓场效应晶体管结构的制备方法，包括：
在n型掺杂氧化镓沟道层上淀积掩膜层，所述掩膜层为金属或者绝缘介质；
利用光刻、显影、干法刻蚀或者湿法腐蚀方法去除待制作的无电子沟道区上方的掩膜层；
在氧气氛围进行高温退火，形成无电子沟道区。
进一步地，所述高温退火温度为300℃-1300℃，高温退火时间≥30s。
 有益效果
本申请不需要干法刻蚀工艺，避免了刻蚀导致的表面粗糙、材料损伤和刻蚀不均匀等问题，有利于降低器件的漏电特性，提升器件的耐压特性和开关特性，同时能够提升器件阈值电压的均匀性，利于大规模生产。此外，高温退火能够修复掩膜区域的材料的缺陷，有望进一步提升器件性能。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的常关型氧化镓场效应晶体管结构的结构示意图；
图2为本申请实施例提供的带栅场板的常关型氧化镓场效应晶体管结构的结构示意图。
其中，图中：
1-衬底层；11-蓝宝石衬底层；12-氧化镓沟道层；2-n型掺杂氧化镓沟道层；21-第一n型掺杂氧化镓沟道层；22-第二n型掺杂氧化镓沟道层；3-源极；4-栅极；5-漏极；6-无电子沟道区；7-栅介质层；8-钝化层；9-栅场板。
本申请的实施方式
为了使本申请所要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
请一并参阅图1至图2，现对本申请提供的常关型氧化镓场效应晶体管结构进行说明。所述常关型氧化镓场效应晶体管结构，自下至上包括1和n型掺杂氧化镓沟道层2，所述n型掺杂氧化镓沟道层2上设有源极3、漏极5和栅极4，所述栅极4位于所述源极3和所述漏极5之间，所述栅极4下方的所述n型掺杂氧化镓沟道层2内设有无电子沟道区6。
本申请提供的常关型氧化镓场效应晶体管结构，与现有技术相比，本申请常关型氧化镓场效应晶体管结构，不需要干法刻蚀工艺，避免了刻蚀导致的表面粗糙、材料损伤和刻蚀不均匀等问题，有利于降低器件的漏电特性，提升器件的耐压特性和开关特性，同时能够提升器件阈值电压的均匀性，利于大规模生产。
请参阅图1，作为本申请提供的常关型氧化镓场效应晶体管结构的一种具体实施方式，所述无电子沟道区6的长度小于等于所述栅极4的长度。
请参阅图1，作为本申请提供的常关型氧化镓场效应晶体管结构的一种具体实施方式，所述无电子沟道区6的数量为大于等于1的整数，所述栅极4的数量为大于等于1的整数，且所述无电子沟道区6均位于所述栅极4的下方。
请参阅图1，作为本申请提供的常关型氧化镓场效应晶体管结构的一种具体实施方式，所述1为至少一层半导体材料、金属材料或者绝缘介质，其中，与所述n型掺杂氧化镓沟道层2相连接的所述1为绝缘介质层。其中，半导体材料为Ga 2O 3、GaN、AlN等，金属材料为镍、钛、铂、钨等，绝缘介质为SiO 2、SiN、Al 2O 3等。
请参阅图1，作为本申请提供的常关型氧化镓场效应晶体管结构的一种具体实施方式，所述衬底层1自下至上包括衬底层11和氧化镓沟道层12。
请参阅图1，作为本申请提供的常关型氧化镓场效应晶体管结构的一种具体实施方式，所述n型掺杂氧化镓沟道层2自下至上包括第一n型掺杂氧化镓沟道层21和第二n型掺杂氧化镓沟道层22，所述第一n型掺杂氧化镓沟道层和所述第二n型掺杂氧化镓沟道层的掺杂浓度不相等。两层浓度不相同有利于提高器件的跨导，改善器件耐压特性。
请参阅图1，作为本申请提供的常关型氧化镓场效应晶体管结构的一种具体实施方式，所述源极3和所述漏极5通过离子注入和高温退火形成欧姆接触，或者通过高温合金形成欧姆接触。
请参阅图1，作为本申请提供的常关型氧化镓场效应晶体管结构的一种具体实施方式，所述源极3与所述n型掺杂氧化镓沟道层、所述漏极5与所述n型掺杂氧化镓沟道层，至少有一个为肖特基接触。
参见图2，作为本申请提供的常关型氧化镓场效应晶体管结构的一种具体实施方式，所述的常关型氧化镓场效应晶体管结构还包括场板，所述场板为源场板、栅场板9和漏场板，或者为其中的任意一个，或者为其中的任意两个。
参见图2，作为本申请提供的常关型氧化镓场效应晶体管结构的一种具体实施方式，所述源场板、所述栅场板9和所述漏场板均至少具有一层。场板结构有利于抑制器件沟道尖峰电场，改善器件耐压特性。
参见图2，作为本申请提供的常关型氧化镓场效应晶体管结构的一种具体实施方式，所述n型掺杂氧化镓沟道层与所述栅极4之间设有栅介质层7。
参见图2，作为本申请提供的常关型氧化镓场效应晶体管结构的一种具体实施方式，所述源极3和所述栅极4之间、所述漏极5和所述栅极4之间具有钝化层8。
参见图2，作为本申请提供的常关型氧化镓场效应晶体管结构的一种具体实施方式，所述钝化层8为一层绝缘介质或者多层绝缘介质。
本申请还提供一种常关型氧化镓场效应晶体管结构的制备方法，包括：
在n型掺杂氧化镓沟道层上淀积掩膜层，所述掩膜层为金属或者绝缘介质；
利用光刻、显影、干法刻蚀或者湿法腐蚀方法去除待制作的无电子沟道区6上方的掩膜层；
在氧气氛围进行高温退火，形成无电子沟道区6。
其中，所述高温退火温度为300℃-1300℃，高温退火时间≥30s。
本申请制备方法的有益效果在于，不需要干法刻蚀工艺，避免了刻蚀导致的表面粗糙、材料损伤和刻蚀不均匀等问题，有利于降低器件的漏电特性，提升器件的耐压特性和开关特性，同时能够提升器件阈值电压的均匀性，利于大规模生产。此外，高温退火能够修复掩膜区域的材料的缺陷，有望进一步提升器件性能。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (15)

  1. 常关型氧化镓场效应晶体管结构，其特征在于，自下至上包括衬底层和n型掺杂氧化镓沟道层，所述n型掺杂氧化镓沟道层上设有源极、漏极和栅极，所述栅极位于所述源极和所述漏极之间，所述栅极下方的所述n型掺杂氧化镓沟道层内设有无电子沟道区。
  2. 如权利要求1所述的常关型氧化镓场效应晶体管结构，其特征在于，所述无电子沟道区的长度小于等于所述栅极的长度。
  3. 如权利要求1所述的常关型氧化镓场效应晶体管结构，其特征在于，所述无电子沟道区的数量为大于等于1的整数，所述栅极的数量为大于等于1的整数，且所述无电子沟道区均位于所述栅极的下方。
  4. 如权利要求1所述的常关型氧化镓场效应晶体管结构，其特征在于，所述衬底层为至少一层半导体材料、金属材料或者绝缘介质，其中，与所述n型掺杂氧化镓沟道层相连接的所述衬底层为绝缘介质层。
  5. 如权利要求4所述的常关型氧化镓场效应晶体管结构，其特征在于，所述衬底层自下至上包括蓝宝石衬底层和氧化镓沟道层。
  6. 如权利要求1所述的常关型氧化镓场效应晶体管结构，其特征在于，所述n型掺杂氧化镓沟道层自下至上包括第一n型掺杂氧化镓沟道层和第二n型掺杂氧化镓沟道层，所述第一n型掺杂氧化镓沟道层和所述第二n型掺杂氧化镓沟道层的掺杂浓度不相等。
  7. 如权利要求1所述的常关型氧化镓场效应晶体管结构，其特征在于，所述源极和所述漏极通过离子注入和高温退火形成欧姆接触，或者通过高温合金形成欧姆接触。
  8. 如权利要求1所述的常关型氧化镓场效应晶体管结构，其特征在于，所述源极与所述n型掺杂氧化镓沟道层、所述漏极与所述n型掺杂氧化镓沟道层，至少有一个为肖特基接触。
  9. 如权利要求1-8任一项所述的常关型氧化镓场效应晶体管结构，其特征在于，所述的常关型氧化镓场效应晶体管结构还包括场板，所述场板为源场板、栅场板和漏场板，或者为其中的任意一个，或者为其中的任意两个。
  10. 如权利要求9所述的常关型氧化镓场效应晶体管结构，其特征在于，所述源场板、所述栅场板和所述漏场板均至少具有一层。
  11. 如权利要求9所述的常关型氧化镓场效应晶体管结构，其特征在于，所述n型掺杂氧化镓沟道层与所述栅极之间设有栅介质层。
  12. 如权利要求9所述的常关型氧化镓场效应晶体管结构，其特征在于，所述源极和所述栅极之间、所述漏极和所述栅极之间具有钝化层。
  13. 如权利要求12所述的常关型氧化镓场效应晶体管结构，其特征在于，所述钝化层为一层绝缘介质或者多层绝缘介质。
  14. 如权利要求1-13任一项所述的常关型氧化镓场效应晶体管结构的制备方法，其特征在于，包括：
    在n型掺杂氧化镓沟道层上淀积掩膜层，所述掩膜层为金属或者绝缘介质；
    利用光刻、显影、干法刻蚀或者湿法腐蚀方法去除待制作的无电子沟道区上方的掩膜层；
    在氧气氛围进行高温退火，形成无电子沟道区。
  15. 如权利要求14所述的常关型氧化镓场效应晶体管结构的制备方法，所述高温退火温度为300℃-1300℃，高温退火时间≥30s。
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