Classifications

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  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
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  • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
  • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
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  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
  • H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
  • H10P14/6512—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials by exposure to a gas or vapour
  • H10P14/6514—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials by exposure to a gas or vapour by exposure to a plasma
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  • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
  • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
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  • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
  • H10P50/262—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by physical means only
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  • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
  • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
  • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
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  • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
  • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
  • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
  • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
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  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/60—Wet etching
  • H10P50/64—Wet etching of semiconductor materials
  • H10P50/642—Chemical etching
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  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/60—Wet etching
  • H10P50/66—Wet etching of conductive or resistive materials
  • H10P50/663—Wet etching of conductive or resistive materials by chemical means only
  • H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only
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  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
  • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
  • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
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  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
  • H10W20/054—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by selectively removing parts thereof
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  • H10W20/01—Manufacture or treatment
  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
  • H10W20/0633—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material using subtractive patterning of the conductive members
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  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
  • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
  • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
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  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
  • H10W20/095—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by irradiating with electromagnetic or particle radiation
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  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
  • H10W20/097—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by thermally treating
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  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/44—Conductive materials thereof
  • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
  • H10W20/4437—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal
  • H10W20/4441—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being a transition metal the principal metal being a refractory metal
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  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
  • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
  • H10P14/6302—Non-deposition formation processes
  • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
  • H10P14/6314—Formation by oxidation, e.g. oxidation of the substrate of a metallic layer

Definitions

• Embodiments of the present disclosure relate to methods for forming semiconductor device structures. More specifically, embodiments of the present disclosure relate to methods of patterning metal layers on a substrate.
• Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors, and resistors on a single chip.
• the evolution of chip design has resulted in greater circuit density to improve the process capability and speed of chips.
• the demands for faster processing capability with greater circuit densities impose corresponding demands on the materials used to fabricate such integrated circuits.
• low resistivity conductive materials, as well as low dielectric constant insulating materials are used to obtain suitable electrical performance from such components.
• Interconnects provide the electrical connections between the various electronic components of an integrated circuit and form the connections between these elements and the device’s external contact elements (e.g. pins) for connecting the integrated circuit to other circuits.
• copper has been the material of choice for interconnect layers.
• conventional copper interconnects exhibit reduced conductivity, making copper an undesirable material for advanced nodes.
• alternative materials have been sought to overcome the deficiencies of copper as an interconnect material.
• One such material is molybdenum.
• Molybdenum interconnects exhibit desirable electrical properties, even at the sub-10 nm scale. Yet, because molybdenum is a high hardness metal, molybdenum interconnect layers remain difficult to pattern during semiconductor device fabrication.
• a method of patterning a molybdenum interconnect layer includes forming a molybdenum layer on a substrate. A masking layer is then formed over the molybdenum layer and patterned to expose areas of the molybdenum layer to an ambient. The exposed areas of the molybdenum are modified with oxygen to form molybdenum oxide portions of the molybdenum interconnect layer. After modification, the molybdenum oxide portions of the molybdenum interconnect layer are removed from the substrate via an etching process.
• a method of forming a metal interconnect layer on a patterned substrate includes forming a molybdenum layer on the patterned substrate.
• a masking layer is formed on the molybdenum layer, the masking layer patterned to expose undesired areas of the molybdenum layer to an ambient.
• the patterned substrate is then exposed to a neutral particle beam to remove the undesired areas of the molybdenum layer.
• a method of patterning a metal interconnect layer on a substrate includes forming a molybdenum interconnect layer on the substrate.
• a mask is formed on the molybdenum layer and patterned to expose areas of the molybdenum interconnect layer.
• the substrate is then placed into a substrate processing region of a substrate processing chamber and exposed to gas-phase H2O at a partial pressure within a range of about 20 bar to about 55 bar and a temperature within a range of about 250°C to about 550°C to remove the exposed areas of the molybdenum interconnect later.
• Figure 1 illustrates a flow diagram of a method for patterning a molybdenum interconnect layer of a device, such as a semiconductor device, according to one embodiment of the present disclosure.
• Figure 2A illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer before portions of one or more layers on the substrate are removed, according to one embodiment of the present disclosure.
• Figure 2B illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer after portions of one or more layers on the substrate have been modified, according to one embodiment of the present disclosure.
• Figure 2C illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer after portions of one or more layers on the substrate have been modified, according to one embodiment of the present disclosure.
• Figure 2D illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer after portions of one or more layers on the substrate have been removed, according to one embodiment of the present disclosure.
• Figure 3 illustrates a flow diagram of a method for patterning a molybdenum interconnect layer of a device, such as a semiconductor device, according to one embodiment of the present disclosure.
• Figure 4A illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer before portions of one or more layers on the substrate have been removed, according to one embodiment of the present disclosure.
• Figure 4B illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer after portions of one or more layers on the substrate have been removed, according to one embodiment of the present disclosure.
• Figure 4C illustrates a schematic cross-sectional view of a portion of a semiconductor device including a molybdenum layer after further portions of one or more layers on the substrate have been removed, according to one embodiment of the present disclosure.
• Figure 5 illustrates a flow diagram of a method for patterning a molybdenum interconnect layer of a device, such as a semiconductor device, according to one embodiment of the present disclosure.
• the present disclosure provides methods for patterning a metal layer of a device (e.g., a semiconductor device) to form features in the interconnect layer as part of a process for manufacturing an interconnect structure of the device.
• the disclosed methods describe processes for patterning a molybdenum layer with improved selectivity.
• the disclosure provides methods for modifying and removing areas of the molybdenum layer by annealing or etching without damaging other device structures or materials.
• Figure 1 is a flow diagram of a method 100 for patterning a molybdenum layer of a device, such as a semiconductor device, according to one embodiment.
• the molybdenum layer can be disposed directly on a substrate surface.
• the molybdenum layer can be disposed on another metal layer, such as a barrier metal layer.
• the molybdenum layer can be disposed on a dielectric layer, such as a silicon dioxide layer.
• the patterning of the molybdenum layer can be used for manufacturing an interconnect structure of the device.
• the patterning method 100 can be performed in a process chamber, such as a plasma process chamber or other suitable process chamber.
• a semiconductor device 200 including a molybdenum layer 202 is positioned in a plasma process chamber, for example, an etching process chamber (not shown).
• the semiconductor device 200 can include one or more semiconductor devices that are in the process of being manufactured or in various stages of fabrication.
• Figure 2A is a schematic cross-sectional view of a portion of the semiconductor device 200 that includes the molybdenum layer 202 before portions of one or more layers disposed on a substrate 201 are removed, according to one embodiment.
• the view in Figure 2A shows the semiconductor device 200 before an initial patterning process (e.g., an oxidation process) is performed to modify portions of the molybdenum layer 202.
• an initial patterning process e.g., an oxidation process
• the semiconductor device 200 includes the substrate 201
• the substrate 201 can be formed of any suitable material such as silicon, crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, silicon on insulator (SOI), carbon doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire, among other materials.
• the substrate 201 is a 200 mm, 300 mm, 450 mm, or other diameter circular substrate.
• the substrate 201 is a rectangular substrate or a square substrate.
• the substrate 201 can further include a buried dielectric layer disposed on a silicon crystalline substrate.
• the molybdenum layer 202 is disposed on the substrate 201. In one embodiment, the molybdenum layer 202 is disposed directly on and in contact with the substrate 201. In other embodiments, the molybdenum layer 202 can be disposed on an intermediate layer (not shown), such as a dielectric layer. In these embodiments, the intermediate layer is disposed directly on and in contact with the substrate 201 , and the molybdenum layer 202 is disposed on the intermediate layer.
• the molybdenum layer 202 is used as an interconnect layer to connect multiple elements or devices of an integrated circuit.
• the semiconductor device 200 further includes a masking layer 203 during one or more stages of fabrication.
• the masking layer 203 can be formed directly on the molybdenum layer 202 or on an intermediate layer (not shown), such as a dielectric layer.
• the masking layer is formed of a material that is unreactive with wet etching solutions.
• the masking layer is formed of a low hardness material.
• the masking layer 203 is a hard mask, such as a carbon hard mask. Alternatively or in addition to the carbon hard mask, the masking layer 203 can be formed of other high hardness materials.
• high hardness materials include, but are not limited to, tungsten carbide (WC), tungsten boron carbide (WBC), tungsten nitride (WN), silicon boride (SiB x ) boron carbide (BC), amorphous carbon, boron nitride (BN), boron carbon nitride (BCN), or another similar material.
• the masking layer 203 materials described above can comprise compounds (e.g., a chemical compound of equal parts tungsten and carbon, a stoichiometric compound, etc.) or a doped material (e.g., a tungsten layer containing a small percentage of carbon).
• the masking layer 203 is a photoresist formed of light sensitive materials, such as naphtoquinone diazide (NQD) or other suitable photoreactive materials.
• NQD naphtoquinone diazide
• the substrate 201 is a thermally oxidized substrate.
• the molybdenum layer 202 may be formed directly on the substrate 201.
• the thermally oxidized substrate includes oxygen at the surface contacting the molybdenum layer 202.
• the oxygen from the thermally oxidized substrate is used to form a passivation layer (not shown) on an exposed surface of the semiconductor device 200.
• the passivation layer stops or substantially reduces further etching when the etching process breaks through the molybdenum layer 202.
• the oxygen from the thermally oxidized substrate can combine with silicon atoms from a silicon-containing gas used to etch the molybdenum layer 202 to form a passivation layer of silicon oxide on exposed portions of the semiconductor device 200 to stop the etching process.
• the passivation layer is described here as being formed in part by oxygen from a thermally oxidized substrate, the oxygen can come from a layer including oxygen that directly underlies the molybdenum layer 202.
• the semiconductor device 200 can further include a barrier layer (not shown) and a low-k insulating dielectric layer (not shown).
• the low-k insulating dielectric layer is disposed over the substrate 201 between the molybdenum layer 202 and the substrate 201.
• the barrier layer can be disposed over the low-k insulating dielectric layer between the molybdenum layer 202 and the low-k insulating dielectric layer.
• the barrier layer can be fabricated from tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AIN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), (silicon isocyanide) SiNC, silicon oxycarbide (SiOC), or other suitable materials.
• the low-k insulating dielectric layer can be formed from SiO containing materials, SiN containing materials, SiOC containing materials, SiC containing materials, carbon-based materials, or other suitable materials.
• FIG. 2B is a schematic cross-sectional view of a portion of the semiconductor device 200 including the molybdenum layer 202 after portions of the masking layer 203 disposed on the molybdenum layer 202 are removed, according to one embodiment.
• the removal of these portions of the masking layer 203 forms voids 205 in the masking layer 203, shown in Figure 2B as trenches, with the bottom of the voids 205 formed (i.e. bordered or partially defined) by the exposed portions 222 of the molybdenum layer 202.
• the removal of portions of the masking layer 203 exposes portions of the molybdenum layer 202.
• the use of the materials described above for the masking layer 203 i.e., the high hardness materials, such as WC
• the materials described above for the masking layer 203 can improve the process of selectively etching features above the molybdenum layer 202, eventually portions or all of the masking layer 203 are removed to form features on the device, such as transistor structures.
• FIG. 2C is a schematic cross-sectional view of a portion of the semiconductor device 200 including the molybdenum layer 202 after exposed portions 222 of the molybdenum layer 202 are oxidized, according to one embodiment.
• Exposed portions 222 may be oxidized by various methods, including but not limited to, direct oxygen ion implantation or oxygen plasma doping.
• implanted oxygen ions may be bombarded in a substantially vertical path against the exposed portions 222 of the molybdenum layer 202 to penetrate the exposed portions 222.
• the implanted ions can penetrate the exposed portions 222 to various depths depending on the power and bias utilized to energize the oxygen ions.
• the exposed portions 222 may be implanted with oxygen ions energized to an accelerating voltage of about 5 KeV to about 30 KeV, such as about 10 KeV to about 20 KeV, and at a dose ranging from about 0.5E16 ions/cm2 to about 5E17 ions/cm2, such as about 1 E16 ions/cm2 to about 1 E17 ions/cm2.
• the exposed portions 222 may be implanted with oxygen ions energized at 10 KeV and dosed at 1 E17 ions/cm2.
• the ion implantation may be performed by beam line or plasma implantation tools.
• a suitable, commercially available processing platform which may be advantageously employed in accordance with the embodiments described herein is the VIISTA ® PLADTM platform available from Applied Materials, Inc., Santa Clara, CA. It is contemplated that other suitably configured implant technology platforms from other manufacturers may also be used in accordance with the embodiments herein.
• the semiconductor device 200 is annealed to form a polycrystalline structure of the molybdenum oxide portions 223.
• the semiconductor device 200 is annealed by various methods, such as furnace annealing or rapid thermal annealing, for example, lamp based or laser annealing.
• the device structure 200 is annealed at a temperature between about 200 °C and about 600 °C, a pressure between about 0.5 bar to about 75 bar water vapor, and a duration between about 15 minutes to about 2 hours.
• the device structure 200 is annealed at a temperature between about 250 °C and about 550 °C, such as between about 300 °C and about 500 °C, such as between about 350 °C and about 450 °C. In some examples, the device structure 200 is annealed at a pressure between about 25 bar and about 55 bar, such as between about 30 bar and about 50 bar, such as between about 35 bar and about 45 bar. In some examples, the device structure 200 is annealed for a duration between about 30 minutes and about 1.5 hours, such as between 45 minutes and 75 minutes. In one example, the device structure 200 is annealed in conditions of 325 °C and 55 bar for about 60 minutes.
• the thermal anneal is performed at high pressure and in the presence of a processing gas, such as hydrogen, deuterium, fluorine, chlorine, ammonium, or other suitable gases for high pressure gas annealing.
• a processing gas such as hydrogen, deuterium, fluorine, chlorine, ammonium, or other suitable gases for high pressure gas annealing.
• Annealing the semiconductor device 200 at high pressure levels facilitates the formation the polycrystalline structure of the molybdenum oxide portions 223 even at low temperatures, for example, less than 350 °C.
• the molybdenum oxide portions 223 are removed from the semiconductor device 200 to form a patterned molybdenum layer 204.
• Figure 2D is a schematic cross-sectional view of a portion of the substrate 201 including the patterned molybdenum layer 204 after the molybdenum oxide portions 223 are removed. The removal of the molybdenum oxide portions 223 forms the voids 205 in the patterned molybdenum layer 204, shown in Figure 2D as trenches with the bottom of the voids 205 formed by a top surface 207 of the substrate 201.
• Molybdenum oxide portions 223 may be removed from the substrate 201 by any suitable process of etching which is selective for molybdenum oxide, including wet etching or dry etching processes.
• the molybdenum oxide portions 223 are removed from the substrate 201 by wet etching with an ammonia solution.
• the ammonia solution is selective for the oxidized portions 223.
• the oxidized portions 223 are removed while the patterned molybdenum layer 204, which is non-oxidized, is not removed by the ammonia solution.
• the ammonia solution may include ammonia hydroxide at a concentration of about 26% w/w to about 30% w/w, such as about 28% w/w.
• the semiconductor device 200 may be exposed to the ammonia solution for etching a desired depth of the molybdenum oxide portions 223, such as for a duration of between about 2 minutes and about 10 minutes.
• the molybdenum oxide portions 223 are removed from the semiconductor device 200 by wet etching with a pH 10 buffer solution.
• the pH 10 buffer solution includes a sodium compound such as sodium tetraborate or sodium hydroxide.
• the semiconductor device 200 may be exposed to the pH 10 buffer solution for etching a desired depth of the molybdenum oxide portions 223, such as for a duration between about 2 minutes and about 10 minutes.
• FIG 3 is a flow diagram of a method 300 for patterning a molybdenum layer of a device, such as a semiconductor device, by neutral atom beam etching, according to one embodiment.
• the molybdenum layer 202 can be disposed directly on the substrate 201 , or on another layer, such as a metal layer or a dielectric layer.
• the patterning of the molybdenum layer 202 according to the current embodiment can be used for manufacturing an interconnect structure of the semiconductor device 200.
• the patterning method 300 is performed in a process chamber, such as a plasma process chamber or a neutral atom beam etching apparatus.
• the semiconductor device 200 (see Figure 4A) including the molybdenum layer 202 is positioned in a plasma process chamber, for example an etching process chamber (not shown).
• the semiconductor device 200 can include one or more semiconductor devices that are in the process of being manufactured or in various stages of fabrication.
• Figure 4A is a schematic cross- sectional view of a portion of the semiconductor device 200 that includes the molybdenum layer 202 before portions of one or more layers disposed on the substrate 201 are removed, according to one embodiment.
• the view in Figure 4A shows the semiconductor device 200 before a patterning process (e.g., a neutral beam etch) is performed to modify portions of the molybdenum layer 202.
• a patterning process e.g., a neutral beam etch
• FIG. 4B is a schematic cross-sectional view of a portion of the semiconductor device 200 including the molybdenum layer 202 after portions of the masking layer 203 disposed on the molybdenum layer 202 are removed, according to one embodiment.
• the removal of these portions of the masking layer 203 forms voids 205 in the masking layer 203, shown in Figure 4B as trenches with the bottom of the voids 205 formed (i.e. bordered or partially defined) by the exposed portions 222 of the molybdenum layer 202.
• the removal of portions of the masking layer 203 exposes portions of the molybdenum layer 202.
• FIG. 4C is a schematic cross-sectional view of a portion of the semiconductor device 200 including the patterned molybdenum layer 204 after exposed portions 222 of the molybdenum layer 202 are removed.
• the removal of the exposed portions 222 forms voids 205 in the patterned molybdenum layer 204, shown in figure 4C as trenches with the bottom of the voids 205 formed by a top surface of the substrate 201.
• the exposed portions 222 of the molybdenum layer 202 may be removed from the semiconductor device 200 by an accelerated atom beam process.
• a suitable, commercially available processing platform which may be advantageously employed in accordance with the embodiments described herein is the NanoAccelTM platform available from Exogenesis Corp., Billerica, Massachusetts. It is contemplated that other suitably configured accelerated atom beam platforms from other manufacturers may also be used in accordance with the embodiments herein.
• the exposed portions 222 of the molybdenum layer 202 may be removed by a gas cluster ion beam (GCIB) etch.
• GCIB gas cluster ion beam
• a pressurized inert gas may be flowed, expanded, and accelerated toward the exposed portions 222 of the molybdenum layer 202 within a processing chamber, transferring energy to and causing removal of the outermost atoms of the exposed portions 222.
• the gas cluster ion beam is formed of argon gas.
• additional gases may be combined with an inert gas to form the gas cluster ion beam, including oxygen (O2), nitrogen (N2), methane (CFU), and sulfur hexafluoride (SF6).
• the gas cluster ion beam may be directed in a substantially vertical path through the voids 205 in the masking layer 203 so as penetrate desired portions of the molybdenum layer 202 and form the patterned molybdenum layer 204. Thus, other device structures or material layers on the semiconductor device 200 are left undamaged during the gas cluster ion beam etch.
• the gas cluster ion beam may be accelerated to an accelerating voltage of 10 KeV to 40 KeV, such as 15 KeV to 35 KeV.
• the gas cluster ion beam is accelerated to an accelerating voltage of 25 KeV.
• the semiconductor device 200 may be exposed to the gas cluster ion beam for any suitable dose time, such as between about 0 seconds and about 30 seconds, including between 2-20 seconds. For example, the semiconductor device 200 may be exposed to the gas cluster ion beam for a dose time of 6, 8, 10, 14, or 18 seconds.
• an accelerated neutral atom beam (ANAB) etch is used to remove the exposed portions 222 of the molybdenum layer 202 from the semiconductor device 200. Similar to GCIB etching, accelerated neutral atom beam etching utilizes a beam of accelerated gas cluster ions, but the gas cluster is dissociated and the charge is removed prior to impacting the surface of the exposed portions 222. The accelerated neutral atom beam is directed in a substantially vertical path through the voids 205 in the masking layer 203 so as to penetrate desired portions of the molybdenum layer 202. Further, each atom inside the neutral atom beam has relatively low energy, leading to limited surface modification of only a few atomic layers and thus, significantly reducing or eliminating etching damage to other materials and layers or the semiconductor device 200.
• ANAB accelerated neutral atom beam
• the accelerated neutral atom beam is accelerated to an accelerating voltage of 10 KeV to 40 KeV, such as 15 KeV to 35 KeV.
• the accelerated neutral atom beam is accelerated to an accelerating voltage of 25 KeV.
• the semiconductor device 200 is exposed to the accelerated neutral atom beam for any suitable dose time such as between about 0 seconds and about 30 seconds, including between 2-20 seconds.
• the semiconductor device 200 may be exposed to the accelerated neutral atom beam for a dose time of 6, 8, 10, 14, or 18 seconds.
• Inert gases, such as argon may be used to form the accelerated neutral atom beam.
• additional gases may be combined with the inert gas, including (O2), nitrogen (N2), methane (CFU), and sulfur hexafluoride (SFe).
• the ANAB etching may be performed at any suitable etching conditions.
• FIG. 5 is a flow diagram of a method 500 for patterning a molybdenum layer of a device, such as a semiconductor device, by high pressure water anneal according to one embodiment.
• the molybdenum layer can be disposed directly on a substrate surface, or on another layer, such as a metal layer or a dielectric layer.
• the patterning of the molybdenum layer according to the current embodiment which may be combined with other embodiments and examples described herein, can be used for manufacturing an interconnect structure of the device.
• the patterning method 500 is performed in a plasma process chamber, such as an etching process chamber or other suitable process apparatus.
• the method 500 is described below with reference to the molybdenum layer being utilized to form an interconnect structure, the method 500 can also be used to advantage with materials other than molybdenum and in other semiconductor device manufacturing applications.
• a semiconductor device including a molybdenum layer is positioned in a plasma process chamber, such as an etching process chamber (not shown).
• the semiconductor device can include one or more semiconductor devices that are in the process of being manufactured.
• the semiconductor device further includes a substrate, the molybdenum layer disposed over the substrate, and a masking layer, for example, similar to the substrate 201 , the molybdenum layer 202, and the masking layer 203 described with regard to Figures 2 and 4.
• the semiconductor device can also include other material layers disposed on the substrate, such as a barrier layer or a low-k insulating layer.
• portions of the masking layer are removed to form exposed portions of the molybdenum layer.
• the removal of these portions of the masking layer forms voids 205 in the masking layer, the bottom of the voids 205 formed by the exposed portions of the molybdenum layer.
• the removal of portions of the masking layer exposes portions of the molybdenum layer.
• the semiconductor device is exposed to a high pressure water anneal (HPWA) process to remove the exposed portions of the molybdenum layer from the semiconductor device.
• HPWA high pressure water anneal
• method 500 describes a high pressure water anneal utilizing water vapor to anneal the semiconductor device, it is contemplated that other gases may be used to anneal the semiconductor device under high pressure.
• the semiconductor device may be annealed at high pressure using hydrogen, deuterium, fluorine, chlorine, ammonium, or other suitable gases.
• the semiconductor device may be annealed using a combination of gases including hydrogen, deuterium, fluorine, chlorine, ammonium, and other suitable gases.
• the processing chamber is pressurized by supplying water vapor from a pressure chamber to the processing chamber, followed by thermal annealing of the device and depressurization of the processing chamber by evacuation of the water vapor.
• the thermal annealing is performed at a temperature of between about 250 °C and about 450 °C, such as between about 300 °C and about 400 °C.
• the thermal annealing is performed at a temperature of between about 325 °C and about 375 °C.
• the processing chamber is pressurized to a pressure of between about 10 bar and about 75 bar, such as between about 20 bar and about 60 bar.
• the processing chamber is pressurized to a pressure of between about 30 bar and about 50 bar.
• the exposure of the device to high pressure water vapor annealing removes the exposed portions of the molybdenum layer, thus forming a patterned molybdenum layer without damaging other device structures or material layers.
• Embodiments of the disclosure include methods for patterning a metal layer of a device to form features in the interconnect layer as part of a process for manufacturing an interconnect structure of the device.
• the disclosed methods describe processes for patterning a molybdenum layer with improved selectivity. Increased selectivity in patterning molybdenum layers enables the formation of interconnect structures, as well as other metal layers, without the disadvantages associated with patterning high hardness materials, including large undercut and damage to other layers and structures stacked within a semiconductor device.
• methods provided herein make molybdenum, as well as other high hardness metals, more desirable and practicable materials for device structures such as interconnect structures.

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• 2019
  • 2019-09-30 JP JP2021529724A patent/JP7507761B2/ja active Active
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