WO2020107148A1 - 显示面板及其驱动方法 - Google Patents

显示面板及其驱动方法 Download PDF

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Publication number
WO2020107148A1
WO2020107148A1 PCT/CN2018/117416 CN2018117416W WO2020107148A1 WO 2020107148 A1 WO2020107148 A1 WO 2020107148A1 CN 2018117416 W CN2018117416 W CN 2018117416W WO 2020107148 A1 WO2020107148 A1 WO 2020107148A1
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WO
WIPO (PCT)
Prior art keywords
trace
signal
voltage feedback
decoupling
display panel
Prior art date
Application number
PCT/CN2018/117416
Other languages
English (en)
French (fr)
Inventor
吕耀朝
程浩
李宗祥
廖加敏
陶文昌
洪贵春
吴振钿
林琳琳
刘祖文
王进
邱鑫茂
石常洪
庄子华
周敏
黄雅雯
刘耀
朱敬光
林剑涛
陈曦
Original Assignee
京东方科技集团股份有限公司
福州京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 福州京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP18926379.1A priority Critical patent/EP3889949A4/en
Priority to PCT/CN2018/117416 priority patent/WO2020107148A1/zh
Priority to CN201880002165.9A priority patent/CN111566720B/zh
Priority to US16/633,388 priority patent/US11158281B2/en
Publication of WO2020107148A1 publication Critical patent/WO2020107148A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0281—Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the embodiments of the present disclosure relate to a display panel and a driving method thereof.
  • Liquid crystal display devices as the most common flat panel display devices, have been widely used in various applications.
  • Organic light emitting diode (Organic Light Emitting Diode, OLED) display devices are gradually gaining popularity due to their advantages of wide viewing angle, high contrast, fast response speed, and higher luminous brightness and lower driving voltage compared to inorganic light emitting display devices. extensive attention.
  • Liquid crystal display devices and organic light-emitting diodes (OLEDs) can be applied to devices with display functions such as mobile phones, monitors, notebook computers, digital cameras, instruments and meters.
  • At least one embodiment of the present disclosure provides a display panel including an array substrate.
  • the display panel includes a display area and a peripheral area surrounding the display area.
  • common voltage traces, voltage feedback traces, periodic signal traces, and decoupling traces are arranged at intervals on the array substrate; the common voltage traces are configured to
  • the pixel array in the display area transmits a common voltage signal for display, the voltage feedback trace is configured to transmit a voltage feedback signal for monitoring the change of the common voltage signal, and the periodic signal trace is configured to The pixel array provides a periodic signal for display, the decoupling trace is located between the periodic signal trace and the voltage feedback trace, and is configured to transmit a decoupling signal, the decoupling signal is used for The coupling distortion caused by the coupling effect of the periodic signal by the voltage feedback signal is reduced.
  • the decoupling signal is a periodic pulse signal; the pulse period of the decoupling signal is equal to the period in which the coupling distortion occurs in the voltage feedback signal, the The phase of the decoupling signal is opposite to the phase of the voltage feedback signal when the coupling distortion occurs.
  • the pulse width of the decoupling signal and the time when the coupling distortion occurs in the voltage feedback signal are equal.
  • the pulse width of the decoupling signal is greater than the time when the coupling distortion occurs in the voltage feedback signal.
  • the periodic signal traces include clock signal traces and/or frame start signal traces.
  • the display panel further includes a signal processing circuit, the signal processing circuit is connected to the decoupling trace, and is configured to output the decoupling signal to The decoupling trace.
  • a ground trace spaced apart from the voltage feedback trace is further provided on the array substrate, and the voltage feedback trace A capacitance to ground is formed between the ground trace.
  • the array substrate in the peripheral area, further includes a first conductive layer and a connection electrode, the first conductive layer is insulated from the ground trace, and An orthographic projection of the first conductive layer on the array substrate and an orthographic projection of the ground trace on the array substrate at least partially overlap, and the first conductive layer is electrically connected to the voltage feedback trace,
  • the capacitance to ground is formed between the first conductive layer and the ground trace; the connection electrode and the first conductive layer are electrically connected through the first via and are connected to the ground trace Insulated, the connection electrode and the voltage feedback trace are electrically connected through a second via.
  • the array substrate in the peripheral area, further includes a first conductive layer and a connection electrode, the first conductive layer is insulated from the voltage feedback trace, The orthographic projection of the first conductive layer on the array substrate and the orthographic projection of the voltage feedback trace on the array substrate at least partially overlap, and the first conductive layer is electrically connected to the ground trace , Whereby the capacitance to ground is formed between the first conductive layer and the voltage feedback trace; the connection electrode and the first conductive layer are electrically connected through the first via and are connected to the voltage The feedback trace is insulated, and the connection electrode and the ground trace are electrically connected through a second via.
  • the first conductive layer and the gate or source/drain of the thin film transistor in the display area are formed of the same material and the same layer.
  • the ground trace and the voltage feedback trace are formed on the array substrate at the same layer and the same material.
  • the display panel provided by an embodiment of the present disclosure further includes a counter substrate.
  • a black matrix is provided on the opposite substrate, the thickness of the black matrix provided in the first area is smaller than the thickness of the black matrix provided in the second area, the first area includes the voltage feedback trace and The area of the orthographic projection of the periodic signal trace on the opposite substrate, and the second area is an area outside the first area on the opposite substrate.
  • the first area further includes an area of the orthographic projection of the common voltage trace and the decoupling trace on the opposite substrate.
  • the counter substrate includes a color filter substrate.
  • At least one embodiment of the present disclosure also provides a driving method for the display panel according to any embodiment of the present disclosure, the driving method includes: transmitting the decoupling signal through the decoupling trace, the decoupling signal The coupling signal is used to reduce coupling distortion of the voltage feedback signal caused by the coupling effect of the periodic signal.
  • the decoupling signal is a periodic pulse signal; the pulse period of the decoupling signal is equal to the period in which the coupling distortion occurs in the voltage feedback signal, the The phase of the decoupling signal is opposite to the phase of the voltage feedback signal when the coupling distortion occurs.
  • the pulse width of the decoupling signal and the time at which the coupling distortion occurs in the voltage feedback signal are equal.
  • the pulse width of the decoupling signal is greater than the time when the coupling distortion occurs in the voltage feedback signal.
  • FIG. 1 is a schematic diagram of a display panel
  • FIG. 2 is a schematic diagram of the part corresponding to the dotted frame in FIG. 1;
  • FIG. 3 is a signal timing diagram of the display panel shown in FIG. 1 when periodic horizontal stripes are defective;
  • FIG. 4 is a schematic diagram of a display panel provided by some embodiments of the present disclosure.
  • FIG. 5 is a schematic diagram 1 of the portion corresponding to the dotted frame in FIG. 4;
  • FIG. 6 is a schematic diagram 2 of the portion corresponding to the dotted frame in FIG. 4;
  • FIG. 7 is a schematic diagram 1 of signals transmitted by voltage feedback traces, clock signal traces, and decoupling traces;
  • FIG. 8 is a schematic diagram 2 of signals transmitted by voltage feedback traces, clock signal traces, and decoupling traces;
  • FIG. 9 is a schematic diagram of another display panel provided by some embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram 1 of the portion corresponding to the dotted frame in FIG. 9;
  • FIG. 11 is a cross-sectional view taken along line AA' in FIG. 10;
  • FIG. 12 is a schematic diagram 2 of the portion corresponding to the dotted frame in FIG. 9;
  • FIG. 13 is a cross-sectional view taken along line BB' in FIG. 12;
  • 14A-14C are three schematic diagrams of cutting the opposite substrates located in the peripheral area
  • FIG. 15 is a cross-sectional view of yet another display panel provided by some embodiments of the present disclosure.
  • 16 is a cross-sectional view of yet another display panel provided by some embodiments of the present disclosure.
  • FIG. 1 shows a schematic diagram of a display panel.
  • the display panel is a liquid crystal display panel.
  • the display panel includes a display area 610 and a peripheral area 620 surrounding the display area 610.
  • a pixel array composed of multiple rows and columns of pixel units (for example, each pixel includes three types of RGB pixel units) is provided in the display area 610 for display operations. It should be noted that, only three rows and three columns of pixel units are schematically shown in FIG. 1, and embodiments of the present disclosure include but are not limited to this.
  • the peripheral area 620 includes a driving circuit area 621 and a trace area 622.
  • a drive circuit for driving the pixel array is provided in the drive circuit area 621.
  • the drive circuit may use a GOA (gate driver on array, array substrate row drive) circuit.
  • a plurality of traces are arranged at intervals in the trace area 622, for example, the plurality of traces may be parallel and insulated when arranged.
  • FIG. 2 shows a schematic diagram of the portion corresponding to the dotted frame in FIG. 1.
  • multiple traces include a common voltage trace VC, a voltage feedback trace FB, a frame start signal trace STV, and multiple clock signal traces (CLK1...CLKN).
  • the ends of the above multiple traces can be connected to the printed circuit board 710 through the electrode pins 730 and the flexible circuit film 720.
  • the circuit provided on the printed circuit board 710 can provide various signals necessary for driving the display operation to the GOA circuit through multiple traces. These signals include a clock signal (CLK), a frame start signal (STV), and a power supply voltage. Signal (VDD), etc.
  • the display operation is mainly performed by the voltage difference between the data voltage applied to the pixel electrode in each pixel unit and the common voltage Vcom applied to the common electrode.
  • the liquid crystal molecules are driven to deflect, thereby realizing various gray scale displays. Therefore, when performing a display operation, the stability of the common voltage Vcom becomes very important.
  • the pixel array may be provided with a common voltage Vcom through a common voltage trace VC.
  • the common voltage Vcom in the display panel may be monitored and reversely compensated according to the change of the common voltage Vcom, so that the common voltage Vcom in the display panel is maintained at a stable value.
  • a voltage feedback trace FB may be provided in the trace area 622, and the voltage feedback trace FB is used to transmit a voltage feedback signal that monitors the change of the common voltage Vcom.
  • the voltage feedback signal can be transmitted to the signal processing circuit provided in the printed circuit board 710, for example, the signal processing circuit can reversely compensate the common voltage Vcom according to the voltage feedback signal, thereby making the common voltage in the display panel Vcom can be maintained at a stable value.
  • the wiring density in the routing area 622 is large.
  • the clock signal provided by multiple clock signal traces (CLK1...CLKN, N is an integer greater than 1) and the frame start signal trace provided by the STV frame start signal are periodic signals.
  • the voltage The voltage feedback signal transmitted by the feedback trace FB is easily affected by the coupling of these periodic signals, resulting in periodic distortion of the voltage feedback signal.
  • the signal processing circuit When the signal processing circuit receives the voltage feedback signal with periodic distortion described above, it will be considered that the common voltage Vcom has changed, and then reverse compensation of the common voltage Vcom will cause the corresponding common voltage Vcom in the display panel to appear corresponding Periodic distortion causes periodic stripes to appear on the display panel when displaying images, which affects the display quality.
  • Fig. 3 shows a schematic diagram of the occurrence of the above-mentioned periodic defective horizontal stripes.
  • the clock signal transmitted by the clock signal trace CLK1 the clock signal transmitted by the clock signal trace CLK1
  • the voltage feedback signal transmitted by the voltage feedback trace FB the common voltage Vcom transmitted by the common voltage trace VC after reverse compensation.
  • the above-mentioned reverse compensation may be doubled or multipled.
  • FIG. 3 is an example of performing multiple reverse compensation.
  • the compensation multiple for reverse compensation needs to be determined according to the actual situation. When the compensation multiple is too large, the signal distortion of the voltage feedback signal due to coupling will also be amplified. Therefore, by reducing the compensation multiple, the above-mentioned periodic poor horizontal stripes can be improved.
  • the already determined compensation factor cannot be fully applied to all generated products. Therefore, it is necessary to reduce the coupling effect of the voltage feedback trace FB in the display panel itself as much as possible.
  • At least one embodiment of the present disclosure provides a display panel including an array substrate.
  • the display panel includes a display area and a peripheral area surrounding the display area.
  • common voltage traces, voltage feedback traces, periodic signal traces, and decoupling traces are arranged at intervals on the array substrate.
  • the common voltage trace is configured to transmit a common voltage signal for display to the pixel array in the display area
  • the voltage feedback trace is configured to transmit a voltage feedback signal for monitoring changes in the common voltage signal
  • the periodic signal trace is configured as Provides a periodic signal for display to the pixel array.
  • the decoupling trace is located between the periodic signal trace and the voltage feedback trace. It is configured to transmit the decoupling signal.
  • the decoupling signal is used to reduce the voltage feedback signal from the periodic signal. Coupling distortion caused by the coupling effect.
  • At least one embodiment of the present disclosure also provides a driving method corresponding to the above display panel.
  • the display panel and the driving method thereof provided by the embodiments of the present disclosure can reduce the coupling effect of the periodic signal on the voltage feedback trace, thereby avoiding the occurrence of poor periodic stripes in the display panel.
  • FIG. 4 shows a schematic diagram of the display panel.
  • the display panel includes an array substrate 100.
  • the display panel includes a display area 410 and a peripheral area 420 surrounding the display area 410.
  • a pixel array composed of a plurality of rows and columns of pixel units (for example, each pixel includes three types of RGB pixel units) is provided in the display area 410 for display operation. It should be noted that, only three rows and three columns of pixel units are schematically shown in FIG. 4, and embodiments of the present disclosure include but are not limited to this.
  • the peripheral area 420 includes a driving circuit area 421 and a trace area 422.
  • a drive circuit for driving the pixel array is provided in the drive circuit area 421.
  • the drive circuit may use a GOA (gate driver on array, array substrate row drive) circuit.
  • a plurality of traces are arranged at intervals in the trace area 422, for example, the plurality of traces are parallel and insulated from each other.
  • FIG. 5 shows a schematic diagram of the portion corresponding to the dotted frame in FIG. 4.
  • a common voltage trace VC, a voltage feedback trace FB, a periodic signal trace, and a decoupling trace DP are provided on the array substrate 100 at intervals.
  • the common voltage trace VC, the voltage feedback trace FB, the periodic signal trace, and the decoupling trace DP may be formed on the array substrate 100 with the same layer and the same material.
  • the heights of the plurality of traces may be the same or different, which is not limited in the embodiments of the present disclosure.
  • forming the same layer and the same material refers to patterning the same material layer through the same patterning process to form multiple structures (for example, multiple traces) It is not necessarily in the same plane in physical space.
  • the ends of the above multiple traces may be connected to the printed circuit board 510 through the electrode pins 530 and the flexible circuit film 520.
  • the circuit provided on the printed circuit board 510 can provide various signals necessary for driving the display operation to the GOA circuit through multiple traces.
  • the common voltage trace VC is configured to transmit the common voltage signal Vcom for display to the pixel array in the display area 410.
  • each pixel unit in the pixel array can drive the liquid crystal to deflect according to the voltage difference between the common voltage signal Vcom and the data voltage applied to the pixel electrode, thereby achieving different gray levels Display.
  • the voltage feedback trace FB is configured to transmit a voltage feedback signal for monitoring changes in the common voltage signal Vcom.
  • the voltage feedback trace FB can monitor the change of the common voltage signal Vcom and output a voltage feedback signal.
  • the voltage feedback trace FB can be connected to the far end of the common voltage trace VC (for example, the end close to the printed circuit board 510 is the near end, and the end far from the printed circuit board 510 is the far end), which can be more accurate Ground to monitor the common voltage signal Vcom.
  • the display panel further includes a signal processing circuit 540, and the voltage feedback trace FB is connected to the signal processing circuit 540, so that the voltage feedback signal can be transmitted to the signal processing circuit 540 for further processing.
  • the signal processing circuit 540 may be provided on the printed circuit board 510.
  • the periodic signal trace is configured to provide a periodic signal for display to the pixel array.
  • these periodic signal traces include multiple clock signal traces (CLK1...CLKN, N is an integer greater than 1) and a frame start signal trace STV.
  • the clock signal trace provides a periodic clock signal to the GOA circuit
  • the frame start signal trace STV provides a periodic frame start signal to the GOA circuit
  • the GOA circuit outputs the clock by the clock signal and the frame start signal. Line scan signal to drive the pixel array for display.
  • the periodic signal traces in the embodiments of the present disclosure include, but are not limited to, the clock signal trace and the frame start signal trace STV shown in FIG. 5, and may also include a frame reset signal trace, for example.
  • the decoupling trace DP is located between the periodic signal trace and the voltage feedback trace FB, and is configured to transmit the decoupling signal and decouple The signal is used to reduce the coupling distortion of the voltage feedback signal caused by the coupling effect of the periodic signal.
  • the relative positions of the common voltage trace VC and the voltage feedback trace FB are not limited.
  • the voltage feedback trace FB is located on the side of the common voltage trace VC away from the clock signal trace CLK1.
  • the voltage feedback trace FB is located on the side of the common voltage trace VC close to the clock signal trace CLK1.
  • FIGS. 7 and 8 show timing diagrams of the decoupling signal, voltage feedback signal, and periodic signal transmitted by the decoupling trace DP. It should be noted that FIGS. 7 and 8 are illustrated by taking the periodic signal as the clock signal as an example.
  • the decoupling signal transmitted by the decoupling trace DP is a periodic pulse signal.
  • the pulse period of the decoupling signal is equal to the period of the coupling distortion of the voltage feedback signal, and the phase of the decoupling signal is opposite to the phase of the coupling distortion of the voltage feedback signal.
  • the phase of the decoupling signal is opposite to that of the voltage feedback signal when the coupling distortion occurs: it means that the potential of the voltage feedback signal when the coupling distortion occurs becomes higher, then the corresponding decoupling signal The potential becomes lower; when the coupling distortion of the voltage feedback signal becomes lower, the potential of the corresponding decoupling signal becomes higher.
  • the display panel further includes a signal processing circuit 540, and a voltage feedback trace FB and a decoupling trace DP are connected to the signal processing circuit 540.
  • the signal processing circuit 540 may The coupled signal is output to the decoupling trace DP.
  • the signal processing circuit 540 may be provided on the printed circuit board 510.
  • the voltage can be reduced
  • the feedback signal is subjected to coupling distortion caused by the coupling effect of the periodic signal, thereby avoiding the occurrence of poor periodic horizontal stripes of the display panel.
  • the pulse width of the decoupling signal and the time for the coupling distortion of the voltage feedback signal are equal.
  • the pulse width of the decoupling signal is greater than the time when the voltage feedback signal is coupled.
  • the coupling distortion of the voltage feedback signal can be reduced by adjusting the pulse width and/or pulse amplitude of the decoupling signal, thereby avoiding the occurrence of periodic stripes.
  • the frequency of the coupling distortion signal caused by the trace FB is 0.3 MHz
  • the frequency of the signal normally fed back by the voltage feedback trace FB due to the fluctuation of the common voltage signal is 240 Hz under normal circumstances. Therefore, a capacitance to ground can be formed on the array substrate, so that the high-frequency coupling distortion signal in the voltage feedback signal can be filtered by the capacitance to ground, and at the same time, the fluctuation of the common voltage signal can be normally fed back.
  • FIG. 10 shows a schematic diagram of the portion corresponding to the dotted frame in FIG. 9.
  • an array substrate 100 is further provided with a distance from the voltage feedback trace FB
  • the ground trace GND has a capacitance to ground between the voltage feedback trace FB and the ground trace GND.
  • the capacitance to ground is connected in parallel between the voltage feedback trace FB and the ground trace GND.
  • the capacitance to ground is formed at the end of the voltage feedback trace FB close to the printed circuit board 510.
  • the array substrate 100 in the peripheral area of the display panel, includes a glass substrate 110 as a base substrate and a first conductive layer 101 provided on the glass substrate 110.
  • the first conductive layer 101 is insulated from the ground trace GND, and the orthographic projection of the first conductive layer 101 on the array substrate (ie, glass substrate 110) and the orthographic projection of the ground trace GND on the array substrate (ie, glass substrate 110) are at least Partial overlap.
  • the first conductive layer 101 and the voltage feedback trace FB are electrically connected, whereby a capacitance to ground is formed between the first conductive layer 101 and the ground trace GND.
  • the voltage feedback trace FB and the ground trace GND are formed on the array substrate (that is, the glass substrate 110) with the same layer and the same material.
  • the voltage feedback trace FB and the ground trace GND can be formed with the same layer and the same material as an electrode in the display area, so that the voltage feedback can be formed in the peripheral area while forming the electrode in the display area through a patterning process Trace FB and ground trace GND.
  • the base substrate may also be a plastic substrate or other types of substrates, which is not limited herein.
  • the first conductive layer 101 and the gate or source/drain of the thin film transistor in the display area are formed in the same layer and the same material.
  • the voltage feedback trace FB and the ground trace GND can be formed by the same patterning process as the gate of the thin film transistor, and the first conductive layer 101 can be The source and drain are formed by the same patterning process.
  • the voltage feedback trace FB and the ground trace GND may be formed by the same patterning process as the source and drain of the thin film transistor, and the first conductive layer 101 may The gate electrode of the thin film transistor is formed by the same patterning process.
  • the embodiments of the present disclosure do not limit this.
  • the array substrate 100 further includes a connection electrode 102, which is electrically connected to the first conductive layer 101 through the first via 103 and is insulated from the ground trace GND to connect the electrode 102 is electrically connected to the voltage feedback trace FB through the second via 104.
  • the array substrate 100 further includes a first insulating layer 105 and a second insulating layer 106.
  • the first conductive layer 101 is insulated from the ground trace GND by the first insulating layer 105.
  • the first via 103 penetrates the second insulating layer 106
  • the second via 104 penetrates the first insulating layer 105 and the second insulating layer 106
  • the connection electrode 102 is formed on the second insulating layer 106 and covers the first via 103 and the first Two via holes 104, so that the connection electrode 102 is electrically connected to the first conductive layer 103 through the first via hole 103, so that the connection electrode 102 is connected to the voltage feedback trace FB through the second via hole 104.
  • the first insulating layer 105 may be formed by the same patterning process as the gate insulating layer in the display area.
  • the second insulating layer 106 may be formed through the same patterning process as the passivation layer in the display area.
  • connection electrode 102 may be made of transparent metal oxide, such as ITO (Indium Tin Oxide).
  • FIGS. 12 and 13 are cross-sectional views taken along line BB′ in FIG. 12.
  • the first conductive The layer 101 is insulated from the voltage feedback trace FB, and the orthographic projection of the first conductive layer 101 on the array substrate (ie, the glass substrate 110) and the orthographic projection of the voltage feedback trace FB on the array substrate (ie, the glass substrate 110) are at least partially Overlap, the first conductive layer 101 and the ground trace GND are electrically connected, whereby a capacitance to ground is formed between the first conductive layer 101 and the voltage feedback trace FB.
  • the connection electrode 102 and the first conductive layer 101 are electrically connected through the first via 103 and insulated from the voltage feedback trace FB, and the connection electrode 102 and the ground trace GND are electrically connected through the second via 104.
  • the display panel provided by some embodiments of the present disclosure, by forming a capacitance to ground between the voltage feedback trace FB and the ground trace GND, the high-frequency coupling distortion signal in the voltage feedback signal can be filtered while In addition, the fluctuation of the common voltage signal can be normally fed back, so that the coupling distortion of the voltage feedback signal can be reduced, and periodic horizontal stripes of the display panel can be avoided.
  • FIGS. 14A, 14B, and 14C respectively show schematic diagrams of uncut, partial cut on the right side, and cut off on the right side of the opposite substrate located in the peripheral area 420, for example, the signal of the coupling distortion of the corresponding voltage feedback trace FB
  • the voltage amplitudes are 0.24V, 0.13V, and 0.1V, respectively.
  • a black matrix BM is generally required in the display area and the peripheral area. Since the black matrix BM needs to have light-shielding properties, a certain amount of conductive particles (for example, carbon particles) are often added to the material of the black matrix BM ), conductive particles generate induced charges under the action of periodic signals (such as clock signals transmitted on clock signal traces), and voltage feedback traces FB may be distorted by the influence of the induced charges. Therefore, in order to reduce the influence of the black matrix BM on the voltage feedback trace FB, the resistance of the black matrix BM can be increased.
  • conductive particles for example, carbon particles
  • the provided display panel further includes a counter substrate 200, for example, the counter substrate 200 is a color filter substrate.
  • the counter substrate 200 is a color filter substrate.
  • a black matrix BM is provided on the opposing substrate, and the thickness of the black matrix BM provided in the first region 210 is smaller than the thickness of the black matrix BM provided in the second region 220.
  • the first area 210 is an area including an orthographic projection of a voltage feedback trace FB and a periodic signal trace (such as a clock signal trace CLK or a frame start signal line) on the opposite substrate 200, and the second area 220 is opposite
  • the area other than the first area 210 on the substrate 200, for example, the second area is other area than the first area 210 in the peripheral area on the opposite substrate 200, for example, the second area is the display area.
  • the thickness of the black matrix BM in the first region 210 can be made smaller than the thickness of the black matrix BM in the second region 220 by adopting a halftone mask process (HTM) when forming the black matrix.
  • HTM halftone mask process
  • 120 in the figure is the sealant.
  • the resistance of the black matrix BM can be reduced, thereby reducing the ability of the black matrix BM to induce charges, thereby reducing the periodic signal to voltage feedback
  • the coupling effect of the trace FB prevents the display panel from having bad periodic stripes.
  • the first region 210 further includes a common voltage trace VC and a decoupling trace The area of orthographic projection of DP on the counter substrate 200.
  • the first area 210 further includes an area where the ground trace GND is orthographically projected on the opposite substrate 200.
  • the display panel shown in FIG. 16 can further reduce the resistance of the black matrix BM, thereby reducing the ability of the black matrix BM to induce charge, and thus reducing the periodic signal to the voltage feedback trace FB Coupling effect, to avoid periodic horizontal stripes in the display panel.
  • Some embodiments of the present disclosure also provide a driving method of the display panel, and the driving method may be used for any display panel provided by the embodiments of the present disclosure.
  • the driving method includes: transmitting a decoupling signal through a decoupling trace DP.
  • the decoupling signal is used to reduce coupling distortion caused by the coupling effect of the periodic signal by the voltage feedback signal.
  • the decoupling signal is a periodic pulse signal; the pulse period of the decoupling signal is equal to the period of the coupling distortion of the voltage feedback signal, and the phase of the decoupling signal is the same as the voltage feedback signal The phase when coupling distortion occurs is reversed.
  • the pulse width of the decoupling signal and the time when the coupling distortion of the voltage feedback signal occurs are equal.
  • the pulse width of the decoupling signal is greater than the time when the coupling distortion of the voltage feedback signal occurs.
  • the driving method provided by the embodiment of the present disclosure can reduce the coupling effect of the periodic signal on the voltage feedback trace FB, thereby avoiding the occurrence of periodic horizontal stripes in the display panel.

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Abstract

一种显示面板及其驱动方法。显示面板包括阵列基板(100)，还包括显示区域(410)和围绕显示区域的周边区域(420)。在周边区域(420)中，在阵列基板(100)上间隔地设置有公共电压走线(VC)、电压反馈走线(FB)、周期性信号走线以及去耦合走线(DP)；公共电压走线(VC)被配置为向显示区域(410)中的像素阵列传输显示所用的公共电压信号，电压反馈走线(FB)被配置为传输用于监测公共电压信号变化的电压反馈信号，周期性信号走线被配置为向像素阵列提供显示所用的周期性信号，去耦合走线(DP)位于周期性信号走线和电压反馈走线(FB)之间，被配置为传输去耦合信号，去耦合信号用于降低电压反馈信号受到周期性信号的耦合作用而产生的耦合畸变。显示面板可以避免发生周期性横纹。

Description

显示面板及其驱动方法 技术领域
本公开实施例涉及一种显示面板及其驱动方法。
背景技术
液晶显示装置(LCD)作为最常见的平板显示装置已经广泛应用于各种应用。有机发光二极管(Organic Light Emitting Diode，OLED)显示装置由于具有视角宽、对比度高、响应速度快以及相比于无机发光显示器件更高的发光亮度、更低的驱动电压等优势而逐渐受到人们的广泛关注。液晶显示装置、有机发光二极管(OLED)可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
发明内容
本公开至少一实施例提供一种显示面板，包括阵列基板，所述显示面板包括显示区域和围绕所述显示区域的周边区域。在所述周边区域中，在所述阵列基板上间隔地设置有公共电压走线、电压反馈走线、周期性信号走线以及去耦合走线；所述公共电压走线被配置为向所述显示区域中的像素阵列传输显示所用的公共电压信号，所述电压反馈走线被配置为传输用于监测所述公共电压信号变化的电压反馈信号，所述周期性信号走线被配置为向所述像素阵列提供显示所用的周期性信号，所述去耦合走线位于所述周期性信号走线和所述电压反馈走线之间，被配置为传输去耦合信号，所述去耦合信号用于降低所述电压反馈信号受到所述周期性信号的耦合作用而产生的耦合畸变。
例如，在本公开一实施例提供的显示面板中，所述去耦合信号为周期性脉冲信号；所述去耦合信号的脉冲周期与所述电压反馈信号发生所述耦合畸变的周期相等，所述去耦合信号的相位与所述电压反馈信号发生所述耦合畸变时的相位相反。
例如，在本公开一实施例提供的显示面板中，所述去耦合信号的脉冲宽度和所述电压反馈信号发生所述耦合畸变的时间相等。
例如，在本公开一实施例提供的显示面板中，所述去耦合信号的脉冲宽度大于所述电压反馈信号发生所述耦合畸变的时间。
例如，在本公开一实施例提供的显示面板中，所述周期性信号走线包括时钟信号走线和/或帧起始信号走线。
例如，在本公开一实施例提供的显示面板中，所述显示面板还包括信号处理电路，所述信号处理电路和所述去耦合走线连接，且被配置为将所述去耦合信号输出至所述去耦合走线。
例如，在本公开一实施例提供的显示面板中，在所述周边区域中，在所述阵列基板上还设置有与所述电压反馈走线间隔的接地走线，在所述电压反馈走线和所述接地走线之间形成有对地电容。
例如，在本公开一实施例提供的显示面板中，在所述周边区域中，所述阵列基板还包括第一导电层和连接电极，所述第一导电层与所述接地走线绝缘，且所述第一导电层在所述阵列基板上的正投影与所述接地走线在所述阵列基板上的正投影至少部分重叠，所述第一导电层与所述电压反馈走线电连接，由此所述对地电容形成在所述第一导电层和所述接地走线之间；所述连接电极与所述第一导电层通过第一过孔电连接，并与所述接地走线绝缘，所述连接电极与所述电压反馈走线通过第二过孔电连接。
例如，在本公开一实施例提供的显示面板中，在所述周边区域中，所述阵列基板还包括第一导电层和连接电极，所述第一导电层与所述电压反馈走线绝缘，且所述第一导电层在所述阵列基板上的正投影与所述电压反馈走线在所述阵列基板上的正投影至少部分重叠，所述第一导电层与所述接地走线电连接，由此所述对地电容形成在所述第一导电层和所述电压反馈走线之间；所述连接电极与所述第一导电层通过第一过孔电连接，并与所述电压反馈走线绝缘，所述连接电极与所述接地走线通过第二过孔电连接。
例如，在本公开一实施例提供的显示面板中，所述第一导电层和所述显示区域中的薄膜晶体管的栅极或源漏极同层同材料形成。
例如，在本公开一实施例提供的显示面板中，所述接地走线和所述电压反馈走线在所述阵列基板上同层同材料形成。
例如，本公开一实施例提供的显示面板还包括对置基板。在所述对置基板上设置有黑矩阵，设置在第一区域中的黑矩阵的厚度小于设置在第二区域中的黑矩阵的厚度，所述第一区域为包括所述电压反馈走线和所述周期性信 号走线在所述对置基板上的正投影的区域，所述第二区域为所述对置基板上所述第一区域外的区域。
例如，在本公开一实施例提供的显示面板中，所述第一区域还包括所述公共电压走线和所述去耦合走线在所述对置基板上的正投影的区域。
例如，在本公开一实施例提供的显示面板中，所述对置基板包括彩膜基板。
本公开至少一实施例还提供一种驱动方法，用于本公开的任一实施例所述的显示面板，该驱动方法包括：通过所述去耦合走线传输所述去耦合信号，所述去耦合信号用于降低所述电压反馈信号受到所述周期性信号的耦合作用而产生的耦合畸变。
例如，在本公开一实施例提供的驱动方法中，所述去耦合信号为周期性脉冲信号；所述去耦合信号的脉冲周期与所述电压反馈信号发生所述耦合畸变的周期相等，所述去耦合信号的相位与所述电压反馈信号发生所述耦合畸变时的相位相反。
例如，在本公开一实施例提供的驱动方法中，所述去耦合信号的脉冲宽度和所述电压反馈信号发生所述耦合畸变的时间相等。
例如，在本公开一实施例提供的驱动方法中，所述去耦合信号的脉冲宽度大于所述电压反馈信号发生所述耦合畸变的时间。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示面板的示意图；
图2为图1中对应虚线框部分的示意图；
图3为图1中所示的显示面板发生周期性横纹不良时的信号时序图；
图4为本公开的一些实施例提供的一种显示面板的示意图；
图5为图4中对应虚线框部分的示意图1；
图6为图4中对应虚线框部分的示意图2；
图7为电压反馈走线、时钟信号走线以及去耦合走线传输的信号的示意图1；
图8为电压反馈走线、时钟信号走线以及去耦合走线传输的信号的示意图2；
图9为本公开的一些实施例提供的另一种显示面板的示意图；
图10为图9中对应虚线框部分的示意图1；
图11为沿图10中A-A'线的剖视图；
图12为图9中对应虚线框部分的示意图2；
图13为沿图12中B-B'线的剖视图；
图14A-图14C为分别对位于周边区域中的对置基板进行切除的三种示意图；
图15为本公开的一些实施例提供的又一种显示面板的剖视图；以及
图16为本公开的一些实施例提供的再一种显示面板的剖视图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1示出了一种显示面板的示意图，例如该显示面板为液晶显示面板。如图1所示，该显示面板包括显示区域610和围绕显示区域610的周边区域620。例如，在显示区域610中设置有由多行和多列像素单元(例如，每个像素包括RGB三种像素单元)构成的像素阵列，以用于显示操作。需要说明的是，在图1中仅示意性地示出了三行三列像素单元，本公开的实施例包括但不限于此。
例如，如图1所示，周边区域620包括驱动电路区域621和走线区域622。在驱动电路区域621中设置有用于驱动像素阵列的驱动电路，例如该驱动电路可以采用GOA(gate driver on array，阵列基板行驱动)电路。在走线区域622中间隔地设置有多条走线，例如该多条走线在排布时可以是平行且绝缘的。图2示出了图1中对应虚线框部分的示意图。例如，如图2所示，多条走线包括公共电压走线VC、电压反馈走线FB、帧起始信号走线STV以及多条时钟信号走线(CLK1…CLKN)。
例如，如图1所示，上述多条走线的末端可以通过电极引脚730以及柔性电路薄膜720连接到印刷电路板710。例如，设置在印刷电路板710上的电路可以通过多条走线向GOA电路提供驱动显示操作所需的各种信号，这些信号包括时钟信号(CLK)、帧起始信号(STV)、电源电压信号(VDD)等。
例如，当图1中的显示面板为液晶显示面板时，显示操作主要是通过施加在每个像素单元中的像素电极上的数据电压和施加在公共电极上的公共电压Vcom之间的电压差来驱动液晶分子进行偏转，从而实现各种不同灰阶的显示。因此，在进行显示操作时，公共电压Vcom的稳定性就变得十分重要。
例如，如图2所示，可以通过公共电压走线VC向像素阵列提供公共电压Vcom。例如，为了使得公共电压Vcom保持稳定，可以对显示面板中的公共电压Vcom进行监测，并根据公共电压Vcom的变化对其进行反向补偿，从而使得显示面板中的公共电压Vcom维持在一个稳定的值。
例如，如图2所示，在走线区域622中可以设置电压反馈走线FB，该电压反馈走线FB用于传输监测公共电压Vcom变化的电压反馈信号。例如，可以将该电压反馈信号传输至设置在印刷电路板710中的信号处理电路，例如该信号处理电路可以根据该电压反馈信号对公共电压Vcom进行反向补偿，从而使得显示面板中的公共电压Vcom可以保持在一个稳定的值。
在采用GOA电路进行驱动的显示面板中，由于需要向GOA电路提供多种不同的信号，所以走线区域622中的布线密度大。例如多个时钟信号走线(CLK1…CLKN，N为大于1的整数)提供的时钟信号和帧起始信号走线STV提供的帧起始信号都是周期性信号，在这种情况下，电压反馈走线FB传输的电压反馈信号容易受到这些周期性信号的耦合影响，导致电压反馈信 号产生周期性畸变。当信号处理电路接收到上述产生周期性畸变的电压反馈信号时，会认为是公共电压Vcom发生了变化，然后对公共电压Vcom进行反向补偿，从而会导致显示面板中的公共电压Vcom出现相应的周期性畸变，从而导致显示面板在显示画面时出现周期性横纹，影响显示质量。
图3示出了发生上述周期性横纹不良的示意图。图3中从上到下依次为时钟信号走线CLK1传输的时钟信号、电压反馈走线FB传输的电压反馈信号以及经过反向补偿后公共电压走线VC传输的公共电压Vcom。需要说明的是，上述反向补偿可以是一倍的，也可以是多倍的。例如，图3中示出的即是进行多倍反向补偿的示例。进行反向补偿的补偿倍数需要根据实际情况进行确定，当补偿倍数过大时，电压反馈信号因为耦合而产生的信号畸变也会被放大，因此通过降低补偿倍数可以改善上述周期性横纹不良。但是由于加工工艺的波动，已经确定好的补偿倍数并不能完全适用于所有生成的产品，所以，需要在显示面板本身中尽可能的减少电压反馈走线FB受到的耦合影响。
本公开至少一实施例提供一种显示面板，包括阵列基板，显示面板包括显示区域和围绕显示区域的周边区域。在周边区域中，在阵列基板上间隔地设置有公共电压走线、电压反馈走线、周期性信号走线以及去耦合走线。公共电压走线被配置为向显示区域中的像素阵列传输显示所用的公共电压信号，电压反馈走线被配置为传输用于监测公共电压信号变化的电压反馈信号，周期性信号走线被配置为向像素阵列提供显示所用的周期性信号，去耦合走线位于周期性信号走线和电压反馈走线之间，被配置为传输去耦合信号，去耦合信号用于降低电压反馈信号受到周期性信号的耦合作用而产生的耦合畸变。
本公开至少一实施例还提供一种对应于上述显示面板的驱动方法。
本公开的实施例提供的显示面板及其驱动方法可以降低周期性信号对电压反馈走线的耦合影响，从而可以避免显示面板发生周期性横纹不良。
下面结合附图对本公开的实施例进行详细说明。
本公开的一些实施例提供一种显示面板，图4示出了该显示面板的示意图。如图4所示，该显示面板包括阵列基板100，显示面板包括显示区域410和围绕显示区域410的周边区域420。例如，在显示区域410中设置有由多行和多列像素单元(例如，每个像素包括RGB三种像素单元)构成的像素 阵列，以用于显示操作。需要说明的是，在图4中仅示意性地示出了三行三列像素单元，本公开的实施例包括但不限于此。
例如，如图4所示，周边区域420包括驱动电路区域421和走线区域422。在驱动电路区域421中设置有用于驱动像素阵列的驱动电路，例如该驱动电路可以采用GOA(gate driver on array，阵列基板行驱动)电路。在走线区域422中间隔地设置有多条走线，例如，该多条走线相互之间是平行且绝缘的。图5示出了图4中对应虚线框部分的示意图。例如，如图5所示，在阵列基板100上间隔地设置有公共电压走线VC、电压反馈走线FB、周期性信号走线以及去耦合走线DP。例如，公共电压走线VC、电压反馈走线FB、周期性信号走线以及去耦合走线DP在阵列基板100上可以同层同材料形成。例如，在垂直于阵列基板100板面的方向上，上述多条走线的高度可以相同，也可以不同，本公开的实施例对此不作限定。
需要说明的是，在本公开的实施例中，“同层同材料形成”是指通过同一次构图工艺对于同一材料层进行构图而形成，所形成的多个结构(例如，多条走线)在物理空间上不一定位于同一平面。
例如，如图4所示，上述多条走线的末端可以通过电极引脚530以及柔性电路薄膜520连接到印刷电路板510。例如，设置在印刷电路板510上的电路可以通过多条走线向GOA电路提供驱动显示操作所需的各种信号。
例如，公共电压走线VC被配置为向显示区域410中的像素阵列传输显示所用的公共电压信号Vcom。例如，当显示面板为液晶显示面板时，像素阵列中的各个像素单元可以根据该公共电压信号Vcom和施加在像素电极上的数据电压之间的电压差来驱动液晶进行偏转，从而实现不同灰阶的显示。
例如，电压反馈走线FB被配置为传输用于监测公共电压信号Vcom变化的电压反馈信号。例如，当公共电压信号Vcom发生波动时，电压反馈走线FB可以监测到公共电压信号Vcom的变化，并输出电压反馈信号。例如，可以将电压反馈走线FB连接于公共电压走线VC的远端(例如，靠近印刷电路板510的一端为近端，而远离印刷电路板510的一端为远端)，从而可以更准确地对公共电压信号Vcom进行监测。例如，在一个示例中，显示面板还包括信号处理电路540，电压反馈走线FB和该信号处理电路540连接，从而可以将电压反馈信号传输至该信号处理电路540以做进一步处理。例如，该信号处理电路540可以设置在印刷电路板510上。
例如，周期性信号走线被配置为向像素阵列提供显示所用的周期性信号。例如，如图5所示，这些周期性信号走线包括多条时钟信号走线(CLK1…CLKN，N为大于1的整数)和帧起始信号走线STV。例如，时钟信号走线向GOA电路提供周期性的时钟信号，帧起始信号走线STV向GOA电路提供周期性的帧起始信号，GOA电路在时钟信号和帧起始信号的驱动下输出逐行扫描信号，以驱动像素阵列进行显示。需要说明的是，本公开的实施例中的周期性信号走线包括但不限于图5中示出的时钟信号走线和帧起始信号走线STV，例如还可以包括帧复位信号走线。
例如，如图5和图6所示，相对于阵列基板100的板面，去耦合走线DP位于周期性信号走线和电压反馈走线FB之间，被配置为传输去耦合信号，去耦合信号用于降低电压反馈信号受到周期性信号的耦合作用而产生的耦合畸变。
需要说明的是，在本公开的实施例提供的显示面板中，对公共电压走线VC和电压反馈走线FB的相对位置不作限定。例如，在图5所示的示例中，电压反馈走线FB位于公共电压走线VC远离时钟信号走线CLK1的一侧。又例如，在图6所示的示例中，电压反馈走线FB位于公共电压走线VC靠近时钟信号走线CLK1的一侧。
图7和图8示出了去耦合走线DP传输的去耦合信号和电压反馈信号以及周期性信号的时序图。需要说明的是，图7和图8是以周期性信号为时钟信号为例进行示意的。
如图7和图8所示，去耦合走线DP传输的去耦合信号为周期性脉冲信号。去耦合信号的脉冲周期与电压反馈信号发生耦合畸变的周期相等，且去耦合信号的相位与电压反馈信号发生耦合畸变时的相位相反。需要说明的是，在本公开的实施例中，去耦合信号的相位与电压反馈信号发生耦合畸变时的相位相反表示：电压反馈信号发生耦合畸变时的电位变高，则相应的去耦合信号的电位变低；电压反馈信号发生耦合畸变时的电位变低，则相应的去耦合信号的电位变高。
如图7和图8所示，当时钟信号走线(CLK1、CLK2、CLK3)传输的时钟信号发生信号变化时(例如从低电平变为高电平时)，由于受到耦合影响，电压反馈走线FB传输的电压反馈信号会发生周期性畸变。当电压反馈信号发生周期性畸变时，使得去耦合信号的相位与电压反馈信号的相位相 反，从而使得去耦合信号走线可以耦合影响电压反馈信号，进而可以降低电压反馈信号受到周期性信号的耦合作用而产生的耦合畸变。
例如，在一个示例中，显示面板还包括信号处理电路540，电压反馈走线FB和去耦合走线DP和该信号处理电路540连接，信号处理电路540可以根据接收到的电压反馈信号，将去耦合信号输出至去耦合走线DP。例如，该信号处理电路540可以设置在印刷电路板510上。
在本公开的一些实施例提供的显示面板中，通过在周期性信号走线和电压反馈走线FB之间设置去耦合走线DP，并使得去耦合走线DP传输去耦合信号，可以降低电压反馈信号受到周期性信号的耦合作用而产生的耦合畸变，从而可以避免显示面板发生周期性横纹不良。
例如，在一个示例中，如图7所示，去耦合信号的脉冲宽度和电压反馈信号发生耦合畸变的时间相等。
又例如，在另一个示例中，如图8所示，去耦合信号的脉冲宽度大于电压反馈信号发生耦合的时间。
在实际调试中，如果显示面板发生周期性横纹不良，可以通过调节去耦合信号的脉冲宽度和/或脉冲幅值来降低电压反馈信号的耦合畸变，从而可以避免发生周期性横纹。
发明人通过进一步的试验发现，对于一个采用60Hz扫描频率且采用10条时钟信号走线(10条时钟信号走线传输的时钟信号为一个循环)的显示面板，例如，时钟信号走线对电压反馈走线FB造成的耦合畸变信号的频率为0.3MHz，而在正常情况下电压反馈走线FB由于公共电压信号的波动而正常反馈的信号的频率为240Hz。所以，可以在阵列基板上形成对地电容，从而利用该对地电容对电压反馈信号中的高频的耦合畸变信号进行滤波，同时又可以正常反馈公共电压信号发生的波动。
本公开的一些实施例还提供一种显示面板，如图9所示，该显示面板与图4所示的显示面板的相同部分这里不再赘述。图10示出了图9中对应虚线框部分的示意图。
如图10和图11所示(图11为沿图10中A-A'线的剖视图)，在显示面板的周边区域420中，在阵列基板100上还设置有与电压反馈走线FB间隔的接地走线GND，在电压反馈走线FB和接地走线GND之间形成有对地电容。该对地电容并联在电压反馈走线FB和接地走线GND之间。例如，该对 地电容形成在电压反馈走线FB靠近印刷电路板510的一端。
如图10和图11所示，在一个示例中，在显示面板的周边区域中，阵列基板100包括作为衬底基板的玻璃基板110和设置在玻璃基板110上的第一导电层101。第一导电层101和接地走线GND绝缘，且第一导电层101在阵列基板(即玻璃基板110)上的正投影与接地走线GND在阵列基板(即玻璃基板110)上的正投影至少部分重叠。第一导电层101和电压反馈走线FB电连接，由此对地电容形成在第一导电层101和接地走线GND之间。
电压反馈走线FB和接地走线GND在阵列基板(即玻璃基板110)上同层同材料形成。例如，电压反馈走线FB和接地走线GND可以与显示区域中的某一电极同层同材料形成，这样可以通过一次构图工艺在形成显示区域中的电极的同时，在周边区域中形成电压反馈走线FB和接地走线GND。例如，在形成电压反馈走线FB的同时还可以形成公共电压走线、时钟信号走线等其它信号走线。示例性的，衬底基板还可以为塑料基板等其他类型的基板，在此不做限定。
例如，第一导电层101和显示区域中的薄膜晶体管的栅极或源漏极同层同材料形成。当显示区域的像素单元的开关元件采用底栅型薄膜晶体管时，电压反馈走线FB和接地走线GND可以与薄膜晶体管的栅极通过同一构图工艺形成，第一导电层101可以与薄膜晶体管的源漏极通过同一构图工艺形成。又例如，当显示区域的像素单元的开关元件采用顶栅型薄膜晶体管时，电压反馈走线FB和接地走线GND可以与薄膜晶体管的源漏极通过同一构图工艺形成，第一导电层101可以与薄膜晶体管的栅极通过同一构图工艺形成。本公开的实施例对此不作限定。
例如，如图10和图11所示，在阵列基板100中还包括连接电极102，连接电极102与第一导电层101通过第一过孔103电连接，并与接地走线GND绝缘，连接电极102与电压反馈走线FB通过第二过孔104电连接。
例如，如图11所示，在阵列基板100中还包括第一绝缘层105和第二绝缘层106。第一导电层101通过第一绝缘层105和接地走线GND绝缘。第一过孔103贯穿第二绝缘层106，第二过孔104贯穿第一绝缘层105和第二绝缘层106，连接电极102形成在第二绝缘层106上并覆盖第一过孔103和第二过孔104，从而使得连接电极102通过第一过孔103和第一导电层103电连接，使得连接电极102通过第二过孔104和电压反馈走线FB连接。
例如，第一绝缘层105可以与显示区域中的栅极绝缘层通过同一构图工艺形成。第二绝缘层106可以与显示区域中的钝化层通过同一构图工艺形成。
在本公开的一些实施例中，连接电极102可以采用透明金属氧化物制作，例如ITO(氧化铟锡)等。
本公开的一些实施例还提供一种显示面板，如图12和图13所示(图13为沿图12中B-B'线的剖视图)，在本公开的一些实施例中，第一导电层101和电压反馈走线FB绝缘，且第一导电层101在阵列基板(即玻璃基板110)上的正投影与电压反馈走线FB在阵列基板(即玻璃基板110)上的正投影至少部分重叠，第一导电层101和接地走线GND电连接，由此对地电容形成在第一导电层101和电压反馈走线FB之间。连接电极102与第一导电层101通过第一过孔103电连接，并与电压反馈走线FB绝缘，连接电极102与接地走线GND通过第二过孔104电连接。
在本公开的一些实施例提供的显示面板中，通过在电压反馈走线FB和接地走线GND之间形成对地电容，从而可以对电压反馈信号中的高频的耦合畸变信号进行滤波，同时又可以正常反馈公共电压信号发生的波动，从而可以降低电压反馈信号的耦合畸变，避免显示面板发生周期性横纹。
发明人通过进一步的试验发现，当显示面板出现周期性横纹时，对位于周边区域420中的对置基板进行切除可以改善周期性横纹不良，横纹的严重程度与对置基板切除的范围成反比。例如，图14A、14B、14C分别表示对位于周边区域420中的对置基板不切除、右侧部分切除、右侧全部切除的示意图，例如，对应的电压反馈走线FB发生耦合畸变的信号的电压幅值分别为0.24V、0.13V、0.1V。
在对置基板上，在显示区域和周边区域中一般需要设置黑矩阵BM，由于黑矩阵BM需要具有遮光特性，所以在黑矩阵BM的材料中往往会添加一定量的导电粒子(例如，碳粒子)，导电粒子在周期性信号(例如时钟信号走线上传输的时钟信号)的作用下产生感应电荷，电压反馈走线FB受到该感应电荷的影响可能会发生信号畸变。所以，为了降低黑矩阵BM对电压反馈走线FB的影响，可以提高黑矩阵BM的阻值。
在本公开的一些实施例中，如图15所示，所提供的显示面板还包括对置基板200，例如，对置基板200为彩膜基板。在对置基板上设置有黑矩阵BM，设置在第一区域210中的黑矩阵BM的厚度小于设置在第二区域220 中的黑矩阵BM的厚度。第一区域210为包括电压反馈走线FB和周期性信号走线(例如时钟信号走线CLK或帧起始信号线)在对置基板200上的正投影的区域，第二区域220为对置基板200上第一区域210外的区域，例如，该第二区域为对置基板200上周边区域中除了第一区域210外的其它区域，例如该第二区域为显示区域。
例如，可以通过在形成黑矩阵时采用半色调掩膜工艺(Half Tone Mask，HTM)来使得第一区域210中的黑矩阵BM的厚度小于第二区域220中的黑矩阵BM的厚度。如图15所示，图中120标识的是封框胶。
在本公开的实施例中，通过减薄第一区域210中的黑矩阵BM的厚度，可以降低黑矩阵BM的阻值，从而降低黑矩阵BM感应电荷的能力，从而降低周期性信号对电压反馈走线FB的耦合影响，避免显示面板发生周期性横纹不良。
例如，在另一些实施例提供的显示面板中，如图16所示，在阵列基板100中设置去耦合走线DP的情形下，第一区域210还包括公共电压走线VC和去耦合走线DP在对置基板200上的正投影的区域。例如，第一区域210还包括接地走线GND在对置基板200上的正投影的区域。和图15所示的实施例相比，图16所示的显示面板可以进一步降低黑矩阵BM的阻值，从而降低黑矩阵BM感应电荷的能力，从而降低周期性信号对电压反馈走线FB的耦合影响，避免显示面板发生周期性横纹不良。
本公开的一些实施例还提供一种显示面板的驱动方法，该驱动方法可以用于本公开的实施例提供的任一显示面板。该驱动方法包括：通过去耦合走线DP传输去耦合信号，去耦合信号用于降低电压反馈信号受到周期性信号的耦合作用而产生的耦合畸变。
例如，在本公开的一些实施例提供的驱动方法中，去耦合信号为周期性脉冲信号；去耦合信号的脉冲周期与电压反馈信号发生耦合畸变的周期相等，去耦合信号的相位与电压反馈信号发生耦合畸变时的相位相反。
例如，在本公开的一些实施例提供的驱动方法中，去耦合信号的脉冲宽度和电压反馈信号发生耦合畸变的时间相等。
例如，在本公开的一些实施例提供的驱动方法中，去耦合信号的脉冲宽度大于电压反馈信号发生耦合畸变的时间。
本公开的实施例提供的驱动方法可以降低周期性信号对电压反馈走线 FB的耦合影响，从而可以避免显示面板发生周期性横纹不良。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (18)

  1. 一种显示面板，包括阵列基板，所述显示面板包括显示区域和围绕所述显示区域的周边区域，其中，
    在所述周边区域中，在所述阵列基板上间隔地设置有公共电压走线、电压反馈走线、周期性信号走线以及去耦合走线；
    所述公共电压走线被配置为向所述显示区域中的像素阵列传输显示所用的公共电压信号，
    所述电压反馈走线被配置为传输用于监测所述公共电压信号变化的电压反馈信号，
    所述周期性信号走线被配置为向所述像素阵列提供显示所用的周期性信号，
    所述去耦合走线位于所述周期性信号走线和所述电压反馈走线之间，被配置为传输去耦合信号，所述去耦合信号用于降低所述电压反馈信号受到所述周期性信号的耦合作用而产生的耦合畸变。
  2. 根据权利要求1所述的显示面板，其中，所述去耦合信号为周期性脉冲信号；
    所述去耦合信号的脉冲周期与所述电压反馈信号发生所述耦合畸变的周期相等，
    所述去耦合信号的相位与所述电压反馈信号发生所述耦合畸变时的相位相反。
  3. 根据权利要求2所述的显示面板，其中，所述去耦合信号的脉冲宽度和所述电压反馈信号发生所述耦合畸变的时间相等。
  4. 根据权利要求2所述的显示面板，其中，所述去耦合信号的脉冲宽度大于所述电压反馈信号发生所述耦合畸变的时间。
  5. 根据权利要求1-4任一所述的显示面板，其中，所述周期性信号走线包括时钟信号走线和/或帧起始信号走线。
  6. 根据权利要求1-5任一所述的显示面板，其中，所述显示面板还包括信号处理电路，
    所述信号处理电路和所述去耦合走线连接，且被配置为将所述去耦合信号输出至所述去耦合走线。
  7. 根据权利要求1-6任一所述的显示面板，其中，在所述周边区域中，在所述阵列基板上还设置有与所述电压反馈走线间隔的接地走线，在所述电压反馈走线和所述接地走线之间形成有对地电容。
  8. 根据权利要求7所述的显示面板，其中，在所述周边区域中，所述阵列基板还包括第一导电层和连接电极，
    所述第一导电层与所述接地走线绝缘，且所述第一导电层在所述阵列基板上的正投影与所述接地走线在所述阵列基板上的正投影至少部分重叠，所述第一导电层与所述电压反馈走线电连接，由此所述对地电容形成在所述第一导电层和所述接地走线之间；
    所述连接电极与所述第一导电层通过第一过孔电连接，并与所述接地走线绝缘，所述连接电极与所述电压反馈走线通过第二过孔电连接。
  9. 根据权利要求7所述的显示面板，其中，在所述周边区域中，所述阵列基板还包括第一导电层和连接电极，
    所述第一导电层与所述电压反馈走线绝缘，且所述第一导电层在所述阵列基板上的正投影与所述电压反馈走线在所述阵列基板上的正投影至少部分重叠，所述第一导电层与所述接地走线电连接，由此所述对地电容形成在所述第一导电层和所述电压反馈走线之间；
    所述连接电极与所述第一导电层通过第一过孔电连接，并与所述电压反馈走线绝缘，所述连接电极与所述接地走线通过第二过孔电连接。
  10. 根据权利要求8或9所述的显示面板，其中，所述第一导电层和所述显示区域中的薄膜晶体管的栅极或源漏极同层同材料形成。
  11. 根据权利要求7-10任一所述的显示面板，其中，所述接地走线和所述电压反馈走线在所述阵列基板上同层同材料形成。
  12. 根据权利要求1-11任一所述的显示面板，还包括对置基板，其中，
    在所述对置基板上设置有黑矩阵，设置在第一区域中的黑矩阵的厚度小于设置在第二区域中的黑矩阵的厚度，
    所述第一区域为包括所述电压反馈走线和所述周期性信号走线在所述对置基板上的正投影的区域，所述第二区域为所述对置基板上所述第一区域外的区域。
  13. 根据权利要求12所述的显示面板，其中，所述第一区域还包括所述公共电压走线和所述去耦合走线在所述对置基板上的正投影的区域。
  14. 根据权利要求12或13所述的显示面板，其中，所述对置基板包括彩膜基板。
  15. 一种如权利要求1所述的显示面板的驱动方法，包括：
    通过所述去耦合走线传输所述去耦合信号，所述去耦合信号用于降低所述电压反馈信号受到所述周期性信号的耦合作用而产生的耦合畸变。
  16. 根据权利要求15所述的驱动方法，其中，所述去耦合信号为周期性脉冲信号；
    所述去耦合信号的脉冲周期与所述电压反馈信号发生所述耦合畸变的周期相等，
    所述去耦合信号的相位与所述电压反馈信号发生所述耦合畸变时的相位相反。
  17. 根据权利要求16所述的驱动方法，其中，所述去耦合信号的脉冲宽度和所述电压反馈信号发生所述耦合畸变的时间相等。
  18. 根据权利要求16所述的驱动方法，其中，所述去耦合信号的脉冲宽度大于所述电压反馈信号发生所述耦合畸变的时间。
PCT/CN2018/117416 2018-11-26 2018-11-26 显示面板及其驱动方法 WO2020107148A1 (zh)

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