WO2020103510A1 - 静电保护电路、阵列基板及显示装置 - Google Patents

静电保护电路、阵列基板及显示装置

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Publication number
WO2020103510A1
WO2020103510A1 PCT/CN2019/102895 CN2019102895W WO2020103510A1 WO 2020103510 A1 WO2020103510 A1 WO 2020103510A1 CN 2019102895 W CN2019102895 W CN 2019102895W WO 2020103510 A1 WO2020103510 A1 WO 2020103510A1
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Prior art keywords
transistor
coupled
gate
protection circuit
electrostatic protection
Prior art date
Application number
PCT/CN2019/102895
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English (en)
French (fr)
Inventor
龙春平
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/642,606 priority Critical patent/US11552070B2/en
Publication of WO2020103510A1 publication Critical patent/WO2020103510A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection
    • G09G2330/045—Protection against panel overheating

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an electrostatic protection circuit, an array substrate, and a display device.
  • Flat panel display technology is widely used in televisions, mobile phones, and public information displays.
  • Flat panel displays may be damaged by static electricity during manufacturing or use.
  • An embodiment of the present disclosure provides an electrostatic protection circuit, including:
  • the first electrostatic discharge terminal, the second electrostatic discharge terminal and the signal line connection terminal are connected to
  • a first discharge sub-circuit coupled between the first electrostatic discharge terminal and the signal line connection terminal;
  • a second discharge sub-circuit coupled between the second electrostatic discharge terminal and the signal line connection terminal; wherein,
  • Each of the first release sub-circuit and the second release sub-circuit includes at least one transistor, and the gates of all the transistors included in the first release sub-circuit and the second release sub-circuit are not Any one of the first electrostatic discharge terminal, the second electrostatic discharge terminal, and the signal line connection terminal is coupled.
  • the first discharge sub-circuit includes a first transistor and a second transistor, and a source of the first transistor is coupled to the first electrostatic discharge terminal Then, the source of the second transistor is coupled to the connection end of the signal line, and the drain of the first transistor and the drain of the second transistor are connected in series to form a first common drain electrode.
  • both the gate of the first transistor and the gate of the second transistor are coupled to the first common drain electrode.
  • both the gate of the first transistor and the gate of the second transistor are floating.
  • the gate of the first transistor is coupled to the first common drain electrode, and the gate of the second transistor is floating.
  • the gate of the first transistor is floating, and the gate of the second transistor is coupled to the first common drain electrode.
  • the second transistor is an N-type transistor, and the ion doping concentration of the active layer of the first transistor is greater than that of the second transistor The ion doping concentration of the layer.
  • the first transistor is an N-type transistor and the second transistor is a P-type transistor; the first electrostatic discharge terminal and the low-potential reference voltage line For coupling, the second electrostatic discharge terminal is coupled to a high-potential reference voltage line.
  • the first transistor is an N-type transistor and the second transistor is an N-type transistor; the first electrostatic discharge terminal and the high-potential reference voltage line For coupling, the second electrostatic discharge terminal is coupled to the low-potential reference voltage line.
  • the first transistor is a P-type transistor
  • the ion doping concentration of the active layer of the second transistor is greater than that of the first transistor The ion doping concentration of the layer.
  • the second release sub-circuit includes a third transistor and a fourth transistor, and a source of the third transistor is coupled to the signal line connection terminal The source of the fourth transistor is coupled to the second electrostatic discharge terminal, and the drain of the third transistor and the drain of the fourth transistor are connected in series to form a second common drain electrode.
  • the gate of the third transistor and the gate of the fourth transistor are both coupled to the second common drain electrode.
  • the gate of the third transistor and the gate of the fourth transistor are both floatingly connected.
  • the gate of the third transistor is coupled to the second common drain electrode, and the gate of the fourth transistor is floating.
  • the gate of the third transistor is floating, and the gate of the fourth transistor is coupled to the second common drain electrode.
  • the fourth transistor is an N-type transistor, and the ion doping concentration of the active layer of the third transistor is greater than that of the fourth transistor The ion doping concentration of the layer.
  • the third transistor is an N-type transistor, and the fourth transistor is a P-type transistor; the first electrostatic discharge terminal and the low-potential reference voltage line For coupling, the second electrostatic discharge terminal is coupled to a high-potential reference voltage line.
  • the third transistor is a P-type transistor
  • the fourth transistor is a P-type transistor
  • the second electrostatic discharge terminal is coupled to the low-potential reference voltage line.
  • the third transistor is a P-type transistor, and the ion doping concentration of the active layer of the fourth transistor is greater than that of the third transistor The ion doping concentration of the layer.
  • the transistor with high ion doping concentration is an N-type transistor or a P-type transistor; the first electrostatic discharge terminal is coupled to a low-potential reference voltage line , The second electrostatic discharge terminal is coupled to the high-potential reference voltage line.
  • the first discharge sub-circuit includes a first transistor and a second transistor, and a source of the first transistor is coupled to the first electrostatic discharge terminal Then, the source of the second transistor is coupled to the connection end of the signal line, and the drain of the first transistor and the drain of the second transistor are connected in series to form a first common drain electrode;
  • the second discharge sub-circuit includes a third transistor and a fourth transistor, the source of the third transistor is coupled to the signal line connection terminal, and the source of the fourth transistor is coupled to the second static discharge terminal Coupled, the drain of the third transistor and the drain of the fourth transistor are connected in series to form a second common drain electrode.
  • the gate of the first transistor and the gate of the second transistor are both coupled to the first common drain electrode, and the third The gate of the transistor and the gate of the fourth transistor are coupled to the second common drain electrode; or,
  • Both the gate of the first transistor and the gate of the second transistor are floating, and the gate of the third transistor and the gate of the fourth transistor are floating; or,
  • the gate of one of the first transistor and the second transistor is coupled to the first common drain electrode, and the gate of the other transistor is floating; of the third transistor and the fourth transistor The gate of one transistor is floating, and the gate of the other transistor is coupled to the second common drain electrode; or,
  • the gate of one of the first transistor and the second transistor is coupled to the first common drain electrode, and the gate of the other transistor is floating; the third transistor and the fourth transistor The gates are all coupled to the second common drain electrode; or,
  • the gates of the first transistor and the second transistor are both coupled to the first common drain electrode; the gate of one of the third transistor and the fourth transistor is common to the second The drain electrode is coupled, and the gate of the other transistor is floating.
  • the present disclosure also provides an array substrate including a display area and a non-display area surrounding the display area, the display area includes a signal line, the non-display area includes an electrostatic protection line, and the non-display area also includes any of the above-mentioned electrostatic protection circuits provided by the embodiments of the present disclosure; wherein,
  • the signal line connection end of the electrostatic protection circuit is coupled to the signal line;
  • Both the first electrostatic discharge terminal and the second electrostatic discharge terminal of the electrostatic protection circuit are coupled to the electrostatic protection line.
  • the above array substrate includes a base substrate, a buffer layer, a semiconductor layer, a gate insulating layer, a first metal layer, and an interlayer that are sequentially stacked on the base substrate An insulating layer, a second metal layer, a passivation layer and a planarization layer, wherein,
  • the semiconductor layer includes an active layer of each transistor, the first metal layer includes a gate of each transistor, and the second metal layer includes a source electrode and a drain electrode of each transistor;
  • the first common drain electrode or the second common drain electrode is coupled to the corresponding gate through a via penetrating the interlayer insulating layer, and the source electrode and the drain electrode respectively pass through the interlayer
  • the insulating layer and the via hole of the gate insulating layer are coupled to the corresponding active layer.
  • the active layers of all the transistors are of an integrated structure, and each of the transistors is a polysilicon transistor.
  • the extension direction of the source electrode of each transistor is arranged parallel to the signal line and perpendicular to the static electricity protection line.
  • the signal line includes a gate line, a data line, or a test signal line;
  • the electrostatic protection line includes a common electrode line, a high potential reference voltage line, or a low potential reference Voltage line.
  • the present disclosure also provides a display device, including any of the above-mentioned array substrates provided by the embodiments of the present disclosure.
  • FIG. 1 is a schematic structural diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure
  • FIG 2 is another schematic structural diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure
  • FIG. 3 is another schematic structural diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • FIG. 4 is another schematic structural diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • FIG. 5 is another schematic structural diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • FIG. 6 is another schematic structural diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • FIG. 7 is another schematic structural diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • 8A is another schematic structural diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • 8B is another schematic structural diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • FIG. 9A is a schematic cross-sectional structure diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • 9B is a schematic structural diagram of a top view of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • 10A is another schematic cross-sectional structure diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • 10B is another schematic diagram of a top view of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • 11A is another schematic cross-sectional structure diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • FIG. 11B is another schematic top view structural diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • 12A is another schematic diagram of a cross-sectional structure of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • 12B is another schematic diagram of a top view of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • FIG. 13A is another schematic cross-sectional structure diagram of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • FIG. 13B is another schematic top structural view of an electrostatic protection circuit provided by an embodiment of the present disclosure.
  • An electrostatic protection circuit provided by an embodiment of the present disclosure, as shown in FIG. 1, includes: a first electrostatic discharge terminal V1, a second electrostatic discharge terminal V2 and a signal line connection terminal L1, and the first electrostatic discharge terminal V1 is connected to the signal line
  • the first discharge subcircuit 1 is coupled between the terminals L1
  • the second discharge subcircuit 2 is coupled between the second electrostatic discharge terminal V2 and the signal line connection terminal L1; both the first release subcircuit 1 and the second release subcircuit 2 are At least one transistor is included, and the gates of all transistors included in the first discharge sub-circuit 1 and the second discharge sub-circuit 2 are not connected to the first electrostatic discharge terminal V1, the second electrostatic discharge terminal V2, and the signal line connection terminal L1.
  • the first electrostatic discharge terminal V1 and the second electrostatic discharge terminal V2 in the electrostatic protection circuit provided by the embodiments of the present disclosure are respectively coupled to the same or different electrostatic protection lines, such as a common electrode line, a high and low potential reference voltage line, etc.
  • the signal line connection terminal L1 is coupled to the signal line, such as a gate line and a data line.
  • the signal line and the electrostatic protection line can be guided by the transistor in the first electrostatic discharge circuit 1 or the second electrostatic discharge circuit 2 It can realize the effective electrostatic discharge of the signal line in the product without affecting the realization of its normal function.
  • the first release sub-circuit 1 and the second release sub-circuit 2 may each include two transistors connected in series .
  • the first release sub-circuit 1 and the second release sub-circuit 2 may each include one transistor or multiple transistors, and the number of transistors included in the first release sub-circuit 1 and the second release sub-circuit 2 It may be the same or different, as long as the coupling relationship can be properly set to achieve the electrostatic discharge of the signal line of the present disclosure, all belong to the protection scope of the present disclosure.
  • the first electrostatic discharge terminal V1 and the second electrostatic discharge terminal V2 are respectively coupled with electrostatic protection lines 3.
  • the signal line connection end L1 is coupled to the signal line as an example for schematic description.
  • the gates of the transistors in the first discharge sub-circuit 1 and the second discharge sub-circuit 2 may both be coupled to the common drain electrodes of two transistors connected in series Pick up.
  • the gate G1 of the first transistor M1 and the gate G2 of the second transistor M2 are both connected to the series-connected first transistor M1 and second transistor M2
  • the first common drain electrode D1 is coupled; in the second release sub-circuit 2, the gate G3 of the third transistor M3 and the gate G4 of the fourth transistor M4 are connected to the third transistor M3 and the fourth transistor M4 connected in series
  • the second common drain electrode D2 is coupled.
  • the first release sub-circuit 1 includes a first transistor M1 and a second transistor M2, and the source S1 of the first transistor M1 is The first electrostatic discharge terminal V1 is coupled, and the gate G1 of the first transistor M1 and the gate G2 of the second transistor M2 are coupled to the first common drain electrode D1 between the first transistor M1 and the second transistor M2 connected in series , The source S2 of the second transistor M2 is coupled to the signal line connection terminal L1;
  • the second release sub-circuit 2 includes a third transistor M3 and a fourth transistor M4.
  • the gate G3 of the third transistor M3 and the gate G4 of the fourth transistor M4 are both connected to the third transistor M3 and the fourth transistor M4 connected in series.
  • the second common drain electrode D2 is coupled, the source S3 of the third transistor M3 is coupled to the signal line connection terminal L1, and the source S4 of the fourth transistor M4 is coupled to the second electrostatic discharge terminal V2.
  • the first transistor M1 in the first release sub-circuit 1, may be an N-type transistor, and the second transistor M2 may be P In the second release sub-circuit 2, the third transistor M3 may be an N-type transistor, the fourth transistor M4 may be a P-type transistor; the first electrostatic discharge terminal V1 is coupled to the low potential reference voltage line VGL, the second The electrostatic discharge terminal V2 is coupled to the high-potential reference voltage line VGH.
  • the voltage of the gate G2 of the P-type second transistor M2 in the first release sub-circuit 1 is relatively small, and the second transistor M2 is opened to form a conductive channel.
  • the first transistor M1 is an N-type transistor
  • the first transistor M1 is opened to form a conductive channel, so the positive voltage on the signal line L is released to low through the second transistor M2 and the first transistor M1
  • the potential reference voltage line VGL that is, the signal line L is connected to the low potential reference voltage line VGL, so that the positive voltage formed by the static charge accumulated on the signal line L can be effectively discharged electrostatically; when the static charge accumulated on the signal line L
  • the formed negative voltage is small (the absolute value is very large)
  • the voltage of the gate G3 of the N-type third transistor M3 in the second release sub-circuit 2 is relatively large, and the third transistor M3 is turned on to form a conductive channel.
  • the four transistors M4 are P-type transistors, and the fourth transistor M4 is turned on to form a conductive channel, so the negative voltage on the signal line L is discharged to the high potential reference voltage line VGH through the third transistor M3 and the fourth transistor M4, that is, the signal line L and The high-potential reference voltage line VGH is turned on, so that the negative voltage formed by the static charge accumulated on the signal line L can be effectively discharged.
  • the electrostatic protection circuit provided in Embodiment 1 of the present disclosure can effectively discharge the positive voltage or the negative voltage formed by the static charge accumulated on the signal line L without affecting the realization of its normal function.
  • the second transistor M2 in the first release sub-circuit 1, may be an N-type transistor, and the first transistor M1 is active
  • the ion doping concentration of the layer is greater than the ion doping concentration of the active layer of the second transistor M2, that is, in the process of manufacturing the first transistor M1, the active layer of the first transistor M1 relatively functions as a switch
  • the active layer of the transistor is doped with a larger ion concentration, so that the first transistor M1 is equivalent to a resistor;
  • the fourth transistor M4 may be an N-type transistor, and the ion doping concentration of the active layer of the third transistor M3 is greater than that of the active layer of the fourth transistor M4, that is In the process of the third transistor M3, the active layer of the transistor that normally functions as a switch is doped with a larger ion concentration in the active layer of the third transistor M3, so that the third transistor M3 is equivalent to a resistor.
  • the transistor with a high ion doping concentration may be an N-type transistor or a P-type transistor.
  • the first transistor M1 may be N-type transistor or P-type transistor
  • the third transistor M3 may be an N-type transistor or a P-type transistor.
  • the first transistor M1 and the third transistor M3 are N-type transistors as an example; the first electrostatic discharge The terminal V1 is coupled to the low potential reference voltage line VGL, and the second electrostatic discharge terminal V2 is coupled to the high potential reference voltage line VGH.
  • the second transistor M2 is turned on to form a conductive channel. Since the first transistor M1 is equivalent to a resistance, the negative voltage on the signal line L passes through the second transistor M2 and the second transistor M2. A transistor M1 is discharged to the low potential reference voltage line VGL, that is, the signal line L and the low potential reference voltage line VGL are turned on, so that the negative voltage formed by the static charge accumulated on the signal line L can be effectively discharged.
  • the electrostatic protection circuit provided in Embodiment 2 of the present disclosure can effectively discharge the positive voltage or negative voltage formed by the static charge accumulated on the signal line L without affecting the realization of its normal function.
  • the gates of the transistors in the first release sub-circuit and the second release sub-circuit are both floating.
  • the first release sub-circuit 1 includes a first transistor M1 and a second transistor M2, the gate G1 of the first transistor M1 and the gate G2 of the second transistor M2 are both floating, and the first transistor The source S1 of M1 is coupled to the first electrostatic discharge terminal V1, and the source S2 of the second transistor M2 is coupled to the signal line connection terminal L1;
  • the second release sub-circuit 2 includes a third transistor M3 and a fourth transistor M4, the gate G3 of the third transistor M3 and the gate G4 of the fourth transistor M4 are both floating, and the source S3 of the third transistor M3 is connected to the signal line The terminal L1 is coupled, and the source S4 of the fourth transistor M4 is coupled to the second electrostatic discharge terminal V2.
  • the first transistor M1 in the first release sub-circuit 1, may be an N-type transistor, and the second transistor M2 may be N
  • the third transistor M3 may be a P-type transistor
  • the fourth transistor M4 may be a P-type transistor; the first electrostatic discharge terminal V1 is coupled to the high potential reference voltage line VGH, the second The electrostatic discharge terminal V2 is coupled to the low potential reference voltage line VGL.
  • the voltage of the gate G3 of the P-type third transistor M3 and the gate of the fourth transistor M4 in the second release sub-circuit 2 The voltage of the electrode G4 is relatively small, the third transistor M3 and the fourth transistor M4 are both turned on to form a conductive channel, and the positive voltage on the signal line L is released to the low potential reference voltage line VGL through the third transistor M3 and the fourth transistor M4 , That is, the signal line L is connected to the low potential reference voltage line VGL, which can effectively discharge the positive voltage formed by the static charge accumulated on the signal line L; when the negative voltage formed by the static charge accumulated on the signal line L is very When the value is small (the absolute value is very large), the voltage of the gate G2 of the N-type second transistor M2 and the gate G1 of the first transistor M1 in the first release sub-circuit 1 are relatively large.
  • the second transistor M2 and the first The transistors M1 are all turned on to form a conductive channel, and the negative voltage on the signal line L is released to the high potential reference voltage line VGH through the second transistor M2 and the first transistor M1, that is, the signal line L is connected to the high potential reference voltage line VGH, thereby The negative voltage formed by the static charge accumulated on the signal line L can be effectively discharged.
  • the electrostatic protection circuit provided in Embodiment 3 of the present disclosure can effectively discharge the positive voltage or the negative voltage formed by the electrostatic charge accumulated on the signal line L without affecting the realization of its normal function.
  • the gate of one transistor in both the first discharge sub-circuit 1 and the second discharge sub-circuit 2 and the common drain electrode between the two transistors connected in series Coupling, the gate of the other transistor is floating.
  • the first discharge sub-circuit 1 includes a first transistor M1 and a second transistor M2, the source S1 of the first transistor M1 is coupled to the first electrostatic discharge terminal V1, and the gate of the first transistor M1
  • the electrode G1 is coupled to the first common drain electrode D1 between the first transistor M1 and the second transistor M2 connected in series, the gate G2 of the second transistor M2 is floating, and the source S2 of the second transistor M2 is connected to the signal line L1 coupling;
  • the second release sub-circuit 2 includes a third transistor M3 and a fourth transistor M4, the gate G3 of the third transistor M3 is floating, the source S3 of the third transistor M3 is coupled to the signal line connection terminal L1, and the fourth transistor M4 The gate G4 is coupled to the second common drain electrode D2 between the third transistor M3 and the fourth transistor M4 connected in series, and the source S4 of the fourth transistor M4 is coupled to the second electrostatic discharge terminal V2.
  • the first transistor M1 in the first release sub-circuit 1, the first transistor M1 may be an N-type transistor, and the second transistor M2 may be P In the second release sub-circuit 2, the third transistor M3 may be an N-type transistor, the fourth transistor M4 may be a P-type transistor; the first electrostatic discharge terminal V1 is coupled to the low potential reference voltage line VGL, the second The electrostatic discharge terminal V2 is coupled to the high-potential reference voltage line VGH.
  • the first transistor M1 is an N-type transistor
  • the first transistor M1 is opened to form a conductive channel, so the positive voltage on the signal line L is released to low through the second transistor M2 and the first transistor M1
  • the potential reference voltage line VGL that is, the signal line L is connected to the low potential reference voltage line VGL, so that the positive voltage formed by the static charge accumulated on the signal line L can be effectively discharged electrostatically; when the static charge accumulated on the signal line L
  • the formed negative voltage is small (the absolute value is very large)
  • the voltage of the gate G3 of the N-type third transistor M3 in the second release sub-circuit 2 is relatively large, and the third transistor M3 is turned on to form a conductive channel.
  • the four transistors M4 are P-type transistors, and the fourth transistor M4 is turned on to form a conductive channel, so the negative voltage on the signal line L is discharged to the high potential reference voltage line VGH through the third transistor M3 and the fourth transistor M4, that is, the signal line L and The high-potential reference voltage line VGH is turned on, so that the negative voltage formed by the static charge accumulated on the signal line L can be effectively discharged.
  • the electrostatic protection circuit provided in Embodiment 4 of the present disclosure can effectively discharge the positive voltage or the negative voltage formed by the static charge accumulated on the signal line L without affecting the realization of its normal function.
  • the first release sub-circuit 1 includes a first transistor M1 and a second transistor M2, and the gate G1 of the first transistor M1 floats
  • the source S1 of the first transistor M1 is coupled to the first electrostatic discharge terminal V1
  • the gate G2 of the second transistor M2 is coupled to the first common drain electrode D1 between the first and second transistors M1 and M2 connected in series Connected, the source S2 of the second transistor M2 is coupled to the signal line connection terminal L1;
  • the second release sub-circuit 2 includes a third transistor M3 and a fourth transistor M4.
  • the gate G3 of the third transistor M3 is coupled to the second common drain electrode D2 between the third transistor M3 and the fourth transistor M4 connected in series.
  • the source S3 of the three transistors M3 is coupled to the signal line connection terminal L1, the gate G4 of the fourth transistor M4 is floating, and the source S4 of the fourth transistor M4 is coupled to the second electrostatic discharge terminal V2.
  • the first transistor M1 may be an N-type transistor
  • the second transistor M2 may be N
  • the third transistor M3 may be a P-type transistor
  • the fourth transistor M4 may be a P-type transistor
  • the first electrostatic discharge terminal V1 is coupled to the high potential reference voltage line VGH
  • the second The electrostatic discharge terminal V2 is coupled to the low potential reference voltage line VGL.
  • the voltage of the gate G3 of the third transistor M3 of P type and the gate of the fourth transistor M4 in the second release sub-circuit 2 The voltage of the electrode G4 is relatively small, the third transistor M3 and the fourth transistor M4 are both turned on to form a conductive channel, and the positive voltage on the signal line L is released to the low potential reference voltage line VGL through the third transistor M3 and the fourth transistor M4 , That is, the signal line L is connected to the low potential reference voltage line VGL, which can effectively discharge the positive voltage formed by the static charge accumulated on the signal line L; when the negative voltage formed by the static charge accumulated on the signal line L is very When the value is small (the absolute value is very large), the voltage of the gate G2 of the N-type second transistor M2 and the gate G1 of the first transistor M1 in the first release sub-circuit 1 are relatively large.
  • the second transistor M2 and the first The transistors M1 are all turned on to form a conductive channel, and the negative voltage on the signal line L is released to the high potential reference voltage line VGH through the second transistor M2 and the first transistor M1, that is, the signal line L is connected to the high potential reference voltage line VGH, thereby The negative voltage formed by the static charge accumulated on the signal line L can be effectively discharged.
  • the electrostatic protection circuit provided in Embodiment 5 of the present disclosure can effectively discharge the positive voltage or the negative voltage formed by the electrostatic charge accumulated on the signal line L without affecting the realization of its normal function.
  • the first release sub-circuit 1 includes a first transistor M1 and a second transistor M2, and the source S1 of the first transistor M1 is The first electrostatic discharge terminal V1 is coupled, the gate G1 of the first transistor M1 is coupled to the first common drain electrode D1 between the first and second transistors M1 and M2 connected in series, and the gate of the second transistor M2 is floating , The source S2 of the second transistor M2 is coupled to the signal line connection terminal L1;
  • the second release sub-circuit 2 includes a third transistor M3 and a fourth transistor M4.
  • the gate G3 of the third transistor M3 is coupled to the second common drain electrode D2 between the third transistor M3 and the fourth transistor M4 connected in series.
  • the gate G4 of the four transistors M4 is floating, the source S3 of the third transistor M3 is coupled to the signal line connection terminal L1, and the source S4 of the fourth transistor M4 is coupled to the second electrostatic discharge terminal V2.
  • the first transistor M1 may be a P-type transistor, and the second transistor M2 is active
  • the ion doping concentration of the layer is greater than the ion doping concentration of the active layer of the first transistor M1, that is, in the process of manufacturing the second transistor M2, the active layer of the second transistor M2 relatively functions as a switch
  • the active layer of the transistor is doped with a larger ion concentration, so that the second transistor M2 is equivalent to a resistor;
  • the third transistor M3 may be a P-type transistor, and the ion doping concentration of the active layer of the fourth transistor M4 is greater than that of the active layer of the third transistor M3, that is During the process of the fourth transistor M4, the active layer of the transistor that normally functions as a switch is doped with a larger ion concentration in the active layer of the fourth transistor M4, so that the fourth transistor M4 is equivalent to a resistor.
  • the transistor with a high ion doping concentration may be an N-type transistor or a P-type transistor.
  • the second transistor M2 may be N-type transistor or P-type transistor.
  • the fourth transistor M4 may be an N-type transistor or a P-type transistor.
  • both the second transistor M2 and the fourth transistor M4 are N-type transistors as an example; the first electrostatic discharge terminal V1 and The low potential reference voltage line VGL is coupled, and the second electrostatic discharge terminal V2 is coupled to the high potential reference voltage line VGH.
  • the third transistor M3 when the positive voltage formed by the static charge accumulated on the signal line L is large, the voltage of the gate G3 of the third transistor M3 is relatively small, and the third transistor M3 is turned on to form a conductive channel.
  • the four-transistor M4 is equivalent to a resistor, so the positive voltage on the signal line L is released to the high-potential reference voltage line VGH through the third transistor M3 and the fourth transistor M4, that is, the signal line L is connected to the high-potential reference voltage line VGH, so that The positive voltage formed by the static charge accumulated on the signal line L performs effective electrostatic discharge; when the negative voltage formed by the static charge accumulated on the signal line L is small (the absolute value is large), since the second transistor M2 is equivalent to a resistance,
  • the first transistor M1 is a P-type transistor, so the first transistor M1 is turned on to form a conductive channel, so the negative voltage on the signal line L is discharged to the low potential reference voltage line VGL through the second transistor M2 and the
  • the electrostatic protection circuit provided in the sixth embodiment of the present disclosure can effectively discharge the positive or negative voltage formed by the static charge accumulated on the signal line L without affecting the realization of its normal function.
  • the first release sub-circuit 1 includes a first transistor M1 and a second transistor M2, and the gate G1 of the first transistor M1 floats
  • the source S1 of the first transistor M1 is coupled to the first electrostatic discharge terminal V1
  • the gate G2 of the second transistor M2 is coupled to the first common drain electrode D1 between the first and second transistors M1 and M2 connected in series Connected, the source S2 of the second transistor M2 is coupled to the signal line connection terminal L1;
  • the second release sub-circuit 2 includes a third transistor M3 and a fourth transistor M4, the gate G3 of the third transistor M3 is floating, and the gate G4 of the fourth transistor M4 is connected to the third transistor M3 and the fourth transistor M3 connected in series
  • the second common drain electrode D2 is coupled, the source S3 of the third transistor M3 is coupled to the signal line connection terminal L1, and the source S4 of the fourth transistor M4 is coupled to the second electrostatic discharge terminal V2.
  • the second transistor M2 may be an N-type transistor, and the first transistor M1 is active
  • the ion doping concentration of the layer is greater than the ion doping concentration of the active layer of the second transistor M2, that is, in the process of manufacturing the first transistor M1, the active layer of the first transistor M1 relatively functions as a switch
  • the active layer of the transistor is doped with a larger ion concentration, so that the first transistor M1 is equivalent to a resistor;
  • the fourth transistor M4 may be an N-type transistor, and the ion doping concentration of the active layer of the third transistor M3 is greater than that of the active layer of the fourth transistor M4, that is In the process of the third transistor M3, the active layer of the transistor that normally functions as a switch is doped with a larger ion concentration in the active layer of the third transistor M3, so that the third transistor M3 is equivalent to a resistor.
  • the transistor with a high ion doping concentration may be an N-type transistor or a P-type transistor.
  • the first transistor M1 may be N-type transistor or P-type transistor.
  • the third transistor M3 may be an N-type transistor or a P-type transistor. In FIG. 7, both the first transistor M1 and the third transistor M3 are N-type transistors.
  • the first electrostatic discharge terminal V1 and The low potential reference voltage line VGL is coupled, and the second electrostatic discharge terminal V2 is coupled to the high potential reference voltage line VGH.
  • the fourth transistor M4 when the positive voltage formed by the static charge accumulated on the signal line L is very large, since the third transistor M3 is equivalent to a resistor, and the fourth transistor M4 is an N-type transistor, the fourth transistor M4 is turned on A conductive channel is formed, so the positive voltage on the signal line L is released to the high-potential reference voltage line VGH through the third transistor M3 and the fourth transistor M4, that is, the signal line L and the high-potential reference voltage line VGH are turned on, thereby enabling the signal line L
  • the positive voltage formed by the accumulated electrostatic charge performs effective electrostatic discharge; when the negative voltage formed by the accumulated electrostatic charge on the signal line L is small (the absolute value is large), the voltage of the gate G2 of the second transistor M2 is relatively large , The second transistor M2 is opened to form a conductive channel.
  • the negative voltage on the signal line L is released to the low-potential reference voltage line VGL through the second transistor M2 and the first transistor M1, that is, the signal line L is turned on with the low-potential reference voltage line VGL, so that the negative voltage formed by the static charge accumulated on the signal line L can be effectively discharged.
  • the electrostatic protection circuit provided in Embodiment 7 of the present disclosure can effectively discharge the positive voltage or the negative voltage formed by the electrostatic charge accumulated on the signal line L without affecting the realization of its normal function.
  • the gate of one transistor in the first discharge sub-circuit 1, is coupled to the first common drain electrode between two transistors connected in series, and the other The gate of one transistor is floating; in the second release sub-circuit, the gates of both transistors are coupled to the common drain electrode of two transistors connected in series; or,
  • the gates of the two transistors are coupled to the common drain electrodes of the two transistors connected in series; in the second release subcircuit, the gate of one transistor is connected between the gates of the two transistors in series The second common drain electrode is coupled, and the gate of the other transistor is floating.
  • the first release sub-circuit 1 includes a first transistor M1 and a second transistor M2, and the second release sub-circuit 2 includes a third Transistor M3 and fourth transistor M4;
  • the source S1 of the first transistor M1 is coupled to the first electrostatic discharge terminal V1, and the gate G1 of the first transistor M1 and the gate G2 of the second transistor M2 are both connected to the series-connected first transistor M1 and second transistor M2
  • the first common drain electrode D1 is coupled, the source S2 of the second transistor M2 is coupled to the signal line connection terminal L1; the gate G3 of the third transistor M3 is floating, and the source S3 of the third transistor M3 is connected to the signal line
  • the terminal L1 is coupled, the gate G4 of the fourth transistor M4 is coupled to the second common drain electrode D2 between the third transistor M3 and the fourth transistor M4 connected in series, and the source S4 of the fourth transistor M4 is discharged from the second static electricity Terminal V2 is coupled; or,
  • the source S1 of the first transistor M1 is coupled to the first electrostatic discharge terminal V1, the gate G1 of the first transistor M1 and the first common between the first transistor M1 and the second transistor M2 connected in series
  • the drain electrode D1 is coupled, the gate G2 of the second transistor M2 is floating, the source S2 of the second transistor M2 is coupled to the signal line connection terminal L1;
  • the gate G3 of the third transistor M3 and the gate of the fourth transistor M4 G4 is coupled to the second common drain electrode D2 between the third transistor M3 and the fourth transistor M4 connected in series, the source S3 of the third transistor M3 is coupled to the signal line connection terminal L1, and the source of the fourth transistor M4 S4 is coupled to the second electrostatic discharge terminal V2.
  • floating the gate of the transistor means that the gate of the transistor is floating and is not coupled to any signal line or discharge line.
  • the positive voltage on the signal line can be released to the high potential reference On the voltage line, release the negative voltage on the signal line to the low potential reference voltage line; of course, release the positive voltage on the signal line to the low potential reference voltage line, and release the negative voltage on the signal line to the high potential reference voltage Online, all belong to the protection scope of the embodiments of the present disclosure, and will not make an example one by one here.
  • electrostatic protection circuit provided by the present disclosure is only a detailed description of the specific circuit structure diagram and the principle of electrostatic discharge of the first embodiment to the eighth embodiment.
  • the types of the four transistors, the gate coupling method of the four transistors, and the doping concentration of the active layer of the transistor can all realize the electrostatic discharge on the signal line.
  • These deformed electrostatic protection circuits belong to the scope of protection of the present disclosure. I will not list them one by one.
  • an embodiment of the present disclosure also provides an array substrate including a display area and a non-display area surrounding the display area, the display area includes a signal line, the non-display area includes an electrostatic protection line, and the non-display area also includes the present disclosure Any one of the above electrostatic protection circuits provided in the embodiments; wherein,
  • the signal line connection end of the electrostatic protection circuit is coupled to the signal line;
  • Both the first electrostatic discharge end and the second electrostatic discharge end of the electrostatic protection circuit are coupled to the electrostatic protection line, and the coupled electrostatic protection lines may be the same or different, which is not limited herein.
  • the implementation of the array substrate can refer to the implementation of the aforementioned electrostatic protection circuit, and the repetition is not repeated here.
  • FIG. 9A is a cross-sectional structure on a base substrate corresponding to the electrostatic protection circuit shown in FIGS. 1 and 2.
  • FIG. 9B is a schematic top view structure on a base substrate corresponding to the electrostatic protection circuit shown in FIGS. 1 and 2;
  • FIG. 10A is a schematic cross-sectional structure diagram on a base substrate corresponding to the electrostatic protection circuit shown in FIG. 4 10B is a schematic view of the top structure on the base substrate corresponding to the electrostatic protection circuit shown in FIG. 4;
  • FIG. 11A is a schematic cross-sectional structure on the base substrate corresponding to the electrostatic protection circuit shown in FIG.
  • FIG. 11B is FIG. 5 is a schematic view of the top structure on the base substrate corresponding to the electrostatic protection circuit
  • FIG. 12A is a schematic cross-sectional structure on the base substrate corresponding to the electrostatic protection circuit shown in FIG. 6, and FIG. 12B is shown in FIG. 6
  • FIG. 12A is a schematic cross-sectional structure diagram on the base substrate corresponding to the electrostatic protection circuit shown in FIG. 7, and FIG. 12B is an electrostatic protection circuit shown in FIG.
  • the semiconductor layer 30 includes the active layers of the transistors in the electrostatic protection circuit provided by the embodiments of the present disclosure. Specifically, the semiconductor layer 30 includes the active layer 31 of the first transistor M1 and the active layer 32 of the second transistor M2 , The active layer 33 of the third transistor M3 and the active layer 34 of the fourth transistor M4;
  • the first metal layer includes the gates of the transistors. Specifically, the first metal layer includes the gate G1 of the first transistor M1, the gate G2 of the second transistor M2, the gate G3 of the third transistor M3, and the fourth transistor M4 Gate G4;
  • the second metal layer includes the source electrode and the drain electrode of each transistor. Specifically, the second metal layer includes the source electrode S1 of the first transistor M1, the drain electrode D1, the source electrode S2 of the second transistor M2, the drain electrode D1, and the third The source electrode S3 and the drain electrode D2 of the transistor M3 and the source electrode S4 and the drain electrode D2 of the fourth transistor M4;
  • the gate of the transistor coupled to the common drain electrode of the two transistors is coupled to the common drain electrode through a via penetrating the interlayer insulating layer, and the source electrode and the drain electrode of each transistor are insulated by the penetrating interlayer insulating layer and the gate, respectively
  • the via of the layer is coupled to the active layer; specifically, as shown in FIGS.
  • the gate of the first transistor M1 coupled to the first common drain electrode D1 of the first transistor M1 and the second transistor M2 G1 and the gate G2 of the second transistor M2 are coupled to the first common drain electrode D1 through a via O1 penetrating the interlayer insulating layer 60 and to the second common drain electrode D2 of the third transistor M3 and the fourth transistor M4
  • the gate G3 of the third transistor M3 and the gate G4 of the fourth transistor M4 are coupled to the second common drain electrode D2 through a via O1 penetrating the interlayer insulating layer 60, and the source electrode S1 and the drain electrode D1 of the first transistor
  • the active layer, ie, the semiconductor layer 30, is coupled to the active layer, ie, the semiconductor layer 30, via vias O2 penetrating the interlayer insulating layer 60 and the gate insulating layer 40, respectively.
  • the via O2 of the polar insulating layer 40 is coupled to the active layer, ie, the semiconductor layer 30.
  • the source electrode S3 and the drain electrode D2 of the third transistor pass through the via O2 penetrating the interlayer insulating layer 60 and the gate insulating layer 40, respectively.
  • the source layer, that is, the semiconductor layer 30 is coupled, and the source electrode S4 and the drain electrode D2 of the fourth transistor are coupled to the active layer, that is, the semiconductor layer 30 through vias O2 penetrating the interlayer insulating layer 60 and the gate insulating layer 40;
  • the coupling relationship shown in FIGS. 10A to 13B refers to the embodiments shown in FIGS. 9A and 9B, except that the floating gate in each transistor is floating and is not coupled to any signal line or discharge line;
  • the electrostatic protection lines (VGH, VGL) are coupled to the source electrodes (S1, S4) of the transistor;
  • the source electrodes (S2, S3) of the two transistors (second transistor M2 and third transistor M3) coupled to the signal line connection terminal L1 pass through the interlayer insulating layer 60 and the gate insulating layer 40 via holes and active
  • the signal line L is coupled to the signal line connection terminal L1.
  • the active layers of all transistors in the electrostatic protection circuit of the present disclosure are of an integrated structure, and each transistor is a polysilicon transistor.
  • transistors in the electrostatic protection circuit may be thin film transistors, field effect transistors, or other devices with the same characteristics.
  • the source electrode extending direction of each transistor is arranged parallel to the signal line and perpendicular to the static electricity protection line.
  • the signal lines may include gate lines, data lines, or test signal lines, where the test signal lines may include clock signal lines or touch signal lines.
  • the gate line is described as an example.
  • the electrostatic discharge principle of other types of signal lines is the same as the electrostatic discharge principle of the gate line, which is not repeated here;
  • the electrostatic protection line may include a common electrode line, a high potential reference voltage line or a low potential reference
  • the voltage line is disclosed by taking the high-potential reference voltage line and the low-potential reference voltage line as examples. Of course, it may also be a common electrode line, which will not be repeated here.
  • embodiments of the present disclosure also provide a display device, including any of the above-mentioned array substrates provided by the embodiments of the present disclosure.
  • the principle of the display device to solve the problem is similar to that of the aforementioned array substrate. Therefore, the implementation of the display device can refer to the implementation of the aforementioned array substrate, and the repetition is not repeated here.
  • the electrostatic protection circuit includes: a first electrostatic discharge terminal, a second electrostatic discharge terminal, and a signal line connection terminal, and the first electrostatic discharge terminal and the signal line connection terminal Is coupled to the first discharge sub-circuit, the second electrostatic discharge terminal and the signal line connection terminal are coupled to the second discharge sub-circuit; the first discharge sub-circuit and the second discharge sub-circuit each include at least one transistor, and all transistors The gate is not coupled to the first electrostatic discharge terminal, the second electrostatic discharge terminal, and the signal line connection terminal.
  • the first electrostatic discharge terminal and the second electrostatic discharge terminal in the electrostatic protection circuit are respectively coupled to electrostatic protection lines such as common electrode lines, high and low potential reference voltage lines, etc.
  • the signal line connection terminals are coupled to signal lines such as gate lines , Data lines, etc.
  • the signal line can be connected to the static electricity through the transistor in the first electrostatic discharge circuit or the second electrostatic discharge circuit
  • the protection line is turned on, so that the electrostatic discharge of the signal line in the product can be achieved without affecting the realization of its normal function.

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Abstract

一种静电保护电路、阵列基板及显示装置，在实际应用时，该静电保护电路中的第一静电释放端(V1)和第二静电释放端(V2)分别耦接静电防护线如公共电极线、高低电位参考电压线等，信号线连接端(L1)耦接信号线如栅线、数据线等，当信号线上积累的静电荷形成的电压过大或过小(绝对值很大)时，可以通过第一静电释放电路(1)或第二静电释放电路(2)中的晶体管将信号线与静电防护线导通，从而能够实现对产品中的信号线进行有效的静电释放，又不影响其正常功能的实现。

Description

静电保护电路、阵列基板及显示装置
相关申请的交叉引用
本申请要求在2018年11月23日提交中国专利局、申请号为201821948211.8、申请名称为“一种静电保护电路、阵列基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及一种静电保护电路、阵列基板及显示装置。
背景技术
平板显示技术广泛应用于电视、手机以及公共信息显示，平板显示器在制造过程中或使用过程中，可能受到静电损害。
静电积累和释放是半导体领域中造成器件损坏的主要因素之一。在相关的显示器制造过程中，布线密集区域的功能导线，如栅线和数据线容易产生静电积累，导致晶体管被击穿，从而不能正常工作。因此，如何有效的将功能导线上积累的静电快速释放是本领域技术人员亟需解决的技术问题。
发明内容
本公开实施例提供了一种静电保护电路，包括：
第一静电释放端、第二静电释放端和信号线连接端；
第一释放子电路，耦接于所述第一静电释放端和所述信号线连接端之间；
第二释放子电路，耦接于所述第二静电释放端和所述信号线连接端之间；其中，
所述第一释放子电路和所述第二释放子电路均包括至少一个晶体管，且所述第一释放子电路和所述第二释放子电路包含的所有所述晶体管的栅极均 未与所述第一静电释放端、所述第二静电释放端和所述信号线连接端任意之一耦接。
可选地，在本公开实施例提供的上述静电保护电路中，所述第一释放子电路包括第一晶体管和第二晶体管，所述第一晶体管的源极与所述第一静电释放端耦接，所述第二晶体管的源极与所述信号线连接端耦接，所述第一晶体管的漏极和所述第二晶体管的漏极串联构成第一公共漏电极。
可选地，在本公开实施例提供的上述静电保护电路中，所述第一晶体管的栅极和所述第二晶体管的栅极均与所述第一公共漏电极耦接。
可选地，在本公开实施例提供的上述静电保护电路中，所述第一晶体管的栅极和所述第二晶体管的栅极均浮接。
可选地，在本公开实施例提供的上述静电保护电路中，所述第一晶体管的栅极与所述第一公共漏电极耦接，所述第二晶体管的栅极浮接。
可选地，在本公开实施例提供的上述静电保护电路中，所述第一晶体管的栅极浮接，所述第二晶体管的栅极与所述第一公共漏电极耦接。
可选地，在本公开实施例提供的上述静电保护电路中，所述第二晶体管为N型晶体管，所述第一晶体管的有源层的离子掺杂浓度大于所述第二晶体管的有源层的离子掺杂浓度。
可选地，在本公开实施例提供的上述静电保护电路中，所述第一晶体管为N型晶体管，所述第二晶体管为P型晶体管；所述第一静电释放端与低电位参考电压线耦接，所述第二静电释放端与高电位参考电压线耦接。
可选地，在本公开实施例提供的上述静电保护电路中，所述第一晶体管为N型晶体管，所述第二晶体管为N型晶体管；所述第一静电释放端与高电位参考电压线耦接，所述第二静电释放端与低电位参考电压线耦接。
可选地，在本公开实施例提供的上述静电保护电路中，所述第一晶体管为P型晶体管，所述第二晶体管的有源层的离子掺杂浓度大于所述第一晶体管的有源层的离子掺杂浓度。
可选地，在本公开实施例提供的上述静电保护电路中，所述第二释放子 电路包括第三晶体管和第四晶体管，所述第三晶体管的源极与所述信号线连接端耦接，所述第四晶体管的源极与所述第二静电释放端耦接，所述第三晶体管的漏极和所述第四晶体管的漏极串联构成第二公共漏电极。
可选地，在本公开实施例提供的上述静电保护电路中，所述第三晶体管的栅极和所述第四晶体管的栅极均与所述第二公共漏电极耦接。
可选地，在本公开实施例提供的上述静电保护电路中，所述第三晶体管的栅极和所述第四晶体管的栅极均浮接。
可选地，在本公开实施例提供的上述静电保护电路中，所述第三晶体管的栅极与所述第二公共漏电极耦接，所述第四晶体管的栅极浮接。
可选地，在本公开实施例提供的上述静电保护电路中，所述第三晶体管的栅极浮接，所述第四晶体管的栅极与所述第二公共漏电极耦接。
可选地，在本公开实施例提供的上述静电保护电路中，所述第四晶体管为N型晶体管，所述第三晶体管的有源层的离子掺杂浓度大于所述第四晶体管的有源层的离子掺杂浓度。
可选地，在本公开实施例提供的上述静电保护电路中，所述第三晶体管为N型晶体管，所述第四晶体管为P型晶体管；所述第一静电释放端与低电位参考电压线耦接，所述第二静电释放端与高电位参考电压线耦接。
可选地，在本公开实施例提供的上述静电保护电路中，所述第三晶体管为P型晶体管，所述第四晶体管为P型晶体管；所述第一静电释放端与高电位参考电压线耦接，所述第二静电释放端与低电位参考电压线耦接。
可选地，在本公开实施例提供的上述静电保护电路中，所述第三晶体管为P型晶体管，所述第四晶体管的有源层的离子掺杂浓度大于所述第三晶体管的有源层的离子掺杂浓度。
可选地，在本公开实施例提供的上述静电保护电路中，其中，离子掺杂浓度高的晶体管为N型晶体管或P型晶体管；所述第一静电释放端与低电位参考电压线耦接，所述第二静电释放端与高电位参考电压线耦接。
可选地，在本公开实施例提供的上述静电保护电路中，所述第一释放子 电路包括第一晶体管和第二晶体管，所述第一晶体管的源极与所述第一静电释放端耦接，所述第二晶体管的源极与所述信号线连接端耦接，所述第一晶体管的漏极和所述第二晶体管的漏极串联构成第一公共漏电极；
所述第二释放子电路包括第三晶体管和第四晶体管，所述第三晶体管的源极与所述信号线连接端耦接，所述第四晶体管的源极与所述第二静电释放端耦接，所述第三晶体管的漏极和所述第四晶体管的漏极串联构成第二公共漏电极。
可选地，在本公开实施例提供的上述静电保护电路中，所述第一晶体管的栅极和所述第二晶体管的栅极均与所述第一公共漏电极耦接，所述第三晶体管的栅极和所述第四晶体管的栅极均与所述第二公共漏电极耦接；或，
所述第一晶体管的栅极和所述第二晶体管的栅极均浮接，所述第三晶体管的栅极和所述第四晶体管的栅极均浮接；或，
所述第一晶体管和所述第二晶体管中的一个晶体管的栅极与所述第一公共漏电极耦接，另一个晶体管的栅极浮接；所述第三晶体管和所述第四晶体管中的一个晶体管的栅极浮接，另一个晶体管的栅极与所述第二公共漏电极耦接；或，
所述第一晶体管和所述第二晶体管中的一个晶体管的栅极与所述第一公共漏电极耦接，另一个晶体管的栅极浮接；所述第三晶体管和所述第四晶体管的栅极均与所述第二公共漏电极耦接；或，
所述第一晶体管和所述第二晶体管的栅极均与所述第一公共漏电极耦接；所述第三晶体管和所述第四晶体管中的一个晶体管的栅极与所述第二公共漏电极耦接，另一个晶体管的栅极浮接。
相应地，本公开还提供了一种阵列基板，包括显示区和包围所述显示区的非显示区，所述显示区包括信号线，所述非显示区包括静电防护线，所述非显示区还包括本公开实施例提供的上述任一所述的静电保护电路；其中，
所述静电保护电路的信号线连接端与所述信号线耦接；
所述静电保护电路的第一静电释放端和第二静电释放端均与所述静电防 护线耦接。
可选地，在本公开实施例提供的上述阵列基板中，包括衬底基板，位于所述衬底基板上依次层叠设置的缓冲层、半导体层、栅极绝缘层、第一金属层、层间绝缘层、第二金属层、钝化层和平坦化层，其中，
所述半导体层包括各所述晶体管的有源层，所述第一金属层包括各所述晶体管的栅极，所述第二金属层包括各所述晶体管的源电极和漏电极；
所述第一公共漏电极或所述第二公共漏电极通过贯穿所述层间绝缘层的过孔与对应的栅极耦接，所述源电极和所述漏电极分别通过贯穿所述层间绝缘层和所述栅极绝缘层的过孔与对应的所述有源层耦接。
可选地，在本公开实施例提供的上述阵列基板中，所有所述晶体管的有源层为一体结构，且各所述晶体管均为多晶硅晶体管。
可选地，在本公开实施例提供的上述阵列基板中，各所述晶体管的源电极延伸方向与所述信号线平行设置，且与所述静电防护线垂直设置。
可选地，在本公开实施例提供的上述阵列基板中，所述信号线包括栅线、数据线或测试信号线；所述静电防护线包括公共电极线、高电位参考电压线或低电位参考电压线。
相应地，本公开还提供了一种显示装置，包括本公开实施例提供的上述任一所述的阵列基板。
附图说明
图1为本公开实施例提供的静电保护电路的一种结构示意图；
图2为本公开实施例提供的静电保护电路的另一种结构示意图；
图3为本公开实施例提供的静电保护电路的另一种结构示意图；
图4为本公开实施例提供的静电保护电路的另一种结构示意图；
图5为本公开实施例提供的静电保护电路的另一种结构示意图；
图6为本公开实施例提供的静电保护电路的另一种结构示意图；
图7为本公开实施例提供的静电保护电路的另一种结构示意图；
图8A为本公开实施例提供的静电保护电路的另一种结构示意图；
图8B为本公开实施例提供的静电保护电路的另一种结构示意图；
图9A为本公开实施例提供的静电保护电路的一种剖面结构示意图；
图9B为本公开实施例提供的静电保护电路的一种俯视结构示意图；
图10A为本公开实施例提供的静电保护电路的另一种剖面结构示意图；
图10B为本公开实施例提供的静电保护电路的另一种俯视结构示意图；
图11A为本公开实施例提供的静电保护电路的另一种剖面结构示意图；
图11B为本公开实施例提供的静电保护电路的另一种俯视结构示意图；
图12A为本公开实施例提供的静电保护电路的另一种剖面结构示意图；
图12B为本公开实施例提供的静电保护电路的另一种俯视结构示意图；
图13A为本公开实施例提供的静电保护电路的另一种剖面结构示意图；
图13B为本公开实施例提供的静电保护电路的另一种俯视结构示意图。
具体实施方式
为了使本公开的目的，技术方案和优点更加清楚，下面结合附图，对本公开实施例提供的静电保护电路、阵列基板及显示装置的具体实施方式进行详细地说明。
附图中各层薄膜厚度和形状不反映静电保护电路的真实比例，目的只是示意说明本公开内容。
本公开实施例提供的一种静电保护电路，如图1所示，包括：第一静电释放端V1、第二静电释放端V2和信号线连接端L1，第一静电释放端V1和信号线连接端L1之间耦接第一释放子电路1，第二静电释放端V2和信号线连接端L1之间耦接第二释放子电路2；第一释放子电路1和第二释放子电路2均包括至少一个晶体管，且第一释放子电路1和第二释放子电路2包含的所有晶体管的栅极均未与第一静电释放端V1、第二静电释放端V2和信号线连接端L1任意之一耦接。
具体地，本公开实施例提供的静电保护电路中的第一静电释放端V1和第 二静电释放端V2分别耦接相同或不同的静电防护线，例如公共电极线、高低电位参考电压线等，信号线连接端L1耦接信号线，例如栅线、数据线等。当信号线上积累的静电荷形成的电压过大或过小(绝对值很大)时，可以通过第一静电释放电路1或第二静电释放电路2中的晶体管将信号线与静电防护线导通，从而能够实现对产品中的信号线进行有效的静电释放，又不影响其正常功能的实现。
在具体实施时，在本公开实施例提供的上述静电保护电路中，如图1-图8B所示，第一释放子电路1和所述第二释放子电路2可以均包括串联的两个晶体管。当然，具体实施时，第一释放子电路1和所述第二释放子电路2可以均包括一个晶体管或多个晶体管，且第一释放子电路1和第二释放子电路2中包含的晶体管数量可以相同也可以不同，只要合理设置耦接关系能够实现本公开的信号线的静电释放，均属于本公开保护的范围。
需要说明的是，为了更好的解释本公开，本公开的实施例提供的静电保护电路的附图中均是以第一静电释放端V1和第二静电释放端V2分别耦接了静电防护线、信号线连接端L1耦接了信号线为例进行示意说明的。
实施例一：
在具体实施时，在本公开实施例提供的上述静电保护电路中，第一释放子电路1和第二释放子电路2中的晶体管的栅极可以均与串联的两个晶体管的公共漏电极耦接。具体的，如图1所示，在第一释放子电路1中，第一晶体管M1的栅极G1和第二晶体管M2的栅极G2均与串联的第一晶体管M1和第二晶体管M2之间的第一公共漏电极D1耦接；在第二释放子电路2中，第三晶体管M3的栅极G3和第四晶体管M4的栅极G4均与串联的第三晶体管M3和第四晶体管M4之间的第二公共漏电极D2耦接。
在具体实施时，在本公开实施例提供的上述静电保护电路中，如图1所示，第一释放子电路1包括第一晶体管M1和第二晶体管M2，第一晶体管M1的源极S1与第一静电释放端V1耦接，第一晶体管M1的栅极G1和第二晶体管M2的栅极G2均与串联的第一晶体管M1和第二晶体管M2之间的第 一公共漏电极D1耦接，第二晶体管M2的源极S2与信号线连接端L1耦接；
第二释放子电路2包括第三晶体管M3和第四晶体管M4，第三晶体管M3的栅极G3和第四晶体管M4的栅极G4均与串联的第三晶体管M3和第四晶体管M4之间的第二公共漏电极D2耦接，第三晶体管M3的源极S3与信号线连接端L1耦接，第四晶体管M4的源极S4与第二静电释放端V2耦接。
在具体实施时，在本公开实施例提供的上述静电保护电路中，如图1所示，在第一释放子电路1中，第一晶体管M1可以为N型晶体管，第二晶体管M2可以为P型晶体管；在第二释放子电路2中，第三晶体管M3可以为N型晶体管，第四晶体管M4可以为P型晶体管；第一静电释放端V1与低电位参考电压线VGL耦接，第二静电释放端V2与高电位参考电压线VGH耦接。
上述实施例一方案中，当信号线L上积累的静电荷形成的正电压很大时，第一释放子电路1中P型的第二晶体管M2的栅极G2电压相对较小，第二晶体管M2被打开形成导电沟道，由于第一晶体管M1为N型晶体管，第一晶体管M1被打开形成导电沟道，因此信号线L上的正电压通过第二晶体管M2和第一晶体管M1释放至低电位参考电压线VGL，即信号线L与低电位参考电压线VGL导通，从而能够将信号线L上积累的静电荷形成的正电压进行有效的静电释放；当信号线L上积累的静电荷形成的负电压很小(绝对值很大)时，第二释放子电路2中N型的第三晶体管M3的栅极G3电压相对较大，第三晶体管M3被打开形成导电沟道，由于第四晶体管M4为P型晶体管，第四晶体管M4被打开形成导电沟道，因此信号线L上的负电压通过第三晶体管M3和第四晶体管M4释放至高电位参考电压线VGH，即信号线L与高电位参考电压线VGH导通，从而能够将信号线L上积累的静电荷形成的负电压进行有效的静电释放。
因此，本公开实施例一中提供的静电保护电路能够对信号线L上积累的静电荷形成的正电压或负电压进行有效的静电释放，又不影响其正常功能的实现。
实施例二：
在具体实施时，在本公开实施例提供的上述静电保护电路中，如图2所示，在第一释放子电路1中，第二晶体管M2为可以N型晶体管，第一晶体管M1的有源层的离子掺杂浓度大于第二晶体管M2的有源层的离子掺杂浓度，即在制作第一晶体管M1的工艺过程中，在第一晶体管M1的有源层中相对正常起到开关作用的晶体管的有源层中掺杂较大的离子浓度，这样第一晶体管M1相当于一个电阻；
在第二释放子电路2中，第四晶体管M4可以为N型晶体管，第三晶体管M3的有源层的离子掺杂浓度大于第四晶体管M4的有源层的离子掺杂浓度，即在制作第三晶体管M3的工艺过程中，在第三晶体管M3的有源层中相对正常起到开关作用的晶体管的有源层中掺杂较大的离子浓度，这样第三晶体管M3相当于一个电阻。
在具体实施时，在本公开实施例提供的上述静电保护电路中，如图2所示，离子掺杂浓度高的晶体管可以为N型晶体管或P型晶体管，具体地，第一晶体管M1可以为N型晶体管或P型晶体管，第三晶体管M3可以为N型晶体管或P型晶体管，具体地，图2中均以第一晶体管M1和第三晶体管M3为N型晶体管为例；第一静电释放端V1与低电位参考电压线VGL耦接，第二静电释放端V2与高电位参考电压线VGH耦接。
需要说明的是，实施例二的图2中的所有晶体管的耦接方式与实施例一的图1中的所有晶体管的耦接方式相同，仅是晶体管的类型不同，因此图2中各晶体管的耦接关系参照图1中的描述，在此不做赘述。
上述实施例二方案中，当信号线L上积累的静电荷形成的正电压很大时，由于第三晶体管M3相当于电阻，因此信号线L上的正电压通过第三晶体管M3释放至第四晶体管M4的栅极G4，N型的第四晶体管M4的被打开形成导电沟道，信号线L上的正电压通过第四晶体管M4释放至高电位参考电压线VGH，即信号线L与高电位参考电压线VGH导通，从而能够将信号线L上积累的静电荷形成的正电压进行有效的静电释放；当信号线L上积累的静电荷形成的负电压很小(绝对值很大)时，第二晶体管M2的栅极G2的正电压 相对较大，第二晶体管M2被打开形成导电沟道，由于第一晶体管M1相当于电阻，因此信号线L上的负电压通过第二晶体管M2和第一晶体管M1释放至低电位参考电压线VGL，即信号线L与低电位参考电压线VGL导通，从而能够将信号线L上积累的静电荷形成的负电压进行有效的静电释放。
因此，本公开实施例二中提供的静电保护电路能够对信号线L上积累的静电荷形成的正电压或负电压进行有效的静电释放，又不影响其正常功能的实现。
实施例三：
在具体实施时，在本公开实施例提供的上述静电保护电路中，第一释放子电路和第二释放子电路中的晶体管的栅极均浮接。具体地，如图3所示，第一释放子电路1包括第一晶体管M1和第二晶体管M2，第一晶体管M1的栅极G1和第二晶体管M2的栅极G2均浮接，第一晶体管M1的源极S1与第一静电释放端V1耦接，第二晶体管M2的源极S2与信号线连接端L1耦接；
第二释放子电路2包括第三晶体管M3和第四晶体管M4，第三晶体管M3的栅极G3和第四晶体管M4的栅极G4均浮接，第三晶体管M3的源极S3与信号线连接端L1耦接，第四晶体管M4的源极S4与第二静电释放端V2耦接。
在具体实施时，在本公开实施例提供的上述静电保护电路中，如图3所示，在第一释放子电路1中，第一晶体管M1可以为N型晶体管，第二晶体管M2可以为N型晶体管；在第二释放子电路2中，第三晶体管M3可以为P型晶体管，第四晶体管M4可以为P型晶体管；第一静电释放端V1与高电位参考电压线VGH耦接，第二静电释放端V2与低电位参考电压线VGL耦接。
上述实施例三方案中，当信号线L上积累的静电荷形成的正电压很大时，第二释放子电路2中P型的第三晶体管M3的栅极G3电压和第四晶体管M4的栅极G4电压都相对较小，第三晶体管M3和第四晶体管M4均被打开形成导电沟道，信号线L上的正电压通过第三晶体管M3和第四晶体管M4释放至低电位参考电压线VGL，即信号线L与低电位参考电压线VGL导通，从而 能够将信号线L上积累的静电荷形成的正电压进行有效的静电释放；当信号线L上积累的静电荷形成的负电压很小(绝对值很大)时，第一释放子电路1中N型的第二晶体管M2的栅极G2电压和第一晶体管M1的栅极G1电压都相对较大，第二晶体管M2和第一晶体管M1均被打开形成导电沟道，信号线L上的负电压通过第二晶体管M2和第一晶体管M1释放至高电位参考电压线VGH，即信号线L与高电位参考电压线VGH导通，从而能够将信号线L上积累的静电荷形成的负电压进行有效的静电释放。
因此，本公开实施例三中提供的静电保护电路能够对信号线L上积累的静电荷形成的正电压或负电压进行有效的静电释放，又不影响其正常功能的实现。
实施例四：
在具体实施时，在本公开实施例提供的上述静电保护电路中，第一释放子电路1和第二释放子电路2中均一个晶体管的栅极与串联的两个晶体管之间的公共漏电极耦接，另一个晶体管的栅极浮接。
具体地，如图4所示，第一释放子电路1包括第一晶体管M1和第二晶体管M2，第一晶体管M1的源极S1与第一静电释放端V1耦接，第一晶体管M1的栅极G1与串联的第一晶体管M1和第二晶体管M2之间的第一公共漏电极D1耦接，第二晶体管M2的栅极G2浮接，第二晶体管M2的源极S2与信号线连接端L1耦接；
第二释放子电路2包括第三晶体管M3和第四晶体管M4，第三晶体管M3的栅极G3浮接，第三晶体管M3的源极S3与信号线连接端L1耦接，第四晶体管M4的栅极G4与串联的第三晶体管M3和第四晶体管M4之间的第二公共漏电极D2耦接，第四晶体管M4的源极S4与第二静电释放端V2耦接。
在具体实施时，在本公开实施例提供的上述静电保护电路中，如图4所示，在第一释放子电路1中，第一晶体管M1可以为N型晶体管，第二晶体管M2可以为P型晶体管；在第二释放子电路2中，第三晶体管M3可以为N型晶体管，第四晶体管M4可以为P型晶体管；第一静电释放端V1与低电位 参考电压线VGL耦接，第二静电释放端V2与高电位参考电压线VGH耦接。
上述实施例四方案中，当信号线L上积累的静电荷形成的正电压很大时，第一释放子电路1中P型的第二晶体管M2的栅极G2电压相对较小，第二晶体管M2被打开形成导电沟道，由于第一晶体管M1为N型晶体管，第一晶体管M1被打开形成导电沟道，因此信号线L上的正电压通过第二晶体管M2和第一晶体管M1释放至低电位参考电压线VGL，即信号线L与低电位参考电压线VGL导通，从而能够将信号线L上积累的静电荷形成的正电压进行有效的静电释放；当信号线L上积累的静电荷形成的负电压很小(绝对值很大)时，第二释放子电路2中N型的第三晶体管M3的栅极G3电压相对较大，第三晶体管M3被打开形成导电沟道，由于第四晶体管M4为P型晶体管，第四晶体管M4被打开形成导电沟道，因此信号线L上的负电压通过第三晶体管M3和第四晶体管M4释放至高电位参考电压线VGH，即信号线L与高电位参考电压线VGH导通，从而能够将信号线L上积累的静电荷形成的负电压进行有效的静电释放。
因此，本公开实施例四中提供的静电保护电路能够对信号线L上积累的静电荷形成的正电压或负电压进行有效的静电释放，又不影响其正常功能的实现。
实施例五：
在具体实施时，在本公开实施例提供的上述静电保护电路中，如图5所示，第一释放子电路1包括第一晶体管M1和第二晶体管M2，第一晶体管M1的栅极G1浮接，第一晶体管M1的源极S1与第一静电释放端V1耦接，第二晶体管M2的栅极G2与串联的第一晶体管M1和第二晶体管M2之间的第一公共漏电极D1耦接，第二晶体管M2的源极S2与信号线连接端L1耦接；
第二释放子电路2包括第三晶体管M3和第四晶体管M4，第三晶体管M3的栅极G3与串联的第三晶体管M3和第四晶体管M4之间的第二公共漏电极D2耦接，第三晶体管M3的源极S3与信号线连接端L1耦接，第四晶体管M4的栅极G4浮接，第四晶体管M4的源极S4与第二静电释放端V2耦接。
在具体实施时，在本公开实施例提供的上述静电保护电路中，如图5所示，在第一释放子电路1中，第一晶体管M1可以为N型晶体管，第二晶体管M2可以为N型晶体管；在第二释放子电路2中，第三晶体管M3可以为P型晶体管，第四晶体管M4可以为P型晶体管；第一静电释放端V1与高电位参考电压线VGH耦接，第二静电释放端V2与低电位参考电压线VGL耦接。
上述实施例五方案中，当信号线L上积累的静电荷形成的正电压很大时，第二释放子电路2中P型的第三晶体管M3的栅极G3电压和第四晶体管M4的栅极G4电压都相对较小，第三晶体管M3和第四晶体管M4均被打开形成导电沟道，信号线L上的正电压通过第三晶体管M3和第四晶体管M4释放至低电位参考电压线VGL，即信号线L与低电位参考电压线VGL导通，从而能够将信号线L上积累的静电荷形成的正电压进行有效的静电释放；当信号线L上积累的静电荷形成的负电压很小(绝对值很大)时，第一释放子电路1中N型的第二晶体管M2的栅极G2电压和第一晶体管M1的栅极G1电压都相对较大，第二晶体管M2和第一晶体管M1均被打开形成导电沟道，信号线L上的负电压通过第二晶体管M2和第一晶体管M1释放至高电位参考电压线VGH，即信号线L与高电位参考电压线VGH导通，从而能够将信号线L上积累的静电荷形成的负电压进行有效的静电释放。
因此，本公开实施例五中提供的静电保护电路能够对信号线L上积累的静电荷形成的正电压或负电压进行有效的静电释放，又不影响其正常功能的实现。
实施例六：
在具体实施时，在本公开实施例提供的上述静电保护电路中，如图6所示，第一释放子电路1包括第一晶体管M1和第二晶体管M2，第一晶体管M1的源极S1与第一静电释放端V1耦接，第一晶体管M1的栅极G1与串联的第一晶体管M1和第二晶体管M2之间的第一公共漏电极D1耦接，第二晶体管M2的栅极浮接，第二晶体管M2的源极S2与信号线连接端L1耦接；
第二释放子电路2包括第三晶体管M3和第四晶体管M4，第三晶体管 M3的栅极G3与串联的第三晶体管M3和第四晶体管M4之间的第二公共漏电极D2耦接，第四晶体管M4的栅极G4浮接，第三晶体管M3的源极S3与信号线连接端L1耦接，第四晶体管M4的源极S4与第二静电释放端V2耦接。
在具体实施时，在本公开实施例提供的上述静电保护电路中，如图6所示，在第一释放子电路1中，第一晶体管M1可以为P型晶体管，第二晶体管M2的有源层的离子掺杂浓度大于第一晶体管M1的有源层的离子掺杂浓度，即在制作第二晶体管M2的工艺过程中，在第二晶体管M2的有源层中相对正常起到开关作用的晶体管的有源层中掺杂较大的离子浓度，这样第二晶体管M2相当于一个电阻；
在第二释放子电路2中，第三晶体管M3可以为P型晶体管，第四晶体管M4的有源层的离子掺杂浓度大于第三晶体管M3的有源层的离子掺杂浓度，即在制作第四晶体管M4的工艺过程中，在第四晶体管M4的有源层中相对正常起到开关作用的晶体管的有源层中掺杂较大的离子浓度，这样第四晶体管M4相当于一个电阻。
在具体实施时，在本公开实施例提供的上述静电保护电路中，离子掺杂浓度高的晶体管可以为N型晶体管或P型晶体管，具体地，如图6所示，第二晶体管M2可以为N型晶体管或P型晶体管，第四晶体管M4可以为N型晶体管或P型晶体管，图6中均以第二晶体管M2和第四晶体管M4为N型晶体管为例；第一静电释放端V1与低电位参考电压线VGL耦接，第二静电释放端V2与高电位参考电压线VGH耦接。
上述实施例六方案中，当信号线L上积累的静电荷形成的正电压很大时，第三晶体管M3的栅极G3电压相对较小，第三晶体管M3被打开形成导电沟道，由于第四晶体管M4相当于电阻，因此信号线L上的正电压通过第三晶体管M3和第四晶体管M4释放至高电位参考电压线VGH，即信号线L与高电位参考电压线VGH导通，从而能够将信号线L上积累的静电荷形成的正电压进行有效的静电释放；当信号线L上积累的静电荷形成的负电压很小(绝对值很大)时，由于第二晶体管M2相当于电阻，第一晶体管M1为P型晶体 管，因此第一晶体管M1被打开形成导电沟道，因此信号线L上的负电压通过第二晶体管M2和第一晶体管M1释放至低电位参考电压线VGL，即信号线L与低电位参考电压线VGL导通，从而能够将信号线L上积累的静电荷形成的负电压进行有效的静电释放。
因此，本公开实施例六中提供的静电保护电路能够对信号线L上积累的静电荷形成的正电压或负电压进行有效的静电释放，又不影响其正常功能的实现。
实施例七：
在具体实施时，在本公开实施例提供的上述静电保护电路中，如图7所示，第一释放子电路1包括第一晶体管M1和第二晶体管M2，第一晶体管M1的栅极G1浮接，第一晶体管M1的源极S1与第一静电释放端V1耦接，第二晶体管M2的栅极G2与串联的第一晶体管M1和第二晶体管M2之间的第一公共漏电极D1耦接，第二晶体管M2的源极S2与信号线连接端L1耦接；
第二释放子电路2包括第三晶体管M3和第四晶体管M4，第三晶体管M3的栅极G3浮接，第四晶体管M4的栅极G4与串联的第三晶体管M3和第四晶体管M3之间的第二公共漏电极D2耦接，第三晶体管M3的源极S3与信号线连接端L1耦接，第四晶体管M4的源极S4与第二静电释放端V2耦接。
在具体实施时，在本公开实施例提供的上述静电保护电路中，如图7所示，在第一释放子电路1中，第二晶体管M2可以为N型晶体管，第一晶体管M1的有源层的离子掺杂浓度大于第二晶体管M2的有源层的离子掺杂浓度，即在制作第一晶体管M1的工艺过程中，在第一晶体管M1的有源层中相对正常起到开关作用的晶体管的有源层中掺杂较大的离子浓度，这样第一晶体管M1相当于一个电阻；
在第二释放子电路2中，第四晶体管M4可以为N型晶体管，第三晶体管M3的有源层的离子掺杂浓度大于第四晶体管M4的有源层的离子掺杂浓度，即在制作第三晶体管M3的工艺过程中，在第三晶体管M3的有源层中相对正常起到开关作用的晶体管的有源层中掺杂较大的离子浓度，这样第三晶体管 M3相当于一个电阻。
在具体实施时，在本公开实施例提供的上述静电保护电路中，离子掺杂浓度高的晶体管可以为N型晶体管或P型晶体管，具体地，如图7所示，第一晶体管M1可以为N型晶体管或P型晶体管，第三晶体管M3可以为N型晶体管或P型晶体管，图7中均以第一晶体管M1和第三晶体管M3为N型晶体管为例；第一静电释放端V1与低电位参考电压线VGL耦接，第二静电释放端V2与高电位参考电压线VGH耦接。
上述实施例七方案中，当信号线L上积累的静电荷形成的正电压很大时，由于第三晶体管M3相当于电阻，第四晶体管M4为N型晶体管，因此第四晶体管M4的被打开形成导电通道，因此信号线L上的正电压通过第三晶体管M3和第四晶体管M4释放至高电位参考电压线VGH，即信号线L与高电位参考电压线VGH导通，从而能够将信号线L上积累的静电荷形成的正电压进行有效的静电释放；当信号线L上积累的静电荷形成的负电压很小(绝对值很大)时，第二晶体管M2的栅极G2电压相对较大，第二晶体管M2被打开形成导电通道，由于第一晶体管M1相当于电阻，因此信号线L上的负电压通过第二晶体管M2和第一晶体管M1释放至低电位参考电压线VGL，即信号线L与低电位参考电压线VGL导通，从而能够将信号线L上积累的静电荷形成的负电压进行有效的静电释放。
因此，本公开实施例七中提供的静电保护电路能够对信号线L上积累的静电荷形成的正电压或负电压进行有效的静电释放，又不影响其正常功能的实现。
实施例八：
在具体实施时，在本公开实施例提供的上述静电保护电路中，在第一释放子电路1中，一个晶体管的栅极与串联的两个晶体管之间的第一公共漏电极耦接，另一个晶体管的栅极浮接；在第二释放子电路中，两个晶体管的栅极均与串联的两个晶体管的公共漏电极耦接；或，
在第一释放子电路中，两个晶体管的栅极均与串联的两个晶体管的公共 漏电极耦接；在第二释放子电路中，一个晶体管的栅极与串联的两个晶体管之间的第二公共漏电极耦接，另一个晶体管的栅极浮接。
在具体实施时，在本公开实施例提供的上述静电保护电路中，如图8A所示，第一释放子电路1包括第一晶体管M1和第二晶体管M2，第二释放子电路2包括第三晶体管M3和第四晶体管M4；其中，
第一晶体管M1的源极S1与第一静电释放端V1耦接，第一晶体管M1的栅极G1和第二晶体管M2的栅极G2均与串联的第一晶体管M1和第二晶体管M2之间的第一公共漏电极D1耦接，第二晶体管M2的源极S2与信号线连接端L1耦接；第三晶体管M3的栅极G3浮接，第三晶体管M3的源极S3与信号线连接端L1耦接，第四晶体管M4的栅极G4与串联的第三晶体管M3和第四晶体管M4之间的第二公共漏电极D2耦接，第四晶体管M4的源极S4与第二静电释放端V2耦接；或，
如图8B所示，第一晶体管M1的源极S1与第一静电释放端V1耦接，第一晶体管M1的栅极G1与串联的第一晶体管M1和第二晶体管M2之间的第一公共漏电极D1耦接，第二晶体管M2的栅极G2浮接，第二晶体管M2的源极S2与信号线连接端L1耦接；第三晶体管M3的栅极G3和第四晶体管M4的栅极G4均与串联的第三晶体管M3和第四晶体管M4之间的第二公共漏电极D2耦接，第三晶体管M3的源极S3与信号线连接端L1耦接，第四晶体管M4的源极S4与第二静电释放端V2耦接。
具体实施时，图8A和图8B所示的静电保护电路进行静电释放的原理可以参见上述实施例一和实施例四，在此不作详述。
需要说明的是，晶体管的栅极浮接是指晶体管的栅极悬空，不与任何的信号线或放电线进行耦接。
需要说明的是，由于信号线上积累的正电荷或负电荷形成的电压的绝对值都远远大于高、低电位参考电压线上的电压，因此可以将信号线上的正电压释放至高电位参考电压线上、将信号线上的负电压释放至低电位参考电压线上；当然，将信号线上的正电压释放至低电位参考电压线上、将信号线上 的负电压释放至高电位参考电压线上，均属于本公开实施例保护的范围，在此不做一一举例。
需要说明的是，本公开提供的静电保护电路只是给出了实施例一至实施例八的具体电路结构图及静电释放的原理的详细说明，当然，具体实施时，只要合理设置本公开实施例中四个晶体管的类型、四个晶体管的栅极耦接方式以及晶体管的有源层的掺杂浓度均可以实现信号线上的静电释放，这些变形的静电保护电路均属于本公开保护的范围，在此不做一一列举。
基于同一公开构思，本公开实施例还提供了一种阵列基板，包括显示区和包围显示区的非显示区，显示区包括信号线，非显示区包括静电防护线，非显示区还包括本公开实施例提供的上述任一种静电保护电路；其中，
静电保护电路的信号线连接端与信号线耦接；
静电保护电路的第一静电释放端和第二静电释放端均与静电防护线耦接，且耦接的静电防护线可以相同也可以不同，在此不做限定。
上述阵列基板解决问题的原理与前述静电保护电路相似，因此该阵列基板的实施可以参见前述静电保护电路的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例提供的上述阵列基板中，如图9A至图13B所示，图9A为图1和图2所示的静电保护电路对应的在衬底基板上的剖面结构示意图，图9B为图1和图2所示的静电保护电路对应的在衬底基板上的俯视结构示意图；图10A为图4所示的静电保护电路对应的在衬底基板上的剖面结构示意图，图10B为图4所示的静电保护电路对应的在衬底基板上的俯视结构示意图；图11A为图5所示的静电保护电路对应的在衬底基板上的剖面结构示意图，图11B为图5所示的静电保护电路对应的在衬底基板上的俯视结构示意图；图12A为图6所示的静电保护电路对应的在衬底基板上的剖面结构示意图，图12B为图6所示的静电保护电路对应的在衬底基板上的俯视结构示意图；图12A为图7所示的静电保护电路对应的在衬底基板上的剖面结构示意图，图12B为图7所示的静电保护电路对应的在衬底基板上的俯视结构示意图；包括衬底基板10，位于衬底基板10上依次层叠设置的缓 冲层20、半导体层30、栅极绝缘层40、第一金属层、层间绝缘层60、第二金属层、钝化层80和平坦化层90，其中，
半导体层30包括各本公开实施例提供的上述静电保护电路中的各晶体管的有源层，具体地，半导体层30包括第一晶体管M1的有源层31、第二晶体管M2的有源层32、第三晶体管M3的有源层33和第四晶体管M4的有源层34；
第一金属层包括各晶体管的栅极，具体地，第一金属层包括第一晶体管M1的栅极G1、第二晶体管M2的栅极G2、第三晶体管M3的栅极G3和第四晶体管M4的栅极G4；
第二金属层包括各晶体管的源电极和漏电极，具体地，第二金属层包括第一晶体管M1的源电极S1、漏电极D1、第二晶体管M2的源电极S2、漏电极D1、第三晶体管M3的源电极S3、漏电极D2和第四晶体管M4的源电极S4、漏电极D2；
与两个晶体管的公共漏电极耦接的晶体管的栅极通过贯穿层间绝缘层的过孔与公共漏电极耦接，各晶体管的源电极和漏电极分别通过贯穿层间绝缘层和栅极绝缘层的过孔与有源层耦接；具体地，如图9A和图9B所示，与第一晶体管M1和第二晶体管M2的第一公共漏电极D1耦接的第一晶体管M1的栅极G1和第二晶体管M2的栅极G2通过贯穿层间绝缘层60的过孔O1与第一公共漏电极D1耦接，与第三晶体管M3和第四晶体管M4的第二公共漏电极D2耦接的第三晶体管M3的栅极G3和第四晶体管M4的栅极G4通过贯穿层间绝缘层60的过孔O1与第二公共漏电极D2耦接，第一晶体管的源电极S1和漏电极D1分别通过贯穿层间绝缘层60和栅极绝缘层40的过孔O2与有源层即半导体层30耦接，第二晶体管的源电极S2和漏电极D1分别通过贯穿层间绝缘层60和栅极绝缘层40的过孔O2与有源层即半导体层30耦接，第三晶体管的源电极S3和漏电极D2分别通过贯穿层间绝缘层60和栅极绝缘层40的过孔O2与有源层即半导体层30耦接，第四晶体管的源电极S4和漏电极D2分别通过贯穿层间绝缘层60和栅极绝缘层40的过孔O2与有源层即 半导体层30耦接；同理，图10A至图13B所示的耦接关系参照图9A和图9B所示的实施例，不同的是各晶体管中浮接的栅极悬空，不与任何信号线或放电线耦接；
静电防护线(VGH、VGL)与晶体管的源电极(S1、S4)耦接；
与信号线连接端L1耦接的两个晶体管(第二晶体管M2和第三晶体管M3)的源电极(S2、S3)通过贯穿层间绝缘层60和栅极绝缘层40的过孔与有源层耦接，信号线L与信号线连接端L1耦接。
在具体实施时，在本公开实施例提供的上述阵列基板中，为了简化制作工艺，本公开的静电保护电路中的所有晶体管的有源层为一体结构，且各晶体管均为多晶硅晶体管。
需要说明的是，本公开实施例提供的上述静电保护电路中的各晶体管的制作方式与相关技术中相同，在此不做详述。
需要说明的是，本公开实施例提供的上述静电保护电路中的晶体管可以为薄膜晶体管或场效应晶体管或其它特性相同的器件。
在具体实施时，在本公开实施例提供的上述阵列基板中，各晶体管的源电极延伸方向与信号线平行设置，且与静电防护线垂直设置。
在具体实施时，在本公开实施例提供的上述阵列基板中，信号线可以包括栅线、数据线或测试信号线，其中测试信号线可以包括时钟信号线或触控信号线，本公开是以栅线为例进行说明的，其它种类的信号线的静电释放原理与栅线的静电释放原理相同，在此不做赘述；静电防护线可以包括公共电极线、高电位参考电压线或低电位参考电压线，本公开是以高电位参考电压线和低电位参考电压线为例进行说明的当然也可以是公共电极线，在此不做赘述。
基于同一公开构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述任一种阵列基板。该显示装置解决问题的原理与前述阵列基板相似，因此该显示装置的实施可以参见前述阵列基板的实施，重复之处在此不再赘述。
本公开实施例提供的静电保护电路、阵列基板及显示装置，该静电保护电路包括：第一静电释放端、第二静电释放端和信号线连接端，第一静电释放端和信号线连接端之间耦接第一释放子电路，第二静电释放端和信号线连接端之间耦接第二释放子电路；第一释放子电路和第二释放子电路均包括至少一个晶体管，且所有晶体管的栅极均不与第一静电释放端、第二静电释放端和信号线连接端耦接。在实际应用时，静电保护电路中的第一静电释放端和第二静电释放端分别耦接静电防护线如公共电极线、高低电位参考电压线等，信号线连接端耦接信号线如栅线、数据线等，当信号线上积累的静电荷形成的电压过大或过小(绝对值很大)时，可以通过第一静电释放电路或第二静电释放电路中的晶体管将信号线与静电防护线导通，从而能够实现对产品中的信号线进行有效的静电释放，又不影响其正常功能的实现。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (28)

  1. 一种静电保护电路，其中，包括：
    第一静电释放端、第二静电释放端和信号线连接端；
    第一释放子电路，耦接于所述第一静电释放端和所述信号线连接端之间；
    第二释放子电路，耦接于所述第二静电释放端和所述信号线连接端之间；其中，
    所述第一释放子电路和所述第二释放子电路均包括至少一个晶体管，且所述第一释放子电路和所述第二释放子电路包含的所有所述晶体管的栅极均未与所述第一静电释放端、所述第二静电释放端和所述信号线连接端任意之一耦接。
  2. 如权利要求1所述的静电保护电路，其中，所述第一释放子电路包括第一晶体管和第二晶体管，所述第一晶体管的源极与所述第一静电释放端耦接，所述第二晶体管的源极与所述信号线连接端耦接，所述第一晶体管的漏极和所述第二晶体管的漏极串联构成第一公共漏电极。
  3. 如权利要求2所述的静电保护电路，其中，所述第一晶体管的栅极和所述第二晶体管的栅极均与所述第一公共漏电极耦接。
  4. 如权利要求2所述的静电保护电路，其中，所述第一晶体管的栅极和所述第二晶体管的栅极均浮接。
  5. 如权利要求2所述的静电保护电路，其中，所述第一晶体管的栅极与所述第一公共漏电极耦接，所述第二晶体管的栅极浮接。
  6. 如权利要求2所述的静电保护电路，其中，所述第一晶体管的栅极浮接，所述第二晶体管的栅极与所述第一公共漏电极耦接。
  7. 如权利要求3或6所述的静电保护电路，其中，所述第二晶体管为N型晶体管，所述第一晶体管的有源层的离子掺杂浓度大于所述第二晶体管的有源层的离子掺杂浓度。
  8. 如权利要求3或5所述的静电保护电路，其中，所述第一晶体管为N 型晶体管，所述第二晶体管为P型晶体管；所述第一静电释放端与低电位参考电压线耦接，所述第二静电释放端与高电位参考电压线耦接。
  9. 如权利要求4或6所述的静电保护电路，其中，所述第一晶体管为N型晶体管，所述第二晶体管为N型晶体管；所述第一静电释放端与高电位参考电压线耦接，所述第二静电释放端与低电位参考电压线耦接。
  10. 如权利要求5所述的静电保护电路，其中，所述第一晶体管为P型晶体管，所述第二晶体管的有源层的离子掺杂浓度大于所述第一晶体管的有源层的离子掺杂浓度。
  11. 如权利要求1所述的静电保护电路，其中，所述第二释放子电路包括第三晶体管和第四晶体管，所述第三晶体管的源极与所述信号线连接端耦接，所述第四晶体管的源极与所述第二静电释放端耦接，所述第三晶体管的漏极和所述第四晶体管的漏极串联构成第二公共漏电极。
  12. 如权利要求11所述的静电保护电路，其中，所述第三晶体管的栅极和所述第四晶体管的栅极均与所述第二公共漏电极耦接。
  13. 如权利要求11所述的静电保护电路，其中，所述第三晶体管的栅极和所述第四晶体管的栅极均浮接。
  14. 如权利要求11所述的静电保护电路，其中，所述第三晶体管的栅极与所述第二公共漏电极耦接，所述第四晶体管的栅极浮接。
  15. 如权利要求11所述的静电保护电路，其中，所述第三晶体管的栅极浮接，所述第四晶体管的栅极与所述第二公共漏电极耦接。
  16. 如权利要求12或15所述的静电保护电路，其中，所述第四晶体管为N型晶体管，所述第三晶体管的有源层的离子掺杂浓度大于所述第四晶体管的有源层的离子掺杂浓度。
  17. 如权利要求12或15所述的静电保护电路，其中，所述第三晶体管为N型晶体管，所述第四晶体管为P型晶体管；所述第一静电释放端与低电位参考电压线耦接，所述第二静电释放端与高电位参考电压线耦接。
  18. 如权利要求13或14所述的静电保护电路，其中，所述第三晶体管 为P型晶体管，所述第四晶体管为P型晶体管；所述第一静电释放端与高电位参考电压线耦接，所述第二静电释放端与低电位参考电压线耦接。
  19. 如权利要求14所述的静电保护电路，其中，所述第三晶体管为P型晶体管，所述第四晶体管的有源层的离子掺杂浓度大于所述第三晶体管的有源层的离子掺杂浓度。
  20. 如权利要求7、10、16和19任一项所述的静电保护电路，其中，离子掺杂浓度高的晶体管为N型晶体管或P型晶体管；所述第一静电释放端与低电位参考电压线耦接，所述第二静电释放端与高电位参考电压线耦接。
  21. 如权利要求1所述的静电保护电路，其中，所述第一释放子电路包括第一晶体管和第二晶体管，所述第一晶体管的源极与所述第一静电释放端耦接，所述第二晶体管的源极与所述信号线连接端耦接，所述第一晶体管的漏极和所述第二晶体管的漏极串联构成第一公共漏电极；
    所述第二释放子电路包括第三晶体管和第四晶体管，所述第三晶体管的源极与所述信号线连接端耦接，所述第四晶体管的源极与所述第二静电释放端耦接，所述第三晶体管的漏极和所述第四晶体管的漏极串联构成第二公共漏电极。
  22. 如权利要求21所述的静电保护电路，其中，所述第一晶体管的栅极和所述第二晶体管的栅极均与所述第一公共漏电极耦接，所述第三晶体管的栅极和所述第四晶体管的栅极均与所述第二公共漏电极耦接；或，
    所述第一晶体管的栅极和所述第二晶体管的栅极均浮接，所述第三晶体管的栅极和所述第四晶体管的栅极均浮接；或，
    所述第一晶体管和所述第二晶体管中的一个晶体管的栅极与所述第一公共漏电极耦接，另一个晶体管的栅极浮接；所述第三晶体管和所述第四晶体管中的一个晶体管的栅极浮接，另一个晶体管的栅极与所述第二公共漏电极耦接；或，
    所述第一晶体管和所述第二晶体管中的一个晶体管的栅极与所述第一公共漏电极耦接，另一个晶体管的栅极浮接；所述第三晶体管和所述第四晶体 管的栅极均与所述第二公共漏电极耦接；或，
    所述第一晶体管和所述第二晶体管的栅极均与所述第一公共漏电极耦接；所述第三晶体管和所述第四晶体管中的一个晶体管的栅极与所述第二公共漏电极耦接，另一个晶体管的栅极浮接。
  23. 一种阵列基板，包括显示区和包围所述显示区的非显示区，所述显示区包括信号线，所述非显示区包括静电防护线，其中，所述非显示区还包括如权利要求1-19任一项所述的静电保护电路；其中，
    所述静电保护电路的信号线连接端与所述信号线耦接；
    所述静电保护电路的第一静电释放端和第二静电释放端均与所述静电防护线耦接。
  24. 如权利要求23所述的阵列基板，其中，包括衬底基板，位于所述衬底基板上依次层叠设置的缓冲层、半导体层、栅极绝缘层、第一金属层、层间绝缘层、第二金属层、钝化层和平坦化层，其中，
    所述半导体层包括各所述晶体管的有源层，所述第一金属层包括各所述晶体管的栅极，所述第二金属层包括各所述晶体管的源电极和漏电极；
    第一公共漏电极或第二公共漏电极通过贯穿所述层间绝缘层的过孔与对应的栅极耦接，所述源电极和所述漏电极分别通过贯穿所述层间绝缘层和所述栅极绝缘层的过孔与对应的所述有源层耦接。
  25. 如权利要求24所述的阵列基板，其中，所有所述晶体管的有源层为一体结构，且各所述晶体管均为多晶硅晶体管。
  26. 如权利要求24所述的阵列基板，其中，各所述晶体管的源电极延伸方向与所述信号线平行设置，且与所述静电防护线垂直设置。
  27. 如权利要求23所述的阵列基板，其中，所述信号线包括栅线、数据线或测试信号线；所述静电防护线包括公共电极线、高电位参考电压线或低电位参考电压线。
  28. 一种显示装置，其中，包括如权利要求23-27任一项所述的阵列基板。
PCT/CN2019/102895 2018-11-23 2019-08-27 静电保护电路、阵列基板及显示装置 WO2020103510A1 (zh)

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN209150116U (zh) 2018-11-23 2019-07-23 京东方科技集团股份有限公司 一种静电保护电路、阵列基板及显示装置
CN111223874A (zh) * 2018-11-27 2020-06-02 北京铂阳顶荣光伏科技有限公司 薄膜场效应晶体管阵列结构及显示装置
CN110676253B (zh) * 2019-09-29 2022-03-22 厦门天马微电子有限公司 一种静电释放电路、阵列基板、显示面板及显示装置
JP7467239B2 (ja) * 2020-06-01 2024-04-15 株式会社ジャパンディスプレイ 電子デバイス及び表示装置
KR20220026172A (ko) * 2020-08-25 2022-03-04 엘지디스플레이 주식회사 디스플레이 장치
CN112419956B (zh) * 2020-11-18 2022-07-12 武汉华星光电半导体显示技术有限公司 静电释放电路及显示面板
CN112967649B (zh) * 2021-02-26 2022-09-23 昆山国显光电有限公司 显示面板和电子设备
CN116799002B (zh) * 2023-08-03 2024-01-30 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1402358A (zh) * 2001-08-22 2003-03-12 联华电子股份有限公司 高基底触发效应的静电放电保护元件结构及其应用电路
CN102054837A (zh) * 2009-11-05 2011-05-11 上海宏力半导体制造有限公司 双向晶闸管以及静电保护电路
JP2011159914A (ja) * 2010-02-03 2011-08-18 Elpida Memory Inc Ｅｓｄ保護回路及び半導体装置
CN103944154A (zh) * 2013-12-11 2014-07-23 厦门天马微电子有限公司 一种静电保护电路及液晶显示器
JP2016058423A (ja) * 2014-09-05 2016-04-21 旭化成エレクトロニクス株式会社 Ｅｓｄ保護回路
CN209150116U (zh) * 2018-11-23 2019-07-23 京东方科技集团股份有限公司 一种静电保护电路、阵列基板及显示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100505619B1 (ko) * 1998-09-29 2005-09-26 삼성전자주식회사 반도체소자의정전하방전회로,그구조체및그구조체의제조방법
US6353520B1 (en) * 1999-06-03 2002-03-05 Texas Instruments Incorporated Shared 5 volt tolerant ESD protection circuit for low voltage CMOS process
US7304827B2 (en) * 2003-05-02 2007-12-04 Zi-Ping Chen ESD protection circuits for mixed-voltage buffers
US7595245B2 (en) * 2005-08-12 2009-09-29 Texas Instruments Incorporated Semiconductor device having a gate electrode material feature located adjacent a gate width side of its gate electrode and a method of manufacture therefor
JP2007116049A (ja) * 2005-10-24 2007-05-10 Toshiba Corp 半導体装置
WO2010123620A1 (en) * 2009-04-24 2010-10-28 Arizona Board of Regents, a body corporate acting for and on behalf of Arizona State University Methods and system for electrostatic discharge protection of thin-film transistor backplane arrays

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1402358A (zh) * 2001-08-22 2003-03-12 联华电子股份有限公司 高基底触发效应的静电放电保护元件结构及其应用电路
CN102054837A (zh) * 2009-11-05 2011-05-11 上海宏力半导体制造有限公司 双向晶闸管以及静电保护电路
JP2011159914A (ja) * 2010-02-03 2011-08-18 Elpida Memory Inc Ｅｓｄ保護回路及び半導体装置
CN103944154A (zh) * 2013-12-11 2014-07-23 厦门天马微电子有限公司 一种静电保护电路及液晶显示器
JP2016058423A (ja) * 2014-09-05 2016-04-21 旭化成エレクトロニクス株式会社 Ｅｓｄ保護回路
CN209150116U (zh) * 2018-11-23 2019-07-23 京东方科技集团股份有限公司 一种静电保护电路、阵列基板及显示装置

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