WO2020103909A1 - 阵列基板、静电放电保护电路和显示装置 - Google Patents

阵列基板、静电放电保护电路和显示装置

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Publication number
WO2020103909A1
WO2020103909A1 PCT/CN2019/119982 CN2019119982W WO2020103909A1 WO 2020103909 A1 WO2020103909 A1 WO 2020103909A1 CN 2019119982 W CN2019119982 W CN 2019119982W WO 2020103909 A1 WO2020103909 A1 WO 2020103909A1
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WO
WIPO (PCT)
Prior art keywords
electrode
signal line
protection device
electrostatic discharge
array substrate
Prior art date
Application number
PCT/CN2019/119982
Other languages
English (en)
French (fr)
Inventor
龙春平
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/956,483 priority Critical patent/US11315920B2/en
Priority to JP2020552757A priority patent/JP7510350B2/ja
Priority to EP19886441.5A priority patent/EP3886164A4/en
Publication of WO2020103909A1 publication Critical patent/WO2020103909A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate, an electrostatic discharge protection circuit, and a display device.
  • Electrostatic discharge is a relatively common phenomenon in the manufacturing, transportation and use of display devices.
  • ESD Electrostatic Discharge
  • the yield of the display device will be greatly reduced.
  • the electronic circuit in the display device may not work properly, resulting in a decrease in the display effect of the display device.
  • an electrostatic discharge protection circuit is provided in the non-display area (such as the bezel area) of the array substrate in the display device to discharge or balance the high voltage static electricity to protect the display device from electrostatic damage during production, transportation and work .
  • an array substrate in one aspect, includes a base substrate, at least one first signal line, at least one second signal line, and at least one electrostatic discharge protection device.
  • the at least one first signal line and at least one second signal line are disposed on the first side of the base substrate.
  • the at least one electrostatic discharge protection device is disposed on the first side of the base substrate, and each of the at least one electrostatic discharge protection device includes a first electrode, a second electrode, and an insulating medium.
  • the first electrode is coupled to one of the at least one first signal line; the second electrode is coupled to one of the at least one second signal line; insulating medium Provided between the first electrode and the second electrode, the insulating medium is configured such that an electrostatic discharge capacitance is formed between the first electrode and the second electrode.
  • the electrostatic discharge capacitor is configured to discharge the static charge on one of the first signal line and the second signal line to which it is coupled to the other.
  • the array substrate includes: a gate layer, a semiconductor layer, and a gate insulating layer.
  • a gate layer is provided on the first side of the base substrate.
  • the gate layer includes the first electrode of the electrostatic discharge protection device and the gate of the driving transistor.
  • a semiconductor layer is disposed on a side of the gate layer near or away from the base substrate.
  • the semiconductor layer includes a second electrode of the electrostatic discharge protection device and an active layer of the driving transistor.
  • a gate insulating layer is provided between the gate layer and the semiconductor layer, and a portion of the gate insulating layer between the first electrode and the second electrode of the electrostatic discharge protection device serves as the insulating medium .
  • the material of the second electrode is a heavily doped semiconductor material, and the doping concentration of the heavily doped semiconductor material is 10 18 / cm 3 to 10 22 / cm 3 .
  • the gate layer is located on a side of the semiconductor layer away from the base substrate.
  • the array substrate further includes: an interlayer insulating layer and a source-drain electrode layer.
  • the interlayer insulating layer is disposed on a side of the gate layer away from the base substrate.
  • a source-drain electrode layer is disposed on a side of the interlayer insulating layer away from the base substrate, the source-drain electrode layer includes the at least one first signal line, the at least one second signal line, and the The source and drain of the drive transistor.
  • the first electrode of the ESD protection device is provided with a first via hole penetrating the interlayer insulating layer on the side away from the base substrate, and the first electrode of the ESD protection device passes through the first electrode The hole is coupled to the first signal line.
  • the second electrode of the ESD protection device is provided with a second via hole penetrating the gate insulation layer and the interlayer insulation layer on the side away from the base substrate, and the second of the ESD protection device The electrode is coupled to the second signal line through the second via.
  • the second electrode of the ESD protection device is provided with a second via on a side away from the base substrate.
  • the ESD protection device further includes a first connection electrode, one end of the first connection electrode is coupled to the second signal line, and the other end of the first connection electrode passes through the one second via One end of the second electrode close to the second signal line is coupled.
  • the second electrode of the ESD protection device is provided with two second vias on a side away from the base substrate.
  • the ESD protection device further includes a second connection electrode, one end of the second connection electrode is coupled to the second signal line, and the other end of the second connection electrode passes through the two second vias
  • a second via hole is coupled to an end of the second electrode far away from the second signal line, and the portion of the second connection electrode except for its two ends passes through the other of the two second via holes
  • a second via is coupled to an end of the second electrode close to the second signal line.
  • the gate layer is located on a side of the semiconductor layer close to the base substrate.
  • the array substrate further includes a source-drain electrode layer disposed on a side of the semiconductor layer away from the base substrate, the source-drain electrode layer includes the at least one first signal line and the at least one second The signal line and the source and drain of the driving transistor.
  • a third via hole penetrating the gate insulating layer is provided on the side of the first electrode of the ESD protection device that is away from the base substrate, and the first electrode of the ESD protection device passes through the third The hole is coupled to the first signal line.
  • the second electrode of the electrostatic discharge protection device is coupled to the second signal line.
  • the array substrate further includes: at least one test control line and at least one test signal line disposed on the first side of the base substrate, each test control in the at least one test control line The line is configured to transmit a test control signal to the array substrate.
  • Each test signal line in the at least one test signal line is configured to transmit a test signal to the array substrate.
  • the at least one first signal line includes the test control line, and the at least one second signal line includes the test signal line.
  • the array substrate includes: a gate line, a data line, a common voltage signal line, a clock signal line, and a level signal line provided on the first side of the base substrate.
  • the at least one first signal line includes at least one of the gate line, the data line, the common voltage signal line, the clock signal line, and the level signal line.
  • the at least one second signal line includes at least one of the gate line, the data line, the common voltage signal line, the clock signal line, and the level signal line.
  • the first electrode of each of the at least two ESD protection devices is coupled to the same first signal line.
  • a part of the second electrode of the ESD protection device is coupled to one second signal line, and another part of the second electrode of the ESD protection device is coupled to another second signal line.
  • the at least two ESD protection devices are divided into at least one group, and each group includes two ESD protection devices; the two ESD protection devices are a first ESD protection device and a second ESD protection device, respectively Discharge protection device.
  • the array substrate further includes a source-drain electrode layer
  • the array substrate further includes: a passivation layer and a pixel electrode layer.
  • the passivation layer is disposed on the side of the source-drain electrode layer away from the base substrate.
  • the pixel electrode layer is disposed on a side of the passivation layer away from the base substrate.
  • the pixel electrode layer includes at least one third connection electrode and a plurality of pixel electrodes.
  • a fourth via hole penetrating at least the passivation layer is provided on the side of the first electrostatic discharge protection device and the second electrode of the second electrostatic discharge protection device far away from the base substrate.
  • Two ends of one third connection electrode of the at least one third connection electrode respectively pass through the fourth vias corresponding to the first electrostatic discharge protection device and the second electrostatic discharge protection device, and
  • An ESD protection device is coupled to the second electrode of the second ESD protection device.
  • the at least two ESD protection devices are divided into at least one group, and each group includes two ESD protection devices; the two ESD protection devices are a first ESD protection device and a second ESD protection device, respectively Discharge protection device.
  • the first electrode of the first electrostatic discharge protection device and the first electrode of the second electrostatic discharge protection device are coupled to the same first signal line through the same via hole.
  • the orthographic projections of the first ESD protection device and the second ESD protection device on the base substrate are symmetrically located on the first signal line where the two are coupled. Both sides of the orthographic projection on the base substrate.
  • the first electrode includes one first sub-electrode and at least two second sub-electrodes arranged side by side, and the first sub-electrode and the at least two second sub-electrodes are both arranged crosswise.
  • the array substrate has a display area and a non-display area, the non-display area is located at the periphery of the display area, and the at least one ESD protection device is disposed in the non-display area.
  • the array substrate further includes at least one pad provided in the non-display area, and each pad of the at least one pad is coupled to the at least one first signal line and is configured to face the at least one A first signal line transmits electrical signals.
  • an electrostatic discharge protection circuit is provided.
  • the electrostatic discharge protection circuit is provided in the array substrate according to any one of the above.
  • the electrostatic discharge protection circuit includes at least one electrostatic discharge protection device, and the at least one static electricity The first end of each of the electrostatic discharge protection devices in the discharge protection device is coupled to one of the at least one first signal line in the array substrate, and the second end is connected to the One second signal line of at least one second signal line is coupled.
  • the electrostatic discharge protection device is configured to discharge the static charge on one of the first signal line and the second signal line to which it is coupled to the other.
  • the electrostatic discharge protection device is a capacitor.
  • At least two first ends of the ESD protection devices are coupled to the same first signal line, and the second ends of the two ESD protection devices are connected to the same second signal line Or different second signal lines are coupled.
  • a display device including the array substrate as described in any one of the above.
  • FIG. 1 is a structural diagram of an electrostatic discharge protection circuit according to the related art
  • FIG. 2A is a structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 2B is a cross-sectional view of the array substrate according to the cross-sectional line AA 'in FIG. 2A;
  • FIG. 2C is an enlarged view of the area M in FIG. 2A;
  • 3A is another structural diagram of an array substrate according to some embodiments of the present disclosure.
  • 3B is a cross-sectional view of the array substrate according to the cross-sectional line BB 'in FIG. 3A;
  • FIG. 4A is another structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 4B is a cross-sectional view of the array substrate according to the cross-sectional line CC 'in FIG. 4A;
  • FIG. 4C is a cross-sectional view of the array substrate according to the cross-sectional line DD 'in FIG. 4A;
  • 5A is another structural diagram of an array substrate according to some embodiments of the present disclosure.
  • 5B is a cross-sectional view of the array substrate according to section line EE 'in FIG. 5A;
  • 6A is another structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 6B is a cross-sectional view of the array substrate according to the cross-sectional line FF 'in FIG. 6A;
  • 6C is a cross-sectional view of the array substrate according to the cross-sectional line GG 'in FIG. 6A;
  • FIG. 7 is a structural diagram of an electrostatic discharge protection circuit according to some embodiments of the present disclosure.
  • FIG. 8 is another structural diagram of an electrostatic discharge protection circuit according to some embodiments of the present disclosure.
  • FIG. 9 is another structural diagram of an electrostatic discharge protection circuit according to some embodiments of the present disclosure.
  • FIG. 10A is another structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 10B is another structural diagram of an array substrate according to some embodiments of the present disclosure.
  • FIG. 11 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “plurality” is two or more.
  • Coupled and its derivatives may be used.
  • some embodiments may be described using the term “coupled” to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components do not directly contact each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content herein.
  • an electrostatic discharge protection circuit is usually provided in the array substrate in the display device to protect the electronic circuit in the display device from electrostatic interference.
  • the array substrate includes a plurality of signal lines such as a gate line, a data line, a clock signal line, a common voltage signal line, and a level signal line. During the manufacturing, transportation, and use of the display device, the plurality of signal lines may accumulate static electricity. At least one of the plurality of signal lines serves as at least one first signal line, and the other of the plurality of signal lines serves as at least one second signal line.
  • the array substrate further includes at least one ESD protection circuit, and each ESD protection circuit is coupled to at least one first signal line of at least one first signal line and at least one second signal line of at least one second signal line to Discharge or equalize the static electricity on the first signal line or the second signal line.
  • the ESD protection circuit includes at least two thin film transistors.
  • the at least two thin film transistors are a first thin film transistor T 1 and a second thin film transistor T 2 , respectively.
  • Both the first electrode and the control electrode of the first thin film transistor T 1 are coupled to a first signal line 1
  • the first electrode and the control electrode of the second thin film transistor T 2 are coupled to a second signal line 2
  • the first electrode of the first thin film transistor T 1 is coupled to the second electrode of the second thin film transistor T 2
  • the second electrode of the first thin film transistor T 1 is coupled to the first electrode of the second thin film transistor T 2 .
  • the insulating medium between the control electrode (gate) and the first and second electrodes (source and drain electrodes) may break down, thereby Cause the threshold voltage of the thin film transistor to drift or the short circuit between the gate and the source and drain electrodes. Therefore, with the above electrostatic discharge protection circuit, in the case of excessive static charge accumulation, if the thin film transistor encounters a large current or a momentary large charge shock, the gate of the thin film transistor may be broken, resulting in the thin film transistor being burned out. Therefore, the electrostatic discharge protection circuit cannot work normally, and the discharge of static charge cannot be realized.
  • the array substrate 100 includes: a base substrate 3, at least one first signal line 1, at least one second signal line 2, and at least one Electrostatic discharge protection device 4.
  • the at least one first signal line 1 and the at least one second signal line 2 are both provided on the first side A side of the base substrate 3, and the side opposite to the first side A side is the first side of the base substrate 3 Side B side.
  • the at least one first signal line is at least one of a plurality of signal lines (eg, gate lines, data lines, level signal lines) provided on the first side A side of the base substrate 3, and the at least one first signal line
  • the two signal lines are the other of the plurality of signal lines (for example, gate lines, data lines, and level signal lines) provided on the first side A side of the base substrate 3.
  • Static electricity may accumulate on the at least one first signal line 1 and the at least one second signal line 2.
  • Each of the at least one ESD protection device 4 includes a first electrode 41, a second electrode 42, and an insulating medium 43.
  • the first electrode 41 is coupled to one of the at least one first signal line 1.
  • the second electrode 42 is coupled to one of the at least one second signal line 2.
  • the insulating medium 43 is provided between the first electrode 41 and the second electrode 42.
  • the insulating medium 43 is configured such that an electrostatic discharge capacitance C is formed between the first electrode 41 and the second electrode 42; the electrostatic discharge capacitance C is configured to The electrostatic charge on one of the coupled first signal line 1 and second signal line 2 is discharged to the other.
  • the array substrate 100 provided by some embodiments of the present disclosure is provided with at least one ESD protection device 4, and the first electrode 41 included in each ESD protection device 4 is coupled to a first signal line 1, and the second electrode 42 is coupled to a second signal line 2, and an electrostatic discharge capacitor C is formed between the first electrode 41 and the second electrode 42, so that when a large amount of static charge accumulates on the first signal line 1, the device 4 is protected by the electrostatic discharge
  • the electrostatic discharge capacitor C formed in the process discharges static charge from the first signal line 1 to the second signal line 2 to play a role of electrostatic shunt.
  • the electrostatic discharge capacitor C formed in the ESD protection device 4 releases the static charge from the second signal line 2 to the first signal line 1 To electrostatic shunt. In this way, whether a large amount of static charge is accumulated on the first signal line 1 or a large amount of static charge on the second signal line 2, the static charge can be discharged through the electrostatic discharge protection device 4 to avoid the static charge from affecting the electronic circuit ( For example, the normal operation of the pixel drive circuit.
  • an electrostatic discharge capacitor C is formed between the first electrode 41 and the second electrode 42 of each electrostatic discharge protection device 4, and the characteristics of the electrostatic discharge capacitor C are used to achieve electrostatic protection: on the one hand, between the two poles of the capacitor The voltage of will not be abrupt, so the electrostatic discharge capacitor C itself has the effect of suppressing static electricity, especially the circuit provided with a large-capacity capacitor does not even need electrostatic discharge protection.
  • the interference of electrostatic discharge on electronic circuits is mainly conducted interference and radiated interference, and static electricity itself is a wide-band signal.
  • the use of capacitors can provide a better discharge path for electrostatic charges without affecting the generated Is electrostatically coupled to sensitive circuits. Therefore, the use of electrostatic discharge capacitor C for decoupling can improve the decoupling ability of the first signal line 1 and the second signal line 2, and enhance the power of the first signal line 1 and the second signal line 2. Anti-interference ability.
  • the electrostatic discharge capacitor C formed between the first electrode 41 and the second electrode 42 of the electrostatic discharge protection device 4 is used to realize the discharge of electrostatic charges, and no device such as a thin film transistor is used. This avoids the problem that in the related art electrostatic discharge protection circuit, the thin film transistor encounters a large current or a momentary large charge impact, which may cause the gate of the thin film transistor to be broken down, resulting in the problem of the thin film transistor being burned out.
  • the array substrate 100 includes: a gate layer 5, a semiconductor layer 6 and a gate insulating layer 7.
  • the gate layer 5 is provided on the first side A side of the base substrate 3.
  • the gate layer 5 includes the first electrode 41 of the electrostatic discharge protection device 4 and the gate of the driving transistor.
  • the semiconductor layer 6 is disposed on the side of the gate layer 5 near or away from the base substrate 3.
  • the semiconductor layer 6 includes the second electrode 42 of the electrostatic discharge protection device 4 and the active layer of the driving transistor.
  • the gate insulating layer 7 is provided between the gate layer 5 and the semiconductor layer 6, and a portion of the gate insulating layer 7 between the first electrode 41 and the second electrode 42 of the electrostatic discharge protection device 4 serves as an insulating medium 43.
  • the first electrode 41 of the ESD protection device 4 and the gate of the drive transistor are provided in the same layer, so that the first electrode 41 of the ESD protection device can be formed in the same layer when the gate of the drive transistor is formed .
  • the second electrode 42 of the ESD protection device 4 and the active layer of the drive transistor are provided in the same layer, so that the second electrode 42 of the ESD protection device can be formed in the same layer when the active layer of the drive transistor is formed.
  • the array substrate 100 since the first electrode 41 and the second electrode 42 in the ESD protection device 4 are respectively provided in the same layer as the gate electrode and the active layer in the driving transistor, it can be patterned at one time
  • the gate electrode of the driving transistor and the first electrode 41 of the ESD protection device 4 are formed by a process, and the active layer of the driving transistor and the second electrode 42 of the ESD protection device 4 can also be formed through a patterning process, which reduces the array substrate 100
  • the manufacturing process steps reduce the preparation time of the array substrate 100 and improve the preparation efficiency.
  • the same mask can be used when forming the gate and the first electrode 41, and the same mask can be used when forming the active layer and the second electrode 42, the number of masks can be reduced, thereby saving costs .
  • the material of the second electrode 42 is a heavily doped semiconductor material, and the doping concentration of the heavily doped semiconductor material is 10 18 / cm 3 to 10 22 / cm 3 .
  • the material of the second electrode 42 may be a heavily doped low temperature poly-silicon (LTPS) material.
  • the second electrode 42 is formed as follows: an amorphous silicon thin film is formed on the first side A side of the base substrate 3 by a deposition process, through laser annealing (ELA, Excimer Laser Annel) or solid phase crystallization (SPC , Solid Phase Crystallization) process, making amorphous silicon thin film crystallized into polycrystalline silicon thin film. Then, the polysilicon film is etched using a photolithography process to form a plurality of first polysilicon structures having the pattern of the second electrode 42 and a plurality of second polysilicon structures having the pattern of the active layer of the driving transistor.
  • ELA Laser annealing
  • SPC Solid Phase Crystallization
  • High-concentration ion implantation is performed on the plurality of first polysilicon structures.
  • the ions are used as donors or acceptors to provide carriers and are embedded in the polysilicon crystal structure.
  • the concentration of the ions can be selected according to actual needs, for example, 10 18 / cm 3 , 10 19 / cm 3 , 10 20 / cm 3 , 10 21 / cm 3 , 10 22 / cm 3, etc., thereby converting multiple first polysilicon structures into multiple low resistance heavy
  • the doped polysilicon structure, and the plurality of low resistance heavily doped polysilicon structures serve as the second electrode 42.
  • the material of the second electrode 42 is set as a heavily doped semiconductor material. Since the resistance of the heavily doped semiconductor material is much smaller than the resistance of the insulating material and much larger than the resistance of the metal material, the resistance of the second electrode 42 is far Far less than the resistance of the insulating medium 43, and much greater than the resistance of the first signal line 1 and the second signal line 2 (the signal line is generally made of metal material), the resistance value is between the heavy material of the insulating material and the metal material Miscellaneous semiconductor materials can be turned on when high voltage and large current occur.
  • the ESD protection device has a variety of different structures according to the arrangement of each functional film layer included in the array substrate 100, and the present disclosure does not limit this, as long as It is sufficient for the electrostatic discharge protection device to play the role of the aforementioned electrostatic protection.
  • the arrangement of each functional film layer of the array substrate 100 and the structure of the corresponding ESD protection device 4 will be exemplarily introduced below.
  • the array substrate 100 further includes: an interlayer insulating layer 8 and source leakage ⁇ ⁇ 9. 9. Polar layer 9.
  • the interlayer insulating layer 8 is disposed on the side of the gate layer 5 away from the base substrate 3.
  • the source-drain electrode layer 9 is disposed on the side of the interlayer insulating layer 8 away from the base substrate 3, and the source-drain electrode layer 9 includes the at least one first signal line 1, the at least one second signal line 2, and a driving transistor Source and drain.
  • the first electrode 41 of the ESD protection device 4 is provided with a first via a penetrating the interlayer insulating layer 8 on the side away from the base substrate 3, and the first electrode 41 of the ESD protection device 4 passes through the first via a is coupled to the first signal line 1.
  • the second electrode 42 of the ESD protection device 4 is provided with a second via b penetrating the gate insulating layer 7 and the interlayer insulating layer 8 on the side away from the base substrate 3, and the second electrode 42 of the ESD protection device 4 passes through The second via b is coupled to the second signal line 2.
  • the at least one first signal line 1, the at least one second signal line 2 and the source and drain of the driving transistor are arranged in the same layer, so that the source and drain of the driving transistor can be formed At the same time, the at least one first signal line 1 and the at least one second signal line 2 are formed in the same layer, thereby reducing the manufacturing process steps of the array substrate 100, reducing the preparation time of the array substrate 100, and improving the preparation efficiency.
  • the second electrode 42 of each ESD protection device 4 is provided with a second via b on the side away from the base substrate 3.
  • the ESD protection device 4 further includes a first connection electrode 44, one end of the first connection electrode 44 is coupled to the second signal line 2, and the other end of the first connection electrode 44 is close to the second electrode 42 through a second via b One end of the second signal line 2 is coupled.
  • the first connection electrode 44 serves to connect the second signal line 2 and the second electrode 42.
  • the static charge on the first signal line 1 can pass through the first electrode 41.
  • the second electrode 42 and the first connection electrode 44 are discharged onto the second signal line 2, or the static charge on the second signal line 2 can be discharged through the first connection electrode 44, the second electrode 42 and the first electrode 41 To the second signal line 2, it acts as an electrostatic shunt.
  • the second electrode 42 of each electrostatic discharge capacitor C is provided with two second via holes b on the side away from the base substrate 3.
  • the ESD protection device 4 further includes a second connection electrode 45, one end of the second connection electrode 45 is coupled to the second signal line 2, the other end of the second connection electrode 45 passes through one of the two second vias b
  • the via hole b is coupled to the end of the second electrode 42 away from the second signal line 2, and the portion of the second connection electrode 45 except for its two ends passes through the other of the two second via holes b
  • One end of the second electrode 42 near the second signal line 2 is coupled.
  • the orthographic projection of the portion of the second connection electrode 45 other than its two ends on the base substrate 3 and the orthographic projection of the first electrode 41 on the base substrate 3 at least partially overlap.
  • the second connection electrode 45 functions to connect the second signal line 2 and the second electrode 42, and since the portion of the second connection electrode 45 other than its both ends is on the base substrate 3
  • the projection at least partially overlaps the orthographic projection of the first electrode 42 on the base substrate 3, so that a portion of the second connection electrode 45 except for its two ends can form a capacitance between the first electrode 41 and the capacitance can serve as static electricity
  • the discharge capacitance is equivalent to the increase of the electrostatic discharge capacitance formed in the electrostatic discharge protection device 4, and when a large amount of static charge is accumulated on the first signal line 1, the static electricity passing between the first electrode 41 and the second electrode 42
  • a large amount of static charge accumulates on the second
  • the array substrate 100 further includes a source-drain electrode layer 9.
  • the source-drain electrode layer 9 is disposed on the side of the semiconductor layer 6 away from the base substrate 3, the source-drain electrode layer 9 includes the at least one first signal line 1, the at least one second signal line 2, and a driving transistor Source and drain.
  • the first electrode 41 of the electric discharge protection device is provided with a third via c through the gate insulating layer 7 on the side away from the base substrate 3.
  • the first electrode 41 of the electrostatic discharge protection device 4 passes through the third via c and A signal line 1 is coupled.
  • the second electrode 42 of the ESD protection device 4 is coupled to the second signal line 2.
  • the at least one first signal line 1, the at least one second signal line 2 and the source and drain of the driving transistor are arranged in the same layer, so that the source and drain of the driving transistor can be formed At this time, the at least one first signal line 1 and the at least one second signal line 2 are formed in the same layer, thereby reducing the manufacturing process steps of the array substrate 100, reducing the preparation time of the array substrate 100, and improving the preparation efficiency.
  • the second electrode 42 and the second signal line 2 can be directly coupled without coupling via vias, which can simplify the manufacturing process of the array substrate 100.
  • the array substrate 100 has a display area AA and a non-display area BB, and the non-display area BB is disposed around the display area AA.
  • the non-display area BB surrounds the display area AA, or, in the case where the display area AA is rectangular, the non-display area BB is disposed on one side, both sides of the display area AA (the opposite sides, or adjacent Two sides) or three sides.
  • the array substrate needs to test the signal lines in the array substrate before shipping, for example, the gate lines or data lines in the array substrate.
  • the following is an example of testing the data lines of the array substrate.
  • at least one test circuit, at least one test control line, and at least one test signal line need to be arranged in the array substrate.
  • each test circuit 12 is disposed on the first side of the base substrate, and each test circuit 12 of the at least one test circuit 12 is respectively coupled to each data line included in the array substrate .
  • each test circuit 12 includes at least one thin film transistor, and the second electrode (drain) of each of the at least one thin film transistor is coupled to one data line.
  • the at least one test control line 1 ' is disposed on the first side of the base substrate, each test control line 1' of the at least one test control line 1 'is respectively connected to each of the at least one test circuit 12
  • the test circuit 12 is coupled.
  • the test control line 1 ' is configured to transmit a test control signal to the array substrate 100, that is, to transmit the test control signal to the at least one test circuit 12 in the array substrate 100.
  • each test circuit 12 includes at least one thin film transistor
  • each test control line 1 ' respectively coupled to the control electrode (gate) of one thin film transistor in each test circuit 12, so that The test circuit 12 is turned on or off by the test control signal transmitted by the test control line 1 '.
  • the test control signal is transmitted to the at least one test control line through the pad in the array substrate 100, the pad is coupled to the control chip, and the control chip provides the test control signal to the pad.
  • the at least one test signal line 2 ' is disposed on the first side of the base substrate, each test signal line 2' in the at least one test signal line 2 'is respectively connected to each of the at least one test circuit 12
  • the test circuit 12 is coupled.
  • the test signal line 2 ' is configured to transmit a test signal to the array substrate 100, that is, to transmit the test signal to the at least one test circuit 12 in the array substrate 100.
  • each test circuit 12 includes at least one thin film transistor
  • each test signal line 2 ' respectively coupled to the first electrode (source) of one thin film transistor in each test circuit 12, to When the test circuit 12 is turned on, the test signal is transmitted to the data line.
  • the test signal is transmitted to the at least one test signal line through the pad in the array substrate 100, the pad is coupled to the control chip, and the control chip provides the test signal to the pad.
  • the at least one test signal line 2 ′ includes two test signal lines 2 ′, wherein one test signal line 2 ′ is connected to an odd number (eg 1, 3, 5, 7) data lines through the test circuit 12 respectively For coupling, another test signal line 2 'is coupled to an even number (eg, 2, 4, 6, 8) data lines through the test circuit 12 respectively.
  • an odd number eg 1, 3, 5, 7
  • another test signal line 2 ' is coupled to an even number (eg, 2, 4, 6, 8) data lines through the test circuit 12 respectively.
  • the above test process of the array substrate 100 is roughly as follows: under the control of the test control signal transmitted by the at least one test control line 1 ', the at least one test circuit is turned on, and the at least one test signal line 2' is transmitted The test signal is transmitted to the corresponding data line to detect the corresponding data line, for example, to detect whether the corresponding data line is open.
  • the at least one test circuit 12, the at least one test control line 1 'and the at least one test signal line 2' are disposed in the non-display area BB.
  • the at least one first signal line 1 includes a test control line 1 '
  • the at least one second signal line 2 includes a test signal line 2'.
  • the at least one ESD protection device 4 is disposed in the non-display area BB, and each ESD protection device 4 is coupled to one of the at least one first signal line 1 and connected to the at least one One of the second signal lines 2 is coupled.
  • the electrostatic discharge protection device 4 can discharge the static charge onto the test signal line 2', or during the test When a large amount of static charge accumulates on the signal line 2 'momentarily, the electrostatic discharge protection device 4 can discharge the static charge to the test control line 1', thereby avoiding the generated electrostatic coupling into the electronic circuit such as the test circuit 12 , To ensure the normal operation of the array substrate 100 test.
  • the array substrate 100 further includes: a gate line, a data line, a common voltage signal line, a clock signal line, and a level signal line disposed on the first side A side of the base substrate 3.
  • the level signal lines include high level (Vgh) signal lines, low level (Vgl) signal lines, first power supply (Vdd) signal lines, second power supply (Vss) signal lines, and the like.
  • a plurality of pixels in the display area AA and each pixel in the plurality of pixels corresponds to a pixel driving circuit.
  • the pixel driving circuit operates so that The display area AA realizes the display.
  • the gate lines, data lines, common voltage signal lines, clock signal lines, and level signal lines may accumulate static electricity, which may affect the normal operation of electronic circuits (such as pixel driving circuits) in the array substrate.
  • the at least one first signal line 1 includes at least one of the gate line, the data line, the common voltage signal line, the clock signal line, and the level signal line By.
  • the at least one second signal line 2 includes at least one of the gate line, the data line, the common voltage signal line, the clock signal line, and the level signal line.
  • the at least one first signal line 1 includes at least one data line and at least one gate line
  • the at least one second signal line 2 is a common voltage signal line.
  • the at least one ESD protection device 4 is located in the non-display area BB, and each ESD protection device 4 is coupled to a first signal line 1 and a second signal line 2.
  • the at least one first signal line 1 and the at least one second signal line 2 are respectively at least one of multiple signal lines included in the array substrate 100.
  • the electrostatic charge on one of the first signal line 1 and the second signal line 2 to which the electrostatic discharge protection device 4 is coupled can be discharged to
  • the static charge accumulated on the gate line or the data line may be discharged to the common voltage signal line, thereby implementing electrostatic shunting, so that the display operation of the array substrate 100 is protected from static electricity.
  • the array substrate 100 further includes at least one pad disposed in the non-display area BB, each of the at least one pad and at least one first signal line 1 coupled, configured to transmit electrical signals to the at least one first signal line 1.
  • the pad is configured to transmit a test control signal to the test control line 1'; at the at least one first signal line 1 In the case of including the gate line, the pad is configured to transmit the gate scan signal to the gate line.
  • the first electrode 41 of each of the at least two ESD protection devices 4 is coupled to the same first signal line 1.
  • a part of the second electrode 42 of the ESD protection device 4 is coupled to a second signal line 2, and the other part of the second electrode 42 of the ESD protection device 4 is connected to another second The signal line 2 is coupled.
  • the first electrode 41 of each ESD protection device 4 in every two ESD protection devices 4 is coupled to the same first signal line 1.
  • one of the ESD protection devices 4 is coupled to one second signal line 2 and the other ESD protection device 4 is coupled to another second signal Line 2 is coupled.
  • the static charge in the case where a large amount of static charge is momentarily accumulated on the first signal line 1, the static charge can be discharged to different second signal lines 2 through at least two electrostatic discharge protection devices 4, and the static charge on the first signal line 1
  • the path of discharge is increased, which makes the discharge of static charge faster and more efficient, and improves the protection effect of electrostatic discharge.
  • the at least two ESD protection devices 4 are divided into at least one group, and each group includes two ESD protection devices 4.
  • the two ESD protection devices 4 are a first ESD protection device 4 and a second ESD protection device 4, respectively.
  • the array substrate 100 further includes the source-drain electrode layer 9, as shown in FIGS. 4A to 4C and FIGS. 6A to 6C, the array substrate 100 further includes: a passivation layer 10 and a pixel electrode layer 11.
  • the passivation layer 10 is disposed on the side of the source-drain electrode layer 9 away from the base substrate 3.
  • the pixel electrode layer 11 is disposed on the side of the passivation layer 10 away from the base substrate 3.
  • the pixel electrode layer 11 includes at least one third connection electrode 11 a and a plurality of pixel electrodes.
  • the first electrode 42 of the first electrostatic discharge protection device 4 and the second electrode 42 of the second electrostatic discharge protection device 4 are each provided with a fourth via d that penetrates at least the passivation layer 10. Two ends of one third connection electrode 11a of the at least one third connection electrode 11a respectively pass through the fourth via holes d corresponding to the first electrostatic discharge protection device 4 and the second electrostatic discharge protection device 4 respectively , Coupled to the second electrode 42 of the first electrostatic discharge protection device 4 and the second electrostatic discharge protection device 4.
  • the at least two ESD protection devices 4 are divided into four groups, and each group includes two ESD protection devices 4.
  • the two ESD protection devices 4 are a first ESD protection device 4-1 and a second ESD protection device 4-2, respectively.
  • the second electrode 42 of the first electrostatic discharge protection device 4-1 and the second electrode 42 of the second electrostatic discharge protection device 4-2 are both provided with a through gate insulating layer 7 on the side away from the base substrate 3 , The fourth via d of the interlayer insulating layer 8 and the passivation layer 10.
  • the two ends of one third connection electrode 11a of the at least one third connection electrode 11a respectively pass through the first corresponding to the first electrostatic discharge protection device 4-1 and the second electrostatic discharge protection device 4-2
  • the four vias d are coupled to the second electrode 42 of the first ESD protection device 4-1 and the second electrode 42 of the second ESD protection device 4-2.
  • the at least two ESD protection devices 4 are divided into four groups, and each group includes two ESD protection devices 4.
  • the two ESD protection devices 4 are a first ESD protection device 4-1 and a second ESD protection device 4-2, respectively.
  • the first electrode 42 of the first electrostatic discharge protection device 4 and the second electrode 42 of the second electrostatic discharge protection device 4 are each provided with a fourth via d penetrating the passivation layer 10 on a side away from the base substrate 3.
  • the two ends of one third connection electrode 11a of the at least one third connection electrode 11a respectively pass through the first corresponding to the first electrostatic discharge protection device 4-1 and the second electrostatic discharge protection device 4-2
  • the four vias d are coupled to the second electrode 42 of the first ESD protection device 4-1 and the second electrode 42 of the second ESD protection device 4-2.
  • the second electrode 42 of the first ESD protection device 4-1 and the second electrode 42 of the second ESD protection device 4-2 are coupled through the third connection electrode 11a, so that When a large amount of static charge accumulates on the signal line 1 momentarily, the static charge can be discharged through the first electrostatic discharge protection device 4-1 and the second electrostatic discharge protection device 4-2 to the corresponding first positions of the two electrostatic discharge protection devices 4
  • the second signal line 2 and the path of the static charge release on the first signal line 1 are increased, which makes the static charge release faster and more efficient, and improves the electrostatic discharge protection effect.
  • the second electrode 42 of one of the ESD protection devices 4 eg, the first ESD protection device 4-1 and the When the coupling is damaged, the static charge cannot be shunted to the second signal line 2 to which the ESD protection device is coupled.
  • the second ESD protection device 4-2) thereby releasing static electricity, thereby improving the stability of the ESD protection device.
  • the at least two ESD protection devices 4 are divided into at least one group, and each group includes two ESD protection devices 4; the two ESD protection devices 4 are respectively the first ESD protection devices 4 ⁇ ⁇ Electrostatic discharge protection device 4.
  • the first electrode 41 of the first ESD protection device 4 and the first electrode 41 of the second ESD protection device 4 are coupled to the same first signal line 1 through the same via hole.
  • the at least two ESD protection devices 4 are in four groups, and each group includes two ESD protection devices 4.
  • the two ESD protection devices 4 are a first ESD protection device 4-1 and a second ESD protection device 4-2, respectively.
  • the first electrode 41 of the first ESD protection device 4-1 and the first electrode 41 of the second ESD protection device 4-2 are coupled to the same first signal line 1 through the same first via a in between Pick up.
  • the two ESD protection devices 4 in each group are coupled to the same first signal line 1 through the same first via a, which can reduce the number of first vias a, thereby saving
  • the preparation steps of the array substrate 100 improve the preparation efficiency.
  • the first ESD protection device 4-1 and the second ESD in each group of ESD protection devices 4 The orthographic projection of the discharge protection device 4-2 on the base substrate 3 is symmetrically located on both sides of the orthographic projection of the first signal line 1 coupled thereto on the base substrate 3.
  • the first electrode 41 included in the ESD protection device 4 includes one first sub-electrode 41a and at least Two second sub-electrodes 41b, the first sub-electrode 41a and the at least two second sub-electrodes 41b are both arranged crosswise.
  • One end of the first sub-electrode 41a is coupled to the first signal line 1 through the first via a.
  • each ESD protection device 4 includes a first electrode 41, a second electrode 42, an insulating medium 43 disposed between the first electrode 41 and the second electrode 42, and a first connection electrode 44
  • each ESD protection device 4 can be regarded as a thin film transistor, wherein the second electrode 42 can be regarded as an active layer ,
  • the first electrode 41 can be regarded as the gate, the first connection electrode 44 can be regarded as one of the source or the drain, and the other of the source or the drain is suspended, formed by the electrostatic discharge protection device 4
  • the electrostatic discharge capacitor C (an electrostatic discharge capacitor formed between the first electrode 41 and the second electrode 42) realizes the discharge of electrostatic charges.
  • each ESD protection device 4 includes a first electrode 41, a second electrode 42, an insulating medium 43 disposed between the first electrode 41 and the second electrode 42, and a second connection electrode 45
  • each ESD protection device 4 can be regarded as a thin film transistor, wherein the second electrode 42 can be regarded as an active layer ,
  • the first electrode 41 can be regarded as a gate
  • the part of the second connection electrode 45 that is in one of the two second vias b, and the part above the second via b can be Regarded as one of the source electrode or the drain electrode
  • the portion of the second connection electrode 45 that is located in the other second via hole b of the two second via holes b, and the portion above the second via hole b Part can be regarded as the other of the source or the drain, and the source and the drain are connected, through the electrostatic discharge capacitance C formed in the thin film transistor (the electrostatic discharge capacitance C formed in the thin film transistor (the electrostatic discharge capacitor
  • each ESD protection device 4 includes a first electrode 41, a second electrode 42, an insulating medium 43 disposed between the first electrode 41 and the second electrode 42, and a first connection electrode 44
  • each ESD protection device 4 can be regarded as a thin film transistor, wherein the second electrode 42 can be regarded as an active layer ,
  • the first electrode 41 can be regarded as the gate
  • the first connection electrode 44 can be regarded as one of the source or the drain
  • the portion of the third connection electrode 11a in and above the fourth via d can be regarded as
  • the other of the source electrode and the drain electrode realizes the discharge of electrostatic charges through an electrostatic discharge capacitor C formed in the thin film transistor (an electrostatic discharge capacitor formed between the first electrode 41 and the second electrode 42).
  • the first electrode 41 includes one first sub-electrode 41a and at least two second sub-electrodes 41b arranged side by side, which is equivalent to making each ESD protection device 4 be regarded as a thin film transistor
  • the double gate thin film transistor can reduce the leakage current of the ESD protection device 4 (think as a thin film transistor) and make the performance of the ESD protection device more stable.
  • Some embodiments of the present disclosure also provide an electrostatic discharge protection circuit 200 disposed in the array substrate 100 as described above.
  • the array substrate 100 includes a display area AA and a non-display area BB, and the ESD protection circuit 200 is located in the non-display area BB.
  • the ESD protection circuit 200 includes at least one ESD protection device 4.
  • the first end of each ESD protection device 4 in the at least one ESD protection device 4 and the array substrate 100 One first signal line 1 of the at least one first signal line 1 is coupled, and the second end is coupled to one second signal line 2 of the at least one second signal line 2 in the array substrate 100.
  • the ESD protection device 4 is configured to discharge the static charge on one of the first signal line 1 and the second signal line 2 to which it is coupled to the other.
  • the at least one first signal line 1 includes the test control line
  • the at least one A second signal line 2 includes the test signal line.
  • the array substrate 100 includes gate lines, data lines, common voltage signal lines, clock signal lines, and level signal lines.
  • the at least one first signal line 1 includes at least one of a gate line, a data line, a common voltage signal line, a clock signal line, and a level signal line.
  • the at least one second signal line 2 includes at least one of a gate line, a data line, a common voltage signal line, a clock signal line, and a level signal line.
  • the electrostatic discharge protection circuit 200 when no static charge is accumulated on the first signal line 1 and the second signal line 2, the electrostatic discharge protection circuit 200 does not work; when an electrostatic discharge occurs, the first signal line 1 instantly gathers A large amount of static charge will be quickly discharged to the second signal line 2 through the ESD protection device 4 in the ESD protection circuit 200, or a large amount of static charge accumulated momentarily in the second signal line 2 will pass through the ESD protection device in the ESD protection circuit 4 Quickly release to the first signal line 1, so as to avoid the static charge from affecting the normal operation of other electronic circuits such as the pixel driving circuit.
  • the electrostatic discharge protection device 4 is a capacitor.
  • capacitor decoupling can improve the decoupling ability of the first signal line 1 and the second signal line 2 and enhance the anti-interference ability of the first signal line 1 and the second signal line 2. Avoid the influence of static electricity on the normal operation of electronic circuits.
  • the first ends of at least two ESD protection devices 4 are coupled to the same first signal line 1, and the second ends of the two ESD protection devices 4
  • the terminal is coupled to the same second signal line 2 or a different second signal line 2.
  • the static charge in the case where a large amount of static charge is momentarily accumulated on the first signal line 1 coupled to the first ends of the at least two electrostatic discharge protection devices 4, the static charge can be protected by at least two electrostatic discharges
  • the device 4 is released to a different second signal line 2 or to the same second signal line 2, the path of the static charge release on the first signal line 1 is increased, which makes the static charge release faster, more efficient, and improved ESD protection effect.
  • the above-mentioned ESD protection circuit 200 has other ways of setting, and the disclosure does not limit this, as long as it can play the role of ESD protection.
  • an embodiment of the present disclosure also provides a display device 300 including the array substrate 100 as described above.
  • the display device 300 provided in the embodiments of the present disclosure may be a liquid crystal display device (Liquid Crystal Display, referred to as LCD); it may also be an organic electroluminescence display device (Organic Light-Emitting Display, referred to as OLED); or a quantum dot electroluminescence Light-emitting display panel (Quantum Dot Light-Emitting Display, referred to as QLED).
  • LCD Liquid Crystal Display
  • OLED Organic Light-Emitting Display
  • QLED Quantum Dot Light-Emitting Display
  • the display device 300 When the display device 300 is a liquid crystal display device, the display device 300 includes, in addition to the array substrate 100, a counter substrate and a liquid crystal layer provided between the counter substrate and the array substrate 100.
  • the display device 300 further includes an encapsulation layer for encapsulating the array substrate 100.
  • the array substrate 100 further includes a pixel driving circuit and a light emitting device, and the light emitting device includes an anode, a light emitting layer, and a cathode.
  • the encapsulation layer may be a thin-film encapsulation layer or a substrate encapsulation layer.
  • the display device may be any product or component with a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.
  • the beneficial effects that can be achieved by the display device 300 provided by the embodiments of the present disclosure are the same as the beneficial effects that can be achieved by the array substrate 100 provided above, and details are not described herein again.

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Abstract

一种阵列基板，所述阵列基板包括：衬底基板、至少一条第一信号线、至少一条第二信号线和至少一个静电放电保护器件。所述至少一条第一信号线和至少一条第二信号线设置于所述衬底基板的第一侧。所述至少一个静电放电保护器件设置于所述衬底基板的第一侧，所述至少一个静电放电保护器件中的每个静电放电保护器件包括：第一电极、第二电极和绝缘介质。第一电极与所述至少一条第一信号线中的一条第一信号线耦接；第二电极与所述至少一条第二信号线中的一条第二信号线耦接；绝缘介质设置于所述第一电极和所述第二电极之间，绝缘介质被配置为使得第一电极和第二电极之间形成静电放电电容。其中，静电放电电容被配置为将其所耦接的第一信号线和第二信号线中的一者上的静电荷释放至另一者上。

Description

阵列基板、静电放电保护电路和显示装置
本申请要求于2018年11月22日提交的、申请号为201821934974.7的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、静电放电保护电路和显示装置。
背景技术
在显示装置制造、运输及使用过程中，静电放电(ESD，Electro Static Discharge)是一种比较常见的现象。在显示装置的生产及运输过程中，受到静电放电的影响，显示装置的良品率会大大降低。在显示装置的工作过程中，受到静电放电的影响，显示装置中的电子电路可能无法正常工作，导致显示装置的显示效果下降。通常，采用在显示装置中的阵列基板的非显示区(例如边框区域)设置静电放电保护电路的方式，将高压静电释放或均衡，以使显示装置在生产、运输及工作过程中免受静电伤害。
发明内容
一方面，提供一种阵列基板。所述阵列基板包括：衬底基板、至少一条第一信号线、至少一条第二信号线和至少一个静电放电保护器件。所述至少一条第一信号线和至少一条第二信号线设置于所述衬底基板的第一侧。所述至少一个静电放电保护器件设置于所述衬底基板的第一侧，所述至少一个静电放电保护器件中的每个静电放电保护器件包括：第一电极、第二电极和绝缘介质。所述第一电极与所述至少一条第一信号线中的一条第一信号线耦接；所述第二电极与所述至少一条第二信号线中的一条第二信号线耦接；绝缘介质设置于所述第一电极和所述第二电极之间，所述绝缘介质被配置为使得所述第一电极和所述第二电极之间形成静电放电电容。其中，所述静电放电电容被配置为将其所耦接的第一信号线和第二信号线中的一者上的静电荷释放至另一者上。
在一些实施例中，所述阵列基板包括：栅极层、半导体层和栅极绝缘层。栅极层设置于所述衬底基板的第一侧，所述栅极层包括所述静电放电保护器件的第一电极、及驱动晶体管的栅极。半导体层设置于所述栅极层靠近或远离所述衬底基板的一侧，所述半导体层包括所述静电放电保护器件的第二电极、及所述驱动晶体管的有源层。栅极绝缘层设置于所述栅极层与所述半导体层之间，所述栅极绝缘层的位于所述静电放电保护器件的第一电极和第二 电极之间的部分作为所述绝缘介质。
在一些实施例中，所述第二电极的材料为重掺杂的半导体材料，所述重掺杂的半导体材料的掺杂浓度为10 18/cm 3～10 22/cm 3。
在一些实施例中，所述栅极层位于所述半导体层远离所述衬底基板的一侧。所述阵列基板还包括：层间绝缘层和源漏电极层。层间绝缘层设置于所述栅极层远离所述衬底基板的一侧。源漏电极层设置于所述层间绝缘层远离所述衬底基板的一侧，所述源漏电极层包括所述至少一条第一信号线、所述至少一条第二信号线、及所述驱动晶体管的源极和漏极。所述静电放电保护器件的第一电极远离所述衬底基板的一侧设置有贯通所述层间绝缘层的第一过孔，所述静电放电保护器件的第一电极通过所述第一过孔与所述第一信号线耦接。所述静电放电保护器件的第二电极远离所述衬底基板的一侧设置有贯通所述栅极绝缘层和所述层间绝缘层的第二过孔，所述静电放电保护器件的第二电极通过所述第二过孔与所述第二信号线耦接。
在一些实施例中，所述静电放电保护器件的第二电极远离所述衬底基板的一侧设置有一个第二过孔。所述静电放电保护器件还包括第一连接电极，所述第一连接电极的一端与所述第二信号线耦接，所述第一连接电极的另一端通过所述一个第二过孔与所述第二电极靠近所述第二信号线的一端耦接。
在一些实施例中，所述静电放电保护器件的第二电极远离所述衬底基板的一侧设置有两个第二过孔。所述静电放电保护器件还包括第二连接电极，所述第二连接电极的一端与所述第二信号线耦接，所述第二连接电极的另一端通过所述两个第二过孔中的一个第二过孔与所述第二电极远离所述第二信号线的一端耦接，所述第二连接电极中除其两端外的部分通过所述两个第二过孔中的另一个第二过孔与所述第二电极靠近所述第二信号线的一端耦接。所述第二连接电极中除其两端外的部分在所述衬底基板上的正投影与所述第一电极在所述衬底基板上的正投影至少部分交叠。
在一些实施例中，所述栅极层位于所述半导体层靠近所述衬底基板的一侧。所述阵列基板还包括：设置于所述半导体层远离所述衬底基板的一侧的源漏电极层，所述源漏电极层包括所述至少一条第一信号线、所述至少一条第二信号线、及所述驱动晶体管的源极和漏极。所述静电放电保护器件的第一电极远离所述衬底基板的一侧设置有贯通所述栅极绝缘层的第三过孔，所述静电放电保护器件的第一电极通过所述第三过孔与所述第一信号线耦接。所述静电放电保护器件的第二电极与所述第二信号线耦接。
在一些实施例中，所述阵列基板还包括：设置于所述衬底基板的第一侧 的至少一条测试控制线和至少一条测试信号线，所述至少一条测试控制线中的每条测试控制线被配置为，向所述阵列基板传输测试控制信号。所述至少一条测试信号线中的每条测试信号线被配置为，向所述阵列基板传输测试信号。所述至少一条第一信号线包括所述测试控制线，所述至少一条第二信号线包括所述测试信号线。
在一些实施例中，所述阵列基板包括：设置于所述衬底基板的第一侧的栅线、数据线、公共电压信号线、时钟信号线、及电平信号线。所述至少一条第一信号线包括所述栅线、所述数据线、所述公共电压信号线、所述时钟信号线、及所述电平信号线中的至少一者。所述至少一条第二信号线包括所述栅线、所述数据线、所述公共电压信号线、所述时钟信号线、及所述电平信号线中的至少一者。
在一些实施例中，至少两个静电放电保护器件中各静电放电保护器件的第一电极与同一条第一信号线耦接。所述至少两个静电放电保护器件中，一部分静电放电保护器件的第二电极与一条第二信号线耦接，另一部分静电放电保护器件的第二电极与另一条第二信号线耦接。
在一些实施例中，所述至少两个静电放电保护器件分成至少一组，每组包括两个静电放电保护器件；所述两个静电放电保护器件分别为第一静电放电保护器件和第二静电放电保护器件。在所述阵列基板还包括源漏电极层的情况下，所述阵列基板还包括：钝化层和像素电极层。钝化层设置于所述源漏电极层远离所述衬底基板一侧。像素电极层设置于所述钝化层远离所述衬底基板的一侧，所述像素电极层包括至少一个第三连接电极、及多个像素电极。
所述第一静电放电保护器件和所述第二静电放电保护器件的第二电极远离所述衬底基板的一侧均设置有至少贯通所述钝化层的第四过孔。所述至少一个第三连接电极中的一个第三连接电极的两端，分别通过所述第一静电放电保护器件和所述第二静电放电保护器件各自对应的第四过孔，与所述第一静电放电保护器件和所述第二静电放电保护器件的第二电极耦接。
在一些实施例中，所述至少两个静电放电保护器件分成至少一组，每组包括两个静电放电保护器件；所述两个静电放电保护器件分别为第一静电放电保护器件和第二静电放电保护器件。所述第一静电放电保护器件的第一电极和所述第二静电放电保护器件的第一电极通过同一个过孔与同一条第一信号线耦接。
在一些实施例中，所述第一静电放电保护器件和所述第二静电放电保护 器件在所述衬底基板上的正投影对称地位于二者所耦接的第一信号线在所述衬底基板上的正投影的两侧。
在一些实施例中，所述第一电极包括一个第一子电极和并排设置的至少两个第二子电极，所述第一子电极与所述至少两个第二子电极均交叉设置。
在一些实施例中，所述阵列基板具有显示区和非显示区，所述非显示区位于所述显示区的周边，所述至少一个静电放电保护器件设置于所述非显示区。所述阵列基板还包括设置于所述非显示区的至少一个衬垫，所述至少一个衬垫中的每个衬垫与所述至少一条第一信号线耦接，被配置为向所述至少一条第一信号线传输电信号。
另一方面，提供一种静电放电保护电路，所述静电放电保护电路设置于如上任一项所述的阵列基板中，所述静电放电保护电路包括至少一个静电放电保护器件，所述至少一个静电放电保护器件中的每个所述静电放电保护器件的第一端与所述阵列基板中的至少一条第一信号线中的一条第一信号线耦接，第二端与所述阵列基板中的至少一条第二信号线中的一条第二信号线耦接。所述静电放电保护器件被配置为将其所耦接的第一信号线和第二信号线中的一者上的静电荷释放至另一者上。
在一些实施例中，所述静电放电保护器件为电容器。
在一些实施例中，至少两个所述静电放电保护器件的第一端与同一条第一信号线耦接，且这两个所述静电放电保护器件的第二端与同一条第二信号线或者不同的第二信号线耦接。
再一方面，提供一种显示装置，包括如上任一项所述的阵列基板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据相关技术中的静电放电保护电路的结构图；
图2A为根据本公开的一些实施例的阵列基板的结构图；
图2B为根据图2A中截面线AA’的阵列基板的剖视图；
图2C为根据图2A中区域M的放大图；
图3A为根据本公开的一些实施例的阵列基板的另一种结构图；
图3B为根据图3A中截面线BB’的阵列基板的剖视图；
图4A为根据本公开的一些实施例的阵列基板的再一种结构图；
图4B为根据图4A中截面线CC’的阵列基板的剖视图；
图4C为根据图4A中截面线DD’的阵列基板的剖视图；
图5A为根据本公开的一些实施例的阵列基板的又一种结构图；
图5B为根据图5A中截面线EE’的阵列基板的剖视图；
图6A为根据本公开的一些实施例的阵列基板的又一种结构图；
图6B为根据图6A中截面线FF’的阵列基板的剖视图；
图6C为根据图6A中截面线GG’的阵列基板的剖视图；
图7为根据本公开的一些实施例的静电放电保护电路的结构图；
图8为根据本公开的一些实施例的静电放电保护电路的另一种结构图；
图9为根据本公开的一些实施例的静电放电保护电路的再一种结构图；
图10A为根据本公开的一些实施例的阵列基板的又一种结构图；
图10B为根据本公开的一些实施例的阵列基板的又一种结构图；
图11为根据本公开的一些实施例的显示装置的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或 暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和及其衍伸的表达。例如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
相关技术中，为了防止静电放电现象对显示装置的正常工作造成影响，通常会在显示装置中的阵列基板中设置静电放电保护电路，以保护显示装置中的电子电路，使其免受静电干扰。
阵列基板包括栅线、数据线、时钟信号线、公共电压信号线及电平信号线等多条信号线，在显示装置的制造、运输及使用过程中，上述多条信号线可能会积累静电。上述多条信号线中的至少一者作为至少一条第一信号线，上述多条信号线中的另一者作为至少一条第二信号线。阵列基板还包括至少一个静电放电保护电路，每个静电放电保护电路与至少一条第一信号线中的一条第一信号线、以及至少一条第二信号线中的一条第二信号线耦接，以将第一信号线或第二信号线上的静电释放或者均衡。
在一些实施例中，如图1所示，静电放电保护电路包括至少两个薄膜晶体管，示例性地，该至少两个薄膜晶体管分别为第一薄膜晶体管T 1和第二薄膜晶体管T 2，其中，第一薄膜晶体管T 1的第一极和控制极均与一条第一信号线1耦接，第二薄膜晶体管T 2的第一极与控制极均与一条第二信号线2耦接，同时第一薄膜晶体管T 1的第一极与第二薄膜晶体管T 2的第二极耦接，第一薄膜晶体管T 1的第二极与第二薄膜晶体管T 2的第一极耦接。
在发生静电放电时，在第一信号线1上瞬间聚积大量静电荷的情况下，第一薄膜晶体管T 1的控制极的电压升高，达到开启电压，第一薄膜晶体管T 1导通，静电荷通过第一薄膜晶体管T 1的第一极传输至其第二极，进而释放至第二信号线2。同理，在第二信号线2上瞬间聚积大量静电荷的情况下，第二薄膜晶体管T 2的控制极的电压升高，达到开启电压，第二薄膜晶体管T 2导通，静电荷通过第二薄膜晶体管T 2的第一极传输至其第二极，进而释放至第一信号线1。从而实现了将第一信号线1或者第二信号线2上所积累的静电荷进行释放，避免静电荷影响显示装置的正常工作。
然而，在薄膜晶体管的控制极遭遇瞬间大电流的冲击的情况下，控制极 (栅极)和第一极、第二极(源、漏电极)之间的绝缘介质有可能发生击穿，从而引起薄膜晶体管阈值电压的漂移或者栅极和源、漏电极之间的短路。因此，采用上述静电放电保护电路，在静电荷积累过多的情况下，如果薄膜晶体管遭遇大电流或者瞬时大电荷冲击，可能会使得薄膜晶体管的栅极被击穿，导致薄膜晶体管被烧坏，从而使得静电放电保护电路无法正常工作，无法实现静电荷的释放。
本公开的一些实施例提供了一种阵列基板100，如图2A～6C所示，阵列基板100包括：衬底基板3、至少一条第一信号线1、至少一条第二信号线2和至少一个静电放电保护器件4。
所述至少一条第一信号线1和所述至少一条第二信号线2均设置于衬底基板3的第一侧A侧，与第一侧A侧相对的一侧为衬底基板3的第二侧B侧。所述至少一条第一信号线为设置于衬底基板3的第一侧A侧的多条信号线(例如栅线、数据线、电平信号线)中的至少一者，所述至少一条第二信号线为设置于衬底基板3的第一侧A侧的多条信号线(例如栅线、数据线、电平信号线)中的另一者。所述至少一条第一信号线1和所述至少一条第二信号线2上均可能会积累静电。
所述至少一个静电放电保护器件4中的每个静电放电保护器件4包括：第一电极41、第二电极42和绝缘介质43。
其中，第一电极41与所述至少一条第一信号线1中的一条第一信号线1耦接。第二电极42与所述至少一条第二信号线2中的一条第二信号线2耦接。绝缘介质43设置于第一电极41和第二电极42之间，绝缘介质43被配置为使得第一电极41和第二电极42之间形成静电放电电容C；静电放电电容C被配置为将其所耦接的第一信号线1和第二信号线2中的一者上的静电荷释放至另一者上。
本公开的一些实施例提供的阵列基板100，通过设置至少一个静电放电保护器件4，且每个静电放电保护器件4所包括的第一电极41与一条第一信号线1耦接，第二电极42与一条第二信号线2耦接，且第一电极41和第二电极42之间形成静电放电电容C，这样当第一信号线1上瞬间聚积大量静电荷时，通过静电放电保护器件4中所形成的静电放电电容C，将静电荷由第一信号线1释放至第二信号线2上，起到静电分流作用。或者，当第二信号线2上瞬间聚积大量静电荷时，通过静电放电保护器件4中所形成的静电放电电容C，将静电荷由第二信号线2释放至第一信号线1上，起到静电分流作用。这样无论是第一信号线1上瞬间聚积大量静电荷还是第二信号线2上瞬间聚 积大量静电荷，均能通过静电放电保护器件4实现将静电荷进行释放，从而避免静电荷影响电子电路(例如像素驱动电路)的正常工作。
在上述静电分流的过程中，每个静电放电保护器件4的第一电极41和第二电极42之间形成静电放电电容C，利用静电放电电容C的特性实现静电防护：一方面，电容两极间的电压不会产生突变，因此静电放电电容C本身即具有抑制静电的效果，尤其是设置有大容量电容的电路甚至不需要静电放电防护。另一方面，由于静电放电对电子电路的的干扰主要为传导干扰和辐射干扰，而静电本身就是一种宽频信号，利用电容可以为静电荷提供一条更好的释放路径，而不会将所产生的静电耦合到敏感电路，因此，采用静电放电电容C去耦能很好的提升第一信号线1和第二信号线2的去耦能力，增强第一信号线1和第二信号线2的抗干扰能力。
由于本公开所提供的阵列基板中，利用静电放电保护器件4的第一电极41和第二电极42之间形成的静电放电电容C实现静电荷的释放，而没有利用薄膜晶体管等器件，因此也就避免了在相关技术的静电放电保护电路中，在薄膜晶体管遭遇大电流或者瞬时大电荷冲击，可能会使得薄膜晶体管的栅极被击穿，导致薄膜晶体管被烧坏的问题。
在一些实施例中，如图2A和图2B所示，阵列基板100包括：栅极层5、半导体层6和栅极绝缘层7。
栅极层5设置于衬底基板3的第一侧A侧，栅极层5包括静电放电保护器件4的第一电极41、及驱动晶体管的栅极。
半导体层6设置于栅极层5靠近或远离所述衬底基板3的一侧，半导体层6包括静电放电保护器件4的第二电极42、及驱动晶体管的有源层。
栅极绝缘层7设置于栅极层5与半导体层6之间，栅极绝缘层7的位于静电放电保护器件4的第一电极41和第二电极42之间的部分作为绝缘介质43。
在上述实施例中，将静电放电保护器件4的第一电极41和驱动晶体管的栅极同层设置，这样可以在形成驱动晶体管的栅极时，同层形成静电放电保护器件的第一电极41。将静电放电保护器件4的第二电极42和驱动晶体管的有源层同层设置，这样可以在形成驱动晶体管的有源层时，同层形成静电放电保护器件的第二电极42。
这样，在进行阵列基板100的制备时，由于将静电放电保护器件4中的第一电极41和第二电极42分别与驱动晶体管中的栅极和有源层同层设置，因此可以通过一次构图工艺形成驱动晶体管的栅极和静电放电保护器件4的 第一电极41，也可以通过一次构图工艺形成驱动晶体管的有源层和静电放电保护器件4的第二电极42，减少了阵列基板100的制作工艺步骤，降低了阵列基板100的制备时间，提高制备效率。并且由于在形成栅极和第一电极41时可以共用同一块掩模板，在形成有源层和第二电极42时可以共用同一块掩模板，因此掩膜板的数量得以减少，从而节省了成本。
在一些实施例中，第二电极42的材料为重掺杂的半导体材料，该重掺杂的半导体材料的掺杂浓度为10 18/cm 3～10 22/cm 3。
示例性地，第二电极42的材料可以为重掺杂的低温多晶硅(LTPS，Low Temperature Poly-silicon)材料。在一些示例中，第二电极42的形成方式如下：利用沉积工艺在衬底基板3的第一侧A侧形成非晶硅薄膜，通过激光退火(ELA，Excimer Laser Annel)或者固相结晶(SPC，Solid Phase Crystallization)工艺，使得非晶硅薄膜结晶成为多晶硅薄膜。然后采用光刻工艺刻蚀多晶硅薄膜，形成具有第二电极42的图案的多个第一多晶硅结构和具有驱动晶体管的有源层的图案的多个第二多晶硅结构。对所述多个第一多晶硅结构进行高浓度离子注入，该离子作为提供载流子的施主或者受主，嵌入多晶硅的晶体结构中，该离子的浓度可以按照实际需要进行选择，例如可以为10 18/cm 3、10 19/cm 3、10 20/cm 3、10 21/cm 3、10 22/cm 3等，从而将多个第一多晶硅结构转化为多个低电阻的重掺杂多晶硅结构，所述多个低电阻的重掺杂多晶硅结构作为第二电极42。
将第二电极42的材料设置为重掺杂的半导体材料，由于重掺杂的半导体材料的电阻远远小于绝缘材料的电阻，且远远大于金属材料的电阻，因此第二电极42的电阻远远小于绝缘介质43的电阻，并且远远大于第一信号线1和第二信号线2(信号线一般为金属材料制成)的电阻，电阻值介于绝缘材料和金属材料之间的重掺杂的半导体材料能够在出现高电压大电流时导通。这样，在第一信号线1或者第二信号线2上没有瞬间聚积大量静电荷或者聚积大量静电荷较少时，第二电极42不会导通，静电放电保护器件4不工作。在第一信号线1或者第二信号线2上瞬间聚积大量静电荷时，施加在第二电极42上的电压较高，第二电极42的电阻值降低，导电性增强，从而第一电极41和第二电极42之间形成静电放电电容C，将第一信号线1上的静电荷释放到第二放电线，或者将第二信号线2上的静电荷释放到第一信号线1上，起到静电分流作用。
本公开的一些实施例所提供的阵列基板100中，根据阵列基板100所包括的各功能膜层的设置方式，静电放电保护器件具有多种不同的结构，本公 开对此并不设限，只要能使静电放电保护器件起到上述静电保护的作用即可。以下对阵列基板100的各功能膜层的设置方式以及对应的静电放电保护器件4的结构进行示例性的介绍。
在栅极层5位于半导体层6远离衬底基板3的一侧的情况下，在一些实施例中，如图2A～图4C所示，阵列基板100还包括：层间绝缘层8和源漏电极层9。
层间绝缘层8设置于栅极层5远离所述衬底基板3的一侧。源漏电极层9设置于层间绝缘层8远离衬底基板3的一侧，源漏电极层9包括所述至少一条第一信号线1、所述至少一条第二信号线2、及驱动晶体管的源极和漏极。
静电放电保护器件4的第一电极41远离衬底基板3的一侧设置有贯通所述层间绝缘层8的第一过孔a，静电放电保护器件4的第一电极41通过第一过孔a与第一信号线1耦接。静电放电保护器件4的第二电极42远离衬底基板3的一侧设置有贯通栅极绝缘层7和层间绝缘层8的第二过孔b，静电放电保护器件4的第二电极42通过第二过孔b与第二信号线2耦接。
上述实施例中，将所述至少一条第一信号线1、所述至少一条第二信号线2和驱动晶体管的源极和漏极同层设置，这样可以在形成驱动晶体管的源极和漏极时，同层形成所述至少一条第一信号线1和所述至少一条第二信号线2，从而减少了阵列基板100的制作工艺步骤，降低了阵列基板100的制备时间，提高制备效率。
在一些示例中，如图2A和图2B所示，每个静电放电保护器件4的第二电极42远离衬底基板3的一侧设置有一个第二过孔b。静电放电保护器件4还包括第一连接电极44，第一连接电极44的一端与第二信号线2耦接，第一连接电极44的另一端通过一个第二过孔b与第二电极42靠近该第二信号线2的一端耦接。
在上述示例中，第一连接电极44起到连接第二信号线2与第二电极42的作用，在静电放电保护器件4工作时，可以将第一信号线1上的静电荷经第一电极41、第二电极42以及第一连接电极44释放至第二信号线2上，或者可以将第二信号线2上的静电荷经第一连接电极44、第二电极42以及第一电极41释放至第二信号线2上，起到静电分流作用。
在另一些示例中，如图3A和图3B所示，每个静电放电电容C的第二电极42远离衬底基板3的一侧设置有两个第二过孔b。静电放电保护器件4还包括第二连接电极45，第二连接电极45的一端与第二信号线2耦接，第二连接电极45的另一端通过两个第二过孔b中的一个第二过孔b与第二电极42 远离第二信号线2的一端耦接，第二连接电极45中除其两端外的部分通过两个第二过孔b中的另一个第二过孔b与第二电极42靠近第二信号线2的一端耦接。
第二连接电极45中除其两端外的部分在所述衬底基板3上的正投影与第一电极41在衬底基板3上的正投影至少部分交叠。
在上述示例中，第二连接电极45起到连接第二信号线2与第二电极42的作用，并且，由于第二连接电极45中除其两端外的部分在衬底基板3上的正投影与第一电极42在衬底基板3上的正投影至少部分交叠，因此第二连接电极45中除其两端外的部分与第一电极41之间能够形成电容，该电容可以作为静电放电电容，相当于增加了静电放电保护器件4中所形成的静电放电电容，在第一信号线1上瞬间聚积大量静电荷的情况下，通过第一电极41和第二电极42之间的静电放电电容C和第二连接电极45中除其两端外的部分与第一电极41之间的静电放电电容C，静电荷由第一电极41同时向第二电极42以及第二连接电极45传输，从而使得静电荷更快的释放至第二信号线2。同样，在第二信号线2上瞬间聚积大量静电荷的情况下，静电荷能够更快地释放至第一信号线1，从而进一步提升了静电放电保护器件4静电防护的效果。
在栅极层5位于半导体层6靠近衬底基板3的一侧的情况下，在一些实施例中，如图5A～图6C所示，阵列基板100还包括：源漏电极层9。
源漏电极层9设置于半导体层6远离所述衬底基板3的一侧，源漏电极层9包括所述至少一条第一信号线1、所述至少一条第二信号线2、及驱动晶体管的源极和漏极。
电放电保护器件的第一电极41远离衬底基板3的一侧设置有贯通栅极绝缘层7的第三过孔c，静电放电保护器件4的第一电极41通过第三过孔c与第一信号线1耦接。静电放电保护器件4的第二电极42与第二信号线2耦接。
上述实施例中，将所述至少一条第一信号线1、所述至少一条第二信号线2和驱动晶体管的源极和漏极同层设置，这样可以在形成驱动晶体管的源极和漏极时，同层形成所述至少一条第一信号线1和所述至少一条第二信号线2，从而减少了阵列基板100的制作工艺步骤，降低了阵列基板100的制备时间，提高制备效率。
由于源漏电极层9与半导体层6相接触，因此第二电极42与第二信号线2可以直接耦接，而不需要通过过孔实现耦接，这样能够简化阵列基板100的制备工艺。
在一些实施例中，如图10A和图10B所示，该阵列基板100具有显示区 AA和非显示区BB，所述非显示区BB设置于所述显示区AA的周边。示例性地，非显示区BB围绕显示区AA，或者，在显示区AA为矩形的情况下，非显示区BB设置于显示区AA的一侧、两侧(相对的两侧，或者相邻的两侧)或者三侧。
在一些实施例中，阵列基板在出厂之前，需要对阵列基板中的信号线进行测试，例如，对阵列基板中的栅线或者数据线进行测试。以下以对阵列基板的数据线进行测试为例进行介绍。对于数据线的测试，需要在阵列基板中布置至少一个测试电路、至少一条测试控制线和至少一条测试信号线。
如图10A所示，所述至少一个测试电路12设置于衬底基板的第一侧，所述至少一个测试电路12中的每个测试电路12分别与阵列基板所包括的每条数据线耦接。示例性地，每个测试电路12包括至少一个薄膜晶体管，所述至少一个薄膜晶体管中每个薄膜晶体管的第二极(漏极)与一条数据线耦接。
所述至少一条测试控制线1’设置于衬底基板的第一侧，所述至少一条测试控制线1’中的每条测试控制线1’分别与所述至少一个测试电路12中的每个测试电路12耦接。测试控制线1’被配置为，向阵列基板100传输测试控制信号，即向阵列基板100中的所述至少一个测试电路12传输测试控制信号。示例性地，在每个测试电路12包括至少一个薄膜晶体管的情况下，每条测试控制线1’分别与每个测试电路12中的一个薄膜晶体管的控制极(栅极)耦接，以使测试电路12在测试控制线1’所传输的测试控制信号的作用下打开或关闭。在一些示例中，测试控制信号通过阵列基板100中的衬垫传输至所述至少一条测试控制线，衬垫与控制芯片耦接，控制芯片提供测试控制信号至衬垫。
所述至少一条测试信号线2’设置于衬底基板的第一侧，所述至少一条测试信号线2’中的每条测试信号线2’分别与所述至少一个测试电路12中的每个测试电路12耦接。测试信号线2’被配置为，向阵列基板100传输测试信号，即向阵列基板100中的所述至少一个测试电路12传输测试信号。示例性地，在每个测试电路12包括至少一个薄膜晶体管的情况下，每条测试信号线2’分别与每个测试电路12中的一个薄膜晶体管的第一极(源极)耦接，以在测试电路12打开时，将测试信号传输至数据线。在一些示例中，测试信号通过阵列基板100中的衬垫传输至所述至少一条测试信号线，衬垫与控制芯片耦接，控制芯片提供测试信号至衬垫。
在一些示例中，所述至少一条测试信号线2’包括两条测试信号线2’，其中一条测试信号线2’通过测试电路12分别与奇数条(例如1、3、5、7) 数据线耦接，另一条测试信号线2’通过测试电路12分别与偶数条(例如2、4、6、8)数据线耦接。
上述阵列基板100的测试过程大致为：在所述至少一条测试控制线1’所传输的测试控制信号的控制下，所述至少一个测试电路打开，将所述至少一条测试信号线2’所传输的测试信号传输至相应的数据线，以检测相应的数据线，例如检测相应的数据线是否开路。
在一些示例中，所述至少一个测试电路12、所述至少一条测试控制线1’和所述至少一条测试信号线2’设置于非显示区BB。
在上述阵列基板100的制备过程中，或者在对阵列基板100进行测试的过程中，所述至少一条测试控制线1’和所述至少一条测试信号线2’上有可能会积累静电，导致对阵列基板100的测试工作受到影响。
在一些实施例中，如图10A所示，所述至少一条第一信号线1包括测试控制线1’，所述至少一条第二信号线2包括测试信号线2’。所述至少一个静电放电保护器件4设置于非显示区BB，每个静电放电保护器件4与所述至少一条第一信号线1中的一条第一信号线1耦接，且与所述至少一条第二信号线2中的一条第二信号线2耦接。
这样，在上述阵列基板100的测试过程中，在测试控制线1’上瞬间聚积大量静电荷的情况下，通过静电放电保护器件4可以将静电荷释放至测试信号线2’上，或者在测试信号线2’上瞬间聚积大量静电荷的情况下，通过静电放电保护器件4可以将静电荷释放至测试控制线1’上，从而避免了所产生的静电耦合到诸如测试电路12等电子电路中，保证了阵列基板100的测试工作的正常进行。
在另一些实施例中，阵列基板100还包括：设置于衬底基板3的第一侧A侧的栅线、数据线、公共电压信号线、时钟信号线、及电平信号线。示例性的，电平信号线包括高电平(Vgh)信号线、低电平(Vgl)信号线、第一电源(Vdd)信号线、第二电源(Vss)信号线等。
显示区AA多个像素，多个像素中的每个像素对应一个像素驱动电路，在数据线所传输的数据信号和栅线所传输的栅极扫描信号的作用下，像素驱动电路进行工作，使得显示区AA实现显示。然而，上述栅线、数据线、公共电压信号线、时钟信号线、及电平信号线有可能会积累静电，从而对阵列基板中的电子电路(例如像素驱动电路)的正常工作造成影响。
在一些实施例中，所述至少一条第一信号线1包括所述栅线、所述数据线、所述公共电压信号线、所述时钟信号线、及所述电平信号线中的至少一 者。所述至少一条第二信号线2包括所述栅线、所述数据线、所述公共电压信号线、所述时钟信号线、及所述电平信号线中的至少一者。示例性地，如图10B所示，所述至少一条第一信号线1包括至少一条数据线和至少一条栅线，所述至少一条第二信号线2为公共电压信号线。所述至少一个静电放电保护器件4位于非显示区BB，每个静电放电保护器件4与一条第一信号线1耦接，以及与一条第二信号线2耦接。
本公开实施例所提供的阵列基板100中，所述至少一条第一信号线1和所述至少一条第二信号线2分别为阵列基板100所包括的多种信号线中的至少一种。这样在阵列基板100进行显示的过程中，通过静电放电保护器件4，可以将静电放电保护器件4所耦接的第一信号线1和第二信号线2中的一者上的静电荷释放至另一者上，例如，可以将栅线或者数据线上所积累的静电荷释放至公共电压信号线上，从而实现静电分流，使得阵列基板100的显示工作免受静电的干扰。
在一些实施例中，如图10A和10B所示，阵列基板100还包括设置于非显示区BB的至少一个衬垫，所述至少一个衬垫中的每个衬垫与至少一条第一信号线1耦接，被配置为向所述至少一条第一信号线1传输电信号。示例性地，在所述至少一条第一信号线1包括测试控制线1’的情况下，衬垫被配置为向测试控制线1’传输测试控制信号；在所述至少一条第一信号线1包括栅线的情况下，衬垫被配置为向栅线传输栅极扫描信号。
在一些实施例中，至少两个静电放电保护器件4中各静电放电保护器件4的第一电极41与同一条第一信号线1耦接。所述至少两个静电放电保护器件4中，一部分静电放电保护器件4的第二电极42与一条第二信号线2耦接，另一部分静电放电保护器件4的第二电极42与另一条第二信号线2耦接。
如图2A～图6C所示，每两个静电放电保护器件4中各静电放电保护器件4的第一电极41与同一条第一信号线1耦接。与同一条第一信号线1耦接的两个静电放电保护器件4中，其中一个静电放电保护器件4与一条第二信号线2耦接，另一个静电放电保护器件4与另一条第二信号线2耦接。
通过这样设置，在第一信号线1上瞬间聚积大量静电荷的情况下，静电荷可以通过至少两个静电放电保护器件4释放至不同的第二信号线2，第一信号线1上静电荷释放的路径得以增加，使得静电荷的释放更加迅速，效率更高，提升了静电放电防护效果。
作为一种可能的设计，所述至少两个静电放电保护器件4分成至少一组，每组包括两个静电放电保护器件4。所述两个静电放电保护器件4分别为第一 静电放电保护器件4和第二静电放电保护器件4。
在阵列基板100还包括源漏电极层9的情况下，如图4A～图4C，及图6A～图6C所示，阵列基板100还包括：钝化层10和像素电极层11。
钝化层10设置于源漏电极层9远离所述衬底基板3一侧。像素电极层11设置于钝化层10远离衬底基板3的一侧，像素电极层11包括至少一个第三连接电极11a、及多个像素电极。
所述第一静电放电保护器件4和所述第二静电放电保护器件4的第二电极42远离所述衬底基板3的一侧均设置有至少贯通钝化层10的第四过孔d。所述至少一个第三连接电极11a中的一个第三连接电极11a的两端，分别通过所述第一静电放电保护器件4和所述第二静电放电保护器件4各自对应的第四过孔d，与第一静电放电保护器件4和第二静电放电保护器件4的第二电极42耦接。
如图4A～图4C所示，在栅极层5位于半导体层6远离衬底基板3的一侧的情况下：
所述至少两个静电放电保护器件4分为四组，每组包括两个静电放电保护器件4。示例性地，所述两个静电放电保护器件4分别为第一静电放电保护器件4-1和第二静电放电保护器件4-2。
所述第一静电放电保护器件4-1的第二电极42和第二静电放电保护器件4-2的第二电极42远离所述衬底基板3的一侧均设置有贯通栅极绝缘层7、层间绝缘层8和钝化层10的第四过孔d。所述至少一个第三连接电极11a中的一个第三连接电极11a的两端，分别通过所述第一静电放电保护器件4-1和所述第二静电放电保护器件4-2各自对应的第四过孔d，与第一静电放电保护器件4-1的第二电极42和第二静电放电保护器件4-2的第二电极42耦接。
如图6A～图6C所示，在栅极层5位于半导体层6靠近衬底基板3的一侧的情况下：
所述至少两个静电放电保护器件4分为四组，每组包括两个静电放电保护器件4。示例性地，所述两个静电放电保护器件4分别为第一静电放电保护器件4-1和第二静电放电保护器件4-2。
所述第一静电放电保护器件4和所述第二静电放电保护器件4的第二电极42远离所述衬底基板3的一侧均设置有贯通钝化层10的第四过孔d。所述至少一个第三连接电极11a中的一个第三连接电极11a的两端，分别通过所述第一静电放电保护器件4-1和所述第二静电放电保护器件4-2各自对应的第四过孔d，与第一静电放电保护器件4-1的第二电极42和第二静电放电保护器 件4-2的第二电极42耦接。
在上述实施例中，通过第三连接电极11a，将第一静电放电保护器件4-1的第二电极42和第二静电放电保护器件4-2的第二电极42耦接，这样在第一信号线1上瞬间聚积大量静电荷的情况下，静电荷可以通过第一静电放电保护器件4-1和第二静电放电保护器件4-2释放至该两个静电放电保护器件4各自对应的第二信号线2，第一信号线1上静电荷释放的路径得以增加，使得静电荷的释放更加迅速，效率更高，提升了静电放电防护效果。
同时，在第一信号线1上瞬间聚积大量静电荷的情况下，在其中一个静电放电保护器件4(例如第一静电放电保护器件4-1)的第二电极42与第二信号线2的耦接处发生损坏的情况下，静电荷无法分流到该静电放电保护器件所耦接的第二信号线2，这时可以通过第三连接电极11a将静电荷分流到另一个静电放电保护器件(第二静电放电保护器件4-2)，进而释放静电，从而提高静电放电保护器件的稳定性。在第二信号线2上瞬间聚积大量静电荷的情况下，在其中一个静电放电保护器件4(例如第一静电放电保护器件4-1)的第一电极41与第一信号线1的连接处发生损坏的情况下，静电荷无法分流到该静电放电保护器件4所耦接的第一信号线1，这时可以通过第三连接电极11a将静电荷分流到另一个静电放电保护器件4(第二静电放电保护器件4-2)，由该静电放电保护器件4将静电荷释放至第一信号线1，实现静电分流，从而提高静电放电保护器件4的稳定性。
在一些实施例中，所述至少两个静电放电保护器件4分成至少一组，每组包括两个静电放电保护器件4；所述两个静电放电保护器件4分别为第一静电放电保护器件4和第二静电放电保护器件4。第一静电放电保护器件4的第一电极41和第二静电放电保护器件4的第一电极41通过同一个过孔与同一条第一信号线1耦接。
示例性地，如图4A所示，所述至少两个静电放电保护器件4四组，每组包括两个静电放电保护器件4。所述两个静电放电保护器件4分别为第一静电放电保护器件4-1和第二静电放电保护器件4-2。第一静电放电保护器件4-1的第一电极41和第二静电放电保护器件4-2的第一电极41通过处于其中间的同一个第一过孔a与同一条第一信号线1耦接。
这样，每组中的两个静电放电保护器件4均通过同一个第一过孔a与同一条第一信号线1耦接，这样可以减少所设置的第一过孔a的数量，从而节省了阵列基板100的制备步骤，提高了制备效率。
在一些示例中，如图4A～图4B所示，在上述所分成的至少一组静电放电 保护器件4中，每组静电放电保护器件4中第一静电放电保护器件4-1和第二静电放电保护器件4-2在衬底基板3上的正投影对称地位于二者所耦接的第一信号线1在所述衬底基板3上的正投影的两侧。
在一些实施例中，如图2C所示，本公开的一些实施例所提供的阵列基板100中，静电放电保护器件4所包括的第一电极41包括一个第一子电极41a和并排设置的至少两个第二子电极41b，第一子电极41a与所述至少两个第二子电极41b均交叉设置。第一子电极41a的一端通过第一过孔a与第一信号线1耦接。
请参见图2A和图2B，每个静电放电保护器件4包括第一电极41、第二电极42、设置于第一电极41和第二电极42之间的绝缘介43，及第一连接电极44，在第二电极42的材料为半导体材料(例如为重掺杂的半导体材料)的情况下，每个静电放电保护器件4可以视作一个薄膜晶体管，其中第二电极42可以视作有源层，第一电极41可以视作栅极，第一连接电极44可以视作源极或者漏极中的一者，源极或者漏极中的另一者悬空，通过静电放电保护器件4中所形成的静电放电电容C(第一电极41和第二电极42之间形成静电放电电容)实现静电荷的释放。
请参见图3A和图3B，每个静电放电保护器件4包括第一电极41、第二电极42、设置于第一电极41和第二电极42之间的绝缘介43，及第二连接电极45，在第二电极42的材料为半导体材料(例如为重掺杂的半导体材料)的情况下，每个静电放电保护器件4可以视作一个薄膜晶体管，其中第二电极42可以视作有源层，第一电极41可以视作栅极，第二连接电极45中处于两个第二过孔b中的一个第二过孔b中的部分，以及位于该第二过孔b的上方的部分可以视作源极或者漏极中的一者，第二连接电极45中处于两个第二过孔b中的另一个第二过孔b中的部分，以及位于该第二过孔b的上方的部分可以视作源极或者漏极中的另一者，且源极和漏极连通，通过薄膜晶体管中所形成的静电放电电容C(第一电极41和第二电极42之间形成静电放电电容)实现静电荷的释放。
请参见图4A和图4B，每个静电放电保护器件4包括第一电极41、第二电极42、设置于第一电极41和第二电极42之间的绝缘介43，及第一连接电极44，在第二电极42的材料为半导体材料(例如为重掺杂的半导体材料)的情况下，每个静电放电保护器件4可以视作一个薄膜晶体管，其中第二电极42可以视作有源层，第一电极41可以视作栅极，第一连接电极44可以视作源极或者漏极中的一者，第三连接电极11a中处于第四过孔d中及其上方的 部分可以视作源极或者漏极中的另一者，通过薄膜晶体管中所形成的静电放电电容C(第一电极41和第二电极42之间形成静电放电电容)实现静电荷的释放。
在上述静电放电保护器件4中，第一电极41包括一个第一子电极41a和并排设置的至少两个第二子电极41b，相当于使得每个静电放电保护器件4所视作的薄膜晶体管形成双栅薄膜晶体管，这样可以降低静电放电保护器件4(视作薄膜晶体管)的漏电流，使静电放电保护器件的性能更稳定。
本公开的一些实施例还提供一种静电放电保护电路200，设置于如上所述的阵列基板100中。
在一些实施例中，如图10A和图10B所示，阵列基板100包括显示区AA和非显示区BB，上述静电放电保护电路200位于非显示区BB。
如图7～图9所示，静电放电保护电路200包括至少一个静电放电保护器件4，所述至少一个静电放电保护器件4中的每个静电放电保护器件4的第一端与阵列基板100中的至少一条第一信号线1中的一条第一信号线1耦接，第二端与阵列基板100中的至少一条第二信号线2中的一条第二信号线2耦接。静电放电保护器件4被配置为将其所耦接的第一信号线1和第二信号线2中的一者上的静电荷释放至另一者上。
在一些示例中，如图10A所示，在阵列基板100包括至少一条测试控制线和至少一条测试信号线的情况下，所述至少一条第一信号线1包括所述测试控制线，所述至少一条第二信号线2包括所述测试信号线。
在另一些示例中，如图10B所示，阵列基板100包括栅线、数据线、公共电压信号线、时钟信号线、及电平信号线。所述至少一条第一信号线1包括所栅线、所数据线、所公共电压信号线、时钟信号线、及所电平信号线中的至少一者。所述至少一条第二信号线2包括栅线、数据线、公共电压信号线、时钟信号线、及所电平信号线中的至少一者。
上述静电放电保护电路200，在第一信号线1和第二信号线2上均没有聚集静电荷时，静电放电保护电路200不工作；当有静电放电发生时，第一信号线1瞬间聚集的大量静电荷会通过静电放电保护电路200中的静电放电保护器件4迅速向第二信号线2释放，或者第二信号线2瞬间聚集的大量静电荷会通过静电放电保护电路中的静电放电保护器件4迅速向第一信号线1释放，从而避免静电荷影响诸如像素驱动电路等其他电子电路的正常工作。
在一些实施例中，静电放电保护器件4为电容器。
由于电容器的两极间的电压不会产生突变，因此电容器本身即具有抑制 静电的效果。并且，电容器具有去耦作用，采用电容器去耦能很好的提升第一信号线1和第二信号线2的去耦能力，增强第一信号线1和第二信号线2的抗干扰能力，避免静电对电子电路的正常工作的影响。
在一些实施例中，如图8和图9所示，至少两个静电放电保护器件4的第一端与同一条第一信号线1耦接，且这两个静电放电保护器件4的第二端与同一条第二信号线2或者不同的第二信号线2耦接。
在上述实施例中，在与所述至少两个静电放电保护器件4的第一端耦接的第一信号线1上瞬间聚集大量静电荷的情况下，静电荷可以通过至少两个静电放电保护器件4释放至不同的第二信号线2，或者释放至同一条第二信号线2，第一信号线1上静电荷释放的路径得以增加，使得静电荷的释放更加迅速，效率更高，提升了静电放电防护效果。
在一些实施例中，上述静电放电保护电路200还有其他的设置方式，本公开对此并不设限，只要能起到静电放电保护的作用即可。
如图11所示，本公开的实施例还提供一种显示装置300，包括如上所述的阵列基板100。
本公开实施例所提供的显示装置300可以是液晶显示装置(Liquid Crystal Display，简称LCD)；也可以是有机电致发光显示装置(Organic Light-Emitting Display，简称OLED)；或者是量子点电致发光显示面板(Quantum Dot Light-Emitting Display，简称QLED)。
在显示装置300为液晶显示装置的情况下，显示装置300除包括阵列基板100外，还包括对向基板以及设置在对向基板、阵列基板100之间的液晶层。
在显示面板300为有机电致发光显示面板的情况下，显示装置300还包括用于封装阵列基板100的封装层。阵列基板100还包括像素驱动电路和发光器件，发光器件包括阳极、发光层和阴极。封装层可以是薄膜封装层，也可以是基板封装层。
另外，本公开的一些实施例所提供的显示装置可以为电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例所提供的显示装置300所能实现的有益效果，与上述所提供的阵列基板100所能达到的有益效果相同，在此不做赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易 想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种阵列基板，包括：
    衬底基板，
    设置于所述衬底基板的第一侧的至少一条第一信号线和至少一条第二信号线；和
    设置于所述衬底基板的第一侧的至少一个静电放电保护器件，所述至少一个静电放电保护器件中的每个静电放电保护器件包括：
    第一电极，所述第一电极与所述至少一条第一信号线中的一条第一信号线耦接；
    第二电极，所述第二电极与所述至少一条第二信号线中的一条第二信号线耦接；和
    设置于所述第一电极和所述第二电极之间的绝缘介质，所述绝缘介质被配置为使得所述第一电极和所述第二电极之间形成静电放电电容；其中，所述静电放电电容被配置为将其所耦接的第一信号线和第二信号线中的一者上的静电荷释放至另一者上。
  2. 根据权利要求1所述的阵列基板，所述阵列基板包括：
    设置于所述衬底基板的第一侧的栅极层，所述栅极层包括所述静电放电保护器件的第一电极、及驱动晶体管的栅极；
    设置于所述栅极层靠近或远离所述衬底基板的一侧的半导体层，所述半导体层包括所述静电放电保护器件的第二电极、及所述驱动晶体管的有源层；
    设置于所述栅极层与所述半导体层之间的栅极绝缘层，所述栅极绝缘层的位于所述静电放电保护器件的第一电极和第二电极之间的部分作为所述绝缘介质。
  3. 根据权利要求2所述的阵列基板，其中，所述第二电极的材料为重掺杂的半导体材料，所述重掺杂的半导体材料的掺杂浓度为10 18/cm 3～10 22/cm 3。
  4. 根据权利要求2或3所述的阵列基板，其中，所述栅极层位于所述半导体层远离所述衬底基板的一侧；
    所述阵列基板还包括：
    设置于所述栅极层远离所述衬底基板的一侧的层间绝缘层；
    设置于所述层间绝缘层远离所述衬底基板的一侧的源漏电极层，所述源漏电极层包括所述至少一条第一信号线、所述至少一条第二信号线、及所述驱动晶体管的源极和漏极；
    所述静电放电保护器件的第一电极远离所述衬底基板的一侧设置有贯通所述层间绝缘层的第一过孔，所述静电放电保护器件的第一电极通过所述第 一过孔与所述第一信号线耦接；
    所述静电放电保护器件的第二电极远离所述衬底基板的一侧设置有贯通所述栅极绝缘层和所述层间绝缘层的第二过孔，所述静电放电保护器件的第二电极通过所述第二过孔与所述第二信号线耦接。
  5. 根据权利要求4所述的阵列基板，其中，所述静电放电保护器件的第二电极远离所述衬底基板的一侧设置有一个第二过孔；
    所述静电放电保护器件还包括：
    第一连接电极，所述第一连接电极的一端与所述第二信号线耦接，所述第一连接电极的另一端通过所述一个第二过孔与所述第二电极靠近所述第二信号线的一端耦接。
  6. 根据权利要求4所述的阵列基板，其中，所述静电放电保护器件的第二电极远离所述衬底基板的一侧设置有两个第二过孔；
    所述静电放电保护器件还包括：
    第二连接电极，所述第二连接电极的一端与所述第二信号线耦接，所述第二连接电极的另一端通过所述两个第二过孔中的一个第二过孔与所述第二电极远离所述第二信号线的一端耦接，所述第二连接电极中除其两端外的部分通过所述两个第二过孔中的另一个第二过孔与所述第二电极靠近所述第二信号线的一端耦接；
    所述第二连接电极中除其两端外的部分在所述衬底基板上的正投影与所述第一电极在所述衬底基板上的正投影至少部分交叠。
  7. 根据权利要求2或3所述的阵列基板，其中，所述栅极层位于所述半导体层靠近所述衬底基板的一侧；
    所述阵列基板还包括：
    设置于所述半导体层远离所述衬底基板的一侧的源漏电极层，所述源漏电极层包括所述至少一条第一信号线、所述至少一条第二信号线、及所述驱动晶体管的源极和漏极；
    所述静电放电保护器件的第一电极远离所述衬底基板的一侧设置有贯通所述栅极绝缘层的第三过孔，所述静电放电保护器件的第一电极通过所述第三过孔与所述第一信号线耦接；
    所述静电放电保护器件的第二电极与所述第二信号线耦接。
  8. 根据权利要求1～7中任一项所述的阵列基板，所述阵列基板还包括：
    设置于所述衬底基板的第一侧的至少一条测试控制线，所述至少一条测试控制线中的每条测试控制线被配置为，向所述阵列基板传输测试控制信号；
    设置于所述衬底基板的第一侧的至少一条测试信号线，所述至少一条测试信号线中的每条测试信号线被配置为，向所述阵列基板传输测试信号；
    所述至少一条第一信号线包括所述测试控制线，所述至少一条第二信号线包括所述测试信号线。
  9. 根据权利要求1～8中任一项所述的阵列基板，所述阵列基板包括：
    设置于所述衬底基板的第一侧的栅线、数据线、公共电压信号线、时钟信号线、及电平信号线；
    所述至少一条第一信号线包括所述栅线、所述数据线、所述公共电压信号线、所述时钟信号线、及所述电平信号线中的至少一者；
    所述至少一条第二信号线包括所述栅线、所述数据线、所述公共电压信号线、所述时钟信号线、及所述电平信号线中的至少一者。
  10. 根据权利要求2～9中任一项所述的阵列基板，其中，至少两个静电放电保护器件中各静电放电保护器件的第一电极与同一条第一信号线耦接；
    所述至少两个静电放电保护器件中，一部分静电放电保护器件的第二电极与一条第二信号线耦接，另一部分静电放电保护器件的第二电极与另一条第二信号线耦接。
  11. 根据权利要求10所述的阵列基板，其中，所述至少两个静电放电保护器件分成至少一组，每组包括两个静电放电保护器件；所述两个静电放电保护器件分别为第一静电放电保护器件和第二静电放电保护器件；
    在所述阵列基板还包括源漏电极层的情况下，所述阵列基板还包括：
    设置于所述源漏电极层远离所述衬底基板一侧的钝化层；和
    设置于所述钝化层远离所述衬底基板一侧的像素电极层，所述像素电极层包括至少一个第三连接电极、及多个像素电极；
    所述第一静电放电保护器件和所述第二静电放电保护器件的第二电极远离所述衬底基板的一侧均设置有至少贯通所述钝化层的第四过孔；
    所述至少一个第三连接电极中的一个第三连接电极的两端，分别通过所述第一静电放电保护器件和所述第二静电放电保护器件各自对应的第四过孔，与所述第一静电放电保护器件和所述第二静电放电保护器件的第二电极耦接。
  12. 根据权利要求11所述的阵列基板，其中，所述至少两个静电放电保护器件分成至少一组，每组包括两个静电放电保护器件；所述两个静电放电保护器件分别为第一静电放电保护器件和第二静电放电保护器件；
    所述第一静电放电保护器件的第一电极和所述第二静电放电保护器件的 第一电极通过同一个过孔与同一条第一信号线耦接。
  13. 根据权利要求11或12所述的阵列基板，其中，所述第一静电放电保护器件和所述第二静电放电保护器件在所述衬底基板上的正投影对称地位于二者所耦接的第一信号线在所述衬底基板上的正投影的两侧。
  14. 根据权利要求1～13中任一项所述的阵列基板，其中，所述第一电极包括一个第一子电极和并排设置的至少两个第二子电极，所述第一子电极与所述至少两个第二子电极均交叉设置。
  15. 根据权利要求1～14中任一项所述的阵列基板，所述阵列基板具有显示区和非显示区，所述非显示区位于所述显示区的周边，所述至少一个静电放电保护器件设置于所述非显示区；
    所述阵列基板还包括设置于所述非显示区的至少一个衬垫，所述至少一个衬垫中的每个衬垫与所述至少一条第一信号线耦接，被配置为向所述至少一条第一信号线传输电信号。
  16. 一种静电放电保护电路，所述静电放电保护电路设置于如权利要求1～15中任一项所述的阵列基板中；
    所述静电放电保护电路包括至少一个静电放电保护器件，所述至少一个静电放电保护器件中的每个所述静电放电保护器件的第一端与所述阵列基板中的至少一条第一信号线中的一条第一信号线耦接，第二端与所述阵列基板中的至少一条第二信号线中的一条第二信号线耦接；
    所述静电放电保护器件被配置为将其所耦接的第一信号线和第二信号线中的一者上的静电荷释放至另一者上。
  17. 根据权利要求16所述的静电放电保护电路，其中，所述静电放电保护器件为电容器。
  18. 根据权利要求16或17所述的静电放电保护电路，至少两个所述静电放电保护器件的第一端与同一条第一信号线耦接，且这两个所述静电放电保护器件的第二端与同一条第二信号线或者不同的第二信号线耦接。
  19. 一种显示装置，包括如权利要求1～15中任一项所述的阵列基板。
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US20200350309A1 (en) 2020-11-05
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