CN103972228A - 静电防护电路以及具有该静电防护电路的显示装置 - Google Patents
静电防护电路以及具有该静电防护电路的显示装置 Download PDFInfo
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Abstract
本发明公开了一种显示装置的静电防护电路,所述静电防护电路包括:驱动电路,被构造为驱动显示图像的显示单元;至少一条时钟信号线,被构造为向驱动电路传输时钟信号;至少一个晶体管,电结合到时钟信号线;以及至少一个电容器,包括结合到晶体管的源电极并结合到晶体管的漏电极的第一电极和被构造为维持电压的第二电极。
Description
技术领域
本发明的实施例涉及一种静电防护电路以及一种包括该静电防护电路的显示装置。
背景技术
通常,与阴极射线管显示器相比,诸如有机发光二极管(OLED)显示器的平板显示装置具有若干优势,例如尺寸小、厚度薄且功耗低,并且能够实现高分辨率且全彩色的图像。这些优势已经使得平板显示装置被广泛地应用在各种领域中。目前,OLED显示装置已经用于计算机、膝上型电脑、手机、TV、音频/视频装置等等。
根据施加给以矩阵形式排列的多个像素中的每个像素的图像数据信号,这样的OLED显示器通过控制传输到有机发光元件的驱动电流的量来显示图像。
通常,将玻璃基底用作显示装置的基底,但是玻璃基底也作为绝缘体,所以在面板制造工艺过程中产生的静电电荷收集在玻璃基底上,因此,导致外部颗粒(诸如灰尘)容易附着到玻璃基底,由此导致工艺故障。此外,面板中的元件可能因为静电而被损坏,因此,期望在平面显示面板中防止静电的收集。
传统地,将屏蔽静电的线或者电阻器插入到显示面板的边缘中。此外,使用二极管的静电防护电路安装在提供用于驱动显示面板的电源电压的线和提供用于照明测试的信号的线之间。
然而,随着显示器的尺寸增加,在制造工艺和模块组装过程中静电荷的出现变得更加频繁。因此,传统技术(诸如用于屏蔽静电的线或者电阻器)不能有效地防止在大尺寸的显示面板中发生静电。此外,当安装静电防护电路时,由于因静电而引起的高电位差导致的在静电防护电路中发生诸如爆炸的事件,所以由于短路而导致的损坏会经常发生。从而,显示面板的驱动会失效。
因此,耐抗静电的显示面板的设计被用于防止显示面板的驱动故障,并且用于防止由于对静电防护电路的爆炸损坏引起的对OLED显示器的显示面板造成损坏,并且同时有效地防止在大尺寸的显示面板中发生静电。
在此背景技术部分中公开的上述信息仅仅是为了增进对本发明的背景技术的理解,并且因此,其可能包含不构成在该国对本领域普通技术人员来说已知的现有技术的信息。
发明内容
本发明的示例实施例可以防止显示面板中静电的发生和流入,以防止显示面板的故障和损坏,并防止由于静电导致的显示装置的制造工艺故障。
此外,可以提供能有效地应用于大尺寸的显示面板的静电防护设计电路,以避免由于在显示装置中的静电的流入而导致的驱动失效,因此提供具有优良品质的显示面板。
根据本发明的一个方面,提供了一种显示装置的静电防护电路,所述静电防护电路包括:驱动电路,被构造为驱动显示图像的显示单元;至少一条时钟信号线,被构造为向驱动电路传输时钟信号;至少一个晶体管,电结合到时钟信号线;以及至少一个电容器,包括结合到晶体管的源电极并结合到晶体管的漏电极的第一电极和被构造为维持电压的第二电极。
时钟信号线可以通过栅极金属线与晶体管的栅电极相结合。
晶体管可以包括:半导体层,包括掺杂有半导体杂质的杂质掺杂区域和未掺杂有任何半导体杂质的本征半导体区域;栅电极层,位于半导体层上;以及栅极绝缘层,在栅电极层和半导体层之间,其中,栅极绝缘层被构造为通过流经时钟信号线的静电电流而产生电打开或者电短路。
半导体层的杂质掺杂区域可以包括:第一杂质掺杂区域;以及第二杂质掺杂区域,与第一杂质掺杂区域相对并且电结合到第一杂质掺杂区域的未与栅电极层叠置的部分。
静电防护电路还可以包括具有电结合到半导体层的杂质掺杂区域的第一电极的电容器,电容器被构造为当栅极绝缘层短路时聚积流入的静电电流。
根据本发明的另一个方面,提供了一种显示装置,所述显示装置包括:显示单元,包括多个像素并被构造为通过基于与图像数据信号相对应的数据电压发射光来显示图像;驱动电路,被构造为驱动显示单元;至少一条时钟信号线,被构造为将时钟信号传输到驱动电路;以及静电防护电路,包括:至少一个晶体管,电结合到时钟信号线;以及至少一个电容器,包括结合到晶体管的源电极和漏电极的第一电极以及被构造为施加有固定电压的第二电极。
静电防护电路可以结合在时钟信号线和驱动电路之间。
时钟信号线可以通过栅极金属线结合到静电防护电路的晶体管的栅电极。
晶体管可以包括:半导体层,包括掺杂有半导体杂质并且电结合到电容器的第一电极的杂质掺杂区域以及未掺杂有任何半导体杂质的本征半导体层;栅电极层,位于半导体层上;以及栅极绝缘层,在栅电极层和半导体层之间。
半导体的杂质掺杂区域可以包括:第一杂质掺杂区域;以及第二杂质掺杂区域,与第一杂质掺杂区域相对并且电结合到第一杂质掺杂区域的未与栅电极层叠置的部分。
栅极绝缘层可以被构造为由于静电电流流经至少一条时钟信号线而引起电打开或者引起电短路。
显示装置还可以包括具有电结合到半导体层的杂质掺杂区域的第一电极的电容器,电容器被构造为当栅极绝缘层短路时聚积流入的静电电流。
附图说明
图1是示出了根据本发明的示例实施例的显示面板的静电防护电路的示意图。
图2是根据本发明的示例实施例的在图1中示出的实施例的静电防护电路的基本单元的电路图。
图3是根据在图1中示出的本发明的示例实施例的沿B-B’线截取的在图1中示出的实施例的静电防护电路中的一部分的放大剖视图。
一些附图标号的描述
CL1、CL2、CL3、CL4:时钟信号线
GL1、GL2、GL3:栅极金属线
T1、T2、T3:静电防护晶体管
C1、C2、C3:电容器
10:本征半导体层区域
11、12:p型杂质掺杂区域
20:栅极绝缘层 30:层间绝缘层
40:时钟信号线 50:栅电极层
60:栅极金属线 70:电容器的第一电极
80:绝缘层 90:电容器的第二电极
具体实施方式
在下文中,将结合示出本发明的示例实施例的附图更充分地描述本发明的实施例。本领域的技术人员将理解的是,所描述的实施例可以以各种不同的方式进行修改,而均未脱离本发明的精神和范围。
可以省略与示例实施例的描述不相关的部分,以使得描述清楚。此外,贯穿本说明书,相同的附图标记指的是相同的元件。
贯穿本说明书和权利要求书,当描述为元件“结合”到另一元件时,该元件可以“直接结合”到另一元件,或者可以通过一个或者多个其他元件“电结合”到其他元件。此外,除非明确地作出相反描述,否则词语“包括”和诸如“包含”或者“包括”的变型将被理解为意指包括所述元件,但是未必要排除任何其他元件。
图1是示出了根据本发明的示例实施例的显示面板的静电防护电路的示意图。
参照图1,根据本发明的本示例实施例,显示面板的静电防护电路设置在显示装置中。在示例实施例中,静电防护电路设置在包括显示面板(或者显示单元)的显示装置中,其中,显示面板(或者显示单元)包括显示图像的多个像素和驱动显示面板的驱动电路。更详细地讲,静电防护电路可以设置在驱动电路和用来向驱动电路传输时钟信号的多个时钟信号线CL1至CL4之间。在图1中,静电防护电路可以设置在多个时钟信号的一侧。
即,根据本发明的本示例实施例,静电防护电路可以分别地电结合(或者电连接)到时钟信号线,以防止或者减小静电放电(ESD)流经向驱动电路传输时钟信号(例如,预定的时钟信号)的时钟信号线的可能性,其中,驱动电路将栅极信号或者扫描信号传输到由显示图像的多个像素形成的像素单元,或者传输到显示面板中的数据源输出电路。
参照图1,根据本示例实施例,静电防护电路由分别地结合(或连接)到时钟信号线CL1至CL4的静电防护晶体管和电容器形成。
即,静电防护电路电结合到传输多个时钟信号的多个时钟信号线中的至少一条时钟信号线,并电结合到均具有与静电防护晶体管的漏电极和源电极电结合的第一电极的电容器。
图1示出了根据本示例实施例的静电防护电路包括三个静电防护晶体管T1-T3和三个电容器C1-C3,但是本发明不限于此。静电防护电路可以包括与多条时钟信号线相对应的多个静电防护晶体管和多个电容器。在图1中,第一线的静电防护晶体管T1包括:源电极1S和漏电极1D,沿相同的线互相结合;以及栅电极1G,形成在源电极1S和漏电极1D的顶部上,并且栅极绝缘层插入在栅电极1G与源电极1S和漏电极1D之间。第一线的静电防护晶体管T1的源电极1S和漏电极1D在其更低的部分处互相结合,并且在栅电极1G层叠的上部中彼此分开。
此外,静电防护晶体管T1的栅电极1G通过栅极金属线GL1与相应的时钟信号线CL3电结合。时钟信号线CL3和栅极金属线GL1通过多个接触孔CH电结合,并且栅极金属线GL1在时钟信号线的一侧延伸并且通过接触孔与静电防护晶体管T1的栅电极1G电结合。
此外,在静电防护晶体管T1的下侧彼此结合的源电极1S和漏电极1D在同一层中结合到第一线的电容器C1的第一电极CE1。第一线的电容器C1由第一电极CE1、绝缘层和第二电极FE形成,其中,第一电极CE1均与静电防护晶体管T1的源电极1S和漏电极1D相结合,绝缘层层叠在第一电极CE1上,第二电极FE层叠在绝缘层上。如图1中所示,作为单个导线层,第二电极FE是形成静电防护电路的电容器C1至C3中每个电容器的第二电极。通过第二电极FE施加固定电压(例如,预设的固定电压),并且在形成静电防护电路的多个电容器的一侧的电极被设定为固定电压的电压。
在图1的示例实施例中,对应于时钟信号结合的静电防护晶体管和电容器形成在具有上述结构的每条线上。即,静电防护晶体管T2和电容器C2结合到时钟信号线CL2,静电防护晶体管T3和电容器C3结合到时钟信号线CL1。
分别将时钟信号线CL1至CL3电连接到静电防护电路的栅极金属线GL1至GL3是用于将时钟信号传输到诸如数据源输出电路、栅极驱动器、扫描驱动器等的驱动电路而结合的金属线。当在栅极金属线中包括在平板工艺中不遵循天线规则(antenna rule)的栅极金属线时,提供与在时钟信号线和驱动电路之间的金属线GL1至GL3相结合的静电防护电路来防止静电流经时钟线号线。
这里,“不遵循天线规则”是指延伸的栅极金属线的面积与结合到栅极金属线的晶体管的栅电极的面积之比大于特定值。
在此,将描述根据本发明的示例实施例的静电防护电路的操作。如图1所示,当外部静电流经时钟信号线CL2时,结合到不遵循天线规则的栅极金属线GL2的静电防护晶体管T2的栅极绝缘层燃毁或者被损坏,以防止外部静电传输显示面板中的其他电路元件。即,增加了在显示面板中与图像显示的电路操作无关的静电防护晶体管,因此,当静电流经多个时钟信号线的一部分时,高静电电流或者低静电电流被引导到增加的静电晶体管,然后静电防护晶体管中的最薄的栅极绝缘层烧毁,以此保护显示面板的驱动电路。
本发明的本示例实施例不限于图1,并且在结合时钟信号线和驱动电路的栅极金属线上可以形成至少一个静电防护电路。
与静电防护晶体管的漏电极和源电极结合的电容器的第二电极FE施加有固定电压并且维持在固定电压,以传导(或引导)外部静电电流至静电防护晶体管。电容器的第一电极与静电防护晶体管的漏电极和源电极相结合,以防止在传导(或引导)静电期间电容器的两个电极之间的电短路,电容器的第二电极FE结合到固定电压的电源。
这里,通过引导静电电流使静电防护晶体管的栅极绝缘层烧毁的含义可以根据高或低水平的静电电流的量而改变,但是其意味着静电电流影响静电防护电路的栅极绝缘层,因此导致电打开(例如,电开路)或者电短路。
当静电防护晶体管电打开时,电的流动停止(或者不连接),从而外部静电不影响显示面板中的电路元件的操作。此外,当静电防护晶体管电短路时,过量的电流流经静电防护晶体管,尽管电流仅聚积在与静电防护晶体管的源-漏电极相结合的电容器的第一电极中,使得相应的电容器维持被充以与第一电极的静电电压和第二电极的固定电压之间的差一样大的电压。因此,可以防止外部静电经由时钟信号线和栅极金属线流入显示面板的驱动电路中。
图2是示出根据本发明的本示例实施例的图1的静电防护电路的基本单元“A”的电路图。
在本发明的示例实施例中,基本单元包括结合到栅极金属线的至少一个晶体管和至少一个电容器,其中,栅极金属线与多个时钟信号线中的相应的一条时钟信号线电结合,从而,静电防护电路包括多个此类晶体管和多个此类电容器。
因此,根据本发明的本示例实施例,部分“A”是静电防护电路的基本单元,并且是结合到多条时钟信号线中的一条时钟信号线(例如,图1中的CL3)的静电防护电路的一部分。例如,部分“A”包括与栅极金属线GL1相结合的第一条线的静电防护晶体管T1和电容器C1,其中,栅极金属线GL1与图1中的时钟信号线CL3相结合。
静电防护晶体管T1包括:栅电极1G,与施加有时钟信号或者外部静电电压的栅极金属线GL1结合;源电极1S;和漏电极1D。源电极1S和漏电极1D共同结合到第一节点N1。
电容器C1包括第一电极和第二电极,其中,第一电极结合到第一节点N1,第二电极结合到传输固定电压VDH的电源。
当外部静电电流被引导至静电防护晶体管T1的栅电极1G,并且因此被引导至栅极绝缘层(即,栅电极的下层短路)时,电容器C1在第一电极中聚积过量的静电电流。此外,电容器C1充有与聚积在第一电极中的静电电压和施加到第二电极的固定电压VDH之间的差相对应的电压,并且维持该充电电压。然后,静电可以存储在静电防护电路中,使得静电不能影响显示面板中的其他电路元件,因此保护显示装置免受静电的影响。
可选择地,当外部静电被引导至静电防护晶体管T1的栅电极1G时,栅极绝缘层(即,栅电极的下层)电打开并且因此电分离,使得静电不能影响显示面板的其他电路元件。
图3是根据本发明的本示例实施例的沿图1的线B-B’截取的图1的静电防护电路的放大剖视图。
虽然在图3中未示出,但是可以根据沿线B-B’截取的部分的剖面结构的最下部(或区域)中的每种构成方式来设置绝缘基底。
即,由氧化硅形成的缓冲层和绝缘基底可以形成在静电防护晶体管T2和电容器C2的最下部(或区域),但是因为此技术内容在本领域中是已知的,所以将不再提供对静电防护电路结构的剖面的进一步描述。
此外,线B-B’是从时钟信号线CL2延伸然后穿过两条时钟信号线CL3和CL4的线,但是为了更好地理解和易于描述,将从图3中省略没有与静电防护晶体管T2电结合的时钟信号线CL3和CL4。
参照图3,首先,形成静电防护晶体管T2的半导体层SCL。半导体层SCL可以由例如多晶硅(Poly-Si)形成。
栅极绝缘层20形成在半导体层SCL上。栅极绝缘层20的构成材料不受具体限制,并且可以例如包括:诸如氧化硅(SiO2)、氮化硅(SiNx)等的无机材料;无机材料的组合;和/或诸如PVP(聚乙烯基苯酚)、聚酰亚胺等的有机材料。通常,栅极绝缘层20是最薄的层,从而栅极绝缘层20在静电防护晶体管中可以因静电的流入而被烧毁,因此可以引起电打开或者电短路。
在形成栅极绝缘层20之后,栅电极层50通过图案化形成在形成有半导体层SCL的区域之上的部分中。
在栅电极层50被图案化之后,利用栅电极层50作为掺杂阻止层来掺杂杂质,并且在图3的示例实施例中,掺入p型杂质,从而形成p型杂质掺杂区域11和12。未掺入有杂质的本征半导体层区域10保持在位于栅电极层50的一部分下方的半导体层SCL中。
p型杂质掺杂区域11和12可以分别形成为源电极和漏电极。虽然在图3中未示出,但是p型杂质掺杂区域11和12可以彼此结合,使得可以在静电防护晶体管T2的另一个位置中形成公共节点。此外,电容器C2的导电层70形成在与公共节点相同的层中。即,p型杂质掺杂区域11和12彼此结合,并且导电层70与p型杂质掺杂区域11和12相结合,并且导电层70形成电容器C2的第一电极CE2。
同时,在形成栅极绝缘层20之后,可以在区域(例如,预定的区域)中通过图案化来形成时钟信号线40。然而,本实施例不限于此,并且可以通过与形成静电防护电路的工艺分开的工艺形成时钟信号线40。
时钟信号线40是用来将时钟信号从控制器传输给驱动电路的金属线。形成金属线的材料没有限制,可以是导电材料或者其合金。例如,金属线可以由诸如钼(Mo)、钽(Ta)、钴(Co)等的金属材料或者其合金形成。
在形成栅电极层50之后,可以在栅电极层50上形成层间绝缘层30。图3示出了形成层间绝缘层30使得其延伸到时钟信号线40的上部,但是示例实施例不限于此。
层间绝缘层30的材料不受具体限制,但是,与栅极绝缘层20类似,层间绝缘层30可以例如由诸如氧化硅(SiO2)、氮化硅(SiNx)等的无机材料、无机材料的组合或者诸如聚乙烯酚(PVP)、聚酰亚胺等的有机材料形成。在图3中,层间绝缘层30形成为单层,但是可以由至少两层形成。此外,层间绝缘层30可以由和栅极绝缘层相同的绝缘材料形成,或者可以由不同的材料形成。
在形成层间绝缘层30之后,通过图案化部分地暴露时钟信号线40和栅电极层50,然后形成栅极金属线60(例如,GL2)。栅极金属线60(GL2)可以由导电金属材料形成,但是其不限于此。例如,栅极金属线60可以由诸如钛(Ti)、铝(Al)等的导电材料或者其合金形成。
栅极金属线60(GL2)通过层间绝缘层30中的暴露时钟信号线40和栅电极层50的接触孔电连接已经图案化的并且被暴露的时钟信号线40和栅电极层50。
因此,流自时钟信号线40的静电电流被传输到栅电极层50。然后,位于栅电极层50和半导体层SCL之间的栅极绝缘层20被烧毁并且因此电打开或者短路。
同时,在导电层形成为电容器C2的第一电极70之后,在第一电极70上层叠绝缘层80。然后,导电层作为电容器C2的第二电极90形成在绝缘层80上。可以施加固定电压给第二电极90。因此,当静电防护晶体管T2的栅极绝缘层20由于静电电流而短路时,静电电流聚积在与源电极和漏电极(即,半导体SCL的杂质掺杂区域11和12)电结合的电容器C2的第一电极70中。因此,静电电流不会流到显示面板的其他电路元件中。
在图3的示例实施例中,可以形成在栅极金属线60(GL2)的上部和电容器C2的第二电极90中的层可以是已知的层,例如层间绝缘层、保护层等,并且这些层可以通过显示面板的制造工艺形成。因为这在本领域中代表普通技术,所以将不提供进一步的描述。
虽然已经结合目前被认为是实际的示例实施例的内容描述了本发明,但是应该理解的是,本发明不限于公开的实施例,而是相反,旨在覆盖包括在权利要求的精神和范围内的各种修改和等同布置。从而,本领域的技术人员能够从具体实施方式中选择和替换。而且,本领域的普通技术人员可以在没有使性能劣化的情况下去除在说明书中描述的组成元件的一部分或者为提高性能而增加组成元件。此外,本领域的普通技术人员可以根据工艺环境或设备来改变说明书中描述的方法的步骤的顺序。因此,其旨在通过权利要求和它们的等同物限定本发明的范围。
Claims (12)
1.一种显示装置的静电防护电路,所述静电防护电路包括:
驱动电路,被构造为驱动显示图像的显示单元;
至少一条时钟信号线,被构造为向驱动电路传输时钟信号;
至少一个晶体管,电结合到时钟信号线;以及
至少一个电容器,包括结合到晶体管的源电极和漏电极的第一电极和被构造为维持电压的第二电极。
2.如权利要求1所述的静电防护电路,其中,时钟信号线通过栅极金属线与晶体管的栅电极相结合。
3.如权利要求1所述的静电防护电路,其中,晶体管包括:
半导体层,包括掺杂有半导体杂质的杂质掺杂区域和未掺杂有任何半导体杂质的本征半导体区域;
栅电极层,位于半导体层上;以及
栅极绝缘层,在栅电极层和半导体层之间,
其中,栅极绝缘层被构造为通过流经时钟信号线的静电电流产生电打开或者电短路。
4.如权利要求3所述的静电防护电路,其中,半导体层的杂质掺杂区域包括:
第一杂质掺杂区域;以及
第二杂质掺杂区域,与第一杂质掺杂区域相对并且电结合到第一杂质掺杂区域的未与栅电极层叠置的部分。
5.如权利要求3所述的静电防护电路,其中,电容器的第一电极电结合到半导体层的杂质掺杂区域,电容器被构造为当栅极绝缘层短路时聚积流入的静电电流。
6.一种显示装置,所述显示装置包括:
显示单元,包括多个像素并被构造为通过基于与图像数据信号相对应的数据电压发射光来显示图像;
驱动电路,被构造为驱动显示单元;
至少一条时钟信号线,被构造为将时钟信号传输到驱动电路;以及
静电防护电路,包括:
至少一个晶体管,电结合到时钟信号线;以及
至少一个电容器,包括结合到晶体管的源电极和漏电极的第一电极以及被构造为施加有固定电压的第二电极。
7.如权利要求6所述的显示装置,其中,静电防护电路结合在时钟信号线和驱动电路之间。
8.如权利要求6所述的显示装置,其中,时钟信号线通过栅极金属线结合到静电防护电路的晶体管的栅电极。
9.如权利要求6所述的显示装置,其中,晶体管包括:
半导体层,包括掺杂有半导体杂质并且电结合到电容器的第一电极的杂质掺杂区域以及未掺杂有任何半导体杂质的本征半导体层;
栅电极层,位于半导体层上;以及
栅极绝缘层,在栅电极层和半导体层之间。
10.如权利要求9所述的显示装置,其中,半导体的杂质掺杂区域包括:
第一杂质掺杂区域;以及
第二杂质掺杂区域,与第一杂质掺杂区域相对并且电结合到第一杂质掺杂区域的未与栅电极层叠置的一部分。
11.如权利要求9所述的显示装置,其中,栅极绝缘层被构造为由于静电电流流经至少一条时钟信号线而引起电打开或者引起电短路。
12.如权利要求11所述的显示装置,其中,电容器的第一电极电结合到半导体层的杂质掺杂区域,电容器被构造为当栅极绝缘层短路时聚积流入的静电电流。
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TW201430807A (zh) | 2014-08-01 |
JP2014146777A (ja) | 2014-08-14 |
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CN103972228B (zh) | 2018-03-27 |
EP2759874A1 (en) | 2014-07-30 |
US9058770B2 (en) | 2015-06-16 |
US20190131380A1 (en) | 2019-05-02 |
US20200066823A1 (en) | 2020-02-27 |
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