WO2020100308A1 - Dispositif à semi-conducteur et procédé de fabrication associé, et structure utilisée au cours de la fabrication du dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur et procédé de fabrication associé, et structure utilisée au cours de la fabrication du dispositif à semi-conducteur Download PDF

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Publication number
WO2020100308A1
WO2020100308A1 PCT/JP2018/042551 JP2018042551W WO2020100308A1 WO 2020100308 A1 WO2020100308 A1 WO 2020100308A1 JP 2018042551 W JP2018042551 W JP 2018042551W WO 2020100308 A1 WO2020100308 A1 WO 2020100308A1
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Prior art keywords
chip
adhesive piece
substrate
semiconductor device
height
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PCT/JP2018/042551
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English (en)
Japanese (ja)
Inventor
昌典 夏川
▲徳▼軒 蘇
麻未 上田
祐也 平本
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日立化成株式会社
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Application filed by 日立化成株式会社 filed Critical 日立化成株式会社
Priority to PCT/JP2018/042551 priority Critical patent/WO2020100308A1/fr
Priority to SG11202104932XA priority patent/SG11202104932XA/en
Priority to PCT/JP2019/044761 priority patent/WO2020100998A1/fr
Priority to KR1020217017011A priority patent/KR20210094555A/ko
Priority to CN201980074797.0A priority patent/CN113039641A/zh
Priority to JP2020556180A priority patent/JPWO2020100998A1/ja
Priority to TW108141611A priority patent/TWI814944B/zh
Publication of WO2020100308A1 publication Critical patent/WO2020100308A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
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    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present disclosure relates to a semiconductor device, a method for manufacturing the same, and a structure used for manufacturing the semiconductor device.
  • Wire bonding is a method of connecting a semiconductor chip and a substrate by using a metal thin wire such as a gold wire.
  • a method called flip chip connection is becoming widespread.
  • Flip-chip connection is a method in which conductive protrusions called bumps are formed on a semiconductor chip or a substrate to directly connect the semiconductor chip and the substrate.
  • Patent Document 1 discloses a semiconductor device in which a first semiconductor element (for example, a controller) is embedded in an adhesive film for adhering a second semiconductor element.
  • the present inventors formed a space by arranging a spacer around the position where the first chip is arranged instead of embedding the first chip with an adhesive film, and the first chip is arranged in this space. After the arrangement, a structure for filling the space with a sealing material was examined. As a result, it has been found that when the space is filled with the sealing material, if the height of the upper surface of the spacer is different from the height of the upper surface of the first chip, the filling with the sealing material tends to be difficult.
  • the present disclosure is a method for manufacturing a semiconductor device in which a first chip is mounted on a substrate and a second chip is arranged above the first chip, and it is possible to prevent the semiconductor device from becoming excessively thick.
  • EN Provided is a manufacturing method capable of easily performing an operation of sealing a first chip and a second chip with a sealing material. Further, the present disclosure provides a semiconductor device which is not excessively thick and has an excellent filling property with an encapsulant, and a structure used for manufacturing the semiconductor device.
  • a method of manufacturing a semiconductor device includes (A) a substrate, a first chip arranged on the substrate, and a plurality of spacers arranged on the substrate and around the first chip.
  • a step of preparing a structure includes (B) preparing a chip with an adhesive piece, comprising a second chip having a size larger than that of the first chip, and an adhesive piece provided on one surface of the second chip And (C) arranging the second chip above the first chip so that the adhesive pieces of the adhesive piece-attached chip are in contact with the upper surfaces of the plurality of spacers, and (D) the first chip.
  • the step of sealing the spacer and the second chip, and the height of the upper surface of the spacer and the height of the upper surface of the first chip match before performing the step (D).
  • the term “match” as used herein means that the difference between the height of the upper surface of the spacer and the height of the upper surface of the first chip is less than 10 ⁇ m.
  • the height of the upper surface of the spacer matches the height of the upper surface of the first chip before the step (D) is carried out means that the chip with the adhesive piece arranged in the step (C) is It means that the adhesive piece is also in contact with the upper surface of the first chip. If the upper surface of the first chip and the adhesive piece are not in contact with each other and there is a gap between the two, it is difficult to fill the gap with the sealing material and a void is likely to occur. On the other hand, if the distance between the upper surface of the first chip and the adhesive piece is sufficiently wide, the filling property of the sealing material is improved, but the semiconductor device tends to be thick. On the other hand, according to the manufacturing method of the present disclosure, excellent filling properties of the sealing material and thinning of the semiconductor device can both be achieved.
  • the height of the upper surface of the spacer and the height of the upper surface of the first chip may match before the step (D) is performed.
  • the height of the upper surface of the spacer may be equal to the height of the upper surface of the first chip, or the structure prepared in the step (A).
  • the upper surface of the spacer is higher than the upper surface of the first chip, and in the subsequent step (C), the height of the upper surface of the spacer and the upper surface of the first chip are crushed by crushing the spacer with the chip with the adhesive piece. May be matched.
  • One mode of the spacer is a dummy chip including a chip and an adhesive piece provided on one surface of the chip.
  • the adhesive piece included in the dummy chip is larger than the adhesive piece included in the chip with the adhesive piece. Is also preferably soft. Further, the adhesive piece included in the dummy chip is preferably thicker than the adhesive piece included in the chip with the adhesive piece.
  • the first chip is mounted on the substrate by flip chip connection.
  • the height of the connecting portion is more likely to vary than when the adhesive film is used to adhere to the board.
  • the top surface of the first chip Is likely to vary in height position. Therefore, when the first chip is mounted by flip-chip connection, in the step (C), the height of the spacer can be adjusted by pressing the spacer with the chip with the adhesive piece so that the height of the spacer can be adjusted.
  • a semiconductor device includes a substrate, a first chip arranged on the substrate, a plurality of spacers arranged on the substrate around the first chip, and above the first chip.
  • a second chip that is arranged and has a larger size than the first chip, an adhesive piece that bonds a plurality of spacers to the second chip, a first chip, a spacer, and a second chip.
  • a sealing material that seals the adhesive chip, and the adhesive piece is in contact with the upper surface of the first chip.
  • the first chip is, for example, a controller chip.
  • the above semiconductor device can be manufactured by the manufacturing method according to the present disclosure.
  • the adhesive piece is in contact with the upper surface of the first chip, it is not excessively thick and is excellent in the filling property of the sealing material.
  • the present disclosure provides a structure used for manufacturing the semiconductor device.
  • the structure according to the first aspect includes a substrate, a first chip arranged on the substrate, and a plurality of spacers arranged on the substrate around the first chip, and the upper surface of the spacer And the height of the upper surface of the first chip match.
  • a structure according to a second aspect includes a substrate, a first chip arranged on the substrate, and a plurality of spacers arranged on the substrate around the first chip, and the upper surface of the spacer Is higher than the upper surface of the first chip, and the spacer is crushed, so that the spacer includes a material whose upper surface height matches the upper surface height of the first chip.
  • the structure according to the present disclosure may be a mode further including a second chip.
  • the structure according to this aspect includes a substrate, a first chip arranged on the substrate, a plurality of spacers arranged on the substrate around the first chip, and arranged above the first chip. And a second chip having a size larger than that of the first chip, and an adhesive piece adhering a plurality of spacers to the second chip, the adhesive piece being an upper surface of the first chip. Touches.
  • a manufacturing method capable of suppressing the above-mentioned problem and easily carrying out the work of sealing the first chip and the second chip with a sealing material.
  • a semiconductor device which is not excessively thick and has an excellent filling property with a sealing material, and a structure used for manufacturing the semiconductor device.
  • FIG. 1 is a sectional view schematically showing a first embodiment of a semiconductor device according to the present disclosure.
  • 2A and 2B are plan views schematically showing an example of the positional relationship between the first chip and the plurality of dummy chips.
  • 3A to 3E are sectional views schematically showing an example of a process of manufacturing a dummy chip.
  • FIG. 4 is a cross-sectional view schematically showing the first embodiment of the structure used for manufacturing the semiconductor device according to the present disclosure.
  • FIG. 5: is sectional drawing which shows an example of the chip
  • FIG. 6 is a cross-sectional view schematically showing a state in which the chip with the adhesive piece shown in FIG. 5 is pressure bonded to the structure shown in FIG.
  • FIG. 5 is sectional drawing which shows an example of the chip
  • FIG. 6 is a cross-sectional view schematically showing a state in which the chip with the adhesive piece shown in FIG. 5 is pressure bonded
  • FIG. 7 is a sectional view schematically showing another embodiment of a structure used for manufacturing a semiconductor device according to the present disclosure.
  • 8 is a cross-sectional view schematically showing a state in which the chip with the adhesive piece shown in FIG. 5 is pressure bonded to the structure shown in FIG.
  • FIG. 1 is a sectional view schematically showing the semiconductor device according to the present embodiment.
  • the semiconductor device 100 shown in this figure includes a substrate 10, a chip S1 (first chip) arranged on the surface of the substrate 10, and two chips S1 arranged on the surface of the substrate 10 and around the chip S1.
  • Dummy chip D spacer
  • chip S2 second chip
  • a wire w for electrically connecting the chips S2, S3, S4 to each other
  • a sealing material 50 for sealing the chips S1, S2, S3, S4, the dummy chip D and the wire w.
  • a cured product Sc of the adhesive piece is arranged between the upper surface of the chip S1 and the upper surfaces of the plurality of dummy chips D and the chip S2.
  • the height of the upper surface of the chip S1 and the height of the upper surface of the dummy chip D match. That is, the cured product Sc is in contact with the upper surface of the chip S1 and the upper surface of the dummy chip D.
  • the substrate 10 may be an organic substrate or a metal substrate such as a lead frame. From the viewpoint of suppressing the warpage of the semiconductor device 100, the substrate 10 has a thickness of, for example, 90 to 300 ⁇ m, or may be 90 to 210 ⁇ m.
  • the chip S1 is, for example, a controller chip, and is mounted on the substrate 10 by flip chip connection.
  • the shape of the chip S1 in a plan view is, for example, a rectangle (square or rectangle).
  • the length of one side of the chip S1 is, for example, 5 mm or less, and may be 2 to 5 mm or 1 to 5 mm.
  • the thickness of the chip S1 is, for example, 10 to 150 ⁇ m, and may be 20 to 100 ⁇ m.
  • the chip S2 is, for example, a memory chip, and is bonded onto the chip S1 and the dummy chip D via the cured product Sc of the adhesive piece.
  • the chip S2 has a larger size than the chip S1 in a plan view.
  • the shape of the chip S2 in a plan view is, for example, a rectangle (square or rectangle).
  • the length of one side of the chip S2 is, for example, 20 mm or less, and may be 4 to 20 mm or 4 to 12 mm.
  • the thickness of the chip S2 is, for example, 10 to 170 ⁇ m, and may be 20 to 120 ⁇ m.
  • the chips S3 and S4 are also memory chips, for example, and are bonded onto the chip S2 via the cured product Sc of the adhesive piece.
  • the length of one side of the chips S3, S4 may be the same as that of the chip S2, and the thickness of the chips S3, S4 may be the same as that of the chip S2.
  • the dummy chip D plays a role of a spacer that forms a space around the chip S1.
  • the dummy chip D is composed of a chip D1 and an adhesive piece Da provided on one surface of the chip D1.
  • two dummy chips D may be arranged at separate positions on both sides of the chip S1, or as shown in FIG.
  • One dummy chip D (shape: square, total of four) may be arranged at a position corresponding to each corner of.
  • the length of one side of the chip D1 in a plan view is, for example, 20 mm or less, and may be 1 to 20 mm or 1 to 12 mm.
  • the thickness of the chip D1 is, for example, 30 to 150 ⁇ m, and may be 80 to 120 ⁇ m.
  • the height of the upper surface of the dummy chip D and the height of the upper surface of the chip S1 match.
  • the position of the upper surface of the chip S1 that is flip-chip connected and the position of the upper surface of the dummy chip D can be matched.
  • a dicing die bonding integrated film 8 (hereinafter, referred to as “film 8” in some cases) is prepared and placed in a predetermined device (not shown).
  • the film 8 includes the base film 1, the pressure-sensitive adhesive layer 2, and the adhesive layer 3A in this order.
  • the base film 1 is, for example, a polyethylene terephthalate film (PET film).
  • PET film polyethylene terephthalate film
  • the pressure-sensitive adhesive layer 2 has a property that its adhesiveness is lowered by being irradiated with ultraviolet rays.
  • the adhesive layer 3A is made of a thermosetting resin composition.
  • the film 8 is attached so that the adhesive layer 3A is in contact with one surface of the wafer W.
  • the wafer W may be single crystal silicon, or may be polycrystal silicon, various ceramics, or a compound semiconductor such as gallium arsenide.
  • the wafer W does not have to be a semiconductor and may be, for example, a glass substrate.
  • the wafer W and the adhesive layer 3A are cut with a dicing blade (see FIG. 3 (c)).
  • the wafer W is diced into individual pieces to form the chips D1.
  • the adhesive layer 3A is diced into individual pieces to form the adhesive pieces Da.
  • the adhesive force between the adhesive layer 2 and the adhesive layer 3A is reduced by irradiating the adhesive layer 2 with ultraviolet rays.
  • the dummy film D is separated from each other by expanding the base film 1.
  • the dummy chip D is peeled from the adhesive layer 2 by pushing up the dummy chip D with the needle 42, and the dummy chip D is picked up by suction with the suction collet 44.
  • a method of manufacturing the semiconductor device 100 will be described with reference to FIGS.
  • the method for manufacturing the semiconductor device 100 includes the following steps (A) to (D).
  • (A) A step of preparing a structure 30A including a substrate 10, a chip S1 arranged on the substrate 10, and a plurality of dummy chips D arranged on the substrate 10 around the chip S1 (FIG. 4). reference).
  • (B) A step of preparing a chip S2a with an adhesive piece, which includes the chip S2 and an adhesive piece Sa provided on one surface of the chip S2 (see FIG. 5).
  • (C) A step of disposing the chip S2 above the chip S1 such that the adhesive pieces Sa are in contact with the upper surfaces of the plurality of dummy chips D and the upper surface of the chip S1 (see FIG. 6).
  • (D) A step of sealing the chips S1, S2, S3, S4, the dummy chip D, and the like.
  • the step (A) is a step of preparing the structure 30A shown in FIG.
  • the structure 30A includes a substrate 10, a chip S1 and a plurality of dummy chips D arranged on the surface thereof, and the height of the upper surface of the chip S1 and the height of the upper surface of the dummy chip D are the same.
  • the chip S1 may be mounted at a predetermined position on the substrate 10 by flip chip connection, and then the dummy chip D may be pressure-bonded to the predetermined position.
  • This pressure bonding treatment is preferably carried out, for example, under conditions of 80 to 180 ° C. and 0.01 to 0.50 MPa for 0.5 to 3.0 seconds.
  • the adhesive piece Da of the dummy chip D may be completely cured at the time of the (A) process, may not be completely cured at this time, and may be completely cured at the time of the (C) process. ..
  • the step (B) is a step of preparing the chip S2a with the adhesive piece shown in FIG.
  • the chip with adhesive piece S2a includes the chip S2 and the adhesive piece Sa provided on one surface thereof.
  • the chip S2a with the adhesive piece can be obtained through a dicing process using, for example, a dicing die bonding integral type film (see FIGS. 3A to 3E).
  • the step (C) is a step of arranging the chip S2a with the adhesive piece above the chip S1 so that the adhesive piece Sa contacts the upper surfaces of the plurality of dummy chips D and the upper surface of the chip S1.
  • the chip S2 is pressure-bonded to the upper surface of the dummy chip D and the upper surface of the chip S1 via the adhesive piece Sa.
  • This pressure bonding treatment is preferably carried out, for example, under conditions of 80 to 180 ° C. and 0.01 to 0.50 MPa for 0.5 to 3.0 seconds.
  • the adhesive piece Sa is cured by heating. This curing treatment is preferably carried out, for example, under conditions of 60 to 175 ° C. and 0.01 to 1.0 MPa for 5 minutes or more. As a result, the adhesive piece Sa becomes the cured product Sc.
  • FIG. 6 is a sectional view schematically showing a structure obtained through the step (C).
  • the structure 40 shown in this figure since there is no gap between the cured product Sc and the chip S1, excellent filling properties of the encapsulant can be achieved in the step (D).
  • the chip S3 is arranged on the chip S2 via the adhesive piece, and further, the chip S4 is arranged on the chip S3 via the adhesive piece. ..
  • the adhesive piece may be a thermosetting resin composition similar to the adhesive piece Sa described above, and becomes a cured product Sc by heat curing (see FIG. 1).
  • the chips S2, S3, S4 and the substrate 10 are electrically connected by the wires w. Note that the number of chips stacked above the chip S1 is not limited to three in this embodiment, and may be set appropriately.
  • Step (D) is a step of sealing the chips S1, S2, S3, S4, the dummy chip D and the wire w with the sealing material 50. Through these steps, the semiconductor device 100 shown in FIG. 1 is completed.
  • thermosetting resin composition The thermosetting resin composition constituting the adhesive piece Da and the adhesive piece Sa will be described.
  • the thermosetting resin composition according to the present embodiment is capable of undergoing a semi-cured (B stage) state and then a completely cured (C stage) state by a subsequent curing treatment.
  • the thermosetting resin composition contains an epoxy resin, a curing agent, and an elastomer, and further contains an inorganic filler, a curing accelerator, and the like, if necessary.
  • the epoxy resin is not particularly limited as long as it cures and has an adhesive action.
  • Bifunctional epoxy resins such as bisphenol A type epoxy resin, bisphenol F type epoxy resin and bisphenol S type epoxy resin, and novolac type epoxy resins such as phenol novolac type epoxy resin and cresol novolac type epoxy resin can be used.
  • polyfunctional epoxy resin glycidylamine type epoxy resin, heterocycle-containing epoxy resin or alicyclic epoxy resin can be applied. These may be used alone or in combination of two or more.
  • the curing agent examples include phenolic resins, ester compounds, aromatic amines, aliphatic amines, and acid anhydrides. Of these, a phenol resin is preferable from the viewpoint of reactivity and stability over time.
  • Commercially available phenolic resins include, for example, Phenolite KA and TD series manufactured by DIC Corporation, Mirex XLC-series and XL series manufactured by Mitsui Chemicals, Inc. (for example, MIlex XLC-LL), Air Water Co., Ltd.
  • HE series for example, HE100C-30
  • MEHC-7800 series for example, MEHC-7800-4S manufactured by Meiwa Kasei Co., Ltd. may be mentioned. These may be used alone or in combination of two or more.
  • the mixing ratio of the epoxy resin and the phenol resin is such that the equivalent ratio of the epoxy equivalent and the hydroxyl equivalent is preferably 0.30 / 0.70 to 0.70 / 0.30, and more preferably 0. 35 / 0.65 to 0.65 / 0.35, more preferably 0.40 / 0.60 to 0.60 / 0.40, and particularly preferably 0.45 / 0.55 to 0.55 / 0. 45.
  • the compounding ratio is within the above range, both curability and fluidity can be easily achieved at sufficiently high levels.
  • Examples of the elastomer include acrylic resin, polyester resin, polyamide resin, polyimide resin, silicone resin, polybutadiene, acrylonitrile, epoxy-modified polybutadiene, maleic anhydride-modified polybutadiene, phenol-modified polybutadiene, and carboxy-modified acrylonitrile.
  • an acrylic resin is preferable as the elastomer, and further obtained by polymerizing a functional monomer having an epoxy group or a glycidyl group such as glycidyl acrylate or glycidyl methacrylate as a crosslinkable functional group.
  • An acrylic resin such as an epoxy group-containing (meth) acrylic copolymer is more preferable.
  • an epoxy group-containing (meth) acrylic acid ester copolymer and an epoxy group-containing acrylic rubber are preferable, and an epoxy group-containing acrylic rubber is more preferable.
  • the epoxy group-containing acrylic rubber is a rubber having an epoxy group, which is mainly composed of an acrylic ester and is mainly composed of a copolymer such as butyl acrylate and acrylonitrile or a copolymer such as ethyl acrylate and acrylonitrile.
  • the acrylic resin may have a crosslinkable functional group such as an alcoholic or phenolic hydroxyl group and a carboxyl group, as well as an epoxy group.
  • acrylic resins are SG-70L, SG-708-6, WS-023 EK30, SG-280 EK23, SG-P3 manufactured by Nagase Chemtech Co., Ltd. (product name, acrylic rubber, weight) Average molecular weight: 800,000, Tg: 12 ° C., solvent is cyclohexanone, etc.
  • the glass transition temperature (Tg) of the acrylic resin is preferably ⁇ 50 to 50 ° C., more preferably ⁇ 30 to 30 ° C.
  • the weight average molecular weight (Mw) of the acrylic resin is preferably 100,000 to 3,000,000, more preferably 500,000 to 2,000,000.
  • Mw means a value measured by gel permeation chromatography (GPC) and converted using a calibration curve based on standard polystyrene. The use of an acrylic resin having a narrow molecular weight distribution tends to form an adhesive piece having excellent embedding properties and high elasticity.
  • the amount of acrylic resin contained in the thermosetting resin composition is preferably 20 to 200 parts by mass, and more preferably 30 to 100 parts by mass, based on 100 parts by mass of the total of the epoxy resin and the epoxy resin curing agent. More preferable. Within this range, control of fluidity during molding, handling at high temperature, and embedding property can be further improved.
  • inorganic filler examples include aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, aluminum borate whiskers, boron nitride and crystallinity.
  • examples thereof include silica and amorphous silica. These may be used alone or in combination of two or more.
  • the average particle size of the inorganic filler is preferably 0.005 ⁇ m to 1.0 ⁇ m, and more preferably 0.05 to 0.5 ⁇ m, from the viewpoint of improving adhesiveness.
  • the surface of the inorganic filler is preferably chemically modified from the viewpoint of compatibility with a solvent and a resin component and adhesive strength. Suitable materials for chemically modifying the surface include silane coupling agents. Examples of the functional group of the silane coupling agent include vinyl group, acryloyl group, epoxy group, mercapto group, amino group, diamino group, alkoxy group and ethoxy group.
  • the content of the inorganic filler with respect to 100 parts by mass of the resin component of the thermosetting resin composition is preferably 20 to 200 parts by mass, more preferably 30 to 100 parts by mass.
  • curing accelerator examples include imidazoles and their derivatives, organic phosphorus compounds, secondary amines, tertiary amines, and quaternary ammonium salts. Imidazole compounds are preferable from the viewpoint of appropriate reactivity.
  • imidazoles include 2-methylimidazole, 1-benzyl-2-methylimidazole, 1-cyanoethyl-2-phenylimidazole, 1-cyanoethyl-2-methylimidazole and the like. These may be used alone or in combination of two or more.
  • the content of the curing accelerator in the thermosetting resin composition is preferably 0.04 to 3 parts by mass, and 0.04 to 0.2 parts by mass based on 100 parts by mass of the total of the epoxy resin and the epoxy resin curing agent. More preferable. When the amount of the curing accelerator added is within this range, both curability and reliability can be achieved.
  • the structure 30A in which the height of the upper surface of the dummy chip D and the height of the upper surface of the chip S1 are the same is prepared in the step (A).
  • a structure whose upper surface is higher than the upper surface of the chip S1 may be prepared in the step (A).
  • the structure 30B shown in FIG. 7 includes a substrate 10, a chip S1 arranged on the substrate 10, and a plurality of dummy chips D arranged on the substrate 10 around the chip S1. Is higher than the upper surface of the chip S1.
  • the height of the upper surface of the dummy chip D and the height of the upper surface of the chip S1 match before the step (D) of the first embodiment (step of sealing with the sealing material 50).
  • the height of the dummy chip D and the height of the upper surface of the chip S1 may be matched by crushing the adhesive piece Da of the dummy chip D with the chip S2a having the adhesive piece (see FIG. 8).
  • the height of the connection portion of the flip chip tends to vary by about 5 ⁇ m, and as a result, the height position of the upper surface of the chip S1 varies by about 5 ⁇ m.
  • the upper surface of the dummy chip D in the step (A) is set.
  • the height and the height of the upper surface of the chip S1 do not have to be exactly the same.
  • the adhesive piece Da of the dummy chip D is made of a material that is crushed by the adhesive piece chip S2a.
  • the adhesive piece Da of the dummy chip D is preferably softer than the adhesive piece Sa of the chip S2a with an adhesive piece.
  • the content of the thermosetting resin of the adhesive piece Da is made larger than that of the adhesive piece Sa, or the elastomer or the inorganic filler of the adhesive piece Da is used. The content of may be smaller than that of the adhesive piece Sa.
  • the adhesive piece Da of the dummy chip D is preferably thicker than the adhesive piece Sa of the chip Sa2 with an adhesive piece.
  • the thickness of the adhesive piece Da is 1.1 to 8 times the thickness of the adhesive piece Sa, and may be 1.2 to 6 times.
  • the present invention is not limited to the above embodiments.
  • the case where the chip S1 is mounted by flip-chip connection is illustrated, but the chip S1 may be fixed to the substrate 10 by an adhesive and then electrically connected by wire bonding.
  • a manufacturing method capable of suppressing the above-mentioned problem and easily carrying out the work of sealing the first chip and the second chip with a sealing material.
  • a semiconductor device which is not excessively thick and has an excellent filling property with a sealing material, and a structure used for manufacturing the semiconductor device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Adhesive Tapes (AREA)

Abstract

La présente invention concerne un procédé de fabrication d'un dispositif à semi-conducteur impliquant (A) une étape de préparation d'une structure qui est pourvue d'un substrat, d'une première puce disposée sur le substrat, et de multiples éléments d'espacement disposés sur le substrat et autour de la première puce, (B) une étape de préparation d'une puce avec une pièce adhésive, ladite puce avec une pièce adhésive comprenant une deuxième puce plus grande que la première puce et une pièce adhésive disposée sur un côté de la deuxième puce, (C) une étape d'agencement de la seconde puce au-dessus de la première puce de telle sorte que la pièce adhésive entre en contact avec la partie supérieure des multiples éléments d'espacement, et (D) une étape pour faire l'étanchéité de la première puce, des éléments d'espacement et de la seconde puce. La hauteur de la partie supérieure des éléments d'espacement et la hauteur de la partie supérieure de la première puce coïncident avant la réalisation de l'étape (D).
PCT/JP2018/042551 2018-11-16 2018-11-16 Dispositif à semi-conducteur et procédé de fabrication associé, et structure utilisée au cours de la fabrication du dispositif à semi-conducteur WO2020100308A1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
PCT/JP2018/042551 WO2020100308A1 (fr) 2018-11-16 2018-11-16 Dispositif à semi-conducteur et procédé de fabrication associé, et structure utilisée au cours de la fabrication du dispositif à semi-conducteur
SG11202104932XA SG11202104932XA (en) 2018-11-16 2019-11-14 Semiconductor device and manufacturing method thereof, and structure used in manufacture of semiconductor device
PCT/JP2019/044761 WO2020100998A1 (fr) 2018-11-16 2019-11-14 Dispositif à semi-conducteur et son procédé de fabrication, et structure utilisée dans la fabrication du dispositif à semi-conducteur
KR1020217017011A KR20210094555A (ko) 2018-11-16 2019-11-14 반도체 장치 및 그 제조 방법, 및 반도체 장치의 제조에 사용되는 구조체
CN201980074797.0A CN113039641A (zh) 2018-11-16 2019-11-14 半导体装置及其制造方法、以及在半导体装置的制造中使用的结构体
JP2020556180A JPWO2020100998A1 (ja) 2018-11-16 2019-11-14 半導体装置及びその製造方法、並びに半導体装置の製造に使用される構造体
TW108141611A TWI814944B (zh) 2018-11-16 2019-11-15 半導體裝置及其製造方法

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PCT/JP2018/042551 WO2020100308A1 (fr) 2018-11-16 2018-11-16 Dispositif à semi-conducteur et procédé de fabrication associé, et structure utilisée au cours de la fabrication du dispositif à semi-conducteur

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PCT/JP2019/044761 WO2020100998A1 (fr) 2018-11-16 2019-11-14 Dispositif à semi-conducteur et son procédé de fabrication, et structure utilisée dans la fabrication du dispositif à semi-conducteur

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TW202038425A (zh) 2020-10-16
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SG11202104932XA (en) 2021-06-29
JPWO2020100998A1 (ja) 2021-09-30
TWI814944B (zh) 2023-09-11
KR20210094555A (ko) 2021-07-29

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