WO2020098467A1 - 余量转移环路、逐次逼近型模数转换器和增益校准方法 - Google Patents

余量转移环路、逐次逼近型模数转换器和增益校准方法 Download PDF

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Publication number
WO2020098467A1
WO2020098467A1 PCT/CN2019/113092 CN2019113092W WO2020098467A1 WO 2020098467 A1 WO2020098467 A1 WO 2020098467A1 CN 2019113092 W CN2019113092 W CN 2019113092W WO 2020098467 A1 WO2020098467 A1 WO 2020098467A1
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Prior art keywords
margin
module
capacitor array
switch module
dac capacitor
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PCT/CN2019/113092
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English (en)
French (fr)
Inventor
郭啸峰
艾萌
戴思特
冯海刚
张宁
檀聿麟
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深圳锐越微技术有限公司
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Publication of WO2020098467A1 publication Critical patent/WO2020098467A1/zh
Priority to US17/318,143 priority Critical patent/US11296714B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
    • H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M3/422—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M3/424—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one
    • H03M3/426—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a multiple bit one the quantiser being a successive approximation type analogue/digital converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0854—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of quantisation noise
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/38—Calibration
    • H03M3/382—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
    • H03M1/1038—Calibration over the full range of the converter, e.g. for correcting differential non-linearity by storing corrected or correction values in one or more digital look-up tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods

Definitions

  • the present application relates to the technical field of semiconductor integrated circuits, in particular to a margin transfer loop, successive approximation analog-to-digital converter and gain calibration method.
  • Sigma-delta noise shaping successive approximation analog-to-digital converter is the latest popular high-precision ADC structure. Its ideological foundation is to convert SAR The margin of the ADC is transferred to the next conversion, in order to improve the accuracy of the SARADC to a higher level, while retaining the characteristics of simple structure, low power consumption, small area, small process adaptability, high performance and stability of the SARADC.
  • SAR ADC Sigma-delta noise shaping successive approximation analog-to-digital converter
  • the main purpose of this application is to provide a margin transfer loop, aiming to realize the ultra-high precision margin transfer of SAR ADC.
  • a margin transfer loop proposed in this application includes a sampling switch module, a logic control circuit, a margin holding capacitor module, a DAC capacitor array, a margin transfer module, a current rudder, a reset switch module, and a charge sharing switch Module;
  • the DAC capacitor array includes a first DAC capacitor array and a second DAC capacitor array that form a differential structure;
  • a differential analog signal is input to the first end of the sampling switch module, the second end of the sampling switch module is connected to the first end of the DAC capacitor array, the second end of the DAC capacitor array, and the charge sharing switch
  • the first end of the module, the first controlled end of the margin transfer module and the input end of the comparator are connected, the input end of the margin transfer module is connected to the power output end of the current rudder, the margin
  • the output end of the transfer module is interconnected with the first end of the remaining capacity capacitor module, the second end of the charge sharing switch module, and the first end of the reset switching module.
  • the two ends and the second end of the reset switch module are both grounded.
  • the controlled end of the sampling switch module, the second controlled end of the margin transfer module, the controlled end of the charge sharing switch module and all The controlled ends of the reset switch module are all connected to the control end of the logic control module;
  • the current rudder is set to output a static working current
  • the logic control circuit is configured to sequentially output control signals at a preset time interval within a preset period to control the reset switch module, the margin transfer module, the sampling switch module, and the charge sharing switch
  • the modules work in sequence;
  • the reset switch module resets the charge of the remaining capacity capacitor module based on the control of the logic control circuit
  • the sampling switch module based on the control and activation of the logic control circuit, inputs an externally input differential analog signal to the DAC capacitor array, so that the DAC capacitor array samples the externally input differential analog signal, and Output differential margin signal;
  • the margin transfer module is configured to, when receiving a differential margin signal generated on the DAC capacitor array, based on the differential margin signal and the control of the logic control circuit, to statically generate the current rudder The working current is output to charge the remaining capacity capacitor module;
  • the charge sharing switch module based on the control of the logic control circuit, after the sampling of the DAC capacitor array is completed, the charge of the remaining holding capacitor module and the DAC capacitor array is shared, and the same difference is generated
  • the margin signal performs the next margin transfer.
  • the margin transfer module includes a first PMOS tube, a second PMOS tube, and a first switching circuit
  • the input terminal of the first switch circuit is the input terminal of the margin transfer module
  • the controlled terminal of the first switch circuit is the second controlled terminal of the margin transfer module
  • the first switch circuit The source of the first PMOS tube and the source of the second PMOS tube are interconnected, the drain of the first PMOS tube and the drain of the second PMOS tube are the margin transfer At the output end of the module, the gate of the first PMOS tube and the gate of the second PMOS tube are the output ends of the margin transfer module.
  • the remaining capacity capacitor module includes a first remaining capacity capacitor and a second remaining capacity capacitor of the same capacitance, the first end of the first remaining capacity capacitor and the drain of the first PMOS tube In connection, the first end of the second remaining holding capacitor is connected to the drain of the second PMOS transistor, and the second end of the first remaining holding capacitor and the second remaining holding capacitor are both grounded.
  • the logic control circuit includes a SAR logic controller and a clock generator
  • the clock generator is configured to output a fixed-width pulse signal to the SAR logic controller, so that the SAR logic controller controls the margin transfer module to charge the margin holding capacitor at a first preset time ;
  • the SAR logic controller is configured to output a control signal to control the operation of the sampling switch module, the margin transfer module, the charge sharing switch module, and the reset switch module.
  • the first end of the first DAC capacitor array is connected to the positive input end of the differential analog signal through a switch unit corresponding to the sampling switch module, and the second end of the first DAC capacitor array is The positive output of the differential margin signal of the DAC capacitor array;
  • the first end of the second DAC capacitor array is connected to the negative input terminal of the differential analog signal through a switch unit corresponding to the sampling switch module, and the second end of the second DAC capacitor array is the DAC capacitor array The negative output of the differential margin signal.
  • the capacitance of the first DAC capacitor array is 4 times the capacitance of the first remaining holding capacitor
  • the capacitance of the second DAC capacitor array is the second remaining holding capacitor 4 times the capacitance value.
  • the capacitance of the first remaining holding capacitor is 32 times the equivalent capacitance of the lowest bit of the first DAC capacitor array
  • the capacitance of the second remaining holding capacitor is 32 times the equivalent capacitance of the lowest bit of the second DAC capacitor array.
  • the current rudder is also connected to a digital controller, and the digital controller is configured to control the static working current of the output change of the current rudder so that the gain of the margin transfer module is kept constant.
  • the present application also proposes a successive approximation analog-to-digital converter, including a comparator, a register connected to the output of the comparator, and a margin transfer loop, the margin transfer loop includes a sampling switch module, a logic control circuit, A margin holding capacitor module, a DAC capacitor array, a margin transfer module, a current rudder, a reset switch module, and a charge sharing switch module; the DAC capacitor array includes a first DAC capacitor array and a second DAC capacitor array that constitute a differential structure;
  • a differential analog signal is input to the first end of the sampling switch module, the second end of the sampling switch module is connected to the first end of the DAC capacitor array, the second end of the DAC capacitor array, and the charge sharing switch
  • the first end of the module, the first controlled end of the margin transfer module and the input end of the comparator are connected, the input end of the margin transfer module is connected to the power output end of the current rudder, the margin
  • the output end of the transfer module is interconnected with the first end of the remaining capacity capacitor module, the second end of the charge sharing switch module, and the first end of the reset switching module.
  • the two ends and the second end of the reset switch module are both grounded.
  • the controlled end of the sampling switch module, the second controlled end of the margin transfer module, the controlled end of the charge sharing switch module and all The controlled ends of the reset switch module are all connected to the control end of the logic control module;
  • the current rudder is set to output a static working current
  • the logic control circuit is configured to sequentially output control signals at a preset time interval within a preset period to control the reset switch module, the margin transfer module, the sampling switch module, and the charge sharing switch
  • the modules work in sequence;
  • the reset switch module resets the charge of the remaining capacity capacitor module based on the control of the logic control circuit
  • the sampling switch module based on the control and activation of the logic control circuit, inputs an externally input differential analog signal to the DAC capacitor array, so that the DAC capacitor array samples the externally input differential analog signal, and Output differential margin signal;
  • the margin transfer module is configured to, when receiving a differential margin signal generated on the DAC capacitor array, based on the differential margin signal and the control of the logic control circuit, to statically generate the current rudder Working current output to charge the remaining capacity capacitor module;
  • the charge sharing switch module based on the control of the logic control circuit, after the sampling of the DAC capacitor array is completed, the charge of the remaining holding capacitor module and the DAC capacitor array is shared, and the same difference is generated
  • the margin signal performs the next margin transfer.
  • the margin transfer module includes a first PMOS tube, a second PMOS tube, and a first switching circuit
  • the input terminal of the first switch circuit is the input terminal of the margin transfer module
  • the controlled terminal of the first switch circuit is the second controlled terminal of the margin transfer module
  • the first switch circuit The source of the first PMOS tube and the source of the second PMOS tube are interconnected, the drain of the first PMOS tube and the drain of the second PMOS tube are the margin transfer At the output end of the module, the gate of the first PMOS tube and the gate of the second PMOS tube are the output ends of the margin transfer module.
  • the remaining capacity capacitor module includes a first remaining capacity capacitor and a second remaining capacity capacitor of the same capacitance, the first end of the first remaining capacity capacitor and the drain of the first PMOS tube In connection, the first end of the second remaining holding capacitor is connected to the drain of the second PMOS transistor, and the second end of the first remaining holding capacitor and the second remaining holding capacitor are both grounded.
  • the logic control circuit includes a SAR logic controller and a clock generator
  • the clock generator is configured to output a fixed-width pulse signal to the SAR logic controller, so that the SAR logic controller controls the margin transfer module to charge the margin holding capacitor at a first preset time ;as well as
  • the SAR logic controller is configured to output a control signal to control the operation of the sampling switch module, the margin transfer module, the charge sharing switch module, and the reset switch module.
  • the first end of the first DAC capacitor array is connected to the positive input end of the differential analog signal through a switch unit corresponding to the sampling switch module, and the second end of the first DAC capacitor array is The positive output of the differential margin signal of the DAC capacitor array;
  • the first end of the second DAC capacitor array is connected to the negative input terminal of the differential analog signal through a switch unit corresponding to the sampling switch module, and the second end of the second DAC capacitor array is the DAC capacitor array The negative output of the differential margin signal.
  • the capacitance of the first DAC capacitor array is 4 times the capacitance of the first remaining holding capacitor
  • the capacitance of the second DAC capacitor array is the second remaining holding capacitor 4 times the capacitance value.
  • the capacitance of the first remaining holding capacitor is 32 times the equivalent capacitance of the lowest bit of the first DAC capacitor array
  • the capacitance of the second remaining holding capacitor is 32 times the equivalent capacitance of the lowest bit of the second DAC capacitor array.
  • the current rudder is also connected to a digital controller, and the digital controller is configured to control the static working current of the output change of the current rudder so that the gain of the margin transfer module is kept constant.
  • the present application also proposes a gain calibration method configured to perform gain calibration on the margin transfer loop as described above.
  • the gain calibration method includes:
  • the DAC capacitor array is controlled to perform analog-to-digital conversion on the digital charge after the residual transfer is matched with the preset binary code value, and the output current of the current rudder is controlled according to the matching result until the DAC capacitor array is converted The matching of the binary code with the preset binary code.
  • the technical solution of the present application forms a margin transfer loop by using a sampling switch module, a logic control circuit, a margin holding capacitor module, a DAC capacitor array, a margin transfer module, a current rudder, a reset switch module, and a charge sharing switch module.
  • the capacitor array includes a first DAC capacitor array and a second DAC capacitor array forming a differential structure.
  • the current rudder is set to output a static operating current
  • the logic control circuit is set to sequentially output control signals at a preset time interval within a preset period.
  • the reset switch module is based on the control of the logic control circuit to reset the charge of the margin holding capacitor module.
  • the sampling switch module is based on the logic control circuit. Control and start, input the externally input differential analog signal to the DAC capacitor array, so that the DAC capacitor array samples the externally input differential analog signal, and output the differential margin signal.
  • the margin transfer module is set to receive the DAC When the differential margin signal generated on the capacitor array is based on the control of the differential margin signal and the logic control circuit, the static working current generated by the current rudder is output to the margin holding capacitor module for charging, and the charge sharing switch module is based on the logic control circuit Control, after the sampling of the DAC capacitor array is completed, the charge of the margin holding capacitor module and the DAC capacitor array is shared, and a new differential margin signal is generated for the next margin transfer, each transferred differential margin signal The same and accumulated to the next conversion, thereby achieving first-order noise shaping and higher conversion accuracy.
  • FIG. 1 is a schematic diagram of a circuit structure of an embodiment of a residual transfer loop of this application
  • Figure 2 is a schematic diagram of the working sequence of the remaining transfer loop of the application
  • Figure 3 is a schematic diagram of the voltage variation of the residual transfer loop of this application.
  • FIG. 4 is a schematic diagram of the structure of the DAC capacitor array in the margin transfer loop of this application.
  • FIG. 5 is a schematic diagram of the steps of the gain calibration method of the present application.
  • This application proposes a margin transfer loop.
  • FIG. 1 is a schematic diagram of a circuit structure of an embodiment of a residual transfer loop of the application
  • FIG. 2 is a schematic diagram of a working sequence of the residual transfer loop of the application
  • FIG. 3 is a residual transfer loop of the application 4 is a schematic diagram of the structure of the DAC capacitor array in the margin transfer loop of this application.
  • the margin transfer loop includes a sampling switch module, a logic control circuit 80, a margin holding capacitor module 60, and a DAC A capacitor array, a margin transfer module 40, a current rudder 30, a reset switch module 50, and a charge sharing switch module 70;
  • the DAC capacitor array includes a first DAC capacitor array 21 and a second DAC capacitor array 22 that constitute a differential structure;
  • the first end of the sampling switch module inputs differential analog signals, Vip and Vin
  • the second end of the sampling switch module is connected to the first end of the DAC capacitor array, and the second end of the DAC capacitor array
  • the first terminal of the charge sharing switch module 70, the first controlled terminal of the margin transfer module 40 and the input terminal of the comparator 200 are connected.
  • the input terminal of the margin transfer module 40 is connected to the The power supply output terminal is connected, and the output terminal of the margin transfer module 40 is connected to the first terminal of the margin holding capacitor module 60, the second terminal of the charge sharing switch module 70, and the first terminal of the reset switch module 50 End interconnection, the second end of the remaining capacity capacitor module 60 and the second end of the reset switch module 50 are both grounded, the controlled end of the sampling switch module, the second end of the margin transfer module 40
  • the controlled terminal, the controlled terminal of the charge sharing switch module 70 and the controlled terminal of the reset switch module 50 are all connected to the control terminal of the logic control module;
  • the current rudder 30 is set to output a static working current
  • the logic control circuit 80 is configured to sequentially output control signals at a preset time interval within a preset period to control the reset switch module 50, the margin transfer module 40, the sampling switch module and the The charge sharing switch module 70 works sequentially;
  • the reset switch module 50 resets the charge of the remaining capacity capacitor module 60 based on the control of the logic control circuit 80;
  • the sampling switch module based on the control and activation of the logic control circuit 80, inputs an externally input differential analog signal to the DAC capacitor array, so that the DAC capacitor array samples the externally input differential analog signal, And output the differential margin signal;
  • the margin transfer module 40 is configured to, when receiving the differential margin signal generated on the DAC capacitor array, control the current rudder 30 based on the differential margin signal and the control of the logic control circuit 80 The generated static working current is output to charge the remaining capacity capacitor module 60;
  • the charge sharing switch module 70 based on the control of the logic control circuit 80, after the sampling of the DAC capacitor array is completed, the charge of the remaining holding capacitor module 60 and the DAC capacitor array is shared and generated The same differential margin signal performs the next margin transfer.
  • the residual transfer loop is suitable for successive approximation type analog-to-digital converters with arbitrary bit widths.
  • the accuracy of the residual transfer loop determines the conversion accuracy of the analog-to-digital converter.
  • Y (Dout) X (Din) + ⁇ q * (1- Z-1)
  • the error will be multiplied by a high-pass transfer function, so the low-frequency noise will be shaped to high-frequency, and then the high-frequency noise will be filtered through the digital filter to achieve ultra-high accuracy.
  • the current rudder 30 controls the current source with different bit weights by inputting a digital signal sequence.
  • the current rudder 30 is also connected to a digital controller and outputs a preset static working current according to the requirements, for example, output 50uA ⁇ 150uA Static working current in the range.
  • the DAC capacitor array includes a first DAC capacitor array 21 and a second DAC capacitor array 22 forming a differential structure
  • the sampling switch module includes a differential connected to the first DAC capacitor array 21 and the second DAC capacitor array 22 and inputting an external output, respectively
  • the first switch unit 11 and the second switch unit 12 of the analog signal, the first switch unit 11 and the second switch unit 12 respectively include switches equal to the number of capacitors of the first DAC capacitor array 21 and the second DAC capacitor array 22, and the sampling switch
  • the unit is also connected to the reference voltage, and switches correspondingly to conduct sampling according to the control of the logic control signal.
  • the first DAC capacitor array 21 includes a first sub-capacitor array and a second sub-capacitor array that are arranged to form different high and low sections
  • the second DAC capacitor array 22 includes a third sub-capacitor array and a fourth that are arranged to form different high and low sections.
  • a plurality of first capacitor units are sequentially arranged from low to high bits in a binary weighted manner according to capacitance
  • a plurality of second sub-capacitor arrays are sequentially arranged in a binary weighted manner from high to low bits.
  • the first sub-capacitor array and the second The sub-capacitor arrays are arranged in parallel.
  • a plurality of third capacitor units are sequentially arranged in a binary weighted manner from low to high according to capacitance.
  • a plurality of fourth sub-capacitor arrays are sequentially arranged in a binary weighted manner from high to low.
  • the third sub-capacitor array and The fourth sub-capacitor arrays are arranged in parallel.
  • the margin transfer module 40 includes a first PMOS transistor Q2, a second PMOS transistor Q3, and a first switch circuit Q1.
  • the input terminal of the first switch circuit Q1 is the input terminal of the margin transfer module 40.
  • the controlled terminal of the first switching circuit Q1 is the second controlled terminal of the margin transfer module 40, the output terminal of the first switching circuit Q1, the source of the first PMOS transistor Q2, and the second
  • the sources of the PMOS transistor Q3 are interconnected, the drain of the first PMOS transistor Q2 and the drain of the second PMOS transistor Q3 are the output ends of the margin transfer module 40, and the gate of the first PMOS transistor Q2
  • the pole and the gate of the second PMOS transistor Q3 are the output ends of the margin transfer module 40.
  • the first switch circuit Q1 receives the control signal output from the logic control circuit 80 and conducts it.
  • the first PMOS tube Q2 and the second PMOS tube Q3 receive the residual differential signal for bias respectively.
  • the differential margin signal (the difference between Vop and Von) can be output after the different MOS tube and fixed pulse width bias.
  • the offset differential signal (Vrp and Vrn) is required. It is illustrated that the first switch circuit Q1 can use a switch with on-off capability, such as a MOS tube, a triode, etc., which is not specifically limited here.
  • the remaining capacity capacitor module 60 includes a first remaining capacity capacitor C1 and a second remaining capacity capacitor C2 having the same capacitance.
  • the capacitance of the first DAC capacitor array 21 is 4 times the capacitance of the first margin holding capacitor C1
  • the capacitance of the second DAC capacitor array 22 is that of the second margin holding capacitor C2 4 times the capacitance value.
  • the logic control circuit 80 When the margin transfer loop initially works, the logic control circuit 80 outputs a control signal to the reset switch module 50, grounding it, so that the charge on the margin holding capacitor is reset to zero, and then after the last conversion of the analog-to-digital converter ,
  • the differential margin signal (the difference between Vop and Von, ie the error ⁇ q * Z-1) remains on the capacitor array, the differential margin signal is output to the margin transfer module 40, and the margin transfer module 40 receives a The S1 signal with a fixed pulse width of T, at this time, the PMOS tube biased by the differential margin signal will charge the residual holding capacitor module 60. After the elapsed time T, the voltage difference between Vrp and Vrn will be charged.
  • gain is determined by the pulse width of the S1 signal, bias circuit, process parameters and the size of the PMOS tube. Therefore, the static working current of the current rudder 30 can be adjusted by a digital controller to make the gain value fixed.
  • the sampling switch module controlled by the sampling signal will sample the DAC capacitor array this time, and keep the differential analog signal Vip-Vin on the CDAC capacitor array.
  • the sharing signal will be When the charge sharing switch module 70 is turned on, the remaining capacity capacitor module 60 and the DAC capacitor array will share the charge.
  • the voltage on the DAC capacity array and the remaining capacity capacitor module 60 becomes 4/5 * (Vip-Vin) + 1/5 * ⁇ q * z-1 * gain, record 4/5 * (Vip-Vin) as X, the voltage of the DAC capacitor array is X + 1/5 * ⁇ q * z-1 * gain, the value of gain can be fixed to 5 by adjusting the static working current of the current rudder 30, then it is X + ⁇ q * z-1.
  • the technical solution of the present application constitutes a margin transfer by using a sampling switch module, a logic control circuit 80, a margin holding capacitor module 60, a DAC capacitor array, a margin transfer module 40, a current rudder 30, a reset switch module 50, and a charge sharing switch module 70 Loop
  • the DAC capacitor array includes a first DAC capacitor array 21 and a second DAC capacitor array 22 forming a differential structure
  • the current rudder 30 is set to output a static operating current
  • the logic control circuit 80 is set to Control signals are output in sequence at preset time intervals to control the reset switch module 50, the margin transfer module 40, the sampling switch module, and the charge sharing switch module 70 to work in sequence.
  • the reset switch module 50 is based on the control of the logic control circuit 80 to reset the margin
  • the charge of the hold capacitor module 60 is reset, and the sampling switch module is activated based on the control of the logic control circuit 80, and inputs the externally input differential analog signal to the DAC capacitor array, so that the DAC capacitor array samples the externally input differential analog signal, and
  • the differential margin signal is output, and the margin transfer module 40 is configured to, when receiving the differential margin signal generated on the DAC capacitor array, based on the differential margin signal and the control of the logic control circuit 80, operate the static state generated by the current rudder 30
  • the current output charges the remaining capacity capacitor module 60, and the charge sharing switch module 70, based on the control of the logic control circuit 80, shares the charge of the remaining capacity capacitor module 60 and the DAC capacitor array after the sampling of the DAC capacitor array is completed. And generate a new differential margin signal for the next margin transfer, each transferred differential margin signal is the same and accumulated to the next conversion, so as to achieve first-order noise shaping and achieve higher conversion
  • the logic control circuit 80 includes a SAR logic controller (not shown) and a clock generator (not shown);
  • the control end of the SAR logic controller is connected to the controlled end of the sampling switch module, the second controlled end of the margin transfer module 40, the controlled end of the charge sharing switch module 70, and the reset
  • the controlled terminal of the switch module 50 is connected, and the signal terminal of the clock generator is connected to the signal terminal of the SAR logic controller;
  • the clock generator is configured to output a fixed-width pulse signal to the SAR logic controller, so that the SAR logic controller controls the margin transfer module 40 to retain the capacitance for the margin for a first preset time Charge
  • the SAR logic controller is configured to output a control signal to control the sampling switch module, the margin transfer module 40, the charge sharing switch module 70, and the reset switch module 50 to work.
  • the SAR logic controller outputs a reset signal to the reset switch module 50, a sampling signal to the sampling switch module, a charge sharing signal to the charge sharing switch module 70, and a fixed output of the received clock generator within a preset period.
  • the width pulse signal is output to the margin transfer module 40 after the reset signal is output, thereby sequentially implementing charge reset, margin transfer, margin holding capacitor module 60 charging, sampling, and charge sharing.
  • the capacitance of the first remaining holding capacitor C1 is 32 times the equivalent capacitance of the lowest bit of the first DAC capacitor array 21;
  • the capacitance of the second remaining holding capacitor C2 is 32 times the equivalent capacitance of the lowest bit of the second DAC capacitor array 22.
  • the digital-to-analog converter is a 12-bit resolution SAR ADC, including the upper 7 bits and the lower 5 bits.
  • the equivalent capacitance value of the lower 5 bits is 1/32 C .
  • the present application also proposes a successive approximation analog-to-digital converter, which includes a comparator 200, a register connected to the output of the comparator 200, and a margin transfer loop as described above.
  • a successive approximation analog-to-digital converter which includes a comparator 200, a register connected to the output of the comparator 200, and a margin transfer loop as described above.
  • the approximate working process of the successive approximation analog-to-digital converter is given: First, the analog input signal is sampled and held, and sent to one end of the comparator 200, and then the control logic generating circuit 30 presets the highest bit of the register to 1, The bits are all cleared, and the analog-to-digital converter outputs one-half of the reference voltage under the control of the reference voltage and the register and sends it to the other end of the comparator 200. If the analog input signal voltage is greater than half of the reference voltage, the comparator 200 outputs 1, and the highest bit of the register is set to 1; otherwise, if the analog input signal voltage is less than half of the reference voltage, the comparator 200 outputs 0 , The highest bit of the register is set to 0.
  • the highest bit of the successive approximation analog-to-digital converter is determined; and then the next highest bit is determined, that is, the second highest bit of the register is preset first, if the most significant bit determined by the previous conversion cycle is 1, then the modulus
  • the converter outputs three-quarters of the reference voltage, and the analog input signal voltage is compared with the three-quarters of the reference voltage to determine the next highest bit of the register; if the most significant bit determined by the previous conversion cycle is 0, then the modulus
  • the converter outputs a quarter of the reference voltage, and the analog input signal voltage is compared with the quarter of the reference voltage to determine the next highest bit of the register. And so on, until the lowest bit of the register is determined, so that the value of the register is successively approaching the final output of the analog-to-digital converter.
  • the present application also proposes a gain calibration method configured to perform gain calibration on the margin transfer loop as described above.
  • the gain calibration method includes:
  • the DAC capacitor array is controlled to perform analog-to-digital conversion on the digital charge after the residual transfer is matched with the preset binary code value, and the output current of the current rudder 30 is controlled according to the matching result until the DAC capacitor array is converted into digital-to-analog Matches the binary code of the preset binary code.
  • the margin transfer loop does not receive externally input differential analog signals, and sets the signal end of the sampling switch module to receive differential analog signals to zero, and sets the second end of the differential structure DAC capacitor array
  • the common mode level Vcm is reset at the same time, that is, the second terminal voltage Vop and Von of the second terminal of the first DAC capacitor array 21 and the second terminal of the second DAC capacitor array 22 are both Vcm, and all CDAC
  • the switches connected to the first end of the capacitor are all connected to Vrefp (positive reference voltage).
  • Vrefp positive reference voltage
  • the margin holding capacitor module 60 the voltage of the first margin holding capacitor C1 will remain unchanged, and the switch of the second margin holding capacitor C2 Switch to Vrefn (negative reference voltage).
  • the voltage value of the first DAC capacitor array 21 is still Vcm, and the voltage value of the second terminal of the second DAC capacitor array 22 will become Vcm–32LSB. That is, the margin of size 32LSB will be transferred to the next margin transfer and charge sharing, that is, the value of the next conversion is 0 + 32LSB * gain * 1/5.
  • the output result of the digital-to-analog converter compare it with the preset binary code 000000100000. If it is larger, it means that the gain is greater than 5.
  • the output current of the current rudder 30 is reduced. Reduce the gain of the margin transfer module 40 and loop several times until the output of the analog-to-digital converter is not greater than 000000100000. If it is smaller, the adjustment is reversed. In the end, a margin transfer loop with an error within 1 + -3% will be obtained, thus achieving an accuracy of more than 16 bits.

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Abstract

本申请公开一种余量转移环路、逐次逼近型模数转换器和增益校准方法，其中，余量转移环路包括采样开关模块、逻辑控制电路、余量保持电容模块、DAC电容阵列、余量转移模块、电流舵、复位开关模块和电荷共享开关模块，逻辑控制电路在预设周期内按照预设的时间间隔依次输出控制信号，以控制复位开关模块、余量转移模块、采样开关模块和电荷共享开关模块依次工作，从而实现余量转移。

Description

余量转移环路、逐次逼近型模数转换器和增益校准方法
相关申请的交叉引用
本申请要求2018年11月16日申请的，申请号为201811372962.4，名称为“余量转移环路、逐次逼近型模数转换器和增益校准方法”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及半导体集成电路技术领域，特别涉及一种余量转移环路、逐次逼近型模数转换器和增益校准方法。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
噪声整形（sigma-delta noise shaping）逐次逼近模数转换器（SAR ADC）是当前最新流行高精度ADC结构，它的思想基础是将SAR ADC的余量转移到下一次转换，以此提高SARADC的精度到一个更高的层次，同时保留SARADC结构简单功耗低面积小工艺适应度高性能稳定的特点。通常对于12位分辨率的SAR ADC而言，其余量已经低于1mV，将1mV左右的余量实现超高精度的转移，是SAR ADC的重点和难点，因此设计合适的余量转移方式非常有必要。
申请内容
本申请的主要目的是提供一种余量转移环路，旨在实现SAR ADC超高精度的余量转移。
为实现上述目的，本申请提出的一种余量转移环路包括采样开关模块、逻辑控制电路、余量保持电容模块、DAC电容阵列、余量转移模块、电流舵、复位开关模块和电荷共享开关模块；所述DAC电容阵列包括构成差分结构的第一DAC电容阵列和第二DAC电容阵列；
所述采样开关模块的第一端输入差分模拟信号，所述采样开关模块的第二端与所述DAC电容阵列的第一端连接，所述DAC电容阵列的第二端、所述电荷共享开关模块的第一端、所述余量转移模块的第一受控端及比较器的输入端连接，所述余量转移模块的输入端与所述电流舵的电源输出端连接，所述余量转移模块的输出端与所述余量保持电容模块的第一端、所述电荷共享开关模块的第二端及所述复位开关模块的第一端互连，所述余量保持电容模块的第二端及所述复位开关模块的第二端均接地，所述采样开关模块的受控端、所述余量转移模块的第二受控端、所述电荷共享开关模块的受控端及所述复位开关模块的受控端均与所述逻辑控制模块的控制端连接；
所述电流舵，设置为输出静态工作电流；
所述逻辑控制电路，设置为在预设周期内按照预设的时间间隔依次输出控制信号，以控制所述复位开关模块、所述余量转移模块、所述采样开关模块和所述电荷共享开关模块依次工作；
所述复位开关模块，基于所述逻辑控制电路的控制，将所述余量保持电容模块的电荷复位；
所述采样开关模块，基于所述逻辑控制电路的控制并启动，将外部输入的差分模拟信号输入至所述DAC电容阵列，以使所述DAC电容阵列对外部输入的差分模拟信号进行采样，并输出差分余量信号；
所述余量转移模块，设置为在接收到所述DAC电容阵列上产生的差分余量信号时，基于所述差分余量信号和所述逻辑控制电路的控制，将所述电流舵产生的静态工作电流输出给所述余量保持电容模块进行充电；
所述电荷共享开关模块，基于所述逻辑控制电路的控制，在所述DAC电容阵列采样结束后，将所述余量保持电容模块与所述DAC电容阵列的电荷进行共享，并产生相同的差分余量信号进行下一次的余量转移。
可选地，所述余量转移模块包括第一PMOS管、第二PMOS管和第一开关电路；
所述第一开关电路的输入端为所述余量转移模块的输入端，所述第一开关电路的受控端为所述余量转移模块的第二受控端，所述第一开关电路的输出端、所述第一PMOS管的源极及所述第二PMOS管的源极互连，所述第一PMOS管的漏极和所述第二PMOS管的漏极为所述余量转移模块的输出端，所述第一PMOS管的栅极和所述第二PMOS管的栅极为所述余量转移模块的输出端。
可选地，余量保持电容模块包括相同电容量的第一余量保持电容和第二余量保持电容，所述第一余量保持电容的第一端与所述第一PMOS管的漏极连接，所述第二余量保持电容的第一端与所述第二PMOS管的漏极连接，所述第一余量保持电容第二端和所述第二余量保持电容均接地。
可选地，所述逻辑控制电路包括SAR逻辑控制器和时钟生成器；
所述SAR逻辑控制器的控制端分别与所述采样开关模块的受控端、所述余量转移模块的第二受控端、所述电荷共享开关模块的受控端及所述复位开关模块的受控端连接，所述时钟生成器的信号端与所述SAR逻辑控制器的信号端连接；
所述时钟生成器，设置为输出固定宽度脉冲信号至所述SAR逻辑控制器，以使所述SAR逻辑控制器控制所述余量转移模块以第一预设时间为所述余量保持电容充电；
所述SAR逻辑控制器，设置为输出控制信号控制所述采样开关模块、所述余量转移模块、所述电荷共享开关模块及所述复位开关模块工作。
可选地，所述第一DAC电容阵列的第一端通过所述采样开关模块对应的开关单元与所述差分模拟信号的正输入端连接，所述第一DAC电容阵列的第二端为所述DAC电容阵列的差分余量信号的正输出端；
所述第二DAC电容阵列的第一端通过所述采样开关模块对应的开关单元与所述差分模拟信号的负输入端连接，所述第二DAC电容阵列的第二端为所述DAC电容阵列的差分余量信号的负输出端。
可选地，所述第一DAC电容阵列的电容量为所述第一余量保持电容的电容值的4倍，所述第二DAC电容阵列的电容量为所述第二余量保持电容的电容值的4倍。
可选地，所述第一余量保持电容的电容量为所述第一DAC电容阵列的最低位的等效电容量的32倍；
所述第二余量保持电容的电容量为所述第二DAC电容阵列的最低位的等效电容量的32倍。
可选地，所述电流舵还与数字控制器连接，所述数字控制器设置为控制所述电流舵输出变化的静态工作电流，以使所述余量转移模块的增益保持恒定。
本申请还提出一种逐次逼近型模数转换器，包括比较器、连接于所述比较器输出端的寄存器以及余量转移环路，所述余量转移环路包括采样开关模块、逻辑控制电路、余量保持电容模块、DAC电容阵列、余量转移模块、电流舵、复位开关模块和电荷共享开关模块；所述DAC电容阵列包括构成差分结构的第一DAC电容阵列和第二DAC电容阵列；
所述采样开关模块的第一端输入差分模拟信号，所述采样开关模块的第二端与所述DAC电容阵列的第一端连接，所述DAC电容阵列的第二端、所述电荷共享开关模块的第一端、所述余量转移模块的第一受控端及比较器的输入端连接，所述余量转移模块的输入端与所述电流舵的电源输出端连接，所述余量转移模块的输出端与所述余量保持电容模块的第一端、所述电荷共享开关模块的第二端及所述复位开关模块的第一端互连，所述余量保持电容模块的第二端及所述复位开关模块的第二端均接地，所述采样开关模块的受控端、所述余量转移模块的第二受控端、所述电荷共享开关模块的受控端及所述复位开关模块的受控端均与所述逻辑控制模块的控制端连接；
所述电流舵，设置为输出静态工作电流；
所述逻辑控制电路，设置为在预设周期内按照预设的时间间隔依次输出控制信号，以控制所述复位开关模块、所述余量转移模块、所述采样开关模块和所述电荷共享开关模块依次工作；
所述复位开关模块，基于所述逻辑控制电路的控制，将所述余量保持电容模块的电荷复位；
所述采样开关模块，基于所述逻辑控制电路的控制并启动，将外部输入的差分模拟信号输入至所述DAC电容阵列，以使所述DAC电容阵列对外部输入的差分模拟信号进行采样，并输出差分余量信号；
所述余量转移模块，设置为在接收到所述DAC电容阵列上产生的差分余量信号时，基于所述差分余量信号和所述逻辑控制电路的控制，将所述电流舵产生的静态工作电流输出给所述余量保持电容模块进行充电；以及
所述电荷共享开关模块，基于所述逻辑控制电路的控制，在所述DAC电容阵列采样结束后，将所述余量保持电容模块与所述DAC电容阵列的电荷进行共享，并产生相同的差分余量信号进行下一次的余量转移。
可选地，所述余量转移模块包括第一PMOS管、第二PMOS管和第一开关电路；
所述第一开关电路的输入端为所述余量转移模块的输入端，所述第一开关电路的受控端为所述余量转移模块的第二受控端，所述第一开关电路的输出端、所述第一PMOS管的源极及所述第二PMOS管的源极互连，所述第一PMOS管的漏极和所述第二PMOS管的漏极为所述余量转移模块的输出端，所述第一PMOS管的栅极和所述第二PMOS管的栅极为所述余量转移模块的输出端。
可选地，余量保持电容模块包括相同电容量的第一余量保持电容和第二余量保持电容，所述第一余量保持电容的第一端与所述第一PMOS管的漏极连接，所述第二余量保持电容的第一端与所述第二PMOS管的漏极连接，所述第一余量保持电容第二端和所述第二余量保持电容均接地。
可选地，所述逻辑控制电路包括SAR逻辑控制器和时钟生成器；
所述SAR逻辑控制器的控制端分别与所述采样开关模块的受控端、所述余量转移模块的第二受控端、所述电荷共享开关模块的受控端及所述复位开关模块的受控端连接，所述时钟生成器的信号端与所述SAR逻辑控制器的信号端连接；
所述时钟生成器，设置为输出固定宽度脉冲信号至所述SAR逻辑控制器，以使所述SAR逻辑控制器控制所述余量转移模块以第一预设时间为所述余量保持电容充电；以及
所述SAR逻辑控制器，设置为输出控制信号控制所述采样开关模块、所述余量转移模块、所述电荷共享开关模块及所述复位开关模块工作。
可选地，所述第一DAC电容阵列的第一端通过所述采样开关模块对应的开关单元与所述差分模拟信号的正输入端连接，所述第一DAC电容阵列的第二端为所述DAC电容阵列的差分余量信号的正输出端；
所述第二DAC电容阵列的第一端通过所述采样开关模块对应的开关单元与所述差分模拟信号的负输入端连接，所述第二DAC电容阵列的第二端为所述DAC电容阵列的差分余量信号的负输出端。
可选地，所述第一DAC电容阵列的电容量为所述第一余量保持电容的电容值的4倍，所述第二DAC电容阵列的电容量为所述第二余量保持电容的电容值的4倍。
可选地，所述第一余量保持电容的电容量为所述第一DAC电容阵列的最低位的等效电容量的32倍；
所述第二余量保持电容的电容量为所述第二DAC电容阵列的最低位的等效电容量的32倍。
可选地，所述电流舵还与数字控制器连接，所述数字控制器设置为控制所述电流舵输出变化的静态工作电流，以使所述余量转移模块的增益保持恒定。
本申请还提出一种增益校准方法，设置为对如上所述的余量转移环路进行增益校准，所述增益校准方法包括：
将余量转移环路的DAC电容阵列的第一端与参考电压连接，DAC电容阵列的第二端与第二电源连接，外部输入的差分模拟信号置零；
控制第二电源输出电源至DAC电容阵列的第二端，以使DAC电容阵列的第二端复位至共模电平，且使DAC电容阵列产生差分余量信号；
控制DAC电容阵列将产生的差分余量信号经所述余量转移模块余量转移至所述余量保持电容模块；
将余量转移后的数值电荷共享给DAC电容阵列；
控制DAC电容阵列将余量转移后的数值电荷进行模数转换后与预设的二进制码值进行匹配，并根据匹配结果对应控制电流舵的输出电流，直至所述DAC电容阵列数模转换后的二进制码与所述预设的二进制码的匹配。
本申请技术方案通过采用采样开关模块、逻辑控制电路、余量保持电容模块、DAC电容阵列、余量转移模块、电流舵、复位开关模块和电荷共享开关模块组成余量转移环路，所述DAC电容阵列包括构成差分结构的第一DAC电容阵列和第二DAC电容阵列，电流舵设置为输出静态工作电流，逻辑控制电路，设置为在预设周期内按照预设的时间间隔依次输出控制信号，以控制复位开关模块、余量转移模块、采样开关模块和电荷共享开关模块依次工作，复位开关模块基于逻辑控制电路的控制，将余量保持电容模块的电荷复位，采样开关模块基于逻辑控制电路的控制并启动，将外部输入的差分模拟信号输入至DAC电容阵列，以使DAC电容阵列对外部输入的差分模拟信号进行采样，并输出差分余量信号，余量转移模块，设置为在接收到DAC电容阵列上产生的差分余量信号时，基于差分余量信号和逻辑控制电路的控制，将电流舵产生的静态工作电流输出给余量保持电容模块进行充电，电荷共享开关模块，基于逻辑控制电路的控制，在DAC电容阵列采样结束后，将余量保持电容模块与DAC电容阵列的电荷进行共享，并产生新的差分余量信号进行下一次的余量转移，每一转移的差分余量信号相同并累积到下一次的转换，从而实现一阶噪声整形，实现更高的转换精度。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请余量转移环路一实施例的电路结构示意图；
图2为本申请余量转移环路工作时序示意图；
图3为本申请余量转移环路电压变化示意图；
图4为本申请余量转移环路中DAC电容阵列结构示意图；
图5为本申请增益校准方法步骤示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，在本申请中涉及“第一”、“第二”等的描述仅设置为描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，全文中出现的“和/或”的含义为：包括三个并列的方案，以“A/B”为例，包括A方案，或B方案，或A和B同时满足的方案，另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出的一种余量转移环路。
如图1至图4所示，图1为本申请余量转移环路一实施例的电路结构示意图，图2为本申请余量转移环路工作时序示意图，图3为本申请余量转移环路电压变化示意图，图4为本申请余量转移环路中DAC电容阵列结构示意图，本实施例中，余量转移环路包括采样开关模块、逻辑控制电路80、余量保持电容模块60、DAC电容阵列、余量转移模块40、电流舵30、复位开关模块50和电荷共享开关模块70；所述DAC电容阵列包括构成差分结构的第一DAC电容阵列21和第二DAC电容阵列22；
所述采样开关模块的第一端输入差分模拟信号，Vip和Vin，所述采样开关模块的第二端与所述DAC电容阵列的第一端连接，所述DAC电容阵列的第二端、所述电荷共享开关模块70的第一端、所述余量转移模块40的第一受控端及比较器200的输入端连接，所述余量转移模块40的输入端与所述电流舵30的电源输出端连接，所述余量转移模块40的输出端与所述余量保持电容模块60的第一端、所述电荷共享开关模块70的第二端及所述复位开关模块50的第一端互连，所述余量保持电容模块60的第二端及所述复位开关模块50的第二端均接地，所述采样开关模块的受控端、所述余量转移模块40的第二受控端、所述电荷共享开关模块70的受控端及所述复位开关模块50的受控端均与所述逻辑控制模块的控制端连接；
所述电流舵30，设置为输出静态工作电流；
所述逻辑控制电路80，设置为在预设周期内按照预设的时间间隔依次输出控制信号，以控制所述复位开关模块50、所述余量转移模块40、所述采样开关模块和所述电荷共享开关模块70依次工作；
所述复位开关模块50，基于所述逻辑控制电路80的控制，将所述余量保持电容模块60的电荷复位；
所述采样开关模块，基于所述逻辑控制电路80的控制并启动，将外部输入的差分模拟信号输入至所述DAC电容阵列，以使所述DAC电容阵列对外部输入的差分模拟信号进行采样，并输出差分余量信号；
所述余量转移模块40，设置为在接收到所述DAC电容阵列上产生的差分余量信号时，基于所述差分余量信号和所述逻辑控制电路80的控制，将所述电流舵30产生的静态工作电流输出给所述余量保持电容模块60进行充电；
所述电荷共享开关模块70，基于所述逻辑控制电路80的控制，在所述DAC电容阵列采样结束后，将所述余量保持电容模块60与所述DAC电容阵列的电荷进行共享，并产生相同的差分余量信号进行下一次的余量转移。
本实施例中，余量转移环路适用于任意位宽的一阶噪声整形逐次逼近型模数转换器，余量转移环路的精度决定模数转换器的转换精度，余量转移的概念是在每次转换结束之后将产生的误差（∂q=Dout-Din，对于SARADC而言，余量即误差）转移并累加到下一次的采样输入，以此在SARADC的基础上实现一个一阶的sigma-delta调制器的功能，并且由于余量转移环路的存在，Y(Dout)=X(Din)+∂q*（1- Z-1），误差将会乘上一个高通的传输函数，因此低频噪声会被整形到高频，再通过数字滤波器滤掉高频噪声实现超高精度。
需要说明的是，电流舵30是通过输入数字信号序列来控制不同位权电流源产生电流，电流舵30还与数字控制器连接并根据需求输出预设的静态工作电流，例如输出50uA~150uA大小范围内的静态工作电流。
所述DAC电容阵列包括构成差分结构的第一DAC电容阵列21和第二DAC电容阵列22，采样开关模块包括分别与第一DAC电容阵列21和第二DAC电容阵列22连接并输入外部输出的差分模拟信号的第一开关单元11和第二开关单元12，第一开关单元11和第二开关单元12分别包括与第一DAC电容阵列21和第二DAC电容阵列22电容数量相等的开关，采样开关单元还与参考电压连接，并根据逻辑控制信号的控制进行开关对应导通进行采样。
第一DAC电容阵列21包括设置为组成高低不同段位的第一子电容阵列和第二子电容阵列，所述第二DAC电容阵列22包括设置为组成高低不同段位的第三子电容阵列和第四子电容阵列，多个第一电容单元按电容量以二进制加权方式由低位到高位依次设置，多个第二子电容阵列以二进制加权方式由高位到低位依次设置，第一子电容阵列和第二子电容阵列并联设置，多个第三电容单元按电容量以二进制加权方式由低位到高位依次设置，多个第四子电容阵列以二进制加权方式由高位到低位依次设置，第三子电容阵列和所述第四子电容阵列并联设置。
所述余量转移模块40包括第一PMOS管Q2、第二PMOS管Q3和第一开关电路Q1，所述第一开关电路Q1的输入端为所述余量转移模块40的输入端，所述第一开关电路Q1的受控端为所述余量转移模块40的第二受控端，所述第一开关电路Q1的输出端、所述第一PMOS管Q2的源极及所述第二PMOS管Q3的源极互连，所述第一PMOS管Q2的漏极和所述第二PMOS管Q3的漏极为所述余量转移模块40的输出端，所述第一PMOS管Q2的栅极和所述第二PMOS管Q3的栅极为所述余量转移模块40的输出端。
第一开关电路Q1接收逻辑控制电路80输出的控制信号并导通，第一PMOS管Q2、第二PMOS管Q3则分别接收余量差分信号进行偏置，根据MOS管的工作原理可知，MOS管的电压越大，MOS管的输出电流越大，差分余量信号（Vop与Von的差值）经过不同的MOS管和固定脉冲宽度偏置后可输出偏置差分信号（Vrp和Vrn），需要说明的是，第一开关电路Q1可采用具有通断能力的开关、例如MOS管，三极管等，在此不做具体限制。
余量保持电容模块60包括相同电容量的第一余量保持电容C1和第二余量保持电容C2，所述第一余量保持电容C1的第一端与所述第一PMOS管Q2的漏极连接，所述第二余量保持电容C2的第一端与所述第二PMOS管Q3的漏极连接，所述第一余量保持电容C1第二端和所述第二余量保持电容C2均接地。
所述第一DAC电容阵列21的电容量为所述第一余量保持电容C1的电容值的4倍，所述第二DAC电容阵列22的电容量为所述第二余量保持电容C2的电容值的4倍。
余量转移环路初始工作时，逻辑控制电路80输出控制信号至复位开关模块50，使其接地，从而将余量保持电容上的电荷归零，然后在上一次模数转换器的转换结束后，当电容阵列上剩余差分余量信号（Vop与Von的差值，即误差∂q*Z-1）时，差分余量信号输出至余量转移模块40，同时余量转移模块40接收到一个固定脉冲宽度为T的S1信号，此时由差分余量信号偏置的PMOS管将对余量保持电容模块60进行充电，在经过时间为T的时长充电结束后，Vrp和Vrn的电压差将为gain*（Vop-Von），即Vrp-Vrn=∂q* z-1*gain，gain由S1信号的脉冲宽度、偏置电路、工艺参数和PMOS管的尺寸决定，因此，可通过数字控制器调整电流舵30的静态工作电流使gain值固定。
在余量电容模块充电结束后，由sampling信号控制的采样开关模块将对DAC电容阵列将进行本次采样，将差分模拟信号Vip-Vin保持在CDAC电容阵列上，在采样结束之后，sharing信号将电荷共享开关模块70导通，余量保持电容模块60和DAC电容阵列将进行电荷共享，共享结束之后，DAC电容阵列和余量保持电容模块60上电压变为4/5*(Vip-Vin）+1/5*∂q* z-1*gain，将4/5*(Vip-Vin）记为X，DAC电容阵列的电压为X+1/5*∂q* z-1*gain，gain值可以通过调整电流舵30的静态工作电流使其固定为5，则为X+∂q* z-1，此次经过模数转换器的转换，可得Y(Dout)+∂q= X（Din）+∂q*z-1，∂q为转换误差，这个新的余量通过余量转移环路累计到下一次的转换，由于每次转换的余量都会乘以系数1累积到下一次的转换，数模转换器将实现一阶sigma-delta调制器的功能，转换误差将被1阶噪声整形，实现更高的转换精度。
本申请技术方案通过采用采样开关模块、逻辑控制电路80、余量保持电容模块60、DAC电容阵列、余量转移模块40、电流舵30、复位开关模块50和电荷共享开关模块70组成余量转移环路，所述DAC电容阵列包括构成差分结构的第一DAC电容阵列21和第二DAC电容阵列22，电流舵30设置为输出静态工作电流，逻辑控制电路80，设置为在预设周期内按照预设的时间间隔依次输出控制信号，以控制复位开关模块50、余量转移模块40、采样开关模块和电荷共享开关模块70依次工作，复位开关模块50基于逻辑控制电路80的控制，将余量保持电容模块60的电荷复位，采样开关模块基于逻辑控制电路80的控制并启动，将外部输入的差分模拟信号输入至DAC电容阵列，以使DAC电容阵列对外部输入的差分模拟信号进行采样，并输出差分余量信号，余量转移模块40，设置为在接收到DAC电容阵列上产生的差分余量信号时，基于差分余量信号和逻辑控制电路80的控制，将电流舵30产生的静态工作电流输出给余量保持电容模块60进行充电，电荷共享开关模块70，基于逻辑控制电路80的控制，在DAC电容阵列采样结束后，将余量保持电容模块60与DAC电容阵列的电荷进行共享，并产生新的差分余量信号进行下一次的余量转移，每一转移的差分余量信号相同并累积到下一次的转换，从而实现一阶噪声整形，实现更高的转换精度。
在一可选实施例中，所述逻辑控制电路80包括SAR逻辑控制器(图未示出)和时钟生成器(图未示出)；
所述SAR逻辑控制器的控制端分别与所述采样开关模块的受控端、所述余量转移模块40的第二受控端、所述电荷共享开关模块70的受控端及所述复位开关模块50的受控端连接，所述时钟生成器的信号端与所述SAR逻辑控制器的信号端连接；
所述时钟生成器，设置为输出固定宽度脉冲信号至所述SAR逻辑控制器，以使所述SAR逻辑控制器控制所述余量转移模块40以第一预设时间为所述余量保持电容充电；
所述SAR逻辑控制器，设置为输出控制信号控制所述采样开关模块、所述余量转移模块40、所述电荷共享开关模块70及所述复位开关模块50工作。
本实施例中，SAR逻辑控制器在预设周期内分别输出复位信号至复位开关模块50、输出采样信号至采样开关模块、输出电荷共享信号至电荷共享开关模块70以及接收时钟生成器输出的固定宽度脉冲信号并在复位信号输出后输出至余量转移模块40，从而依次实现电荷复位、余量转移、余量保持电容模块60充电、采样以及电荷共享。
在一可选实施例中，所述第一余量保持电容C1的电容量为所述第一DAC电容阵列21的最低位的等效电容量的32倍；
所述第二余量保持电容C2的电容量为所述第二DAC电容阵列22的最低位的等效电容量的32倍。
本实施例中，数模转换器为12位分辨率的SAR ADC，包括高7位和低5位，当第一余量保持电容C1和第二余量保持电容C2的电容量均为1C时，低5位的等效电容值为则为1/32 C。
本申请还提出一种逐次逼近型模数转换器，包括比较器200、连接于所述比较器200输出端的寄存器以及如上所述的余量转移环路，该主题一的具体结构参照上述实施例，由于本逐次逼近型模数转换器采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有技术效果，在此不再一一赘述。
本实施例中给出了逐次逼近型模数转换器的大致工作过程：首先模拟输入信号被采样保持，送入比较器200的一端，然后控制逻辑产生电路30将寄存器最高位预置1，其他位全部清零，模数转换器在参考电压和寄存器的控制下输出参考电压的二分之一送入比较器200的另一端。如果模拟输入信号电压大于参考电压的二分之一，那么比较器200输出1，寄存器最高位定为1；否则，如果模拟输入信号电压小于参考电压的二分之一，那么比较器200输出0，寄存器最高位定为0。这样，逐逐次逼近型模数转换器最高位就确定了；进而再确定次高位，即先预置寄存器次高位为1，如果前一个转换周期确定的最高有效位为1，那么此时模数转换器输出参考电压的四分之三，模拟输入信号电压与参考电压的四分之三比较大小，从而确定寄存器次高位；如果前一个转换周期确定的最高有效位为0，那么此时模数转换器输出参考电压的四分之一，模拟输入信号电压与参考电压的四分之一比较大小，从而确定寄存器次高位。依此类推，直到寄存器的最低位确定为止，这样寄存器的值即逐次逼近型模数转换器的最终输出。
本申请还提出一种增益校准方法，设置为对如上所述的余量转移环路进行增益校准，所述增益校准方法包括：
将余量转移环路的DAC电容阵列的第一端与参考电压连接，DAC电容阵列的第二端与第二电源连接，外部输入的差分模拟信号置零；
控制第二电源输出电源至DAC电容阵列的第二端，以使DAC电容阵列的第二端复位至共模电平，且使DAC电容阵列产生差分余量信号；
控制DAC电容阵列将产生的差分余量信号经所述余量转移模块40余量转移至所述余量保持电容模块60；
将余量转移后的数值电荷共享给DAC电容阵列；
控制DAC电容阵列将余量转移后的数值电荷进行模数转换后与预设的二进制码值进行匹配，并根据匹配结果对应控制电流舵30的输出电流，直至所述DAC电容阵列数模转换后的二进制码与所述预设的二进制码的匹配。
本实施例中，在校准过程中，余量转移环路不接收外部输入的差分模拟信号，并将采样开关模块接收差分模拟信号的信号端置为零，将差分结构DAC电容阵列的第二端被同时复位共模电平Vcm，即此时第一DAC电容阵列21的第二端和第二DAC电容阵列22的第二端的第二端电压Vop，Von的值都是Vcm，并将所有CDAC电容的第一端连接开关都接到Vrefp（正参考电压），对于余量保持电容模块60而言，第一余量保持电容C1的电压将保持不变，第二余量保持电容C2的开关切换到Vrefn（负参考电压），此时第一DAC电容阵列21的电压值仍然是Vcm，第二DAC电容阵列22的第二端的电压值将变为Vcm–32LSB，此次进行余量转移，即此时大小为32LSB的余量将转移到下一次余量转移和电荷共享，即下一次转换的值是0+32LSB*gain*1/5。
根据此时数模转换器的输出结果，将它与预设的二进制码000000100000对比，如果较大则说明gain大于5，通过调整数字控制器的值来降低电流舵30的输出电流，以此来降低余余量转移模块40的增益，循环数次，直到模数转换器的输出不大于000000100000。如果较小则反之调整。最终将得到一个误差在1+-3%以内的余量转移环路，从而实现16bits以上的精度。
以上所述仅为本申请的优选实施例，并非因此限制本申请的专利范围，凡是在本申请的发明构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (17)

  1. 一种余量转移环路，其中，包括采样开关模块、逻辑控制电路、余量保持电容模块、DAC电容阵列、余量转移模块、电流舵、复位开关模块和电荷共享开关模块；所述DAC电容阵列包括构成差分结构的第一DAC电容阵列和第二DAC电容阵列；
    所述采样开关模块的第一端输入差分模拟信号，所述采样开关模块的第二端与所述DAC电容阵列的第一端连接，所述DAC电容阵列的第二端、所述电荷共享开关模块的第一端、所述余量转移模块的第一受控端及比较器的输入端连接，所述余量转移模块的输入端与所述电流舵的电源输出端连接，所述余量转移模块的输出端与所述余量保持电容模块的第一端、所述电荷共享开关模块的第二端及所述复位开关模块的第一端互连，所述余量保持电容模块的第二端及所述复位开关模块的第二端均接地，所述采样开关模块的受控端、所述余量转移模块的第二受控端、所述电荷共享开关模块的受控端及所述复位开关模块的受控端均与所述逻辑控制模块的控制端连接；
    所述电流舵，设置为输出静态工作电流；
    所述逻辑控制电路，设置为在预设周期内按照预设的时间间隔依次输出控制信号，以控制所述复位开关模块、所述余量转移模块、所述采样开关模块和所述电荷共享开关模块依次工作；
    所述复位开关模块，基于所述逻辑控制电路的控制，将所述余量保持电容模块的电荷复位；
    所述采样开关模块，基于所述逻辑控制电路的控制并启动，将外部输入的差分模拟信号输入至所述DAC电容阵列，以使所述DAC电容阵列对外部输入的差分模拟信号进行采样，并输出差分余量信号；
    所述余量转移模块，设置为在接收到所述DAC电容阵列上产生的差分余量信号时，基于所述差分余量信号和所述逻辑控制电路的控制，将所述电流舵产生的静态工作电流输出给所述余量保持电容模块进行充电；以及
    所述电荷共享开关模块，基于所述逻辑控制电路的控制，在所述DAC电容阵列采样结束后，将所述余量保持电容模块与所述DAC电容阵列的电荷进行共享，并产生相同的差分余量信号进行下一次的余量转移。
  2. 如权利要求1所述的余量转移环路，其中，所述余量转移模块包括第一PMOS管、第二PMOS管和第一开关电路；
    所述第一开关电路的输入端为所述余量转移模块的输入端，所述第一开关电路的受控端为所述余量转移模块的第二受控端，所述第一开关电路的输出端、所述第一PMOS管的源极及所述第二PMOS管的源极互连，所述第一PMOS管的漏极和所述第二PMOS管的漏极为所述余量转移模块的输出端，所述第一PMOS管的栅极和所述第二PMOS管的栅极为所述余量转移模块的输出端。
  3. 如权利要求2所述的余量转移环路，其中，余量保持电容模块包括相同电容量的第一余量保持电容和第二余量保持电容，所述第一余量保持电容的第一端与所述第一PMOS管的漏极连接，所述第二余量保持电容的第一端与所述第二PMOS管的漏极连接，所述第一余量保持电容第二端和所述第二余量保持电容均接地。
  4. 如权利要求2所述的余量转移环路，其中，所述逻辑控制电路包括SAR逻辑控制器和时钟生成器；
    所述SAR逻辑控制器的控制端分别与所述采样开关模块的受控端、所述余量转移模块的第二受控端、所述电荷共享开关模块的受控端及所述复位开关模块的受控端连接，所述时钟生成器的信号端与所述SAR逻辑控制器的信号端连接；
    所述时钟生成器，设置为输出固定宽度脉冲信号至所述SAR逻辑控制器，以使所述SAR逻辑控制器控制所述余量转移模块以第一预设时间为所述余量保持电容充电；以及
    所述SAR逻辑控制器，设置为输出控制信号控制所述采样开关模块、所述余量转移模块、所述电荷共享开关模块及所述复位开关模块工作。
  5. 如权利要求3所述的余量转移环路，其中，所述第一DAC电容阵列的第一端通过所述采样开关模块对应的开关单元与所述差分模拟信号的正输入端连接，所述第一DAC电容阵列的第二端为所述DAC电容阵列的差分余量信号的正输出端；
    所述第二DAC电容阵列的第一端通过所述采样开关模块对应的开关单元与所述差分模拟信号的负输入端连接，所述第二DAC电容阵列的第二端为所述DAC电容阵列的差分余量信号的负输出端。
  6. 如权利要求5所述的余量转移环路，其中，所述第一DAC电容阵列的电容量为所述第一余量保持电容的电容值的4倍，所述第二DAC电容阵列的电容量为所述第二余量保持电容的电容值的4倍。
  7. 如权利要求6所述的余量转移环路，其中，所述第一余量保持电容的电容量为所述第一DAC电容阵列的最低位的等效电容量的32倍；
    所述第二余量保持电容的电容量为所述第二DAC电容阵列的最低位的等效电容量的32倍。
  8. 如权利要求7所述的余量转移环路，其中，所述电流舵还与数字控制器连接，所述数字控制器设置为控制所述电流舵输出变化的静态工作电流，以使所述余量转移模块的增益保持恒定。
  9. 一种逐次逼近型模数转换器，其中，包括比较器、连接于所述比较器输出端的寄存器以及余量转移环路，所述余量转移环路包括采样开关模块、逻辑控制电路、余量保持电容模块、DAC电容阵列、余量转移模块、电流舵、复位开关模块和电荷共享开关模块；所述DAC电容阵列包括构成差分结构的第一DAC电容阵列和第二DAC电容阵列；
    所述采样开关模块的第一端输入差分模拟信号，所述采样开关模块的第二端与所述DAC电容阵列的第一端连接，所述DAC电容阵列的第二端、所述电荷共享开关模块的第一端、所述余量转移模块的第一受控端及比较器的输入端连接，所述余量转移模块的输入端与所述电流舵的电源输出端连接，所述余量转移模块的输出端与所述余量保持电容模块的第一端、所述电荷共享开关模块的第二端及所述复位开关模块的第一端互连，所述余量保持电容模块的第二端及所述复位开关模块的第二端均接地，所述采样开关模块的受控端、所述余量转移模块的第二受控端、所述电荷共享开关模块的受控端及所述复位开关模块的受控端均与所述逻辑控制模块的控制端连接；
    所述电流舵，设置为输出静态工作电流；
    所述逻辑控制电路，设置为在预设周期内按照预设的时间间隔依次输出控制信号，以控制所述复位开关模块、所述余量转移模块、所述采样开关模块和所述电荷共享开关模块依次工作；
    所述复位开关模块，基于所述逻辑控制电路的控制，将所述余量保持电容模块的电荷复位；
    所述采样开关模块，基于所述逻辑控制电路的控制并启动，将外部输入的差分模拟信号输入至所述DAC电容阵列，以使所述DAC电容阵列对外部输入的差分模拟信号进行采样，并输出差分余量信号；
    所述余量转移模块，设置为在接收到所述DAC电容阵列上产生的差分余量信号时，基于所述差分余量信号和所述逻辑控制电路的控制，将所述电流舵产生的静态工作电流输出给所述余量保持电容模块进行充电；以及
    所述电荷共享开关模块，基于所述逻辑控制电路的控制，在所述DAC电容阵列采样结束后，将所述余量保持电容模块与所述DAC电容阵列的电荷进行共享，并产生相同的差分余量信号进行下一次的余量转移。
  10. 如权利要求9所述的逐次逼近型模数转换器，其中，所述余量转移模块包括第一PMOS管、第二PMOS管和第一开关电路；
    所述第一开关电路的输入端为所述余量转移模块的输入端，所述第一开关电路的受控端为所述余量转移模块的第二受控端，所述第一开关电路的输出端、所述第一PMOS管的源极及所述第二PMOS管的源极互连，所述第一PMOS管的漏极和所述第二PMOS管的漏极为所述余量转移模块的输出端，所述第一PMOS管的栅极和所述第二PMOS管的栅极为所述余量转移模块的输出端。
  11. 如权利要求10所述的逐次逼近型模数转换器，其中，余量保持电容模块包括相同电容量的第一余量保持电容和第二余量保持电容，所述第一余量保持电容的第一端与所述第一PMOS管的漏极连接，所述第二余量保持电容的第一端与所述第二PMOS管的漏极连接，所述第一余量保持电容第二端和所述第二余量保持电容均接地。
  12. 如权利要求10所述的逐次逼近型模数转换器，其中，所述逻辑控制电路包括SAR逻辑控制器和时钟生成器；
    所述SAR逻辑控制器的控制端分别与所述采样开关模块的受控端、所述余量转移模块的第二受控端、所述电荷共享开关模块的受控端及所述复位开关模块的受控端连接，所述时钟生成器的信号端与所述SAR逻辑控制器的信号端连接；
    所述时钟生成器，设置为输出固定宽度脉冲信号至所述SAR逻辑控制器，以使所述SAR逻辑控制器控制所述余量转移模块以第一预设时间为所述余量保持电容充电；以及
    所述SAR逻辑控制器，设置为输出控制信号控制所述采样开关模块、所述余量转移模块、所述电荷共享开关模块及所述复位开关模块工作。
  13. 如权利要求11所述的逐次逼近型模数转换器，其中，所述第一DAC电容阵列的第一端通过所述采样开关模块对应的开关单元与所述差分模拟信号的正输入端连接，所述第一DAC电容阵列的第二端为所述DAC电容阵列的差分余量信号的正输出端；
    所述第二DAC电容阵列的第一端通过所述采样开关模块对应的开关单元与所述差分模拟信号的负输入端连接，所述第二DAC电容阵列的第二端为所述DAC电容阵列的差分余量信号的负输出端。
  14. 如权利要求13所述的逐次逼近型模数转换器，其中，所述第一DAC电容阵列的电容量为所述第一余量保持电容的电容值的4倍，所述第二DAC电容阵列的电容量为所述第二余量保持电容的电容值的4倍。
  15. 如权利要求14所述的逐次逼近型模数转换器，其中，所述第一余量保持电容的电容量为所述第一DAC电容阵列的最低位的等效电容量的32倍；
    所述第二余量保持电容的电容量为所述第二DAC电容阵列的最低位的等效电容量的32倍。
  16. 如权利要求15所述的逐次逼近型模数转换器，其中，所述电流舵还与数字控制器连接，所述数字控制器设置为控制所述电流舵输出变化的静态工作电流，以使所述余量转移模块的增益保持恒定。
  17. 一种增益校准方法，设置为对如权利要求1至8任意一项所述的余量转移环路进行增益校准，其中，所述增益校准方法包括：
    将余量转移环路的DAC电容阵列的第一端与参考电压连接，DAC电容阵列的第二端与第二电源连接，外部输入的差分模拟信号置零；
    控制第二电源输出电源至DAC电容阵列的第二端，以使DAC电容阵列的第二端复位至共模电平，且使DAC电容阵列产生差分余量信号；
    控制DAC电容阵列将产生的差分余量信号经所述余量转移模块余量转移至所述余量保持电容模块；
    将余量转移后的数值电荷共享给DAC电容阵列；
    控制DAC电容阵列将余量转移后的数值电荷进行模数转换后与预设的二进制码值进行匹配，并根据匹配结果对应控制电流舵的输出电流，直至所述DAC电容阵列数模转换后的二进制码与所述预设的二进制码的匹配。
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