WO2020098091A1 - 显示基板及其制作方法和显示装置 - Google Patents

显示基板及其制作方法和显示装置 Download PDF

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WO2020098091A1
WO2020098091A1 PCT/CN2018/123685 CN2018123685W WO2020098091A1 WO 2020098091 A1 WO2020098091 A1 WO 2020098091A1 CN 2018123685 W CN2018123685 W CN 2018123685W WO 2020098091 A1 WO2020098091 A1 WO 2020098091A1
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layer
gate insulating
substrate
insulating layer
gate
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French (fr)
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葛邦同
付婷婷
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HKC Co Ltd
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HKC Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/23—Cleaning during device manufacture during, before or after processing of insulating materials

Definitions

  • the present application relates to the field of display technology, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
  • liquid crystal display which include a liquid crystal panel and a backlight module.
  • the working principle of the liquid crystal panel is to place liquid crystal molecules in two parallel glass substrates, and apply a driving voltage on the two glass substrates to control the rotation direction of the liquid crystal molecules, so as to refract the light of the backlight module to generate a picture.
  • a thin film transistor liquid crystal display includes a liquid crystal panel and a backlight module.
  • the liquid crystal panel includes a color filter substrate (Color Filter Substrate, CF Substrate, also known as a color filter substrate), a thin film transistor array substrate (Thin Film Transistor Substrate, TFT Substrate) With a mask, there are transparent electrodes on the opposite inner side of the substrate. A layer of liquid crystal molecules (Liquid Crystal, LC) is sandwiched between the two substrates.
  • the stability of TFT devices is particularly important for the stability of products.
  • the threshold voltage is the most important evaluation standard parameter used to evaluate the stability of the device. When the threshold voltage is less than 0, the device has to turn off the TFT device through a very high gate-source voltage negative voltage, affecting the stability of the device.
  • the application provides a display substrate capable of improving device stability, a manufacturing method thereof and a display device.
  • the present application provides a method for manufacturing a display substrate, including the steps of:
  • the method further includes the following steps: performing plasma cleaning on the surface of the second structure layer or the third structure layer.
  • the steps of sequentially stacking and forming the first structure layer, the second structure layer, the third structure layer, the fourth structure layer, and the fifth structure layer on the substrate include:
  • Forming the second structure layer on the gate that is, a gate insulating layer, the gate insulating layer covering the gate;
  • the fourth structure layer including a source electrode and a drain electrode
  • the fifth structure layer is formed on the source electrode and the drain electrode, and the fifth structure layer includes a passivation layer and a transparent electrode layer.
  • ammonia gas is used for ionization to perform plasma cleaning.
  • oxygen is used for ionization to perform plasma cleaning.
  • hydrogen gas is used for the first ionization and the first plasma cleaning is performed; after that, nitrous oxide is used for the second ionization For the second plasma cleaning.
  • hydrogen gas is used for the first ionization and the first plasma cleaning is performed; Oxygen is ionized a second time and plasma cleaned a second time.
  • the steps of sequentially forming the first structural layer, the second structural layer, the third structural layer, the fourth structural layer, and the fifth structural layer on the substrate include:
  • the first structure layer including a source electrode and a drain electrode
  • the fifth structure layer is formed on the gate, and the fifth structure layer includes a passivation layer and a transparent electrode layer.
  • the present application also discloses a display substrate, including: a substrate, and a gate electrode, a gate insulating layer, an active layer, a source electrode, and a drain electrode stacked on the substrate; wherein, the active layer The contact surface with the gate insulating layer is plasma cleaned.
  • the display substrate includes: multiple thin film transistors and multiple pixel electrodes, the multiple pixel electrodes are controlled by corresponding thin film transistor switches, and the thin film transistor switches include the gate, the gate insulating layer, The active layer, the source and the drain, and the contact surface of the active layer and the gate insulating layer of the thin film transistor are plasma cleaned.
  • the plasma includes nitrogen ions and hydrogen ions.
  • the gate is provided on the substrate; the gate insulating layer is provided on the gate; the gate insulating layer has an oxide layer formed after plasma cleaning;
  • the active layer is provided on the gate insulating layer; the source electrode and the drain electrode are provided on both sides of the upper surface of the active layer;
  • the display substrate further includes: a passivation layer and a transparent electrode layer , The passivation layer and the transparent electrode layer are provided on the drain and the source.
  • the plasma is oxygen ions.
  • the thickness of the oxide layer is 1 to 20 angstroms.
  • the source electrode and the drain electrode are provided on the substrate; the active layer is provided on the source electrode and the drain electrode; the active layer is formed by oxidation after plasma cleaning
  • the gate insulating layer is provided on the active layer; the gate is provided on the gate insulating layer; wherein, the display substrate further includes: a passivation layer and a transparent electrode layer; A passivation layer and a transparent electrode layer are provided on the gate.
  • the plasma is oxygen ions.
  • the present application also discloses a display device including a display panel, the display panel including the above-mentioned display substrate.
  • the display substrate is an array substrate
  • the display panel further includes a common substrate, and the common substrate and the array substrate are opposite to each other.
  • the display device is one of a twisted nematic display device, a plane switching display device, and a multi-quadrant vertical alignment display device.
  • the stability of the display substrate device is particularly important for the stability of the product.
  • the threshold voltage is the most important evaluation standard parameter used to evaluate the stability of the device.
  • a large amount of positive charge accumulates at the interface between the gate insulating layer and the active layer of the display substrate to form an internal electric field.
  • the internal electric field will attract channel electrons to form a conductive channel on the gate insulating layer.
  • the device requires a high gate-source voltage and a negative voltage.
  • the display substrate device is turned off, which affects the stability of the device.
  • This solution adopts plasma cleaning to process the contact surface between the gate insulating layer and the active layer, eliminate the positive charge accumulated on the contact surface, reduce the size of the internal electric field formed by the positive charge, and thus improve the stability of the device.
  • FIG. 1 is a schematic view of an untreated ion distribution according to an embodiment of the present application
  • FIG. 2 is a schematic diagram of ion distribution after processing in an embodiment of the present application.
  • FIG. 3 is a flowchart of a method for manufacturing a display panel according to an embodiment of the application.
  • 4a to 4g are schematic diagrams of a display substrate structure according to an embodiment of the present application.
  • FIG. 5 is a flowchart of a method for manufacturing a display panel according to another embodiment of the present application.
  • FIG. 6 is a schematic diagram of a display device according to an embodiment of the application.
  • connection should be understood in a broad sense, for example, it can be fixed connection or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • installation should be understood in a broad sense, for example, it can be fixed connection or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • the display substrate includes a substrate 104, a gate 110, a gate insulating layer 120, and an active layer 130.
  • the gate 110 is disposed on the substrate 104.
  • the gate insulating layer 120 covers the gate 110, and the active layer 130 is disposed on the gate insulating layer 120, wherein the active layer 130 includes: an amorphous silicon layer 131 and a doped layer 132, doped
  • the layer 132 is provided on the amorphous silicon layer 131, and the amorphous silicon layer 131 is provided on the gate insulating layer 120.
  • the contact surface 105 of the gate insulating layer 120 and the active layer 130 accumulates a large amount
  • the positive electric charge forms an internal electric field.
  • the stability of the display substrate device is particularly important for the stability of the product.
  • the threshold voltage is the most important evaluation standard parameter used to evaluate the stability of the device.
  • An embodiment of the present application discloses a method for manufacturing a display substrate.
  • FIG. 2 it is a schematic diagram of ion distribution after plasma cleaning treatment of the present application.
  • the method includes the steps of forming a first structure layer and a The second structure layer, the third structure layer, the fourth structure layer and the fifth structure layer, after forming the second structure layer and before forming the third structure layer, further include the following steps:
  • the surface of the third structural layer is plasma cleaned.
  • This solution uses plasma cleaning to treat the contact surface 105 of the second structure layer (ie, 120 in FIG. 2) and the third structure layer (as in 130 in FIG. 2).
  • FIG. 2 is a schematic diagram of ion distribution after plasma cleaning treatment of the present application.
  • the method includes the steps of forming a first structure layer and a The second structure layer, the third structure layer, the fourth structure layer and the fifth structure layer, after forming the second structure layer and before forming the third structure layer, further include the following steps:
  • the surface of the third structural layer is plasma
  • the contact surface 105 of the second structure layer and the third structure layer of the display substrate in the system accumulates a large amount of positive charges to form an internal electric field, which will attract channel electrons to form a conductive channel on the second structure layer.
  • the negative voltage of the gate-source voltage turns off the display substrate device, which affects the stability of the device.
  • the positive charge accumulated in the contact surface 105 is eliminated, the number of positive charges is significantly reduced, and the size of the internal electric field formed by the positive charge is reduced, thereby improving the stability of the device.
  • the display substrate 101 includes: a substrate 104, and a gate electrode 110, a gate insulating layer 120, an active layer 130, a source electrode and a drain electrode stacked on the substrate 104; wherein, the The active layer 130 includes an amorphous silicon layer 131 and a doped layer 132, and the contact surface 105 of the amorphous silicon layer 131 and the gate insulating layer 120 is plasma cleaned.
  • the display substrate includes: a plurality of thin film transistor switches (Thin Film Transistor, TFT) and a plurality of pixel electrodes, the plurality of pixel electrodes are controlled by corresponding thin film transistor switches, and the thin film transistor switches include the gate The electrode 110, the gate insulating layer 120, the active layer 130, the source and the drain, and the contact surfaces of the active layer and the gate insulating layer of the thin film transistor are plasma cleaned.
  • TFT Thin Film Transistor
  • FIGS. 3 and 4a to 4g a method flow and a corresponding structure diagram of a display substrate are shown.
  • the first structure layer and the second structure layer are sequentially stacked on the substrate
  • the steps of the third structural layer, the fourth structural layer and the fifth structural layer include:
  • S34 forming the third structural layer, that is, the active layer, on the gate insulating layer; wherein the active layer includes an amorphous silicon layer and a doped layer, and the doped layer is disposed on the amorphous silicon layer ;
  • S35 forming the fourth structure layer on the active layer, the fourth structure layer including a source electrode and a drain electrode;
  • the fifth structure layer is formed on the source electrode and the drain electrode.
  • the fifth structure layer includes a passivation layer and a transparent electrode layer.
  • the transparent electrode layer is connected to the drain electrode through a contact hole.
  • This application uses plasma cleaning to treat the surface of the gate insulating layer, eliminate the positive charge accumulated on the contact surface of the active layer and the gate insulating layer, reduce the size of the internal electric field formed by the positive charge, and the threshold voltage is greater than zero, thereby improving the stability of the device Plasma cleaning is performed on the gate insulating layer.
  • the dielectric of the gate insulating layer is more stable, which makes the TFT more stable and has better performance.
  • oxygen ionization is used on the gate insulating layer to form oxygen ions for plasma cleaning.
  • Oxygen ionization is used on the gate insulating layer to form oxygen ions for plasma cleaning.
  • a dense silicon oxide insulating layer can be formed to make the TFT more stable.
  • oxygen ions are negative ions, which can also eliminate the positive accumulation of the interface. Charge, reduce the size of the internal electric field formed by the positive charge, so that the threshold voltage is greater than zero, thereby improving the stability of the device.
  • the gate 110 is disposed on the substrate 104, the gate insulating layer 120 is disposed on the gate 110; the gate insulating layer 120 has oxygen An oxide layer formed after ion cleaning; the active layer 130 is disposed on the gate insulating layer 120: the source electrode 140 and the drain electrode 150 are respectively disposed on both sides of the upper surface of the active layer 130;
  • the display substrate further includes a passivation layer 160 and a transparent electrode layer 170.
  • the passivation layer 160 and the transparent electrode layer 170 are disposed on the drain electrode 150 and the source electrode 140.
  • the active layer 130 includes an amorphous silicon layer 131 and a doped layer 132.
  • the doped layer 132 is disposed on the amorphous silicon layer 131.
  • the thin film transistor is a bottom gate type, and the gate insulating layer 120 is disposed on the gate 110.
  • the thickness of the oxide layer is 1 to 20 angstroms. By controlling the plasma treatment time, the thickness of the oxide layer can be controlled according to the required performance requirements; the selectable range of the thickness of the oxide layer is 1 to 20 angstroms.
  • the gate insulating layer 120 can also be plasma cleaned with other gases such as ammonia or nitrous oxide.
  • Ammonia gas ionization is used on the gate insulating layer to form nitrogen ions and hydrogen ions for plasma cleaning.
  • This solution uses ammonia gas ionization to form nitrogen ions and hydrogen ions for plasma cleaning treatment on the surface of the gate insulating layer, eliminating the positive charge accumulated on the interface between the active layer and the gate insulating layer, reducing the size of the internal electric field formed by the positive charge The voltage is greater than zero, thereby improving the stability of the device.
  • hydrogen gas is first used for ionization to form hydrogen ions for plasma cleaning; then Then, use nitrous oxide or oxygen for the second ionization to form nitrogen ions and oxygen ions or only oxygen ions for plasma cleaning.
  • This solution uses hydrogen ionization to form hydrogen ions for plasma cleaning, which can significantly reduce the size of the internal electric field formed by positive charges; however, too much hydrogen ions remain, which will affect the performance of the TFT and make more porous holes on the surface of the film layer in the subsequent process; Then use nitrous oxide or oxygen for the second plasma cleaning, while further reducing the size of the internal electric field formed by the positive charge, the residual hydrogen ions in the first plasma cleaning step can be further cleaned, so that The performance of the display substrate is more stable.
  • the first structure layer, the second structure layer, the third structure layer, the fourth structure layer, and the first structure layer are sequentially formed on the substrate.
  • the steps of the five structural layers include:
  • S51 forming the first structure layer on the substrate, the first structure layer including a source electrode and a drain electrode;
  • S53 Perform plasma cleaning on the active layer
  • the fifth structural layer includes a passivation layer and a transparent electrode layer.
  • the source electrode and the drain electrode are provided on the substrate; the active layer is provided on the source electrode and the drain electrode; the active layer is formed after being cleaned by oxygen ionization to form oxygen ions An oxide layer; the gate insulating layer is disposed on the active layer; the gate is disposed on the gate insulating layer, wherein the display substrate further includes: a passivation layer and a transparent electrode layer ; The passivation layer and the transparent electrode layer are provided on the gate.
  • this solution uses plasma cleaning to treat the surface of the active layer, which can effectively eliminate the positive charge accumulated on the interface between the active layer and the gate insulating layer, and reduce the size of the internal electric field formed by the positive charge.
  • the threshold voltage is greater than zero, thereby improving the stability of the device.
  • a display device 100 including a display panel 101, the display panel 101 includes a display substrate 102 and a common substrate 103, the common The substrate 103 and the display substrate 102 are opposite to each other.
  • the display substrate is an array substrate.
  • a color filter that is, a color film substrate
  • the film adopts COA (Color Filter Array) technology to set the color filter on the array substrate.
  • the panel of this application can be TN panel (Twisted Nematic, twisted nematic panel), IPS panel (In-Plane Switching, plane switching), VA panel (Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology), of course, also Can be other types of panels, just apply.
  • TN panel Transmission Nematic, twisted nematic panel
  • IPS panel In-Plane Switching, plane switching
  • VA panel Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology

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  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种显示基板（101）及其制作方法和显示装置。显示基板（101）的制作方法包括步骤：依次在衬底（104）上叠加形成第一结构层、第二结构层、第三结构层、第四结构层和第五结构层，在形成第二结构层之后且在形成第三结构层之前，还包括如下步骤：对第二结构层的表面进行等离子体清洗。

Description

显示基板及其制作方法和显示装置
本申请要求于2018年11月14日提交中国专利局，申请号为CN201811350776.0，申请名称为“一种显示基板及其制作方法和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示基板及其制作方法和显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着科技的发展和进步，液晶显示器由于具备机身薄、省电和辐射低等热点而成为显示器的主流产品，得到了广泛应用。市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶面板及背光模组(backlight module)。液晶面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，并在两片玻璃基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。其中，薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)由于具有低的功耗、优异的画面品质以及较高的生产良率等性能，已经逐渐占据了显示领域的主导地位。同样，薄膜晶体管液晶显示器包含液晶面板和背光模组，液晶面板包括彩膜基板(Color Filter Substrate，CF Substrate，也称彩色滤光片基板)、薄膜晶体管阵列基板(Thin Film Transistor Substrate，TFT Substrate)和光罩(Mask)，上述基板的相对内侧存在透明电极。两片基板之间夹一层液晶分子(Liquid Crystal，LC)。
在TFT(Thin Film Transistor，薄膜晶体管)工艺生产流程中，TFT器件稳定对产品稳定性尤为重要。阈值电压是用来评估器件的稳定性最重要的评估标准参数。当阈值电压小于0时，器件得通过很高的栅源电压负电压使TFT器件关闭，影响器件的稳定性。
发明内容
本申请提供一种能提高器件稳定性的显示基板及其制作方法和显示装置。
为实现上述目的，本申请提供了一种显示基板的制作方法，包括步骤：
依次在衬底上叠加形成第一结构层、第二结构层、第三结构层、第四结构层和第五结构层，在形成所述第二结构层之后且在形成第三结构层之前，还包括如下步骤：对所述第二结构层或第三结构层的表面进行等离子体清洗。
可选的，所述依次在衬底上叠加形成第一结构层、第二结构层、第三结构层、第四结构 层和第五结构层的步骤包括：
在所述衬底上形成第一金属层，并将所述第一金属层两侧的区域蚀刻掉，形成所述第一结构层，即栅极；
在所述栅极上形成所述第二结构层，即栅极绝缘层，所述栅极绝缘层覆盖所述栅极；
在所述栅极绝缘层上进行等离子体清洗；
在所述栅极绝缘层上形成所述第三结构层，即有源层；
在所述有源层上形成所述第四结构层，所述第四结构层包括源极和漏极；以及
在所述源极和所述漏极上形成所述第五结构层，所述第五结构层包括钝化层和透明电极层。
可选的，在所述栅极绝缘层上进行等离子体清洗的步骤中，使用氨气进行电离，以进行等离子体清洗。
可选的，在所述栅极绝缘层上进行等离子体清洗的步骤中，使用氧气进行电离，以进行等离子体清洗。
可选的，在所述栅极绝缘层上进行等离子体清洗的步骤中，先使用氢气进行第一次电离，进行第一次等离子体清洗；之后，再用一氧化二氮进行第二次电离，进行第二次等离子体清洗。
可选的，在所述栅极绝缘层上进行等离子体清洗的步骤中，在所述栅极绝缘层上，先使用氢气进行第一次电离，进行第一次等离子体清洗；之后，再用氧气进行第二次电离，进行第二次等离子体清洗。
可选的，所述依次在衬底上形成第一结构层、第二结构层、第三结构层、第四结构层和第五结构层的步骤包括：
在所述衬底上形成所述第一结构层，所述第一结构层包括源极和漏极；
在所述源极和所述漏极上形成所述第二结构层，即有源层；
在所述有源层上进行等离子体清洗；
在所述有源层上形成所述第三结构层，即栅极绝缘层；
在所述栅极绝缘层上形成所述第四结构层，即栅极；以及
在所述栅极上形成所述第五结构层，所述第五结构层包括钝化层和透明电极层。
本申请还公开了一种显示基板，包括：衬底，以及在所述衬底上层叠设置的栅极、栅极绝缘层、有源层、源极和漏极；其中，所述有源层和栅极绝缘层的接触面经等离子体清洗处理。
可选的，所述显示基板包括：多个薄膜晶体管和多个像素电极，所述多个像素电极由对应的薄膜晶体管开关控制，所述薄膜晶体管开关包括所述栅极、栅极绝缘层、有源层、源极 和漏极，所述薄膜晶体管的有源层和栅极绝缘层的接触面经等离子体清洗处理。
可选的，所述等离子体包括氮离子和氢离子。
可选的，所述栅极设置在所述衬底上；所述栅极绝缘层设置在所述栅极上；所述栅极绝缘层有经等离子体清洗后形成的一层氧化层；所述有源层设置在所述栅极绝缘层上；所述源极和漏极，分别设置在有源层的上表面两侧；其中，所述显示基板还包括：钝化层和透明电极层，所述钝化层和透明电极层，设置漏极和源极上。
可选的，所述等离子体为氧离子。
可选的，所述显示基板中，所述氧化层的厚度为1至20埃米。
可选的，所述源极和漏极设置在所述衬底上；所述有源层设置在所述源极和漏极上；所述有源层有经等离子体清洗后形成一层氧化层；所述栅极绝缘层设置在所述有源层上；所述栅极设置在所述栅极绝缘层上；其中，所述显示基板还包括：钝化层和透明电极层；所述钝化层和透明电极层设置在所述栅极上。
可选的，所述等离子体为氧离子。
本申请还公开了一种显示装置，包括显示面板，所述显示面板包括上述的显示基板。
可选的，所述显示基板为阵列基板，所述显示面板还包括公共基板，所述公共基板和所述阵列基板对置。
可选的，所述显示装置为扭曲向列型显示装置、平面转换显示装置和多象限垂直配向显示装置中的一种。
在显示基板工艺生产流程中，显示基板器件稳定对产品稳定性尤为重要。阈值电压是用来评估器件的稳定性最重要的评估标准参数。显示基板的栅极绝缘层与有源层界面积累大量的正电荷形成一个内电场，内电场会吸引沟道电子于栅极绝缘层上形成导电沟道，器件需要很高的栅源电压负电压使显示基板器件关闭，影响器件的稳定性。本方案采用等离子体清洗处理栅极绝缘层和有源层的接触面，消除该接触面积累的正电荷，降低正电荷形成内电场的大小，从而提高器件的稳定性。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请一实施例未经过处理的离子分布示意图；
图2是本申请一实施例经过处理后的离子分布示意图；
图3是本申请一实施例一种显示面板的制作方法流程图；
图4a到图4g是本申请一实施例一种显示基板结构的示意图；
图5是本申请另一实施例一种显示面板的制作方法流程图；
图6是本申请一实施例一种显示装置的示意图。
具体实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
下面结合附图和可选的实施例对本申请作进一步说明。
图1为一种未公开的显示基板的结构示意图，显示基板包括：衬底104、栅极110、栅极绝缘层120以及有源层130，栅极110设置在所述衬底104上，所述栅极绝缘层120覆盖所述栅极110，所述有源层130设置在所述栅极绝缘层120上，其中有源层130包括：非晶 硅层131和掺杂层132，掺杂层132设置在非晶硅层131上，所述非晶硅层131设置在所述栅极绝缘层120上,所述栅极绝缘层120和所述有源层130的接触面105，积累大量的正电荷形成一个内电场。在显示基板工艺生产流程中，显示基板器件稳定对产品稳定性尤为重要。阈值电压是用来评估器件的稳定性最重要的评估标准参数。
而本申请实施例公开了一种显示基板的制作方法，如图2所示为本申请经过等离子体清洗处理后的离子分布示意图，包括步骤：依次在衬底上叠加形成第一结构层、第二结构层、第三结构层、第四结构层和第五结构层，在形成所述第二结构层之后且在形成第三结构层之前，还包括如下步骤：对所述第二结构层或第三结构层的表面进行等离子体清洗。本方案采用等离子体清洗处理第二结构层(即如图2的120)和第三结构层(如图2中的130)的接触面105，相对于未经过处理的方案来说，如图1中的显示基板的第二结构层与第三结构层的接触面105积累大量的正电荷形成一个内电场，内电场会吸引沟道电子于第二结构层上形成导电沟道，器件需要很高的栅源电压负电压使显示基板器件关闭，影响器件的稳定性。而本方案，经过等离子体清洗后，消除该接触面105积累的正电荷，正电荷的数量明显减少，降低正电荷形成内电场的大小，从而提高器件的稳定性。
对应的，所述显示基板101包括：衬底104，以及在所述衬底上104层叠设置的栅极110、栅极绝缘层120、有源层130、源极和漏极；其中，所述有源层130包括非晶硅层131和掺杂层132，所述非晶硅层131和栅极绝缘层120的接触面105经等离子体清洗处理。其中，所述显示基板包括：多个薄膜晶体管开关(Thin Film Transistor，TFT)和多个像素电极，多个所述像素电极，由对应的薄膜晶体管开关控制，所述薄膜晶体管开关包括所述栅极110、栅极绝缘层120、有源层130、源极和漏极，所述薄膜晶体管的有源层和栅极绝缘层的接触面经等离子体清洗处理。
如图3和图4a至图4g所示，示出了显示基板的方法流程和对应的结构图，在一实施例中，所述依次在衬底上叠加形成第一结构层、第二结构层、第三结构层、第四结构层和第五结构层的步骤包括：
S31：在所述衬底上形成第一金属层，并将所述第一金属层两侧的区域蚀刻掉，形成所述第一结构层，即栅极；
S32：在所述栅极上形成所述第二结构层，即栅极绝缘层，所述栅极绝缘层覆盖栅极；
S33：在所述栅极绝缘层上进行等离子体清洗；
S34：在所述栅极绝缘层上形成所述第三结构层，即有源层；其中，所述有源层包括非晶硅层和掺杂层，掺杂层设置在非晶硅层上；
S35：在所述有源层上形成所述第四结构层，所述第四结构层包括源极和漏极；
S36：在所述源极和所述漏极上形成所述第五结构层，所述第五结构层包括钝化层和透 明电极层，透明电极层通过接触孔与漏极连接。
本申请采用等离子体清洗处理栅极绝缘层的表面，消除有源层和栅极绝缘层接触面积累的正电荷，降低正电荷形成内电场的大小，阈值电压大于零，从而提高器件的稳定性；在栅极绝缘层上进行等离子体清洗，相对于在有源层的沟道内进行离子注入，栅极绝缘层的介电性更稳定，使得TFT更稳定，性能更好。
在一实施例中，在所述栅极绝缘层上进行离子注入的步骤中，在所述栅极绝缘层上使用氧气电离形成氧离子进行等离子体清洗。在栅极绝缘层上使用氧气电离形成氧离子进行等离子体清洗，一方面是可以形成致密的氧化硅绝缘层，使TFT的稳定性更好，二是氧离子为负离子同样可以消除界面积累的正电荷，降低正电荷形成内电场的大小，从而使阈值电压大于零，从而提高器件的稳定性。
对应的，所述显示基板中，所述栅极110设置在所述衬底104上，所述栅极绝缘层120设置在所述栅极110上；所述栅极绝缘层120上有经氧离子清洗后形成的一层氧化层；所述有源层130设置在所述栅极绝缘层120上：所述源极140和漏极150，分别设置在有源层130的上表面两侧；所述显示基板还包括钝化层160和透明电极层170，所述钝化层160和透明电极层170，设置在所述漏极150和源极140上。其中，所述有源层130包括非晶硅层131和掺杂层132，掺杂层132设置在非晶硅层131上。所述显示基板中，所述薄膜晶体管为底栅型，所述栅极绝缘层120设置在所述栅极110上。其中，所述显示基板中，所述氧化层的厚度为1至20埃米。通过控制等离子体处理的时间，可以根据需要的性能需求控制所述氧化层的厚度；所述氧化层的厚度的可选范围为1至20埃米。
当然，所述栅极绝缘层120上还可以通过氨气或一氧化二氮等其他气体进行等离子体清洗，在一实施例中，在所述栅极绝缘层上进行离子注入的步骤中，在所述栅极绝缘层上使用氨气电离形成氮离子和氢离子进行等离子体清洗。本方案采用氨气电离形成氮离子和氢离子进行等离子体清洗处理栅极绝缘层的表面，消除有源层和栅极绝缘层接触面积累的正电荷，降低正电荷形成内电场的大小，阈值电压大于零，从而提高器件的稳定性。
或者，在一实施例中，在所述栅极绝缘层上进行等离子体清洗的步骤中，在所述栅极绝缘层上，先使用氢气进行第一次电离形成氢离子进行等离子体清洗；之后，再用一氧化二氮或氧气进行第二次电离，形成氮离子和氧离子或只有氧离子，进行等离子体清洗。本方案先采用氢气电离形成氢离子进行等离子体清洗，可显著降低正电荷形成的内电场大小；但氢离子残留过多，会影响TFT性能，使得后续工艺中膜层表面会形成较多孔洞；之后再使用一氧化二氮或氧气进行第二次等离子体清洗，在进一步降低正电荷形成的内电场大小的同时，还可以对第一次等离子清洗步骤中的残留的氢离子进行进一步清洗，使得显示基板的性能更加稳定。
如图5所示公开了另一实施例的流程图，在一实施例中，所述依次在衬底上形成第一结构层、第二结构层、第三结构层、第四结构层和第五结构层的步骤包括：
S51：在所述衬底上形成所述第一结构层，所述第一结构层包括源极和漏极；
S52：在所述源极和所述漏极上形成所述第二结构层，即有源层；
S53：在所述有源层上进行等离子体清洗；
S54：在所述有源层上形成所述第三结构层，即栅极绝缘层；
S55：在所述栅极绝缘层上形成所述第四结构层，即栅极；以及
S56：在所述栅极上形成所述第五结构层，所述第五结构层包括钝化层和透明电极层。
对应的，所述源极和漏极设置在所述衬底上；所述有源层设置在所述源极和漏极上；所述有源层有经氧气电离形成氧离子清洗后形成的一层氧化层；所述栅极绝缘层设置在所述有源层上；所述栅极设置在所述栅极绝缘层上，其中，所述显示基板还包括：钝化层和透明电极层；所述钝化层和透明电极层设置在所述栅极上。
对于顶栅型的TFT结构，本方案采用等离子体清洗处理有源层的表面，可以很有效的消除有源层和栅极绝缘层接触面积累的正电荷，降低正电荷形成内电场的大小，阈值电压大于零，从而提高器件的稳定性。
作为本申请的另一实施例，如图6为一种显示装置的框图，公开了一种显示装置100，包括显示面板101，所述显示面板101包括显示基板102和公共基板103，所述公共基板103和所述显示基板102对置，所述显示基板为阵列基板，所述公共基,103上可设置彩色滤光片(即彩膜基板)，所述公共基板上也可不设置彩色滤光片，采用COA(Color Filter on Array)技术，将彩色滤光片设置在阵列基板上。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
本申请的面板可以是TN面板(Twisted Nematic，即扭曲向列型面板)、IPS面板(In-PlaneSwitching，平面转换)、VA面板(Multi-domain Vertical Alignment，多象限垂直配向技术)，当然，也可以是其他类型的面板，适用即可。
以上内容是结合具体的可选实施方式对本申请所作的详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (18)

  1. 一种显示基板的制作方法，包括步骤：
    依次在衬底上叠加形成第一结构层、第二结构层、第三结构层、第四结构层和第五结构层，其特征在于:在形成所述第二结构层之后且在形成第三结构层之前，还包括如下步骤:对所述第二结构层或第三结构层的表面进行等离子体清洗。
  2. 如权利要求1所述显示基板的制作方法，其中，所述依次在衬底上叠加形成第一结构层、第二结构层、第三结构层、第四结构层和第五结构层的步骤包括：
    在所述衬底上形成第一金属层，并将所述第一金属层两侧的区域蚀刻掉，形成所述第一结构层，即栅极；
    在所述栅极上形成所述第二结构层，即栅极绝缘层，所述栅极绝缘层覆盖所述栅极；
    在所述栅极绝缘层上进行等离子体清洗；
    在所述栅极绝缘层上形成所述第三结构层，即有源层；
    在所述有源层上形成所述第四结构层，所述第四结构层包括源极和漏极；以及
    在所述源极和所述漏极上形成所述第五结构层，所述第五结构层包括钝化层和透明电极层。
  3. 如权利要求2所述显示基板的制作方法，其中，在所述栅极绝缘层上进行等离子体清洗的步骤中，使用氨气进行电离，以进行等离子体清洗。
  4. 如权利要求2所述显示基板的制作方法，其中，在所述栅极绝缘层上进行等离子体清洗的步骤中，使用氧气进行电离，以进行等离子体清洗。
  5. 如权利要求2所述显示基板的制作方法，其中，在所述栅极绝缘层上进行等离子体清洗的步骤中，先使用氢气进行第一次电离，进行第一次等离子体清洗；之后，再用一氧化二氮进行第二次电离，进行第二次等离子体清洗。
  6. 如权利要求2所述显示基板的制作方法，其中，在所述栅极绝缘层上进行等离子体清洗的步骤中，在所述栅极绝缘层上，先使用氢气进行第一次电离，进行第一次等离子体清洗；之后，再用氧气进行第二次电离，进行第二次等离子体清洗。
  7. 如权利要求1所述显示基板的制作方法，其中，所述依次在衬底上形成第一结构层、第二结构层、第三结构层、第四结构层和第五结构层的步骤包括：
    在所述衬底上形成所述第一结构层，所述第一结构层包括源极和漏极；
    在所述源极和所述漏极上形成所述第二结构层，即有源层；
    在所述有源层上进行等离子体清洗；
    在所述有源层上形成所述第三结构层，即栅极绝缘层；
    在所述栅极绝缘层上形成所述第四结构层，即栅极；以及
    在所述栅极上形成所述第五结构层，所述第五结构层包括钝化层和透明电极层。
  8. 一种显示基板，包括：
    衬底，以及在所述衬底上层叠设置的栅极、栅极绝缘层、有源层、源极和漏极；
    其中，所述有源层和栅极绝缘层的接触面经等离子体清洗处理。
  9. 如权利要求8所述显示基板，其中，所述显示基板包括：
    多个薄膜晶体管开关，以及
    多个像素电极，由对应的薄膜晶体管开关控制；
    所述薄膜晶体管开关包括所述栅极、栅极绝缘层、有源层、源极和漏极，所述薄膜晶体管的有源层和栅极绝缘层的接触面经等离子体清洗处理。
  10. 如权利要求8所述显示基板，其中，所述等离子体包括氮离子和氢离子。
  11. 如权利要求8所述显示基板，其中，
    所述栅极设置在所述衬底上；
    所述栅极绝缘层设置在所述栅极上；
    所述栅极绝缘层有经等离子体清洗后形成一层氧化层；
    所述有源层设置在所述栅极绝缘层上；
    所述源极和漏极，分别设置在所述有源层的上表面两侧；
    其中，所述显示基板还包括：钝化层和透明电极层，所述钝化层和透明电极层设置在所述漏极和源极上。
  12. 如权利要求11所述显示基板，其中，所述等离子体为氧离子。
  13. 如权利要求11所述显示基板，其中，所述显示基板中，所述氧化层的厚度为1至20埃米。
  14. 如权利要求8所述显示基板，其中，
    所述源极和漏极设置在所述衬底上；
    所述有源层设置在所述源极和漏极上；
    所述有源层有经等离子体清洗后形成一层氧化层；
    所述栅极绝缘层设置在所述有源层上；以及
    所述栅极设置在所述栅极绝缘层上；
    其中，所述显示基板还包括：钝化层和透明电极层；所述钝化层和透明电极层设置在所述栅极上。
  15. 如权利要求14所述显示基板，其中，所述等离子体为氧离子。
  16. 一种显示装置，包括显示面板，所述显示面板包括显示基板,所述显示基板包括： 衬底，以及在所述衬底上层叠设置的栅极、栅极绝缘层、有源层、源极和漏极；
    其中，所述有源层和栅极绝缘层的接触面经等离子体清洗处理。
  17. 如权利要求16所述显示装置，其中，所述显示基板为阵列基板，所述显示面板还包括公共基板，所述公共基板和所述阵列基板对置。
  18. 如权利要求16所述显示装置，其中，所述显示装置为扭曲向列型显示装置、平面转换显示装置和多象限垂直配向显示装置中的一种。
PCT/CN2018/123685 2018-11-14 2018-12-26 显示基板及其制作方法和显示装置 Ceased WO2020098091A1 (zh)

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