WO2020097939A1 - 一种误差校正方法及时间交织模数转换器 - Google Patents

一种误差校正方法及时间交织模数转换器 Download PDF

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Publication number
WO2020097939A1
WO2020097939A1 PCT/CN2018/116039 CN2018116039W WO2020097939A1 WO 2020097939 A1 WO2020097939 A1 WO 2020097939A1 CN 2018116039 W CN2018116039 W CN 2018116039W WO 2020097939 A1 WO2020097939 A1 WO 2020097939A1
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value
codewords
adc
preset range
codeword
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PCT/CN2018/116039
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English (en)
French (fr)
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高方
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华为技术有限公司
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Priority to CN201880099458.3A priority Critical patent/CN113016140A/zh
Priority to PCT/CN2018/116039 priority patent/WO2020097939A1/zh
Priority to EP18939896.9A priority patent/EP3872994A4/en
Publication of WO2020097939A1 publication Critical patent/WO2020097939A1/zh
Priority to US17/319,899 priority patent/US11476861B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/0697—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy in time, e.g. using additional comparison cycles
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/0607—Offset or drift compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0624—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0836—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of phase error, e.g. jitter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
    • H03M1/1215—Interleaved, i.e. using multiple converters or converter parts for one channel using time-division multiplexing

Definitions

  • the embodiments of the present application relate to the technical field of electronic circuits, in particular to an error correction method and a time-interleaved analog-to-digital converter.
  • the time interleaved analog-to-digital converter is sampled by multiple parallel analog-to-digital converters (ADC) in an alternating time manner.
  • ADC analog-to-digital converter
  • sampling time mismatch that is, the deviation between the sampling time of two adjacent ADCs deviates from the ideal time deviation .
  • the embodiments of the present application disclose an error correction method and TIADC, which are used to adjust the deviation of sampling time existing between ADCs by adjusting codewords corresponding to ADCs.
  • the first aspect discloses an error correction method applied to a TIADC including multiple ADCs, to determine whether the current value of the codeword of the first ADC among the multiple ADCs is within a preset range, and the first ADC When the current value of the code word is not within the preset range, adjust the multiple code words corresponding to the multiple ADCs one by one, and use the adjusted multiple code words to control the frequency-divided clock circuit to generate and Multiple sampling clocks corresponding to multiple ADCs. It can be seen that, when the current value of the code word of the ADC is not within the preset range, the deviation of the sampling time existing between the ADCs can be adjusted by adjusting the code words corresponding to all ADCs one-to-one.
  • the adjustment value may be determined according to the current values and preset ranges of the multiple codewords, and then the current values of the multiple codewords are adjusted according to the adjustment values, so as to adjust the codewords corresponding to the multiple ADCs After that, it can be ensured that the value of the codeword of the first ADC is within a preset range.
  • half of the difference between the sum of the maximum value and the minimum value of the multiple codewords and the codeword range can be determined as the adjustment value.
  • the code word range is the difference between the maximum value and the minimum value of the preset range.
  • the difference between the maximum value in the multiple codewords and the upper boundary of the preset range may be determined as the adjustment value.
  • the difference between the minimum value in the multiple codewords and the lower boundary of the preset range may be determined as the adjustment value.
  • the difference between the current value of the multiple codewords and the adjusted value can be used as the respective value of the adjusted multiple codewords.
  • the difference between the maximum value in the multiple codewords and the lower boundary of the preset range may be determined as the adjustment value.
  • the difference between the minimum value of the plurality of codewords and the upper boundary of the preset range may be determined as the adjustment value.
  • the current values of the multiple codewords may be added to the adjusted values as respective values of the adjusted multiple codewords.
  • the deviation between the sampling time of the first ADC and the sampling time of the second ADC may be obtained first, and then it is judged whether the deviation has converged, and the first ADC is judged only if the deviation is not converged. Whether the current value of the code word of is within the preset range can avoid unnecessary processing, thereby improving the efficiency of adjusting the deviation of the sampling time existing between ADCs.
  • the second ADC is a reference ADC among multiple ADCs.
  • the codeword corresponding to the first ADC when the current value of the codeword of the first ADC is within a preset range, the codeword corresponding to the first ADC is adjusted according to a preset step size, and the code corresponding to the adjusted first ADC is used Word, control the frequency-divided clock circuit to generate the sampling clock corresponding to the first ADC, so that when the current value of the code word of the first ADC is within the preset range, it can be adjusted by adjusting the code word corresponding to the first ADC There is a deviation in sampling time between ADCs.
  • the preset range may be a deviation range that allows sampling time that exists between multiple ADCs in the analog domain.
  • the frequency-divided clock circuit may be an analog phase locked loop (Phase Locked Loop, PLL).
  • PLL Phase Locked Loop
  • the second aspect discloses a TIADC, which includes multiple ADCs, an error estimation circuit, and a frequency-divided clock circuit.
  • the error estimation circuit is used to determine whether the current value of the codeword of the first ADC among the multiple ADCs is within a preset range, When the current value of the codeword of the first ADC is not within the preset range, adjust the multiple codewords corresponding to the multiple ADCs one-to-one, and send the adjusted multiple codewords to the frequency divider Clock circuit; frequency-divided clock circuit is used to generate multiple sampling clocks corresponding to multiple ADCs one by one by using the adjusted multiple codewords. It can be seen that, when the current value of the code word of the ADC is not within the preset range, the deviation of the sampling time existing between the ADCs can be adjusted by adjusting the code words corresponding to all ADCs one-to-one.
  • the error estimation circuit may first determine the adjustment value according to the current values and preset ranges of the multiple codewords, and then adjust the current values of the multiple codewords according to the adjustment values, so that After the code word is adjusted, it can be ensured that the value of the code word of the first ADC is within a preset range.
  • the error estimation circuit may determine half of the difference between the sum of the maximum value and the minimum value of the plurality of codewords and the range of the codeword as the adjustment value.
  • the code word range is the difference between the maximum value and the minimum value of the preset range.
  • the error estimation circuit may determine the difference between the maximum value in the plurality of codewords and the upper boundary of the preset range as the adjustment value.
  • the error estimation circuit may determine the difference between the minimum value of the plurality of codewords and the lower boundary of the preset range as the adjustment value.
  • the error estimation circuit may use the difference between the current value of the multiple codewords and the adjusted value as the respective value of the adjusted multiple codewords.
  • the error estimation circuit may determine the difference between the maximum value in the multiple codewords and the lower boundary of the preset range as the adjustment value.
  • the error estimation circuit may determine the difference between the minimum value in the plurality of codewords and the upper boundary of the preset range as the adjustment value.
  • the error estimation circuit may add the current values of the multiple codewords to the adjusted values as the respective values of the adjusted multiple codewords.
  • the error estimation circuit is also used to obtain the deviation between the sampling time of the first ADC and the sampling time of the second ADC, to determine whether the deviation has converged, and to determine the first ADC ’s Whether the current value of the codeword is within a preset range can avoid unnecessary processing, thereby improving the efficiency of adjusting the deviation of the sampling time existing between ADCs.
  • the second ADC is a reference ADC among multiple ADCs.
  • the error estimation circuit is also used to adjust the codeword corresponding to the first ADC according to a preset step size when the current value of the codeword of the first ADC is within a preset range, and
  • the codeword of the first ADC is sent to the frequency-divided clock circuit;
  • the frequency-divided clock circuit is also used to generate the sampling clock corresponding to the first ADC using the adjusted codeword corresponding to the first ADC, so that the codeword of the first ADC
  • the deviation of the sampling time existing between the ADCs can be adjusted by adjusting the codeword corresponding to the first ADC.
  • the preset range may be a deviation range that allows sampling time that exists between multiple ADCs in the analog domain.
  • the frequency-divided clock circuit may be an analog PLL.
  • FIG. 1 is a schematic structural diagram of a TIADC disclosed in an embodiment of the present application
  • FIG. 3 is a schematic diagram of codeword adjustment corresponding to an ADC disclosed in an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of another error correction method disclosed in an embodiment of the present application.
  • the embodiments of the present application disclose an error correction method and TIADC, which are used to adjust the deviation of sampling time existing between ADCs by adjusting codewords corresponding to ADCs. The details will be described below.
  • FIG. 1 is a schematic structural diagram of a TIADC disclosed in an embodiment of the present application.
  • the TIADC may include multiple ADCs, error estimation circuits, and frequency-divided clock circuits, where:
  • the error estimation circuit is used to determine whether the current value of the codeword of the first ADC in the plurality of ADCs is within a preset range, and when the current value of the codeword of the first ADC is not within the preset range, Adjust multiple code words corresponding to multiple ADCs one by one, and send the adjusted multiple code words to the frequency-divided clock circuit;
  • the frequency-divided clock circuit is used to respectively generate a plurality of sampling clocks corresponding to a plurality of ADCs by using the adjusted plurality of code words.
  • the output terminals of the frequency-divided clock circuit are respectively coupled to the clock input terminals of multiple ADCs, and the error estimation circuit is respectively coupled to the multiple ADCs and the frequency-divided clock circuits.
  • there is a coupling relationship between two circuits, two devices or circuits and devices that is, there is a connection relationship between two circuits, two devices or circuits and devices, and between two circuits, two Other devices or circuits may or may not be connected between devices or between circuits and devices.
  • the coupling between the error estimation circuit and the frequency-divided clock circuit may be a single-way coupling or a multi-way coupling.
  • one ADC can be selected from multiple ADCs as the reference ADC.
  • the other ADCs are ADCs that need to be calibrated.
  • the ADC that is being calibrated can be called a calibration ADC.
  • the above-mentioned first ADC may be referred to as a correction ADC.
  • the error estimation circuit adjusting multiple code words corresponding to multiple ADCs one-to-one may include:
  • the error estimation circuit determines the adjustment value according to the current values and preset ranges of multiple codewords
  • the error estimation circuit adjusts the current values of the multiple codewords according to the adjustment value.
  • the error estimation circuit determining the adjustment value according to the current value and the preset range of the multiple codewords may include:
  • the error estimation circuit determines the half of the difference between the sum of the maximum value and the minimum value of the multiple code words and the code word range as the adjustment value, where the code word range is the difference between the maximum value and the minimum value of the preset range.
  • the error estimation circuit determining the adjustment value according to the current value and the preset range of the multiple codewords may include:
  • the error estimation circuit determines the difference between the maximum value in the plurality of codewords and the upper boundary of the preset range as the adjustment value.
  • the error estimation circuit determining the adjustment value according to the current value and the preset range of the multiple codewords may include:
  • the error estimation circuit determines the difference between the minimum value of the plurality of code words and the lower boundary of the preset range as the adjustment value.
  • the error estimation circuit adjusts the current values of the multiple codewords according to the adjustment values, including:
  • the error estimation circuit takes the difference between the current value of the multiple codewords and the adjusted value as the value of the adjusted multiple codewords.
  • the error estimation circuit determines the adjustment value according to the current value and the preset range of the multiple codewords, including:
  • the error estimation circuit determines the difference between the maximum value in the plurality of codewords and the lower boundary of the preset range as the adjustment value.
  • the error estimation circuit determines the adjustment value according to the current value and the preset range of the multiple codewords, including:
  • the error estimation circuit determines the difference between the minimum value in the plurality of code words and the upper boundary of the preset range as the adjustment value.
  • the error estimation circuit adjusting the current values of the multiple codewords according to the adjustment value may include:
  • the error estimation circuit adds the current values of the plurality of codewords to the adjusted values as the respective values of the adjusted plurality of codewords.
  • the error estimation circuit is further used to obtain the deviation between the sampling time of the first ADC and the sampling time of the second ADC, to determine whether the deviation has converged, and to determine the deviation only when the deviation has not converged. Whether the current value of an ADC code word is within a preset range.
  • the second ADC is a reference ADC among the multiple ADCs.
  • the error estimation circuit is also used to adjust the codeword corresponding to the first ADC according to the preset step size and send when the current value of the codeword of the first ADC is within a preset range To divide the clock circuit;
  • the frequency-divided clock circuit is also used to generate the sampling clock corresponding to the first ADC by using the adjusted codeword corresponding to the first ADC.
  • the preset range is a deviation range that allows sampling time existing between multiple ADCs in the analog domain.
  • the frequency-divided clock circuit may be an analog PLL.
  • FIG. 2 is a schematic flowchart of an error correction method disclosed in an embodiment of the present application.
  • this error correction method is applied to the TIADC shown in FIG. 1.
  • the error correction method may include the following steps. 201. Determine whether the current value of the codeword of the first ADC is within the preset range. In the case that the current value of the codeword of the first ADC is not within the preset range, perform step 202. If the current value of the codeword is within the preset range, step 203 is executed.
  • the first ADC when it is necessary to correct the deviation of the sampling time existing between the ADCs, it can be determined whether the current value of the codeword of the first ADC among the multiple ADCs is within a preset range, and the first The current value of the codeword of the ADC, and then determine whether the current value of the codeword of the first ADC is within a preset range.
  • the boundary value may or may not be included within the preset range.
  • the first ADC may be any ADC among the ADCs in the plurality of ADCs included in the TIADC that needs to be corrected.
  • the preset range is the deviation range of the sampling time allowed between ADCs in the analog domain.
  • the multiple codewords corresponding to the multiple ADCs may be adjusted first, and then the adjustments are used respectively.
  • the subsequent multiple codewords control the frequency-divided clock circuit to generate multiple sampling clocks one-to-one corresponding to the multiple ADCs, so that the adjusted codeword value of the first ADC is within a preset range.
  • the adjustment value may be determined according to the current values and preset ranges of multiple codewords first, and then the current values of the multiple codewords are adjusted according to the adjustment values.
  • half of the difference between the sum of the maximum value and the minimum value of the multiple codewords and the codeword range can be determined as the adjustment value.
  • the difference between the maximum value in the multiple codewords and the upper boundary of the preset range may also be determined as the adjustment value.
  • the difference between the minimum value of the multiple codewords and the lower boundary of the preset range may also be determined as the adjustment value.
  • the codeword range is the difference between the maximum value and the minimum value of the preset range.
  • the codeword corresponding to the ADC is an array of registers in the ADC.
  • the value of the codeword corresponding to the ADC can be the binary value of the array of registers in the ADC It can also be the decimal value of the array composed of registers in the ADC, or other decimal values of the array composed of registers in the ADC, which is not limited in this embodiment.
  • the difference between the current value of the multiple codewords and the adjustment value can be directly used as the respective value of the adjusted multiple codewords, and then step 201 is executed again.
  • FIG. 3 is a schematic diagram of codeword adjustment corresponding to an ADC disclosed in an embodiment of the present application. Assume that the preset range in FIG. 3 is (0, 128), where 0 is the lower boundary and 128 is the upper boundary.
  • ADC1 is a reference ADC, and the value of its codeword can be constant at 64 and the maximum value among the values of codewords in all ADCs. It can be seen that the code word of ADCN has been decreasing. At time t1, the value of the code word of ADCN is 0. If it is not adjusted, it will exceed the preset range.
  • the code word adjustment of other ADCs is similar to this, and will not be repeated one by one.
  • the difference between the maximum value in multiple codewords and the lower boundary of the preset range may be determined as the adjustment value, and the minimum value in multiple codewords and the upper boundary of the preset range may also be determined. The difference is determined as the adjustment value.
  • the current values of the multiple codewords can be directly added to the adjustment values to obtain the respective values of the adjusted multiple codewords, and then step 201 is executed again.
  • the preset range in FIG. 3 is (0, 128), where 0 is the lower boundary and 128 is the upper boundary.
  • ADC1 is a reference ADC, and the value of its codeword can be constant at 64 and the maximum value among the values of codewords in all ADCs.
  • the code word of ADCN has been decreasing.
  • the codeword corresponding to the first ADC when it is determined that the current value of the codeword of the first ADC is within a preset range, the codeword corresponding to the first ADC may be adjusted according to a preset step size, and then the adjusted first ADC may be used The corresponding codeword controls the frequency-divided clock circuit to generate the sampling clock corresponding to the first ADC.
  • the codeword corresponding to the first ADC is adjusted for the first time in this calibration period, the direction of the codeword corresponding to the first ADC will not be adjusted in which direction will make the sampling time of the first ADC and the sampling time of the second ADC The deviation between them decreases, so you can choose one direction to adjust, that is, you can add a positive value or a negative value.
  • the adjustment of the codeword corresponding to the first ADC may be based on a preset step size, the preset step size is the minimum value of the adjustable codeword, and the absolute value of each adjusted value may be the preset step size, It can also be an integer multiple of the preset step size. For example, when the gap between the deviation and the ideal deviation is large, the adjusted value can be larger, and when the gap between the deviation and the ideal deviation is small, the adjusted value can be smaller.
  • FIG. 4 is a schematic flowchart of another error correction method disclosed in an embodiment of the present application.
  • the error correction method is applied to the TIAD shown in FIG. 1.
  • the error correction method may include the following steps. 401. Obtain a deviation between the sampling time of the first ADC and the sampling time of the second ADC.
  • the deviation between the sampling time of the first ADC and the sampling time of the second ADC may be acquired. It may be that the sampling clock of the first ADC and the sampling clock of the second ADC are obtained first, and then the time between the sampling time of the first ADC and the sampling time of the second ADC is determined according to the sampling clock of the first ADC and the sampling clock of the second ADC deviation.
  • the deviation between the sampling time of the first ADC and the sampling time of the second ADC may also be obtained in other ways, which is not limited in this embodiment.
  • Obtaining the sampling clock of the first ADC and the sampling clock of the second ADC may be obtained by monitoring the working time of the first ADC and the second ADC, or may be obtained by other means, which is not limited in this embodiment.
  • the first ADC is any ADC that needs to be corrected among the multiple ADCs included in the TIADC
  • the second ADC is the reference ADC among the multiple ADCs included in the TIADC. 402. Determine whether the deviation has converged. If the deviation has not converged, go to step 403. If the deviation has converged, go to step 406.
  • step 403 is executed. If the deviation has converged, step 406 is executed.
  • the deviation can be judged based on the deviation and N deviations. N deviations are between the sampling time of the first ADC and the sampling time of the second ADC and are adjacent to the deviation, and N is greater than 1. Integer. Therefore, after the deviation between the sampling time of the first ADC and the sampling time of the second ADC is acquired for the first and second times in this correction period, step 402 does not need to be performed, but step 403 is directly performed.
  • the deviation After acquiring the deviation between the sampling time of the first ADC and the sampling time of the second ADC for the third and subsequent times in this calibration cycle, it is necessary to first determine whether the deviation has converged according to the deviation and N deviations, that is, to determine this N + Whether a deviation fluctuates above and below a certain value, and the fluctuation range is less than the threshold.
  • the deviation is determined to converge, and it is determined that the N + 1 deviations do not fluctuate above or below a certain value, or the fluctuation range If it is greater than or equal to the threshold, it is determined that the deviation has not converged.
  • step 403. Determine whether the current value of the codeword of the first ADC is within the preset range. In the case that the current value of the codeword of the first ADC is not within the preset range, step 404 is executed. If the current value of the code word is within the preset range, step 405 is executed.
  • the preset range is the deviation range of the sampling time allowed between ADCs in the analog domain.
  • the multiple codewords corresponding to the multiple ADCs may be adjusted first, and then the adjustments are used respectively.
  • the subsequent multiple codewords control the frequency-divided clock circuit to generate multiple sampling clocks one-to-one corresponding to the multiple ADCs, so that the adjusted codeword value of the first ADC is within a preset range.
  • the adjustment value may be determined according to the current values and preset ranges of multiple codewords first, and then the current values of the multiple codewords are adjusted according to the adjustment values.
  • half of the difference between the sum of the maximum value and the minimum value of the multiple codewords and the codeword range can be determined as the adjustment value.
  • the difference between the maximum value in the multiple codewords and the upper boundary of the preset range may also be determined as the adjustment value.
  • the difference between the minimum value of the multiple codewords and the lower boundary of the preset range may also be determined as the adjustment value.
  • the codeword range is the difference between the maximum value and the minimum value of the preset range.
  • the codeword corresponding to the ADC is an array of registers in the ADC.
  • the value of the codeword corresponding to the ADC can be the binary value of the array of registers in the ADC It can also be the decimal value of the array composed of registers in the ADC, or other decimal values of the array composed of registers in the ADC, which is not limited in this embodiment.
  • the difference between the current value of the multiple codewords and the adjustment value can be directly used as the respective value of the adjusted multiple codewords, and then step 201 is executed again.
  • FIG. 3 is a schematic diagram of a codeword adjustment disclosed in an embodiment of the present application. Assume that the preset range in FIG. 3 is (0, 128), where 0 is the lower boundary and 128 is the upper boundary.
  • ADC1 is a reference ADC, and the value of its codeword can be constant at 64 and the maximum value among the values of codewords in all ADCs. It can be seen that the code word of ADCN has been decreasing. At time t1, the value of the code word of ADCN is 0. If it is not adjusted, it will exceed the preset range.
  • the code word adjustment of other ADCs is similar to this, and will not be repeated one by one.
  • the difference between the maximum value in multiple codewords and the lower boundary of the preset range may be determined as the adjustment value, and the minimum value in multiple codewords and the upper boundary of the preset range may also be determined. The difference is determined as the adjustment value.
  • the current values of the multiple codewords can be directly added to the adjustment values to obtain the respective values of the adjusted multiple codewords, and then step 201 is executed again.
  • the preset range in FIG. 3 is (0, 128), where 0 is the lower boundary and 128 is the upper boundary.
  • ADC1 is a reference ADC, and the value of its codeword can be constant at 64 and the maximum value among the values of codewords in all ADCs.
  • the code word of ADCN has been decreasing.
  • the codeword corresponding to the first ADC when it is determined that the current value of the codeword of the first ADC is within a preset range, the codeword corresponding to the first ADC may be adjusted according to a preset step size, and then the adjusted first ADC may be used The corresponding codeword controls the frequency-divided clock circuit to generate the sampling clock corresponding to the first ADC.
  • the codeword corresponding to the first ADC is adjusted for the first time in this calibration period, the direction of the codeword corresponding to the first ADC will not be adjusted in which direction will make the sampling time of the first ADC and the sampling time of the second ADC The deviation between them decreases, so you can choose one direction to adjust, that is, you can add a positive value or a negative value.
  • the adjustment of the codeword corresponding to the first ADC may be based on a preset step size, the preset step size is the minimum value of the adjustable codeword, and the absolute value of each adjusted value may be the preset step size, It can also be an integer multiple of the preset step size. For example, when the gap between the deviation and the ideal deviation is large, the adjusted value can be larger, and when the gap between the deviation and the ideal deviation is small, the adjusted value can be smaller.
  • step 401 Determine whether multiple ADCs have been corrected. If multiple ADCs have not been corrected, step 401 is executed.
  • step 401 is executed.

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Abstract

一种误差校正方法及时间交织模数转换器TIADC，该方法应用于包括多个模数转换器ADC的TIADC，包括：判断多个ADC中的第一ADC的码字的当前值是否处在预设范围内；在第一ADC的码字的当前值未处在预设范围内的情况下，对与多个ADC一一对应的多个码字进行调整；分别利用调整后的多个码字，控制分频时钟电路生成与多个ADC一一对应的多个采样时钟。本申请实施例，可以通过调整ADC对应的码字来调整ADC之间存在的采样时间的偏差。

Description

一种误差校正方法及时间交织模数转换器 技术领域
本申请实施例涉及电子电路技术领域，具体涉及一种误差校正方法及时间交织模数转换器。
背景技术
时间交织模数转换器(Time interleaved Analog-to-Digital Converter，TIADC)由多个并行的模数转换器(Analog-to-Digital Converter，ADC)采用时间交替方式进行采样。然而，由于模拟电路不可能做到完全一致，导致各ADC之间存在各种类型的失配，如采样时间失配，即相邻两个ADC的采样时间之间的偏差偏离了理想的时间偏差，导致采样的波形产生失真，以致频谱上产生杂波且无杂散动态范围(Spurious Free Dynamic Range，SFDR)严重恶化。因此，为了保证各ADC的采样时间之间的偏差接近理想偏差，如何调整ADC之间存在的采样时间的偏差成为一个亟待解决的技术问题。
申请内容
本申请实施例公开了一种误差校正方法及TIADC，用于通过调整ADC对应的码字来调整ADC之间存在的采样时间的偏差。
第一方面公开一种误差校正方法，该误差校正方法应用于包括多个ADC的TIADC，判断多个ADC中的第一ADC的码字的当前值是否处在预设范围内，在第一ADC的码字的当前值未处在预设范围内的情况下，对与多个ADC一一对应的多个码字进行调整，分别利用调整后的多个码字，控制分频时钟电路生成与多个ADC一一对应的多个采样时钟。可见，在ADC的码字的当前值未处在预设范围内的情况下，可以通过调整与所有ADC一一对应的码字来调整ADC之间存在的采样时间的偏差。
在一个实施例中，可以先根据多个码字的当前值和预设范围确定调整值，之后根据调整值对多个码字的当前值进行调整，以便在对多个ADC对应的码字调整后，可以保证第一ADC的码字的值处于预设范围内。
在一个实施例中，可以将多个码字中的最大值与最小值之和与码字量程的差值的一半确定为调整值。其中，码字量程为预设范围的最大值与最小值的差值。
在一个实施例中，可以将多个码字中的最大值与预设范围的上边界的差值确定为调整值。
在一个实施例中，可以将多个码字中的最小值与预设范围的下边界的差值确定为调整值。
在一个实施例中，可以分别将多个码字的当前值与调整值的差值作为调整后的多个码字各自的值。
在一个实施例中，可以将多个码字中的最大值与预设范围的下边界的差值确定为调整值。
在一个实施例中，可以将多个码字中的最小值与预设范围的上边界的差值确定为调整 值。
在一个实施例中，可以分别将多个码字的当前值加上调整值作为调整后的多个码字各自的值。
在一个实施例中，可以先获取第一ADC的采样时间与第二ADC的采样时间之间的偏差，之后判断该偏差是否收敛，在判断出该偏差未收敛的情况下，才判断第一ADC的码字的当前值是否处在预设范围内，可以避免不必要的处理过程，从而可以提高调整ADC之间存在的采样时间的偏差效率。其中，第二ADC为多个ADC中的参考ADC。
在一个实施例中，在第一ADC的码字的当前值处于预设范围内的情况下，根据预设步长调整第一ADC对应的码字，并利用调整后的第一ADC对应的码字，控制分频时钟电路生成第一ADC对应的采样时钟，以便在第一ADC的码字的当前值处在预设范围内的情况下，可以通过调整与第一ADC对应的码字来调整ADC之间存在的采样时间的偏差。
在一个实施例中，预设范围可以为在模拟域允许多个ADC之间存在的采样时间的偏差范围。
在一个实施例中，分频时钟电路可以为模拟锁相环(Phase Locked Loop，PLL)。
第二方面公开一种TIADC，包括多个ADC、误差估计电路和分频时钟电路，误差估计电路用于判断多个ADC中的第一ADC的码字的当前值是否处在预设范围内，在第一ADC的码字的当前值未处在预设范围内的情况下，对与多个ADC一一对应的多个码字进行调整，并将调整后的多个码字发送给分频时钟电路；分频时钟电路用于分别利用调整后的多个码字生成与多个ADC一一对应的多个采样时钟。可见，在ADC的码字的当前值未处在预设范围内的情况下，可以通过调整与所有ADC一一对应的码字来调整ADC之间存在的采样时间的偏差。
在一个实施例中，误差估计电路可以先根据多个码字的当前值和预设范围确定调整值，之后根据调整值对多个码字的当前值进行调整，以便在对多个ADC对应的码字调整后，可以保证第一ADC的码字的值处于预设范围内。
在一个实施例中，误差估计电路可以将多个码字中的最大值与最小值之和与码字量程的差值的一半确定为调整值。其中，码字量程为预设范围的最大值与最小值的差值。
在一个实施例中，误差估计电路可以将多个码字中的最大值与预设范围的上边界的差值确定为调整值。
在一个实施例中，误差估计电路可以将多个码字中的最小值与预设范围的下边界的差值确定为调整值。
在一个实施例中，误差估计电路可以分别将多个码字的当前值与调整值的差值作为调整后的多个码字各自的值。
在一个实施例中，误差估计电路可以将多个码字中的最大值与预设范围的下边界的差值确定为调整值。
在一个实施例中，误差估计电路可以将多个码字中的最小值与预设范围的上边界的差值确定为调整值。
在一个实施例中，误差估计电路可以分别将多个码字的当前值加上调整值作为调整后 的多个码字各自的值。
在一个实施例中，误差估计电路还用于获取第一ADC的采样时间与第二ADC的采样时间之间的偏差，判断偏差是否收敛，在偏差未收敛的情况下，才判断第一ADC的码字的当前值是否处在预设范围内，可以避免不必要的处理过程，从而可以提高调整ADC之间存在的采样时间的偏差效率。其中，第二ADC为多个ADC中的参考ADC。
在一个实施例中，误差估计电路还用于在第一ADC的码字的当前值处在预设范围内的情况下，根据预设步长调整第一ADC对应的码字，并将调整后的第一ADC的码字发送给分频时钟电路；分频时钟电路还用于利用调整后的第一ADC对应的码字生成第一ADC对应的采样时钟，以便在第一ADC的码字的当前值处在预设范围内的情况下，可以通过调整与第一ADC对应的码字来调整ADC之间存在的采样时间的偏差。
在一个实施例中，预设范围可以为在模拟域允许多个ADC之间存在的采样时间的偏差范围。
在一个实施例中，分频时钟电路可以为模拟PLL。
附图说明
图1是本申请实施例公开的一种TIADC的结构示意图；
图2是本申请实施例公开的一种误差校正方法的流程示意图；
图3是本申请实施例公开的一种ADC对应的码字调整示意图；
图4是本申请实施例公开的另一种误差校正方法的流程示意图。
具体实施方式
本申请实施例公开了一种误差校正方法及TIADC，用于通过调整ADC对应的码字来调整ADC之间存在的采样时间的偏差。以下进行详细说明。
请参阅图1，图1是本申请实施例公开的一种TIADC的结构示意图。如图1所示，该TIADC可以包括多个ADC、误差估计电路和分频时钟电路，其中：
误差估计电路，用于判断多个ADC中的第一ADC的码字的当前值是否处在预设范围内，在第一ADC的码字的当前值未处在预设范围内的情况下，对与多个ADC一一对应的多个码字进行调整，并将调整后的多个码字发送给分频时钟电路；
分频时钟电路，用于分别利用调整后的多个码字生成与多个ADC一一对应的多个采样时钟。
本实施例中，分频时钟电路的输出端分别耦合多个ADC的时钟输入端，误差估计电路分别耦合多个ADC和分频时钟电路。其中，两个电路之间、两个器件之间或电路与器件之间耦合，即两个电路之间、两个器件之间或电路与器件之间存在连接关系，且两个电路之间、两个器件之间或电路与器件之间可以接入其它器件或电路，也可以不接入其它器件或电路。误差估计电路与分频时钟电路之间的耦合可以为单路耦合，也可以为多路耦合。在对TIADC中的ADC的采样时间之间的偏差进行校正时，可以从多个ADC中任选一个ADC作为参考ADC，其它ADC为需要校正的ADC，正在校正的ADC可以称为校正ADC。上 述第一ADC可以称为校正ADC。
作为一种可能的实施方式，误差估计电路对与多个ADC一一对应的多个码字进行调整可以包括：
误差估计电路根据多个码字的当前值和预设范围确定调整值；
误差估计电路根据调整值对多个码字的当前值进行调整。
作为一种可能的实施方式，误差估计电路根据多个码字的当前值和预设范围确定调整值可以包括：
误差估计电路将多个码字中的最大值与最小值之和与码字量程的差值的一半确定为调整值，其中，码字量程为预设范围的最大值与最小值的差值。
作为一种可能的实施方式，误差估计电路根据多个码字的当前值和预设范围确定调整值可以包括：
误差估计电路将多个码字中的最大值与预设范围的上边界的差值确定为调整值。
作为一种可能的实施方式，误差估计电路根据多个码字的当前值和预设范围确定调整值可以包括：
误差估计电路将多个码字中的最小值与预设范围的下边界的差值确定为调整值。
作为一种可能的实施方式，误差估计电路根据调整值对多个码字的当前值进行调整，包括：
误差估计电路分别将多个码字的当前值与调整值的差值作为调整后的多个码字各自的值。
作为一种可能的实施方式，误差估计电路根据多个码字的当前值和预设范围确定调整值，包括：
误差估计电路将多个码字中的最大值与预设范围的下边界的差值确定为调整值。
作为一种可能的实施方式，误差估计电路根据多个码字的当前值和预设范围确定调整值，包括：
误差估计电路将多个码字中的最小值与预设范围的上边界的差值确定为调整值。
作为一种可能的实施方式，误差估计电路根据调整值对多个码字的当前值进行调整可以包括：
误差估计电路分别将多个码字的当前值加上调整值作为调整后的多个码字各自的值。
作为一种可能的实施方式，误差估计电路，还用于获取第一ADC的采样时间与第二ADC的采样时间之间的偏差，判断偏差是否收敛，在偏差未收敛的情况下，才判断第一ADC的码字的当前值是否处在预设范围内。其中，第二ADC为所述多个ADC中的参考ADC。
作为一种可能的实施方式，误差估计电路，还用于在第一ADC的码字的当前值处在预设范围内的情况下，根据预设步长调整第一ADC对应的码字并发送给分频时钟电路；
分频时钟电路，还用于利用调整后的第一ADC对应的码字生成第一ADC对应的采样时钟。
作为一种可能的实施方式，预设范围为在模拟域允许多个ADC之间存在的采样时间的偏差范围。
作为一种可能的实施方式，分频时钟电路可以为模拟PLL。
请参阅图2，图2是本申请实施例公开的一种误差校正方法的流程示意图。其中，该误差校正方法应用于图1所示的TIADC。如图2所示，该误差校正方法可以包括以下步骤。201、判断第一ADC的码字的当前值是否处在预设范围内，在第一ADC的码字的当前值未处在预设范围内的情况下，执行步骤202，在第一ADC的码字的当前值处在预设范围内的情况下，执行步骤203。
本实施例中，当需要对ADC之间存在的采样时间的偏差进行校正时，可以判断多个ADC中的第一ADC的码字的当前值是否处在预设范围内，可以先获取第一ADC的码字的当前值，之后判断第一ADC的码字的当前值是否处于预设范围内。处于预设范围内可以包括边界值，也可以不包括边界值。其中，第一ADC可以为TIADC包括的多个ADC中需要校正的ADC中的任一ADC。其中，预设范围为模拟域允许ADC之间存在的采样时间的偏差范围。
202、对与多个ADC一一对应的多个码字进行调整，并分别利用调整后的多个码字控制分频时钟电路生成与多个ADC一一对应的多个采样时钟。
本实施例中，在判断出第一ADC的码字的当前值未处在预设范围内的情况下，可以先对与多个ADC一一对应的多个码字进行调整，之后分别利用调整后的多个码字控制分频时钟电路生成与多个ADC一一对应的多个采样时钟，以便调整后的第一ADC的码字的值处于预设范围内。可以先根据多个码字的当前值和预设范围确定调整值，之后根据调整值对多个码字的当前值进行调整。
本实施例中，可以将多个码字中的最大值与最小值之和与码字量程的差值的一半确定为调整值。也可以将多个码字中的最大值与预设范围的上边界的差值确定为调整值。还可以将多个码字中的最小值与预设范围的下边界的差值确定为调整值。其中，码字量程为预设范围的最大值与最小值的差值，ADC对应的码字为ADC中寄存器组成的数组，ADC对应的码字的值可以为ADC中寄存器组成的数组的二进制值，也可以为ADC中寄存器组成的数组的十进制值，还可以为ADC中寄存器组成的数组的其它进制值，本实施例不作限定。在确定出调整值之后，可以直接分别将多个码字的当前值与调整值的差值作为调整后的多个码字各自的值，之后再次执行步骤201。请参阅图3，图3是本申请实施例公开的一种ADC对应的码字调整示意图。假设图3中的预设范围为(0，128)，其中，0是下边界，128是上边界。ADC1为参考ADC，其码字的值可以恒定为64且为所有ADC中码字的值中的最大值。可以看到，ADCN的码字一直处于减小趋势，在t1时刻，ADCN的码字的值为0，如果不调整，将会超出预设范围。因此，根据本申请的方案，可以将多个ADC的码字中的最大值与最小值的和与码字量程之差的一半作为调整值Δ，即Δ＝((64+0)-128)/2＝-32；将各个ADC的码字在t1时刻的值减去调整值，得到各个ADC的码字在t2时刻的值，可以看到，在t2时刻，ADC1的码字的值为64-(-32)＝96，ADCN的码字的值为0-(-32)＝32，其它ADC的码字调整与此类似，不一一赘述。也可以将多个码字中的最大值与预设范围的上边界的差值确定为调整值Δ，即Δ＝64-128＝-64；将各个ADC的码字在t1时刻的值减去调整值，得到各个ADC的码字在t2时刻的值，可以看到，在t2时刻，ADC1的码字的值为64-(-64)＝128，ADCN 的码字的值为0-(-64)＝64，其它ADC的码字调整与此类似，不一一赘述。
本实施例中，也可以将多个码字中的最大值与预设范围的下边界的差值确定为调整值，还可以将多个码字中的最小值与预设范围的上边界的差值确定为调整值。在确定出调整值之后，可以直接分别将多个码字的当前值加上调整值得到调整后的多个码字各自的值，之后再次执行步骤201。假设图3中的预设范围为(0，128)，其中，0是下边界，128是上边界。ADC1为参考ADC，其码字的值可以恒定为64且为所有ADC中码字的值中的最大值。可以看到，ADCN的码字一直处于减小趋势，在t1时刻，ADCN的码字的值为0，如果不调整，将会超出预设范围。因此，根据本申请的方案，可以将多个码字中的最大值与预设范围的下边界的差值确定为调整值Δ，即Δ＝64-0＝64；将各个ADC的码字在t1时刻的值加上调整值，得到各个ADC的码字在t2时刻的值，可以看到，在t2时刻，ADC1的码字的值为64+64＝128，ADCN的码字的值为0+64＝64，其它ADC的码字调整与此类似，不一一赘述。
203、根据预设步长调整第一ADC对应的码字，并利用调整后的第一ADC对应的码字控制分频时钟电路生成第一ADC对应的采样时钟。
本实施例中，在判断出第一ADC的码字的当前值处于预设范围内的情况下，可以先根据预设步长调整第一ADC对应的码字，之后利用调整后的第一ADC对应的码字控制分频时钟电路生成第一ADC对应的采样时钟。在本校正周期中第一次对第一ADC对应的码字进行调整时，由于不知道往哪个方向调整第一ADC对应的码字会使第一ADC的采样时间与第二ADC的采样时间之间的偏差减小，因此，可以任选一个方向进行调整，即可以是加一个正值，也可以是加一个负值。在本校正周期中第二次对第一ADC对应的码字进行调整时，可以先判断第一ADC的采样时间与第二ADC的采样时间之间的第二次偏差是否小于第一次偏差，在判断出第二次偏差小于第一次偏差的情况下，继续沿着原来的方向进行码字调整；在判断第二次偏差大于第一次偏差的情况下，沿着反方向进行码字调整。其中，第一ADC对应的码字的调整可以是基于预设步长进行的，预设步长为可以调整的码字的最小值，每次调整的值的绝对值可以是预设步长，也可以是预设步长的整数倍。例如，在偏差与理想偏差之间的差距较大的情况下，调整的值可以大一点，在偏差与理想偏差之间的差距较小的情况下，调整的值可以小一点。
请参阅图4，图4是本申请实施例公开的另一种误差校正方法的流程示意图。其中，该误差校正方法应用于图1所示的TIAD。如图4所示，该误差校正方法可以包括以下步骤。401、获取第一ADC的采样时间与第二ADC的采样时间之间的偏差。
本实施例中，当需要对ADC之间存在的采样时间的偏差进行校正时，可以获取第一ADC的采样时间与第二ADC的采样时间之间的偏差。可以是先获取第一ADC的采样时钟和第二ADC的采样时钟，之后根据第一ADC的采样时钟和第二ADC的采样时钟确定第一ADC的采样时间与第二ADC的采样时间之间的偏差。也可以通过其它方式获取第一ADC的采样时间与第二ADC的采样时间之间的偏差，本实施例不作限定。获取第一ADC的采样时钟和第二ADC的采样时钟，可以通过监测第一ADC和第二ADC的工作时间来获取，也可以通过其它方式来获取，本实施例不作限定。其中，第一ADC是TIADC包括的多个ADC中需要校正的任一ADC，第二ADC为TIADC包括的多个ADC中的参考ADC。 402、判断偏差是否收敛，在偏差未收敛的情况下，执行步骤403，在偏差收敛的情况下，执行步骤406。
本实施例中，获取到第一ADC的采样时间与第二ADC的采样时间之间的偏差之后，可以先判断偏差是否收敛，在判断出偏差未收敛的情况下，执行步骤403，在判断出偏差收敛的情况下，执行步骤406。可以根据该偏差与N个偏差判断该偏差是否收敛，N个偏差为第一ADC的采样时间与第二ADC的采样时间之间的，且与该偏差相邻的偏差，且N为大于1的整数。因此，在本校正周期中第一次和第二次获取到第一ADC的采样时间与第二ADC的采样时间之间的偏差之后，不需要执行步骤402，而是直接执行步骤403。在本校正周期第三次及之后获取到第一ADC的采样时间与第二ADC的采样时间之间的偏差之后，需要先根据该偏差与N个偏差判断该偏差是否收敛，即判断这N+1个偏差是否在某个值上下波动，且波动范围小于阈值。在判断出这N+1个偏差在某个值上下波动，且波动范围小于阈值的情况下，确定该偏差收敛，在判断出这N+1个偏差未在某个值上下波动，或波动范围大于或等于阈值的情况下，确定该偏差未收敛。
403、判断的第一ADC的码字的当前值是否处在预设范围内，在第一ADC的码字的当前值未处在预设范围内的情况下，执行步骤404，在第一ADC的码字的当前值处在预设范围内的情况下，执行步骤405。
本实施例中，在判断出偏差未收敛的情况下，判断多个ADC中的第一ADC的码字的当前值是否处在预设范围内，可以先获取第一ADC的码字的当前值，之后判断第一ADC的码字的当前值是否处于预设范围内。处于预设范围内可以包括边界值，也可以不包括边界值。其中，预设范围为模拟域允许ADC之间存在的采样时间的偏差范围。
404、对与多个ADC一一对应的多个码字进行调整，并分别利用调整后的多个码字控制分频时钟电路生成与多个ADC一一对应的多个采样时钟。
本实施例中，在判断出第一ADC的码字的当前值未处在预设范围内的情况下，可以先对与多个ADC一一对应的多个码字进行调整，之后分别利用调整后的多个码字控制分频时钟电路生成与多个ADC一一对应的多个采样时钟，以便调整后的第一ADC的码字的值处于预设范围内。可以先根据多个码字的当前值和预设范围确定调整值，之后根据调整值对多个码字的当前值进行调整。
本实施例中，可以将多个码字中的最大值与最小值之和与码字量程的差值的一半确定为调整值。也可以将多个码字中的最大值与预设范围的上边界的差值确定为调整值。还可以将多个码字中的最小值与预设范围的下边界的差值确定为调整值。其中，码字量程为预设范围的最大值与最小值的差值，ADC对应的码字为ADC中寄存器组成的数组，ADC对应的码字的值可以为ADC中寄存器组成的数组的二进制值，也可以为ADC中寄存器组成的数组的十进制值，还可以为ADC中寄存器组成的数组的其它进制值，本实施例不作限定。在确定出调整值之后，可以直接分别将多个码字的当前值与调整值的差值作为调整后的多个码字各自的值，之后再次执行步骤201。请参阅图3，图3是本申请实施例公开的一种码字调整示意图。假设图3中的预设范围为(0，128)，其中，0是下边界，128是上边界。ADC1为参考ADC，其码字的值可以恒定为64且为所有ADC中码字的值中的最大值。可以看到，ADCN的码字一直处于减小趋势，在t1时刻，ADCN的码字的值为0，如果不调整，将会超 出预设范围。因此，根据本申请的方案，可以将多个ADC的码字中的最大值与最小值的和与码字量程之差的一半作为调整值Δ，即Δ＝((64+0)-128)/2＝-32；将各个ADC的码字在t1时刻的值减去调整值，得到各个ADC的码字在t2时刻的值，可以看到，在t2时刻，ADC1的码字的值为64-(-32)＝96，ADCN的码字的值为0-(-32)＝32，其它ADC的码字调整与此类似，不一一赘述。也可以将多个码字中的最大值与预设范围的上边界的差值确定为调整值Δ，即Δ＝64-128＝-64；将各个ADC的码字在t1时刻的值减去调整值，得到各个ADC的码字在t2时刻的值，可以看到，在t2时刻，ADC1的码字的值为64-(-64)＝128，ADCN的码字的值为0-(-64)＝64，其它ADC的码字调整与此类似，不一一赘述。
本实施例中，也可以将多个码字中的最大值与预设范围的下边界的差值确定为调整值，还可以将多个码字中的最小值与预设范围的上边界的差值确定为调整值。在确定出调整值之后，可以直接分别将多个码字的当前值加上调整值得到调整后的多个码字各自的值，之后再次执行步骤201。假设图3中的预设范围为(0，128)，其中，0是下边界，128是上边界。ADC1为参考ADC，其码字的值可以恒定为64且为所有ADC中码字的值中的最大值。可以看到，ADCN的码字一直处于减小趋势，在t1时刻，ADCN的码字的值为0，如果不调整，将会超出预设范围。因此，根据本申请的方案，可以将多个码字中的最大值与预设范围的下边界的差值确定为调整值Δ，即Δ＝64-0＝64；将各个ADC的码字在t1时刻的值加上调整值，得到各个ADC的码字在t2时刻的值，可以看到，在t2时刻，ADC1的码字的值为64+64＝128，ADCN的码字的值为0+64＝64，其它ADC的码字调整与此类似，不一一赘述。
405、根据预设步长调整第一ADC对应的码字，并利用调整后的第一ADC对应的码字控制分频时钟电路生成第一ADC对应的采样时钟。
本实施例中，在判断出第一ADC的码字的当前值处于预设范围内的情况下，可以先根据预设步长调整第一ADC对应的码字，之后利用调整后的第一ADC对应的码字控制分频时钟电路生成第一ADC对应的采样时钟。在本校正周期中第一次对第一ADC对应的码字进行调整时，由于不知道往哪个方向调整第一ADC对应的码字会使第一ADC的采样时间与第二ADC的采样时间之间的偏差减小，因此，可以任选一个方向进行调整，即可以是加一个正值，也可以是加一个负值。在本校正周期中第二次对第一ADC对应的码字进行调整时，可以先判断第一ADC的采样时间与第二ADC的采样时间之间的第二次偏差是否小于第一次偏差，在判断出第二次偏差小于第一次偏差的情况下，继续沿着原来的方向进行码字调整；在判断第二次偏差大于第一次偏差的情况下，沿着反方向进行码字调整。其中，第一ADC对应的码字的调整可以是基于预设步长进行的，预设步长为可以调整的码字的最小值，每次调整的值的绝对值可以是预设步长，也可以是预设步长的整数倍。例如，在偏差与理想偏差之间的差距较大的情况下，调整的值可以大一点，在偏差与理想偏差之间的差距较小的情况下，调整的值可以小一点。
406、判断是否校正完多个ADC，在未校正完多个ADC的情况下，执行步骤401。
本实施例中，在判断出该偏差收敛的情况下，继续判断是否校正完多个ADC，即判断本校正周期是否校正完所有ADC，在判断出校正完多个ADC的情况下，表明本校正周期已完成，将结束；在判断出未校正完多个ADC的情况下，表明本校正周期未完成，可以将未校正的ADC中的任一ADC确定为第二ADC，并执行步骤401。
以上所述的具体实施方式，对本申请的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本申请的具体实施方式而已，并不用于限定本申请的保护范围，凡在本申请的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本申请的保护范围之内。

Claims (26)

  1. 一种误差校正方法，其特征在于，应用于包括多个模数转换器ADC的时间交织模数转换器TIADC，包括：
    判断所述多个ADC中的第一ADC的码字的当前值是否处在预设范围内；
    在所述第一ADC的码字的当前值未处在所述预设范围内的情况下，对与所述多个ADC一一对应的多个码字进行调整；
    分别利用调整后的多个码字，控制分频时钟电路生成与所述多个ADC一一对应的多个采样时钟。
  2. 根据权利要求1所述的方法，其特征在于，对与所述多个ADC一一对应的多个码字进行调整，包括：
    根据所述多个码字的当前值和所述预设范围确定调整值；
    根据所述调整值对所述多个码字的当前值进行调整。
  3. 根据权利要求2所述的方法，其特征在于，根据所述多个码字的当前值和所述预设范围确定调整值，包括：
    将所述多个码字中的最大值与最小值之和与码字量程的差值的一半确定为所述调整值，其中，所述码字量程为所述预设范围的最大值与最小值的差值。
  4. 根据权利要求2所述的方法，其特征在于，根据所述多个码字的当前值和所述预设范围确定调整值，包括：
    将所述多个码字中的最大值与所述预设范围的上边界的差值确定为所述调整值。
  5. 根据权利要求2所述的方法，其特征在于，根据所述多个码字的当前值和所述预设范围确定调整值，包括：
    将所述多个码字中的最小值与所述预设范围的下边界的差值确定为所述调整值。
  6. 根据权利要求2-5任一项所述的方法，其特征在于，根据所述调整值对所述多个码字的当前值进行调整，包括：
    分别将所述多个码字的当前值与所述调整值的差值作为所述调整后的多个码字各自的值。
  7. 根据权利要求2所述的方法，其特征在于，根据所述多个码字的当前值和所述预设范围确定调整值，包括：
    将所述多个码字中的最大值与所述预设范围的下边界的差值确定为所述调整值。
  8. 根据权利要求2所述的方法，其特征在于，根据所述多个码字的当前值和所述预设范围确定调整值，包括：
    将所述多个码字中的最小值与所述预设范围的上边界的差值确定为所述调整值。
  9. 根据权利要求7或8所述的方法，其特征在于，根据所述调整值对所述多个码字的当前值进行调整，包括：
    分别将所述多个码字的当前值加上所述调整值作为所述调整后的多个码字各自的值。
  10. 根据权利要求1-9任一项所述的方法，其特征在于，所述方法还包括：
    获取所述第一ADC的采样时间与第二ADC的采样时间之间的偏差，所述第二ADC为所述多个ADC中的参考ADC；
    判断所述偏差是否收敛；
    在所述偏差未收敛的情况下，则执行判断所述多个ADC中的第一ADC的码字的当前值是否处在预设范围内的步骤。
  11. 根据权利要求1-10任一项所述的方法，其特征在于，所述方法还包括：
    在所述第一ADC的码字的当前值处在所述预设范围内的情况下，根据预设步长调整所述第一ADC对应的码字；
    并利用调整后的所述第一ADC对应的码字，控制所述分频时钟电路生成所述第一ADC对应的采样时钟。
  12. 根据权利要求1-11任一项所述的方法，其特征在于，所述预设范围为在模拟域允许所述多个ADC之间存在的采样时间的偏差范围。
  13. 根据权利要求1-12任一项所述的方法，其特征在于，所述分频时钟电路为模拟锁相环PLL。
  14. 一种TIADC，其特征在于，包括多个ADC、误差估计电路和分频时钟电路，其中：
    所述误差估计电路，用于判断所述多个ADC中的第一ADC的码字的当前值是否处在预设范围内，在所述第一ADC的码字的当前值未处在所述预设范围内的情况下，对与所述多个ADC一一对应的多个码字进行调整，并将调整后的多个码字发送给所述分频时钟电路；
    所述分频时钟电路，用于分别利用调整后的多个码字生成与所述多个ADC一一对应的多个采样时钟。
  15. 根据权利要求14所述的TIADC，其特征在于，所述误差估计电路对与所述多个ADC一一对应的多个码字进行调整，包括：
    所述误差估计电路根据所述多个码字的当前值和所述预设范围确定调整值；
    所述误差估计电路根据所述调整值对所述多个码字的当前值进行调整。
  16. 根据权利要求15所述的TIADC，其特征在于，所述误差估计电路根据所述多个码字的当前值和所述预设范围确定调整值，包括：
    所述误差估计电路将所述多个码字中的最大值与最小值之和与码字量程的差值的一半确定为所述调整值，其中，所述码字量程为所述预设范围的最大值与最小值的差值。
  17. 根据权利要求15所述的TIADC，其特征在于，所述误差估计电路根据所述多个码字的当前值和所述预设范围确定调整值，包括：
    所述误差估计电路将所述多个码字中的最大值与所述预设范围的上边界的差值确定为所述调整值。
  18. 根据权利要求15所述的TIADC，其特征在于，所述误差估计电路根据所述多个码字的当前值和所述预设范围确定调整值，包括：
    所述误差估计电路将所述多个码字中的最小值与所述预设范围的下边界的差值确定为所述调整值。
  19. 根据权利要求15-18任一项所述的TIADC，其特征在于，所述误差估计电路根据所述调整值对所述多个码字的当前值进行调整，包括：
    所述误差估计电路分别将所述多个码字的当前值与所述调整值的差值作为所述调整后的多个码字各自的值。
  20. 根据权利要求15所述的TIADC，其特征在于，所述误差估计电路根据所述多个码字的当前值和所述预设范围确定调整值，包括：
    所述误差估计电路将所述多个码字中的最大值与所述预设范围的下边界的差值确定为所述调整值。
  21. 根据权利要求15所述的TIADC，其特征在于，所述误差估计电路根据所述多个码字的当前值和所述预设范围确定调整值，包括：
    所述误差估计电路将所述多个码字中的最小值与所述预设范围的上边界的差值确定为所述调整值。
  22. 根据权利要求20或21所述的TIADC，其特征在于，所述误差估计电路根据所述调整值对所述多个码字的当前值进行调整，包括：
    所述误差估计电路分别将所述多个码字的当前值加上所述调整值，作为所述调整后的多个码字各自的值。
  23. 根据权利要求14-22任一项所述的TIADC，其特征在于，所述误差估计电路，还用于获取所述第一ADC的采样时间与第二ADC的采样时间之间的偏差，判断所述偏差是否收敛，在所述偏差未收敛的情况下，则执行判断所述多个ADC中的第一ADC的码字的当前值 是否处在预设范围内的步骤，所述第二ADC为所述多个ADC中的参考ADC。
  24. 根据权利要求14-23任一项所述的TIADC，其特征在于，所述误差估计电路，还用于在所述第一ADC的码字的当前值处在所述预设范围内的情况下，根据预设步长调整所述第一ADC对应的码字；
    所述分频时钟电路，还用于利用调整后的所述第一ADC对应的码字生成所述第一ADC对应的采样时钟。
  25. 根据权利要求14-24任一项所述的TIADC，其特征在于，所述预设范围为在模拟域允许所述多个ADC之间存在的采样时间的偏差范围。
  26. 根据权利要求14-25任一项所述的TIADC，其特征在于，所述分频时钟电路为模拟PLL。
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