WO2020094044A1 - Dispositif à semi-conducteurs et son procédé de fabrication - Google Patents

Dispositif à semi-conducteurs et son procédé de fabrication Download PDF

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Publication number
WO2020094044A1
WO2020094044A1 PCT/CN2019/115932 CN2019115932W WO2020094044A1 WO 2020094044 A1 WO2020094044 A1 WO 2020094044A1 CN 2019115932 W CN2019115932 W CN 2019115932W WO 2020094044 A1 WO2020094044 A1 WO 2020094044A1
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source
drain region
forming
manufacturing
semiconductor substrate
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PCT/CN2019/115932
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English (en)
Chinese (zh)
Inventor
肖魁
方冬
卞铮
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无锡华润上华科技有限公司
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Publication of WO2020094044A1 publication Critical patent/WO2020094044A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a semiconductor device structure and a method of manufacturing the same.
  • Trench VDMOS products are more widely used power devices.
  • the maturity of the trench process further reduces the size of the cell.
  • the trench area passes through the bottom of the P-type base region, the channel formed is located Between the source region and the drift region, the on-resistance is greatly reduced compared to the ordinary VDMOS eliminating the JFET region, so the trench VDMOS greatly improves the performance of the MOS power device.
  • the structure adopted today is that the polysilicon gate plane in the trench is lower than the silicon plane, the manufacturing process is etching trench, growing gate oxygen, polysilicon deposition, polysilicon etching, well region formation, NSD formation, hole Formation, metal electrode formation, back process.
  • the masks used based on the above manufacturing methods include at least trench masks, NSD masks, CT masks, and metal masks. Secondly, to improve performance, such as passivation layer masks will also be added.
  • one aspect of the present invention provides a semiconductor device, including: a semiconductor substrate; a trench formed in the semiconductor substrate; an interlayer dielectric layer formed in the trench and the semiconductor substrate Above; contact holes formed in the interlayer dielectric layer and the semiconductor substrate; first source / drain regions and second source / drain regions, the first source / drain regions and the second source / Drain regions are formed through the contact holes.
  • a further aspect of the present invention provides a manufacturing method, including: providing a semiconductor substrate; forming a trench in the semiconductor substrate; forming an interlayer dielectric layer above the trench and the semiconductor substrate; A contact hole is formed on the interlayer dielectric layer, and the contact hole extends from the top to the bottom of the interlayer dielectric layer; the first source / drain region is formed through the contact hole implantation; and the second source is formed through the contact hole implantation / Drain area.
  • the invention can omit the source / drain region mask plate, at the same time omit the manufacturing lithography link, and save the manufacturing cost.
  • FIG. 1A to 1J show schematic cross-sectional views of devices obtained by relevant steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention
  • FIGS. 2A to 2K show schematic cross-sectional views of a device obtained by relevant steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention
  • FIG. 3 shows a schematic diagram of relevant steps of a method for manufacturing a VDMOS device according to an embodiment of the present invention.
  • first element, component, region, layer, or section discussed below can be represented as a second element, component, region, layer, or section.
  • Spatial relationship terms such as “below”, “below”, “below”, “below”, “above”, “above”, etc. It can be used here for the convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then elements or features described as “below” or “beneath” or “below” will be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “below” can include both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. In this way, changes from the shown shape due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments of the present invention should not be limited to the specific shapes of the regions shown here, but include shape deviations due to, for example, manufacturing. For example, an implanted area shown as a rectangle generally has round or curved features and / or implant concentration gradients at its edges, rather than a binary change from the implanted area to the non-implanted area. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is proceeding. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the present invention.
  • the present invention provides an aspect of the present invention to provide a semiconductor device and a manufacturing method thereof, including: a semiconductor substrate; a trench formed in the semiconductor substrate; an interlayer dielectric layer, Formed above the trench and the semiconductor substrate; contact holes formed in the interlayer dielectric layer and the semiconductor substrate; the first source / drain region and the second source / drain region, the Both the first source / drain region and the second source / drain region are formed through the contact hole.
  • the source / drain mask can be omitted, and the photolithography process can be omitted, which can save manufacturing costs.
  • VDMOS manufacturing process of the VDMOS will be described below with reference to the cross-sectional schematic diagram of the device obtained by the relevant steps of the method for manufacturing a semiconductor device according to an embodiment of the present invention shown in FIGS. 1 to 1J.
  • step 1 a silicon wafer 100 is provided as a substrate, and a silicon epitaxial layer 101 is formed on the silicon substrate, as shown in FIG. 1A.
  • Step 2 forming a first oxide layer 102, forming a first oxide layer 102 on the silicon epitaxial layer 101, and forming a trench, forming the trench in the first oxide layer 102 and the silicon epitaxial layer 101, the first oxide layer It is a thermal oxide layer, as shown in Figure 1B.
  • the first oxide layer 102 above the silicon epitaxial layer 101 is removed.
  • Step 3 forming a second oxide layer 103 and filling polysilicon, forming a second oxide layer 103 on the surface of the silicon epitaxial layer 101 and the trench, the second oxide layer is a gate oxide layer GOX, and depositing polysilicon on the surface of the gate oxide layer GOX To fill the trench and above the trench.
  • the method further includes the step of etching the polysilicon layer 104, and the polysilicon layer 104 is etched.
  • the height of the etched polysilicon layer 104 is lower than the top surface of the groove, as shown in FIG.
  • Step 4 a well region 105 is formed, and a P well region is implanted in the silicon epitaxial layer 101, as shown in FIG. 1D;
  • step 5 an NSD, that is, an N-type first source / drain region 106 is formed, and an N-type first source / drain region 106 is implanted into the well region 105, as shown in FIG. 1E.
  • step 6 an interlayer dielectric layer (ILD) 107 is formed, and an interlayer dielectric layer 107 is formed over the trench and the first source / drain region 106, as shown in FIG. 1F.
  • ILD interlayer dielectric layer
  • Step 7 forming a hole 108, forming a contact hole (CT) 108 on the interlayer dielectric layer 107, the contact hole 108 extending from the top to the bottom of the interlayer dielectric layer 107, and the bottom of the contact hole 108 is located in the
  • CT contact hole
  • Step 8 Deepen the hole and further process the CT contact hole, such as photolithography, to deepen the depth of the contact hole 108, as shown in FIG. 1H.
  • step 9 the PSD, that is, the P-type second source / drain region 109 is implanted through the contact hole 108, as shown in FIG. 1I.
  • Step 10 forming a cell structure, forming contact layers 1101, 1102 above the interlayer dielectric layer 107 and below the silicon wafer 100, and forming leads through the contact layers 1101, 1102, respectively, connected to the source (S) and the drain Pole (D), thereby forming a cell structure, as shown in Figure 1J.
  • a lithography step is required.
  • a mask plate, a glue coating, a development exposure, and a glue removal step are used. Therefore, preparation The process is complicated and the cost is rising and the efficiency is low.
  • step 1 a silicon wafer 200 is provided as a substrate, and a silicon epitaxial layer 201 is formed on the silicon substrate, as shown in FIG. 2A.
  • the silicon wafer 200 and the silicon epitaxial layer 201 are used as a semiconductor substrate.
  • the semiconductor substrate material may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V Compound semiconductors also include multilayer structures composed of these semiconductors or silicon on insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) And germanium on insulator (GeOI), etc.
  • Devices such as NMOS and / or PMOS may be formed on the semiconductor substrate.
  • a conductive member may also be formed in the semiconductor substrate, and the conductive member may be the gate, source, or drain of the transistor.
  • Step 2 forming a first oxide layer 202, forming a first oxide layer 202 on the silicon epitaxial layer 201, and forming a trench, forming the trench in the first oxide layer 202 and the silicon epitaxial layer 201, the first oxide layer It is a thermal oxide layer TOX, as shown in FIG. 2B.
  • the first oxide layer 202 may use various oxides, such as silicon dioxide.
  • the first oxide layer can be produced by methods such as thermal oxidation, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition) and the like.
  • the step of removing the first oxide layer 202 is also included.
  • Step 3 forming a second oxide layer 203 and filling polysilicon, forming a second oxide layer 203 on the surface of the silicon epitaxial layer and the trench, the second oxide layer is a gate oxide layer GOX, and depositing polysilicon on the surface of the gate oxide layer GOX, Fill the trench and above the trench.
  • the method further includes the step of etching the polysilicon layer 204 to etch the polysilicon layer 204.
  • the height of the etched polysilicon layer 204 is lower than the top surface of the groove, as shown in FIG. 2C.
  • the second oxide layer 203 can be made of various insulating materials, such as oxide, nitride, oxynitride, and the like.
  • the second oxide layer can be produced by methods such as thermal oxidation, PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition) and the like.
  • the second oxide layer uses TEOS (ethyl orthosilicate, Si (OC2H5) 4) oxide, that is, silicon dioxide formed by TEOS (ethyl orthosilicate, Si (OC 2 H 5 ) 4 ) Floor.
  • TEOS ethyl orthosilicate, Si (OC2H5)
  • the second oxide layer 203 is manufactured by a furnace tube process, the process temperature is 680 degrees exemplarily, and the thickness of the second oxide layer 203 is exemplarily
  • Step 4 a well region 205 is formed, and a well region of a second doping type, such as a P-type well region 205, is implanted into the silicon epitaxial layer 201, as shown in FIG. 2D.
  • a well region of a second doping type such as a P-type well region 205
  • the well region 205 may also be of the first doping type, such as an N-well region.
  • step 5 an interlayer dielectric layer (ILD) 207 is formed, and an interlayer dielectric layer 207 is formed over the trench and well region 205, as shown in FIG. 2E.
  • ILD interlayer dielectric layer
  • the interlayer dielectric layer is deposited between different layers to isolate the conductive layer to be deposited next.
  • the interlayer dielectric layer usually refers to the insulating layer between the semiconductor layer and the metal layer, which can be a single layer
  • the layer structure may be a multi-layer structure.
  • Step 6 forming a hole contact hole 208, forming a contact hole (CT) 208 on the interlayer dielectric layer 207, the contact hole 208 extends from the top to the bottom of the interlayer dielectric layer 207, and the contact hole 208 The bottom is located on the upper surface of the well region 205, as shown in FIG. 2F.
  • CT contact hole
  • a first source / drain region 206 is formed, and a first source / drain region 206 is formed in the well region 205.
  • the first source / drain region 206 is of a first doping type, for example, an N-type source / drain region, As shown in FIG. 2G; the first source / drain region 206 may also be of a second doping type, such as a P-type source / drain region.
  • the implantation of the first source / drain region 206 is completed through the contact hole 208.
  • the first source / drain region 206 is formed by implantation, and an ion implantation doping process may be used. This process is to implant an ion beam accelerated to a certain high energy into the surface layer of a solid material to change the surface layer physical and Chemical process. Implanting corresponding impurity atoms into the semiconductor (such as implanting boron, phosphorus or arsenic into silicon) can change the surface conductivity or form a PN junction to form N-type source / drain regions, and choose to implant phosphorus or arsenic into silicon However, when forming P-type source / drain regions, boron is implanted in silicon. Of course, the choice of dopant is not limited to the above.
  • the first doping type and the second doping type generally refer to P-type or N-type, where the first doping type and the second doping type are opposite, such as the first doping
  • the hetero type is one of P type, low doped P-type, and high doped P + type
  • the second doped type is one of N type, low doped N- type, and high doped N + type.
  • the first doping type is one of N-type, low-doping N-type, and high-doping N + type
  • the second doping type is P-type, low-doping P-type, and high-doping P + type one of them.
  • Step 9 Expand the size of the first source / drain region 206 to expand to the lateral region to make it larger and closer to the trench position, as shown in FIG. 2H; the way to expand the size of the first source / drain region Heat treatment can be used.
  • Step 10 Deepen the hole and further process the contact hole 208, such as photolithography, to deepen the depth of the contact hole 208 so that the bottom of the contact hole 208 is lower than the lower surface of the first source / drain region, As shown in Figure 2I.
  • Step 11 forming a second source / drain region 209, and forming the second source / drain region 209 through the deepened contact hole 208, such as a P-type source / drain region, as shown in FIG. 2J; the source / drain region 209 also It may be a first doping type N-type source / drain region.
  • step 10 further includes the step of filling the contact hole 208.
  • Step 12 forming a cell structure, forming contact layers 2101,2102 above the interlayer dielectric layer ILD207 and below the silicon wafer substrate, and forming leads through the contact layers 2101,2102, respectively, connected to the source Pole (S) and drain (D), thereby forming a cell structure, as shown in Figure 2K.
  • an etching method may be used, and the etching includes wet etching and / or dry etching.
  • the method of mask implantation is used.
  • the embodiment shown in FIG. 2 is:
  • the step of forming the first source / drain region is formed after the step of etching the interlayer dielectric layer to form the CT contact hole, and the mask plate is not used in the process of forming the N-type source / drain region, and the manufacturing process is omitted
  • the lithography link in the process saves manufacturing costs, reduces process complexity, and improves production efficiency.
  • the diffusion can be realized by a thermal process, and the manufacturing process can be fully compatible with the existing process.
  • the first source / drain region mask and the corresponding lithography link are not used in the process of forming the first source / drain region, therefore, in the embodiment shown in FIG. 2, during the formation of the cell device , It can reduce the use of mask plate and photolithography process, on the premise of fully compatible with the existing process, to achieve the reduction of process complexity, improve production efficiency, save production costs, etc.
  • a method of manufacturing a semiconductor device characterized in that it includes:
  • Step S101 providing a semiconductor substrate
  • Step S102 forming a trench in the semiconductor substrate
  • Step S103 forming an interlayer dielectric layer above the trench and the semiconductor substrate
  • Step S104 forming a contact hole on the interlayer dielectric layer, the contact hole extending from the top to the bottom of the interlayer dielectric layer;
  • Step S105 forming a first source / drain region through the contact hole implantation
  • Step S106 forming a second source / drain region through the contact hole implantation.
  • the present invention also provides a semiconductor device, including: a semiconductor substrate; a trench formed in the semiconductor substrate; an interlayer dielectric layer formed in the trench and the Above the semiconductor substrate; contact holes formed in the interlayer dielectric layer and the semiconductor substrate; first source / drain regions and second source / drain regions, the first source / drain regions and the The second source / drain regions are all formed through the contact holes.
  • the semiconductor device further includes a well region formed in the semiconductor substrate, and both the first source / drain region and the second source / drain region are formed in the well region.
  • the semiconductor device further includes contact layers formed above and below the semiconductor device, respectively, connected to the source electrode and the drain electrode, thereby forming a cell structure.
  • the present invention can omit the source / drain region mask, and at the same time omit the manufacturing lithography link, saving manufacturing costs.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Dispositif à semi-conducteurs et son procédé de fabrication. Le procédé consiste à : fournir un substrat à semi-conducteurs ; former une tranchée dans le substrat à semi-conducteurs ; former une couche diélectrique intercouche sur la tranchée et sur le substrat à semi-conducteurs ; former un trou de contact sur la couche diélectrique intercouche, le trou de contact s'étendant à partir de l'extrémité supérieure de la couche diélectrique intercouche jusqu'au fond de celle-ci ; former une première région de source/drain par injection au moyen du trou de contact ; et former une seconde région de source/drain par injection au moyen du trou de contact.
PCT/CN2019/115932 2018-11-06 2019-11-06 Dispositif à semi-conducteurs et son procédé de fabrication WO2020094044A1 (fr)

Applications Claiming Priority (2)

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CN201811314323.2 2018-11-06
CN201811314323.2A CN111146288A (zh) 2018-11-06 2018-11-06 一种半导体器件及其制造方法

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WO2020094044A1 true WO2020094044A1 (fr) 2020-05-14

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CN113690296A (zh) * 2020-05-19 2021-11-23 无锡华润上华科技有限公司 沟槽栅igbt器件及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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