CN103035713A - FinFET器件及其制造方法 - Google Patents

FinFET器件及其制造方法 Download PDF

Info

Publication number
CN103035713A
CN103035713A CN2011104261134A CN201110426113A CN103035713A CN 103035713 A CN103035713 A CN 103035713A CN 2011104261134 A CN2011104261134 A CN 2011104261134A CN 201110426113 A CN201110426113 A CN 201110426113A CN 103035713 A CN103035713 A CN 103035713A
Authority
CN
China
Prior art keywords
electrode parts
fin structure
semiconductor device
insulating material
fin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011104261134A
Other languages
English (en)
Other versions
CN103035713B (zh
Inventor
刘继文
王昭雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN103035713A publication Critical patent/CN103035713A/zh
Application granted granted Critical
Publication of CN103035713B publication Critical patent/CN103035713B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41791Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/517Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/518Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

本发明公开了一种半导体器件以及制造半导体器件的方法。示例性的半导体器件包括:衬底,该沉底包括设置在衬底上方的鳍结构。该鳍结构包括一个或多个鳍。半导体器件进一步包括设置在衬底上方的绝缘材料。半导体器件进一步包括设置在部分鳍结构以及部分绝缘材料上方的栅极结构。该栅极结构横贯鳍结构中的每个鳍。半导体器件进一步包括由具有连续的并且不间断的表面区域的材料所形成的源极部件和漏极部件。该源极部件和漏极部件包括位于平面中的表面,该表面与位于绝缘材料、鳍结构的一个或多个鳍中的每个鳍以及栅极结构的平行平面中的表面直接接触。本发明还提供了FinFET器件及其制造方法。

Description

FinFET器件及其制造方法
技术领域
本发明一般地涉及半导体领域,更具体地来说,涉及半导体器件以及制造半导体器件的方法。
背景技术
半导体集成电路(IC)工业经历了迅速的发展。在IC的发展过程中,通常增大了功能密度(即,每个芯片区域的互连器件的数量),而减小了几何尺寸(即,使用制造工艺可以制造的最小部件(或线))。这种按比例缩小的工艺的优点在于提高了生产效率并且降低了相关费用。这种按比例缩小也增加了处理和制造IC的复杂性,并且为了实现这些进步,IC的制造也需要类似的发展。
例如,在寻求更高的器件密度、更高的性能以及更低的费用的过程中,随着半导体工艺发展到纳米技术工艺节点,制造和设计中的挑战导致鳍状的场效应晶体管(FinFET)器件的发展。尽管现有的FinFET器件以及制造FinFET器件的方法已大体上满足了其预期目的,但并不是在所有方面都能够完全令人满意。
发明内容
为了解决现有技术中所存在的缺陷,根据本发明的一方面,提供了一种半导体器件,包括:衬底,包括设置在所述衬底上方的鳍结构,其中,所述鳍结构包括一个或多个鳍;绝缘材料,设置在所述衬底上方;栅极结构,设置在所述鳍结构的部分以及所述绝缘材料的部分上方,其中,所述栅极结构横贯所述鳍结构中的每个鳍;以及源极部件和漏极部件,由具有连续的并且不间断的表面区域的材料形成,其中,所述源极部件和所述漏极部件包括位于平面中的表面,所述表面与位于所述绝缘材料、所述鳍结构的一个或多个鳍中的每个鳍以及所述栅极结构的平行平面中的表面直接接触。
在该半导体器件中,所述衬底选自由体硅和绝缘体上硅(SOI)所构成的组。
在该半导体器件中,所述栅极结构包括:栅极介电层;栅电极,设置在所述栅极介电层上方;以及栅极隔离件,设置在所述栅电极的侧壁上方。
在该半导体器件中,所述半导体器件是P型金属氧化物半导体(PMOS)鳍状场效应晶体管(FinFET)器件或N型金属氧化物半导体(NMOS)FinFET器件之一,并且其中,在集成电路器件中包括所述半导体器件。
在该半导体器件中,所述绝缘材料包括:具有高度(h2)的表面,在所述表面上方没有设置所述绝缘材料;以及具有高度(h3)的表面,在所述表面上方设置有所述绝缘材料,所述高度h2大于所述高度h3。
在该半导体器件中,所述源极部件和所述漏极部件包括高度(h1),所述高度大于紧邻着所述源极部件和所述漏极部件并且与所述源极部件和所述漏极部件直接接触的所述绝缘材料的高度(h2)。
在该半导体器件中,所述源极部件和所述漏极部件与所述衬底、所述绝缘材料、所述栅极隔离件以及所述鳍结构的每个鳍直接接触。
根据本发明的另一方面,提供了一种半导体器件,包括:衬底;鳍结构,所述鳍结构包括一个或多个设置在所述衬底上方的鳍,所述鳍结构包括:位于第一公共面中的第一表面和位于第二公共面中的第二表面,所述第一公共面和所述第二公共面不同;介电层,设置在所述鳍结构的中心部分上方;栅电极,设置在所述介电层上方,所述栅电极横贯一个或多个鳍并且将所述半导体器件的源极区域与漏极区域分开,所述源极区域和所述漏极区域限定在其间的所述一个或多个鳍中的每个的沟道区域;第一栅极隔离件和第二栅极隔离件,所述第一栅极隔离件形成在所述栅电极的第一侧壁上,而所述第二栅极隔离件形成在所述栅电极的第二侧壁上,所述第一栅极隔离件包括位于所述第一公共面中的表面,而所述第二栅极隔离件包括位于所述第二公共面中的表面;以及应变的源极部件和应变的漏极部件,直接形成在所述源极区域和所述漏极区域中的所述衬底上方,所述应变的源极部件和所述应变的漏极部件由具有连续的并且不间断的表面区域的材料形成。
该半导体器件进一步包括:绝缘材料,设置在衬底上方,所述绝缘材料包括:位于所述第一公共面中的第一表面以及位于所述第二公共面中的第二表面,其中,所述应变的源极部件和所述应变的漏极部件包括:第一表面,与位于所述第一公共面中的所述鳍结构的所述第一表面、所述绝缘材料的所述第一表面、以及所述第一栅极隔离件的所述表面直接接触并且平行,以及第二表面,与位于所述第二公共面中的与所述鳍结构的所述第二表面、所述绝缘材料的所述第二表面、以及所述第二栅极隔离件的所述表面直接接触并且平行。
在该半导体器件中,所述应变的源极部件和所述应变的漏极部件包括硅锗。
在该半导体器件中,所述第一公共面和所述第二公共面基本上平行。
在该半导体器件中,所述半导体衬底和所述鳍结构包括硅。
根据本发明的又一方面,提供了一种制造半导体器件的方法,包括:提供衬底;形成鳍结构,所述鳍结构包括位于所述衬底上方的一个或多个鳍;在所述鳍结构上方沉积绝缘材料;去除所述绝缘材料的部分,以暴露所述鳍结构的所述一个或多个鳍中的每个鳍的部分;在所述鳍结构的所述一个或多个鳍中的每个鳍的所述暴露部分上方形成栅极结构,所述栅极结构将所述半导体器件的源极区域与漏极区域分开;去除所述源极区域和所述漏极区域中的所述绝缘材料;以及在所述源极区域和所述漏极区域中形成源极部件和漏极部件,所述源极部件和所述漏极部件具有连续的并且不间断的表面区域。
在该方法中,形成所述鳍结构包括使用硬掩模的蚀刻工艺。
在该方法中,去除所述绝缘材料的部分以暴露所述鳍结构的所述一个或多个鳍中的每个鳍的部分包括:以所述源极区域和所述漏极区域中的所述绝缘材料不被去除的方式实施蚀刻工艺。
在该方法中,去除所述绝缘材料的部分以暴露所述鳍结构的所述一个或多个鳍中的每个鳍的部分包括:在所述源极区域和所述漏极区域中的所述绝缘材料上方形成掩模层;以及实施蚀刻工艺,以去除未被所述掩模层覆盖的所述绝缘材料的部分,从而暴露所述鳍结构的所述一个或多个鳍中的每个鳍的部分。
在该方法中,形成所述栅极结构包括:形成所述栅电极以及在所述栅电极的第一侧壁和第二侧壁上形成第一栅极隔离件和第二栅极隔离件。
在该方法中,提供所述衬底包括:提供包括硅的衬底,并且其中,形成所述源极部件和所述漏极部件包括:直接在所述硅衬底上方外延(epi)生长半导体材料。
在该方法中,外延(epi)生长所述半导体材料包括:填充所述源极区域和所述漏极区域,使得所述半导体材料的部分与所述第一栅极隔离件和所述第二栅极隔离件直接接触。
在该方法中,去除所述源极区域和所述漏极区域中的所述绝缘材料包括:暴露所述衬底的表面,以及其中,形成所述源极部件和所述漏极部件包括:在所述衬底的所述暴露表面上方外延(epi)生长半导体材料,所述半导体材料和所述鳍结构具有不同的晶格常数。
附图说明
当结合附图进行阅读时,根据下面详细的描述可以更好地理解本发明。应该强调的是,根据工业中的标准实践,各种部件没有被按比例绘制并且仅仅用于说明的目的。实际上,为了清楚的讨论,各种部件的尺寸可以被任意放大或缩小。
图1是示出根据本发明的各个方面制造半导体器件的方法的流程图;
图2A至图9A示出的是根据图1的方法,在各个制造阶段中的半导体器件的一个实施例的透视图;
图2B至9B分别示出了图2A至9A中所示的半导体器件的部分或整体的示意性横截面侧视图。
具体实施方式
以下发明提供了多种不同实施例或实例,用于实现本发明的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然,这些仅是实例并且不旨在限制本发明。例如,在以下描述中,在第二部件上方或上形成第一部件可以包括第一部件和第二部件以直接接触形成的实施例,也可以包括其他部件可以形成在第一部件和第二部件之间使得第一部件和第二部件不直接接触的实施例。另外,本发明可以在多个实例中重复参考符号和/或字符。这种重复用于简化和清楚,并且其本身没有指定所述各个实施例和/或配置之间的关系。同时,在不背离本发明的范围的条件下,在此所公开的部件可以以在此所示出的示例性实施例的不同方式进行布置、结合或配置。可以理解,本领域的技术人员能够设计出(尽管在此没有进行明确的描述)包括本发明的原理的各种等效结构。
得益于本发明的一个或多个实施例的器件的实例是半导体器件。例如,这种器件是鳍状场效应晶体管(FinFET)。例如,该FinFET器件可以是P型金属氧化物半导体(PMOS)FinFET器件或N型金属氧化物半导体(NMOS)FinFET器件。下面的公开内容将继续以FinFET为实例来说明本发明的各个实施例。然而,可以理解,除非特殊要求,否则本发明不应该局限于特定类型的器件。
根据图1和图2A至图9A,图2B至图9B,下面共同描述了方法100以及半导体器件200。图1是根据本发明的各个方面制造集成电路器件的方法100的流程图。在本实施例中,方法100用于制造集成电路器件,该集成电路器件包括鳍状场效应晶体管(FinFET)器件。该方法100以框102开始,其中提供了衬底。在框104中,将鳍结构形成在衬底上方。鳍结构的形成可以包括:图案化掩模层以及使用掩模层来蚀刻半导体衬底。在框106中,将介电层沉积在鳍结构上方。可以沉积介电层,使得该介电层覆盖该鳍结构。可以实施平坦化工艺,使得介电层的顶面平坦化,暴露出鳍结构的顶部。该方法继续进行到框108,其中,对于介电层实施蚀刻工艺,从而暴露出鳍结构的部分侧壁。该蚀刻工艺可以包括:在源极区域和漏极区域中的介电层上方沉积光刻胶层以及在FinFET器件的中心区域中实施蚀刻工艺,从而在该中心区域中暴露出鳍结构的部分侧壁。在框110中,在部分鳍结构上方形成了栅叠层。形成该栅叠层可以包括:在中心区域中的鳍结构上方沉积介电层;在该介电层上方形成栅极结构;并且在栅极结构的壁上并且与源极和漏极(S/D)区域相邻地形成栅极隔离件。该方法100继续进行到框112,其中对于S/D区域中的介电层实施蚀刻工艺。该蚀刻工艺可以包括:在介电层上沉积光刻胶层以及蚀刻介电层,从而暴露出衬底的表面。在框114中,将半导体材料形成在S/D区域中。形成半导体材料可以包括:在S/D区域中的暴露的衬底上方外延(epi)生长应变的半导体材料。方法100继续进行到框116,在其中完成了集成电路器件的制造。可以在方法100之前、之间、以及之后提供额外的步骤,并且对于该方法的其他实施例而言,所述步骤中的一些步骤可以被替换或去除。下面的论述说明的是根据图1的方法100所制造的集成电路器件的各个实施例。
图2A至图9A示出了根据图1的方法,在各个制造阶段中的半导体器件的一个实施例的示意图。另外,图2B至图9B分别示出了沿着线a-a所截取的图2A至图9A中所示的半导体器件的部分或整体的示意性横截面侧视图。在本发明中,半导体器件是FinFET器件。该FinFET器件包括任何以鳍为基础的多栅极晶体管。可以在微处理器、存储单元和/或其他集成电路器件中包括FinFET器件200。为了清楚地更好地理解本发明的创造性概念,已经简化了图2A、图2B至图9A、图9B。可以在FinFET器件200中添加额外的部件,而对于半导体器件200的其他实施例而言,下面所描述的这些部件中的一些可以被替换或删除。
参考图2A和图2B,FinFET器件200包括衬底(例如,晶圆)210。衬底210是体硅衬底。可选地,衬底210包括元素半导体,诸如,晶体结构的硅或锗;化合物半导体,诸如,硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;或其组合。可选地,衬底210包括绝缘体上硅(SOI)衬底。可以使用注氧隔离(SIMOX)、晶圆接合和/或其他适当的方法来制造该SOI衬底。衬底210可以包括多种掺杂区域和其他适当的部件。
参考图2A和图2B,介电层212形成在衬底210上方。可以通过任意适当的工艺将介电层212形成任意适当的厚度。在本实施例中,介电层212包括氧化硅并且通过CVD或热氧化工艺形成该介电层212。该热氧化工艺可以是干式工艺或湿式工艺。在多个实例中,可以通过物理汽相沉积(PVD)、原子层沉积(ALD)、高密度等离子体CVD(HDPCVD)、其他适当的方法和/或其组合来形成该氧化硅。例如,CVD工艺可以使用包括六氯乙硅烷(HCD或Si2Cl6)、二氯二硅烷(DCS或SiHCl2)、二(三甲基甲硅烷基)乙炔(BTBAS或C8H22N2Si)以及乙硅烷(DS或Si2H6)的化学物质。
掩模层214形成在介电层212上方。掩模层214可以是停止/硬掩模层。通过任意适当的工艺将掩模层214形成为任意适当的厚度。掩模层214可以包括以下材料,诸如,氮化硅、氧化硅、氮氧化硅、碳化硅、碳氮化硅、非晶硅、多晶硅、其他适当的材料或其组合。在本实施例中,掩模层214包括氮化硅,并且掩模层214通过CVD工艺形成。在各个实例中,可以通物理汽相沉积(PVD)、原子层沉积(ALD)、高密度等离子体CVD(HDPCVD)、其他适当的方法和/或其组合来形成该氮化硅。例如,CVD工艺可以使用包括六氯乙硅烷(HCD或Si2Cl6)、二氯二硅烷(DCS或SiHCl2)、二(三甲基甲硅烷基)乙炔(BTBAS或C8H22N2Si)以及乙硅烷(DS或Si2H6)的化学物质。
光刻胶层216形成在掩模层214上方。通过任意适当的工艺将光刻胶层216形成为任意适当的厚度。
参考图3A和图3B,通过任意适当的工艺(诸如,光刻工艺和蚀刻工艺)形成鳍结构218(包括多个鳍218a、218b以及218c)。例如,在本实施例中,通过将光刻胶层216曝光成图案,实施曝光后烘烤工艺并且对光刻胶层216进行显影以形成掩蔽元件(masking element)来形成鳍结构218,该掩蔽元件包括了光刻胶层216和掩模层214。光刻胶层216的图案化可以包括以下处理步骤:光刻胶涂覆、软烘、掩模对准、将图案曝光、曝光后烘焙、将光刻胶显影以及硬烘。也可以通过其他适当的方法(诸如,无掩模光刻、电子束曝光(electron-beam writing)、离子束曝光以及分子压印)来实施或替代该图案化。然后,可以在蚀刻工艺中使用掩蔽元件(包括光刻胶层216和掩模层214),从而在衬底210中蚀刻鳍结构218。蚀刻工艺使用图案化的掩模层214来限定出将被蚀刻的区域并且保护FinFET器件200的其他区域。蚀刻工艺可以包括湿蚀刻工艺、干蚀刻工艺或其组合。可以通过使用反应离子蚀刻(RIE)的蚀刻工艺和/或其他适当工艺来形成鳍结构218。在一个实例中,根据掩模层214所限定的图案,可以使用氢氟酸(HF)或含有缓冲剂的HF来蚀刻介电层212,从而暴露衬底210。在一个实例中,用于蚀刻衬底210的干蚀刻工艺包括具有含氟的气体的化学物质。在另一个实例中,干蚀刻的化学物质包括CF4、SF6或NF3。可选地,通过双重图案化光刻(DPL,double-patterning lithography)工艺来形成鳍结构218。DPL是一种通过将图案分成两个间隔的图案来在衬底上构造图案的方法。DPL能够增强部件(例如,鳍)的密度。可以使用包括双重曝光(例如,使用两个掩模组)的各种DPL方法。
参考图4A和图4B,绝缘材料220沉积在衬底210上方(以及鳍结构218上方)。沉积绝缘材料220,使得绝缘材料包围着鳍结构218的每个鳍218a、218b、218c并且使鳍结构218的每个鳍218a、218b、218c与其他鳍隔离。绝缘材料220可以包括以下绝缘材料,诸如,氧化硅、氮化硅、氮氧化硅、低k材料、空气间隙、其他适当的材料或其组合。在本实施例中,绝缘材料220包括氧化硅。可以通过CVD工艺沉积该氧化硅。在各个实例中,可以通过物理汽相沉积(PVD)、原子层沉积(ALD)、高密度等离子体CVD(HDPCVD)、其他适当的方法和/或其组合来形成该氧化硅。可选地,可以通过高纵横比工艺(HARP)来形成该氧化硅。在各个实施例中,可以生长任选的热氧化物沟槽衬垫来改善沟槽界面。例如,CVD工艺可以使用包括六氯乙硅烷(HCD或Si2Cl6)、二氯二硅烷(DCS或SiHCl2)、二(三甲基甲硅烷基)乙炔(BTBAS或C8H22N2Si)以及乙硅烷(DS或Si2H6)的化学物质。绝缘材料220可以具有多层结构,例如,热氧化物衬垫层和形成在衬垫上方的氮化硅。
参考图5A和图5B,在FinFET器件200上实施平坦化工艺。在一个实施例中,该平坦化工艺包括化学机械抛光(CMP)工艺,将该化学机械抛光工艺应用于FinFET器件200,从而去除绝缘材料220的多余部分。可以实施该平坦化工艺,使得去除介电层212,因此暴露出鳍结构218。
参考图6A和图6B,将蚀刻工艺用于对FinFET器件20的中心区域中的多余的绝缘材料220进行回蚀,由此暴露出鳍结构218的部分侧壁。该蚀刻工艺可以包括湿蚀刻、干蚀刻工艺或其组合。在一个实例中,干蚀刻工艺可以包括:形成光刻胶层,图案化该光刻胶层,蚀刻绝缘材料220,以及去除光刻胶层。在另一个实例中,用于蚀刻隔离材料的干蚀刻工艺可以包括化学物质,该化学物质包括含氟气体。在另一个实例中,干蚀刻的化学物质包括CF4、SF6或NF3
参考图7A和图7B,FinFET器件200包括栅极结构222。栅极结构222横贯鳍结构218,而在所述的实施例中,该栅极结构形成在鳍结构218的中心部分上方。栅极结构222可以包括:栅极介电层224、栅电极226以及栅极隔离件228。栅极介电层224包括以下介电材料,诸如,氧化硅、高k介电材料、其他适当的介电材料或其组合。高k介电材料的实例包括HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、氧化锆、氧化铝、二氧化铪-三氧化二铝(HfO2-Al2O3)合金、其他适当的高k介电材料和/或其组合。栅电极226包括多晶硅和/或金属,该金属包括Al、Cu、Ti、Ta、W、Mo、TaN、NiSi、CoSi、TiN、WN、TiAl、TiAlN、TaCN、TaC、TaSiN、其他导电材料或其组合。可以在先栅极工艺或后栅极工艺中形成栅电极226。栅极结构222可以包括多个其他层,例如,覆盖层、界面层、扩散层、阻挡层或其组合。可以在栅极结构222上方形成硬掩模层。该硬掩模层可以包括氧化硅、氮化硅、氮氧化硅、碳化硅、其他适当的材料或其组合。
栅极结构222通过适当工艺形成,该适当工艺包括沉积工艺、光刻图案化工艺以及蚀刻工艺。该沉积工艺包括:化学汽相沉积(CVD)、物理汽相沉积(PVD)、原子层沉积(ALD)、高密度等离子体CVD(HDPCVD)、金属有机物CVD(MOCVD)、远程等离子体CVD(RPCVD)、等离子体增强CVD(PECVD)、低压CVD(LPCVD)、原子层CVD(ALCVD)、常压CVD(APCVD)、电镀、其他适当的方法或其组合。光刻图案化工艺包括光刻胶涂覆(例如,旋涂)、软烘、掩模对准、曝光、曝光后烘焙、将光刻胶显影、清洗、烘干(例如,硬烘)、其他适当工艺或其组合。可选地,可以通过其他方法(诸如,无掩模光刻、电子束曝光、离子束曝光)来实施或替代该光刻曝光工艺。在又一个可选方式中,该光刻图案化工艺可以实施纳米压印技术。蚀刻工艺包括:干蚀刻、湿蚀刻、和/或其他蚀刻方法。
参考图8A和图8B,去除了部分绝缘材料220,从而限定出源极和漏极(S/D)区域230。S/D区域230限定在其间的沟道区域232。沟道区域232包括位于由栅极结构222所覆盖的鳍结构218中的鳍218a、218b、218c的内部的区域。可以去除部分绝缘材料220,使得衬底210的顶面暴露出来和/或使得鳍结构218中的每个鳍218a、218b、218c的侧壁暴露出来。去除部分绝缘材料220,使得第一公共面形成在栅极结构222的一个面上,而第二公共面形成在栅极结构222的另一个面上。第一公共面是共用的并且包括绝缘材料222的表面、每个鳍218a、218b、218c的表面、栅极介电层224的表面以及栅极隔离件228之一的表面。第二公共面(在图8中该公共面被栅极结构222遮挡着)包括与第一公共面相类似的位于栅极结构222的反面上的部件,第二公共面包括另一个栅极隔离件228的表面。第二公共面基本上与第一公共面平行。
可以通过任意适当的工艺去除部分绝缘材料220。在本实施例中,例如,通过蚀刻工艺去除部分绝缘材料220。该蚀刻工艺可以包括湿蚀刻或干蚀刻工艺或其组合。在一个实例中,干蚀刻工艺可以包括:形成光刻胶层、图案化光刻胶层、蚀刻绝缘材料220以及去除光刻胶层。在另一个实例中,用于蚀刻隔离材料的干蚀刻工艺可以包括化学物质,该化学物质包括了含氟气体。在另一个实例中,干蚀刻的化学物质包括:CF4、SF6或NF3
参考图9A和图9B,FinFET器件200包括形成在S/D区域230中的源极和漏极(S/D)部件234。可以通过在位于S/D区域230中的暴露的衬底210上方沉积半导体材料236来形成S/D部件234。S/D部件234包括第一表面,该第一表面与位于第一公共面中的绝缘材料220、鳍218a、218b、218c、栅极介电层224以及栅极隔离件228的表面相邻、直接接触并且平行;和第二表面,该第二表面与位于第二公共面中的绝缘材料220、鳍218a、218b、218c、栅极介电层224以及栅极隔离件228的表面相邻、直接接触并且平行。如所示,S/D部件234由具有连续的并且不间断的表面区域的材料形成。
可以通过适当工艺(诸如,外延或外延的(epi)工艺)沉积半导体材料236。该外延工艺可以包括CVD沉积技术(例如,汽相外延(VPE)和/或超高真空CVD(UHV-CVD)、分子束外延和/或其他适当工艺。该外延工艺可以使用气态和/或液态前体,该前体与鳍结构218的组成成分(例如,硅)以及暴露的衬底210相互作用。在所述实施例中,FinFET器件200是PMOS器件,并且由此,S/D部件234产生应变并且包括由硅锗外延沉积工艺而形成的硅锗(SiGe)。在FinFET器件200是PMOS器件情况下,S/D部件234的晶格常数大于衬底210(以及鳍结构218)的晶格常数。可选地,FinFET器件200可以是NMOS器件,并且由此,S/D部件234产生应变并且包括碳化硅(SiC)或硅(Si)。在一些实施例中,碳化硅(SiC)或硅(Si)可以包括一个或多个用于位错,从而增大沟道区域232上的S/D部件234的应变。在FinFET器件200是NMOS器件的情况下,S/D部件234的晶格常数小于衬底210(以及鳍结构218)的晶格常数。可以通过在S/D部件234的沉积(生长)期间向外延工艺的源极材料中添加杂质或在其沉积生长工艺之后通过离子注入工艺来对S/D部件234进行掺杂。例如,硅外延层可以掺杂有磷(用于形成Si:P epi层)。掺杂的外延层可以具有渐变的掺杂轮廓。在形成应变的S/D部件234之前或之后可以实施注入、扩散和/或退火工艺,从而在p型的(如果FinFET器件200是PMOS器件)或n型的(如果FinFET器件200是NMOS器件)的FinFET器件200的S/D区域230中形成重掺杂的S/D(HDD)部件。
如图9A和图9B中所示,应变的S/D部件234包括连续的矩形/方形轮廓/结构,该轮廓/结构具有连续并且不间断的表面区域。应变的S/D部件234包括高度h1,该高度大于与应变的S/D部件234相邻的绝缘材料220的高度h2。绝缘材料220的高度h2大于在其上形成了栅极结构222的绝缘材料220的高度h3。从衬底210的顶部到相应结构中的每个的相应区域来测量相应结构的高度。如所示的,部分应变的S/D部件234与衬底210、绝缘材料220、鳍结构218的鳍218a、218b、218c中的每个、栅极介电层224以及栅极隔离件228相邻并且直接接触。同时,部分绝缘材料220在栅极介电层224以及部分栅极结构222上方延伸。另外,如所示的,S/D部件234由连续的材料(具有连续的和不间断的表面区域)形成,该连续的材料从衬底210的顶部延伸达到高度h1,该高度h1大于紧邻着S/D部件234并且与该S/D部件直接接触的绝缘材料220的高度h2。
方法100和FinFET器件200的优点在于,S/D 234部件具有较大的并且连续不间断的表面区域。与传统的FinFET器件相比,应变的S/D部件234的更大的表面区域为FinFET器件200的沟道区域232提供了增大的/更大的应变,由此改进了在沟道区域232的电流方向上的载流子迁移率。另外,在当前工艺中,容易实现为了实现本文所述的具有更大区域的应变结构所公开的方法。不同的实施例可以具有不同的优点,而对任何实施例来说没有任何特定的优点是必须的。
FinFET器件200可以包括额外的部件,可以通过后续的处理工艺形成这些额外的部件。例如,各种接触件/通孔/线以及多层互连部件(例如,金属层和层间电介质)都可以形成在衬底210上方,将各种接触件/通孔/线以及多层互连部件配置成连接FinFET器件200的各个部件或结构。这些额外的部件可以为FinFET器件200提供电互连。例如,多层互连包括垂直互连(诸如,通常的通孔或接触件)和水平互连,诸如,金属线。包括铜、钨和/或硅化物的各种导电材料可以实现各种互连部件。在一个实例中,使用单镶嵌工艺和/或双镶嵌工艺来形成与铜相关的多层互连结构。
由此提供了一种半导体器件。示例性的半导体器件包括衬底,该沉底包括设置在衬底上方的鳍结构。该鳍结构包括一个或多个鳍。半导体器件进一步包括设置在衬底上方的绝缘材料。半导体器件进一步包括栅极结构,设置在部分鳍结构以及部分绝缘材料上方。该栅极结构横贯鳍结构中的每个鳍。半导体器件进一步包括由具有连续的并且不间断的表面区域的材料所形成的源极部件和漏极部件。该源极部件和漏极部件包括位于平面中的表面,该表面与绝缘材料、鳍结构的一个或多个鳍中的每个以及栅极结构的平行平面内的表面直接接触。
在一些实施例中,衬底选自于由体硅和绝缘体上硅(SOI)所构成的组。在各个实施例中,栅极结构包括:栅极介电层;栅电极,设置在栅极介电层上方;以及栅极隔离件,设置在栅电极的侧壁上。在特定的实施例中,半导体器件是PMOS FinFET器件或NMOS FinFET器件之一,并且其中,在集成电路器件中包括半导体器件。在一些实施例中,绝缘材料包括:具有高度(h2)的表面,在该表面上没有设置绝缘材料;以及具有高度(h3)的表面,在该表面上设置有绝缘材料。高度h2大于高度h3。在各个实施例中,源极部件和漏极部件包括高度(h1),该高度大于紧邻着源极部件和漏极部件并且与该源极部件和漏极部件直接接触的绝缘材料的高度(h2)。在实施例中,该源极部件和漏极部件导致在沟道区域中的电流方向上产生压应力。在另一个实施例中,源极部件和漏极部件导致在沟道区域中的电流方向上产生张应力。在各个实施例中,源极部件和漏极部件与衬底、绝缘材料、栅极隔离件以及鳍结构的每个鳍直接接触。
还提供了半导体器件的一个可选的实施例。该示例性的半导体器件包括衬底和鳍结构,该鳍结构包括一个或多个设置在衬底上方的鳍。该鳍结构包括位于第一公共面中的第一表面和位于第二公共面中的第二表面。第一公共面和第二公共面不同。半导体器件进一步包括设置在鳍结构的中心部分上方的介电层。半导体器件进一步包括设置在介电层上方的栅电极。该栅电极横贯一个或多个鳍结构并且将半导体器件的源极区域与漏极区域分开。源极区域和漏极区域在其间限定出了一个或多个鳍中的每个的沟道区域。半导体器件进一步包括:第一栅极隔离件,形成在栅电极的第一侧壁上以及第二栅极隔离件,形成在栅电极的第二侧壁上。半导体器件进一步包括直接形成在源极区域和漏极区域中的衬底上方的应变的源极部件和漏极部件。该应变的源极部件和漏极部件由连续的材料形成。
在一些实施例中,半导体器件进一步包括设置在衬底上方的绝缘材料。该绝缘材料包括位于第一公共面中的第一表面以及位于第二公共面中的第二表面。应变的源极部件和漏极部件包括:第一表面,与位于第一公共面中的鳍结构的第一表面、绝缘材料的第一表面以及第一栅极隔离件的表面直接接触并且平行;以及第二表面,与位于第二公共面中的鳍结构的第二表面、绝缘材料的第二表面以及第二栅极隔离件的表面直接接触并且平行。
在一些实施例中,应变的源极和漏极部件包括硅锗。在各个实施例中,第一公共面和第二公共面基本上平行。在特定的实施例中,半导体衬底和鳍结构包括硅。
还提供了一种方法。该方法包括:提供衬底并且形成包括一个或多个位于衬底上方的鳍的鳍结构。该方法进一步包括:在鳍结构上方沉积绝缘材料并且去除该绝缘材料的部分,使得暴露鳍结构的一个或多个鳍中的每个鳍的部分。该方法进一步包括:在鳍结构的一个或多个鳍中的每个鳍的暴露部分上方形成栅极结构。该栅极结构将半导体器件的源极区域与漏极区域分开。该方法进一步包括:去除源极区域和漏极区域中的绝缘材料并且在源极区域和漏极区域中形成源极部件和漏极部件。该源极部件和漏极部件具有连续的并且不间断的表面区域。
在一些实施例中,形成鳍结构包括使用了硬掩模的蚀刻工艺。在特定的实施例中,去除部分绝缘材料,使得暴露鳍结构的一个或多个鳍中的每个鳍的部分包括:实施蚀刻工艺,使得没有去除源极区域和漏极区域中的绝缘材料。在各个实施例中,去除部分绝缘材料暴露出鳍结构的一个或多个鳍中的每个鳍的部分包括:在源极和漏极区域中的绝缘材料上方形成掩模层;以及实施蚀刻工艺,使得未被掩模层覆盖的绝缘材料的部分被去除,由此暴露出鳍结构的一个或多个鳍中的每个鳍的部分。在实施例中,形成栅极结构包括:形成栅电极以及在栅电极的第一侧壁和第二侧壁上方形成第一栅极隔离件和第二栅极隔离件。在其他实施例中,提供衬底包括:提供包括硅的衬底,而形成源极部件和漏极部件包括:直接在硅衬底上方外延(epi)生长半导体材料。在又一些实施例中,外延(epi)生长半导体材料包括:填充源极区域和漏极区域,使得部分半导体材料与第一栅极隔离件和第二栅极隔离件直接接触。在一些实施例中,去除源极区域和漏极区域中的绝缘材料包括:暴露出衬底的表面,并且形成源极部件和漏极部件包括:在暴露的衬底表面上外延(epi)生长半导体材料,该半导体材料和鳍结构具有不同的晶格常数。
上面论述了若干实施例的部件,使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解,可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到,这种等效构造并不背离本发明的主旨和范围,并且在不背离本发明的主旨和范围的情况下,可以进行多种变化、替换以及改变。

Claims (10)

1.一种半导体器件,包括:
衬底,包括设置在所述衬底上方的鳍结构,其中,所述鳍结构包括一个或多个鳍;
绝缘材料,设置在所述衬底上方;
栅极结构,设置在所述鳍结构的部分以及所述绝缘材料的部分上方,其中,所述栅极结构横贯所述鳍结构中的每个鳍;以及
源极部件和漏极部件,由具有连续的并且不间断的表面区域的材料形成,其中,所述源极部件和所述漏极部件包括位于平面中的表面,所述表面与位于所述绝缘材料、所述鳍结构的一个或多个鳍中的每个鳍以及所述栅极结构的平行平面中的表面直接接触。
2.根据权利要求1所述的半导体器件,其中,所述衬底选自由体硅和绝缘体上硅(SOI)所构成的组。
3.根据权利要求1所述的半导体器件,其中,所述栅极结构包括:栅极介电层;栅电极,设置在所述栅极介电层上方;以及栅极隔离件,设置在所述栅电极的侧壁上方。
4.根据权利要求1所述的半导体器件,其中,所述半导体器件是P型金属氧化物半导体(PMOS)鳍状场效应晶体管(FinFET)器件或N型金属氧化物半导体(NMOS)FinFET器件之一,并且其中,在集成电路器件中包括所述半导体器件。
5.根据权利要求1所述的半导体器件,其中,所述绝缘材料包括:具有高度(h2)的表面,在所述表面上方没有设置所述绝缘材料;以及具有高度(h3)的表面,在所述表面上方设置有所述绝缘材料,所述高度h2大于所述高度h3。
6.根据权利要求1所述的半导体器件,其中,所述源极部件和所述漏极部件包括高度(h1),所述高度大于紧邻着所述源极部件和所述漏极部件并且与所述源极部件和所述漏极部件直接接触的所述绝缘材料的高度(h2)。
7.根据权利要求3所述的半导体器件,其中,所述源极部件和所述漏极部件与所述衬底、所述绝缘材料、所述栅极隔离件以及所述鳍结构的每个鳍直接接触。
8.一种半导体器件,包括:
衬底;
鳍结构,所述鳍结构包括一个或多个设置在所述衬底上方的鳍,所述鳍结构包括:位于第一公共面中的第一表面和位于第二公共面中的第二表面,所述第一公共面和所述第二公共面不同;
介电层,设置在所述鳍结构的中心部分上方;
栅电极,设置在所述介电层上方,所述栅电极横贯一个或多个鳍并且将所述半导体器件的源极区域与漏极区域分开,所述源极区域和所述漏极区域限定在其间的所述一个或多个鳍中的每个的沟道区域;
第一栅极隔离件和第二栅极隔离件,所述第一栅极隔离件形成在所述栅电极的第一侧壁上,而所述第二栅极隔离件形成在所述栅电极的第二侧壁上,所述第一栅极隔离件包括位于所述第一公共面中的表面,而所述第二栅极隔离件包括位于所述第二公共面中的表面;以及
应变的源极部件和应变的漏极部件,直接形成在所述源极区域和所述漏极区域中的所述衬底上方,所述应变的源极部件和所述应变的漏极部件由具有连续的并且不间断的表面区域的材料形成。
9.根据权利要求8所述的半导体器件,进一步包括:
绝缘材料,设置在衬底上方,所述绝缘材料包括:位于所述第一公共面中的第一表面以及位于所述第二公共面中的第二表面,
其中,所述应变的源极部件和所述应变的漏极部件包括:
第一表面,与位于所述第一公共面中的所述鳍结构的所述第一表面、所述绝缘材料的所述第一表面、以及所述第一栅极隔离件的所述表面直接接触并且平行,以及
第二表面,与位于所述第二公共面中的与所述鳍结构的所述第二表面、所述绝缘材料的所述第二表面、以及所述第二栅极隔离件的所述表面直接接触并且平行。
10.一种制造半导体器件的方法,包括:
提供衬底;
形成鳍结构,所述鳍结构包括位于所述衬底上方的一个或多个鳍;
在所述鳍结构上方沉积绝缘材料;
去除所述绝缘材料的部分,以暴露所述鳍结构的所述一个或多个鳍中的每个鳍的部分;
在所述鳍结构的所述一个或多个鳍中的每个鳍的所述暴露部分上方形成栅极结构,所述栅极结构将所述半导体器件的源极区域与漏极区域分开;
去除所述源极区域和所述漏极区域中的所述绝缘材料;以及
在所述源极区域和所述漏极区域中形成源极部件和漏极部件,所述源极部件和所述漏极部件具有连续的并且不间断的表面区域。
CN201110426113.4A 2011-10-04 2011-12-16 FinFET器件及其制造方法 Active CN103035713B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/252,892 US8723272B2 (en) 2011-10-04 2011-10-04 FinFET device and method of manufacturing same
US13/252,892 2011-10-04

Publications (2)

Publication Number Publication Date
CN103035713A true CN103035713A (zh) 2013-04-10
CN103035713B CN103035713B (zh) 2016-03-09

Family

ID=47991749

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110426113.4A Active CN103035713B (zh) 2011-10-04 2011-12-16 FinFET器件及其制造方法

Country Status (4)

Country Link
US (3) US8723272B2 (zh)
KR (1) KR101279195B1 (zh)
CN (1) CN103035713B (zh)
TW (1) TWI458096B (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104241366A (zh) * 2013-06-07 2014-12-24 台湾积体电路制造股份有限公司 FinFET器件的源极区和漏极区中的位错形成
CN105097517A (zh) * 2014-04-25 2015-11-25 中芯国际集成电路制造(上海)有限公司 一种FinFET器件及其制造方法、电子装置
CN106158587A (zh) * 2015-05-15 2016-11-23 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN106252350A (zh) * 2015-06-15 2016-12-21 台湾积体电路制造股份有限公司 FinFET器件和形成方法
CN106531631A (zh) * 2015-09-09 2017-03-22 中国科学院微电子研究所 一种形成鳍的方法及结构
US9768256B2 (en) 2014-03-21 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of dislocations in source and drain regions of FinFET devices
CN109411338A (zh) * 2017-08-15 2019-03-01 台湾积体电路制造股份有限公司 制造半导体元件的方法
CN110993569A (zh) * 2018-10-02 2020-04-10 南亚科技股份有限公司 半导体装置及其制作方法

Families Citing this family (232)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064892B2 (en) 2011-08-30 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices utilizing partially doped stressor film portions and methods for forming the same
US8802535B2 (en) * 2012-05-02 2014-08-12 International Business Machines Corporation Doped core trigate FET structure and method
US9142400B1 (en) 2012-07-17 2015-09-22 Stc.Unm Method of making a heteroepitaxial layer on a seed area
US9006786B2 (en) 2013-07-03 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of semiconductor device
US9147682B2 (en) 2013-01-14 2015-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Fin spacer protected source and drain regions in FinFETs
US9368619B2 (en) 2013-02-08 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method for inducing strain in vertical semiconductor columns
US9466668B2 (en) 2013-02-08 2016-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Inducing localized strain in vertical nanowire transistors
KR102003276B1 (ko) * 2013-02-14 2019-07-24 삼성전자 주식회사 반도체 소자 제조 방법
US9209247B2 (en) 2013-05-10 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned wrapped-around structure
US20150024584A1 (en) * 2013-07-17 2015-01-22 Global Foundries, Inc. Methods for forming integrated circuits with reduced replacement metal gate height variability
EP3767672A1 (en) * 2013-09-27 2021-01-20 Intel Corporation Low leakage non-planar access transistor for embedded dynamic random access memeory (edram)
US9646872B2 (en) * 2013-11-13 2017-05-09 Taiwan Semiconductor Manufacturing Company Limited Systems and methods for a semiconductor structure having multiple semiconductor-device layers
US9087743B2 (en) * 2013-11-20 2015-07-21 Globalfoundries Inc. Silicon-on-insulator finFET with bulk source and drain
US9136384B2 (en) * 2013-12-05 2015-09-15 Stmicroelectronics, Inc. Method for the formation of a FinFET device having partially dielectric isolated Fin structure
US9112033B2 (en) * 2013-12-30 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain structure of semiconductor device
US9246005B2 (en) 2014-02-12 2016-01-26 International Business Machines Corporation Stressed channel bulk fin field effect transistor
US20150255555A1 (en) * 2014-03-05 2015-09-10 Globalfoundries Inc. Methods of forming a non-planar ultra-thin body device
US9548303B2 (en) 2014-03-13 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices with unique fin shape and the fabrication thereof
US9443769B2 (en) 2014-04-21 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wrap-around contact
US9461170B2 (en) 2014-04-23 2016-10-04 Taiwan Semiconductor Manufacturing Company Ltd. FinFET with ESD protection
US10177133B2 (en) 2014-05-16 2019-01-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including source/drain contact having height below gate stack
US9608116B2 (en) 2014-06-27 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. FINFETs with wrap-around silicide and method forming the same
US9966471B2 (en) 2014-06-27 2018-05-08 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked Gate-All-Around FinFET and method forming the same
US9299803B2 (en) 2014-07-16 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method for semiconductor device fabrication
US10079283B2 (en) 2014-07-17 2018-09-18 E Ink Holdings Inc. Manufacturing method of a transistor
US9614088B2 (en) 2014-08-20 2017-04-04 Taiwan Semiconductor Manufacturing Company Ltd. Metal gate structure and manufacturing method thereof
US10263108B2 (en) 2014-08-22 2019-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-insensitive epitaxy formation
US9847329B2 (en) 2014-09-04 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Structure of fin feature and method of making same
US9450093B2 (en) 2014-10-15 2016-09-20 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device structure and manufacturing method thereof
US9437484B2 (en) 2014-10-17 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Etch stop layer in integrated circuits
US9478642B2 (en) * 2014-11-10 2016-10-25 Globalfoundries Inc. Semiconductor junction formation
US9508858B2 (en) 2014-11-18 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Contacts for highly scaled transistors
US9466494B2 (en) 2014-11-18 2016-10-11 Taiwan Semiconductor Manufacturing Company, Ltd. Selective growth for high-aspect ration metal fill
US9287403B1 (en) * 2014-12-05 2016-03-15 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET and method for manufacturing the same
US9613850B2 (en) 2014-12-19 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lithographic technique for feature cut by line-end shrink
US9412817B2 (en) 2014-12-19 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide regions in vertical gate all around (VGAA) devices and methods of forming same
US9780214B2 (en) 2014-12-22 2017-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including Fin- FET and manufacturing method thereof
US9515071B2 (en) 2014-12-24 2016-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Asymmetric source/drain depths
US9876114B2 (en) 2014-12-30 2018-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D FinFET metal gate
KR102262827B1 (ko) 2014-12-30 2021-06-08 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9502567B2 (en) 2015-02-13 2016-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor fin structure with extending gate structure
US9929242B2 (en) * 2015-01-12 2018-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9991384B2 (en) 2015-01-15 2018-06-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
US9391078B1 (en) 2015-01-16 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for finFET devices
US9349859B1 (en) 2015-01-29 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Top metal pads as local interconnectors of vertical transistors
US9406680B1 (en) 2015-02-13 2016-08-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
US9859115B2 (en) 2015-02-13 2018-01-02 National Taiwan University Semiconductor devices comprising 2D-materials and methods of manufacture thereof
US9673112B2 (en) 2015-02-13 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor fabrication with height control through active region profile
US9564493B2 (en) 2015-03-13 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Devices having a semiconductor material that is semimetal in bulk and methods of forming the same
US9406675B1 (en) 2015-03-16 2016-08-02 Taiwan Semiconductor Manufacturing Company Ltd. FinFET structure and method of manufacturing the same
US9502502B2 (en) 2015-03-16 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US9698048B2 (en) 2015-03-27 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating semiconductor device
US9570557B2 (en) 2015-04-29 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Tilt implantation for STI formation in FinFET structures
US10483262B2 (en) 2015-05-15 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Dual nitride stressor for semiconductor device and method of manufacturing
US9741829B2 (en) 2015-05-15 2017-08-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9761683B2 (en) 2015-05-15 2017-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9530889B2 (en) 2015-05-21 2016-12-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10062779B2 (en) 2015-05-22 2018-08-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10269968B2 (en) * 2015-06-03 2019-04-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures and manufacturing method thereof
US9647071B2 (en) 2015-06-15 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. FINFET structures and methods of forming the same
US9685368B2 (en) 2015-06-26 2017-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure having an etch stop layer over conductive lines
US10403744B2 (en) 2015-06-29 2019-09-03 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices comprising 2D-materials and methods of manufacture thereof
TWI647845B (zh) * 2015-06-29 2019-01-11 聯華電子股份有限公司 半導體結構及其製作方法
US9818872B2 (en) 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US11424399B2 (en) 2015-07-07 2022-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated thermoelectric devices in Fin FET technology
US9418886B1 (en) 2015-07-24 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming conductive features
US9536980B1 (en) 2015-07-28 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Gate spacers and methods of forming same
US9583623B2 (en) 2015-07-31 2017-02-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including fin structures disposed over buffer structures and manufacturing method thereof
US9721887B2 (en) 2015-08-19 2017-08-01 Taiwan Semiconductor Manufacturing Company, Ltd Method of forming metal interconnection
US9564363B1 (en) 2015-08-19 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming butted contact
US9831090B2 (en) 2015-08-19 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for semiconductor device having gate spacer protection layer
US9698100B2 (en) 2015-08-19 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for interconnection
US9786602B2 (en) 2015-08-21 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnection structure and methods of fabrication the same
US10164096B2 (en) 2015-08-21 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9728402B2 (en) 2015-08-21 2017-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Flowable films and methods of forming flowable films
US9666581B2 (en) 2015-08-21 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET with source/drain structure and method of fabrication thereof
US9490136B1 (en) 2015-08-31 2016-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming trench cut
US9647122B2 (en) 2015-09-15 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same
US10032873B2 (en) 2015-09-15 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same
US9680017B2 (en) 2015-09-16 2017-06-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including Fin FET and manufacturing method thereof
US9613856B1 (en) 2015-09-18 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming metal interconnection
US9972529B2 (en) 2015-09-28 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming metal interconnection
US10163797B2 (en) 2015-10-09 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Forming interlayer dielectric material by spin-on metal oxide deposition
US9735052B2 (en) 2015-10-12 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Metal lines for interconnect structure and method of manufacturing same
US9711533B2 (en) 2015-10-16 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices having different source/drain proximities for input/output devices and non-input/output devices and the method of fabrication thereof
US9659864B2 (en) 2015-10-20 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for forming self-aligned via with selectively deposited etching stop layer
US9647116B1 (en) 2015-10-28 2017-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating self-aligned contact in a semiconductor device
US9818690B2 (en) 2015-10-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned interconnection structure and method
US10121858B2 (en) 2015-10-30 2018-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Elongated semiconductor structure planarization
US9627531B1 (en) 2015-10-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Field-effect transistor with dual vertical gates
TWI683395B (zh) 2015-11-12 2020-01-21 聯華電子股份有限公司 鰭狀電晶體與鰭狀電晶體的製作方法
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US9899387B2 (en) 2015-11-16 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US10020304B2 (en) * 2015-11-16 2018-07-10 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor, semiconductor device and fabricating method thereof
US10164051B2 (en) 2015-11-16 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US9633999B1 (en) 2015-11-16 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for semiconductor mid-end-of-line (MEOL) process
US9960273B2 (en) 2015-11-16 2018-05-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure with substrate isolation and un-doped channel
US9773879B2 (en) 2015-11-30 2017-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
US10340348B2 (en) 2015-11-30 2019-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing finFETs with self-align contacts
US10163719B2 (en) 2015-12-15 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming self-alignment contact
US9873943B2 (en) 2015-12-15 2018-01-23 Taiwan Semiconductor Manufacturing Co., Ltd. Apparatus and method for spatial atomic layer deposition
US9728501B2 (en) 2015-12-21 2017-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming trenches
DE102016119024B4 (de) 2015-12-29 2023-12-21 Taiwan Semiconductor Manufacturing Co. Ltd. Verfahren zum Herstellen einer FinFET-Vorrichtung mit epitaktischen Elementen mit flacher Oberseite
US11264452B2 (en) 2015-12-29 2022-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Hetero-tunnel field-effect transistor (TFET) having a tunnel barrier formed directly above channel region, directly below first source/drain region and adjacent gate electrode
US10490552B2 (en) 2015-12-29 2019-11-26 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device having flat-top epitaxial features and method of making the same
US9887128B2 (en) 2015-12-29 2018-02-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method and structure for interconnection
US10163704B2 (en) 2015-12-29 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
US9614086B1 (en) 2015-12-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Conformal source and drain contacts for multi-gate field effect transistors
US11088030B2 (en) 2015-12-30 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
US9899269B2 (en) 2015-12-30 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd Multi-gate device and method of fabrication thereof
US10115796B2 (en) 2016-01-07 2018-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method of pulling-back sidewall metal layer
US10811262B2 (en) 2016-01-14 2020-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a uniform and thin silicide layer on an epitaxial source/ drain structure and manufacturing method thereof
US9881872B2 (en) 2016-01-15 2018-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating a local interconnect in a semiconductor device
US10727094B2 (en) 2016-01-29 2020-07-28 Taiwan Semiconductor Manufacturing Co., Ltd Thermal reflector device for semiconductor fabrication tool
US10283605B2 (en) 2016-01-29 2019-05-07 Taiwan Semiconductor Manufacturing Co., Ltd Self-aligned metal gate etch back process and device
US10163912B2 (en) 2016-01-29 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Method for semiconductor device fabrication with improved source drain proximity
US9812451B2 (en) 2016-02-03 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd Field effect transistor contact with reduced contact resistance
US10535558B2 (en) 2016-02-09 2020-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming trenches
US9543161B1 (en) 2016-02-10 2017-01-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method of planarizating film
US9947756B2 (en) 2016-02-18 2018-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof
US9825036B2 (en) 2016-02-23 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for semiconductor device
US9754822B1 (en) 2016-03-02 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method
US9570556B1 (en) 2016-03-03 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9755019B1 (en) 2016-03-03 2017-09-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10056407B2 (en) 2016-03-04 2018-08-21 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor device and a method for fabricating the same
US10109627B2 (en) 2016-03-08 2018-10-23 Taiwan Semiconductor Manufacturing Co., Ltd. Enlarging spacer thickness by forming a dielectric layer over a recessed interlayer dielectric
US9711402B1 (en) 2016-03-08 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming contact metal
US9911611B2 (en) 2016-03-17 2018-03-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming openings in a material layer
US9779984B1 (en) 2016-03-25 2017-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming trenches with different depths
DE102016114724B4 (de) 2016-03-25 2021-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Verfahren zum Ausbilden von Gräben mit unterschiedlichen Tiefen und Vorrichtung
US10366900B2 (en) * 2016-03-25 2019-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10340383B2 (en) 2016-03-25 2019-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having stressor layer
US9748389B1 (en) 2016-03-25 2017-08-29 Taiwan Semiconductor Manufacturing Co., Ltd. Method for semiconductor device fabrication with improved source drain epitaxy
US9548366B1 (en) 2016-04-04 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. Self aligned contact scheme
US9847477B2 (en) 2016-04-12 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a bottom electrode of a magnetoresistive random access memory cell
US9805951B1 (en) 2016-04-15 2017-10-31 Taiwan Semiconductor Manufacturing Co., Ltd. Method of integration process for metal CMP
US10163898B2 (en) 2016-04-25 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods of forming FinFETs
US10475847B2 (en) 2016-04-28 2019-11-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having stress-neutralized film stack and method of fabricating same
US9893062B2 (en) 2016-04-28 2018-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
US9899266B2 (en) 2016-05-02 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET structures and methods of forming the same
US11127629B2 (en) 2016-05-17 2021-09-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
US10276662B2 (en) 2016-05-31 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming contact trench
US9917085B2 (en) 2016-05-31 2018-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate isolation structure and method forming same
US9899382B2 (en) 2016-06-01 2018-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor (FinFET) device structure with different gate profile and method for forming the same
US9941386B2 (en) 2016-06-01 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with fin structure and method for forming the same
US10109467B2 (en) 2016-06-01 2018-10-23 Taiwan Semiconductor Manufacturing Co., Ltd. Advanced exhaust system
US9627258B1 (en) 2016-06-15 2017-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a contact
US10164032B2 (en) 2016-06-17 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned contact and manufacturing method thereof
US10515822B2 (en) 2016-06-20 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method for preventing bottom layer wrinkling in a semiconductor device
US10008414B2 (en) 2016-06-28 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for widening Fin widths for small pitch FinFET devices
US10685873B2 (en) 2016-06-29 2020-06-16 Taiwan Semiconductor Manufacturing Co., Ltd. Etch stop layer for semiconductor devices
US10115624B2 (en) 2016-06-30 2018-10-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method of semiconductor integrated circuit fabrication
US10164098B2 (en) 2016-06-30 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device
US9768064B1 (en) 2016-07-14 2017-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Formation method of semiconductor device structure
US9640540B1 (en) 2016-07-19 2017-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for an SRAM circuit
US9870926B1 (en) 2016-07-28 2018-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US9721805B1 (en) 2016-07-29 2017-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Formation method of semiconductor device structure
US10121873B2 (en) 2016-07-29 2018-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate and contact plug design and method forming same
US10199500B2 (en) 2016-08-02 2019-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer film device and method
US10164111B2 (en) 2016-08-03 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and methods of manufacture
US10510850B2 (en) 2016-08-03 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10043886B2 (en) 2016-08-03 2018-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate formation through etch back process
US9929271B2 (en) 2016-08-03 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10522536B2 (en) 2016-08-03 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device with gate stacks
US9991205B2 (en) 2016-08-03 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
KR102460862B1 (ko) * 2016-08-04 2022-10-28 삼성전자주식회사 반도체 장치
US9997524B2 (en) 2016-08-24 2018-06-12 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor memory device and manufacturing method thereof
US10269926B2 (en) 2016-08-24 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Purging deposition tools to reduce oxygen and moisture in wafers
US9865697B1 (en) 2016-08-25 2018-01-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
US9812358B1 (en) 2016-09-14 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET structures and methods of forming the same
US10008418B2 (en) 2016-09-30 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method of semiconductor integrated circuit fabrication
US10026840B2 (en) 2016-10-13 2018-07-17 Taiwan Semiconductor Manufacturing Co., Ltd. Structure of semiconductor device with source/drain structures
US10510618B2 (en) 2016-10-24 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET EPI channels having different heights on a stepped substrate
US9865589B1 (en) 2016-10-31 2018-01-09 Taiwan Semiconductor Manufacturing Co., Ltd. System and method of fabricating ESD FinFET with improved metal landing in the drain
US10872889B2 (en) 2016-11-17 2020-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor component and fabricating method thereof
US10529861B2 (en) 2016-11-18 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET structures and methods of forming the same
US10049930B2 (en) 2016-11-28 2018-08-14 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device and operation method thereof
US11437516B2 (en) 2016-11-28 2022-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for growing epitaxy structure of finFET device
US10043665B2 (en) 2016-11-28 2018-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Formation method of semiconductor device structure with semiconductor nanowire
US9837539B1 (en) 2016-11-29 2017-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of forming
US10510598B2 (en) 2016-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned spacers and method forming same
US9812363B1 (en) 2016-11-29 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of forming same
US9881834B1 (en) 2016-11-29 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Contact openings and methods forming same
US10490661B2 (en) 2016-11-29 2019-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Dopant concentration boost in epitaxially formed material
US9935173B1 (en) 2016-11-29 2018-04-03 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure
US10515951B2 (en) * 2016-11-29 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9985134B1 (en) 2016-11-29 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods of forming FinFETs
US10290546B2 (en) 2016-11-29 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Threshold voltage adjustment for a gate-all-around semiconductor structure
US10008416B2 (en) 2016-11-30 2018-06-26 Taiwan Semiconductor Manufacturing Co., Ltd. Forming a protective layer to prevent formation of leakage paths
US10707316B2 (en) 2016-12-09 2020-07-07 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure with gate structure
US10157781B2 (en) 2016-12-14 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor structure using polishing process
US9865595B1 (en) 2016-12-14 2018-01-09 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device with epitaxial structures that wrap around the fins and the method of fabricating the same
US10651171B2 (en) 2016-12-15 2020-05-12 Taiwan Semiconductor Manufacturing Co. Ltd. Integrated circuit with a gate structure and method making the same
US10049936B2 (en) 2016-12-15 2018-08-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having merged epitaxial features with Arc-like bottom surface and method of making the same
US9972571B1 (en) 2016-12-15 2018-05-15 Taiwan Semiconductor Manufacturing Co., Ltd. Logic cell structure and method
US10431670B2 (en) 2016-12-15 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd Source and drain formation technique for fin-like field effect transistor
US10079289B2 (en) 2016-12-22 2018-09-18 Taiwan Semiconductor Manufacturing Co., Ltd. Metal gate structure and methods thereof
US10164106B2 (en) 2016-12-29 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
US9985023B1 (en) 2017-02-21 2018-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure
US9859364B1 (en) 2017-03-03 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and manufacturing method thereof
US10153198B2 (en) 2017-04-07 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Low-resistance contact plugs and method forming same
US10522643B2 (en) 2017-04-26 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Device and method for tuning threshold voltage by implementing different work function metals in different segments of a gate
US10522417B2 (en) 2017-04-27 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET device with different liners for PFET and NFET and method of fabricating thereof
US10541319B2 (en) * 2017-08-30 2020-01-21 Taiwan Semiconductor Manufacturing Co., Ltd. Fin structures having varied fin heights for semiconductor device
US10453753B2 (en) 2017-08-31 2019-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Using a metal-containing layer as an etching stop layer and to pattern source/drain regions of a FinFET
US10276697B1 (en) 2017-10-27 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Negative capacitance FET with improved reliability performance
US10522557B2 (en) 2017-10-30 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Surface topography by forming spacer-like components
US10366915B2 (en) 2017-11-15 2019-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET devices with embedded air gaps and the fabrication thereof
US10510894B2 (en) 2017-11-30 2019-12-17 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation structure having different distances to adjacent FinFET devices
US10756114B2 (en) 2017-12-28 2020-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor circuit with metal structure and manufacturing method
KR102402763B1 (ko) * 2018-03-27 2022-05-26 삼성전자주식회사 반도체 장치
US10854615B2 (en) 2018-03-30 2020-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET having non-merging epitaxially grown source/drains
US10861973B2 (en) 2018-06-27 2020-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Negative capacitance transistor with a diffusion blocking layer
US11302535B2 (en) 2018-06-27 2022-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Performing annealing process to improve fin quality of a FinFET semiconductor
US10665506B2 (en) 2018-06-27 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with reduced via bridging risk
US10388771B1 (en) 2018-06-28 2019-08-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method and device for forming cut-metal-gate feature
US10790352B2 (en) 2018-06-28 2020-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. High density capacitor implemented using FinFET
US10886226B2 (en) 2018-07-31 2021-01-05 Taiwan Semiconductor Manufacturing Co, Ltd. Conductive contact having staircase barrier layers
US10998241B2 (en) 2018-09-19 2021-05-04 Taiwan Semiconductor Manufacturing Co., Ltd. Selective dual silicide formation using a maskless fabrication process flow
US11210447B2 (en) 2018-09-26 2021-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Reconfiguring layout and sizing for transistor components to simultaneously optimize logic devices and non-logic devices
US11222958B2 (en) 2018-09-28 2022-01-11 Taiwan Semiconductor Manufacturing Co., Ltd. Negative capacitance transistor with external ferroelectric structure
US11069793B2 (en) 2018-09-28 2021-07-20 Taiwan Semiconductor Manufacturing Co., Ltd. Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers
US10629752B1 (en) * 2018-10-11 2020-04-21 Applied Materials, Inc. Gate all-around device
US11139203B2 (en) 2018-10-22 2021-10-05 Taiwan Semiconductor Manufacturing Co., Ltd. Using mask layers to facilitate the formation of self-aligned contacts and vias
US10971605B2 (en) 2018-10-22 2021-04-06 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy dielectric fin design for parasitic capacitance reduction
US11101347B2 (en) 2018-11-29 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Confined source/drain epitaxy regions and method forming same
US11282934B2 (en) 2019-07-26 2022-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Structure for metal gate electrode and method of fabrication
US11508822B2 (en) 2019-09-25 2022-11-22 Taiwan Semiconductor Manufacturing Co., Ltd. Source/drain via having reduced resistance
US11557590B2 (en) 2020-02-19 2023-01-17 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor gate profile optimization
DE102020123264B4 (de) * 2020-03-30 2022-11-10 Taiwan Semiconductor Manufacturing Co. Ltd. Halbleitervorrichtung und Verfahren zu dessen Herstellung
US11764220B2 (en) 2020-04-27 2023-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device by patterning a serpentine cut pattern
US11769821B2 (en) 2020-05-15 2023-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a corner spacer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070001198A1 (en) * 2004-08-11 2007-01-04 Hynix Semiconductor Inc. Semiconductor device and method for forming the same
US20070037356A1 (en) * 2003-09-09 2007-02-15 Wagner Tina J Method of manufacture of raised source drain MOSFET with top notched gate structure filled with dielectric plug
US20090095980A1 (en) * 2007-10-16 2009-04-16 Chen-Hua Yu Reducing Resistance in Source and Drain Regions of FinFETs

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7456476B2 (en) * 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
KR100532353B1 (ko) * 2004-03-11 2005-11-30 삼성전자주식회사 핀 전계 효과 트랜지스터 및 그 제조방법
US7190050B2 (en) * 2005-07-01 2007-03-13 Synopsys, Inc. Integrated circuit on corrugated substrate
KR100661229B1 (ko) * 2005-12-29 2006-12-22 동부일렉트로닉스 주식회사 반도체 소자의 핀형 트랜지스터 제조 방법
US7494884B2 (en) * 2006-10-05 2009-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. SiGe selective growth without a hard mask
US7923337B2 (en) * 2007-06-20 2011-04-12 International Business Machines Corporation Fin field effect transistor devices with self-aligned source and drain regions
US8153493B2 (en) * 2008-08-28 2012-04-10 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET process compatible native transistor
US8138030B2 (en) * 2009-09-15 2012-03-20 International Business Machines Corporation Asymmetric finFET device with improved parasitic resistance and capacitance

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070037356A1 (en) * 2003-09-09 2007-02-15 Wagner Tina J Method of manufacture of raised source drain MOSFET with top notched gate structure filled with dielectric plug
US20070001198A1 (en) * 2004-08-11 2007-01-04 Hynix Semiconductor Inc. Semiconductor device and method for forming the same
US20090095980A1 (en) * 2007-10-16 2009-04-16 Chen-Hua Yu Reducing Resistance in Source and Drain Regions of FinFETs

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104241366A (zh) * 2013-06-07 2014-12-24 台湾积体电路制造股份有限公司 FinFET器件的源极区和漏极区中的位错形成
CN104241366B (zh) * 2013-06-07 2017-06-13 台湾积体电路制造股份有限公司 FinFET器件的源极区和漏极区中的位错形成
US10153344B2 (en) 2014-03-21 2018-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of dislocations in source and drain regions of FinFET devices
US11211455B2 (en) 2014-03-21 2021-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of dislocations in source and drain regions of FinFET devices
US10741642B2 (en) 2014-03-21 2020-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of dislocations in source and drain regions of finFET devices
US9768256B2 (en) 2014-03-21 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of dislocations in source and drain regions of FinFET devices
CN105097517A (zh) * 2014-04-25 2015-11-25 中芯国际集成电路制造(上海)有限公司 一种FinFET器件及其制造方法、电子装置
CN105097517B (zh) * 2014-04-25 2018-07-20 中芯国际集成电路制造(上海)有限公司 一种FinFET器件及其制造方法、电子装置
CN106158587B (zh) * 2015-05-15 2019-03-01 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN106158587A (zh) * 2015-05-15 2016-11-23 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN106252350A (zh) * 2015-06-15 2016-12-21 台湾积体电路制造股份有限公司 FinFET器件和形成方法
CN106252350B (zh) * 2015-06-15 2019-06-11 台湾积体电路制造股份有限公司 FinFET器件和形成方法
CN106531631A (zh) * 2015-09-09 2017-03-22 中国科学院微电子研究所 一种形成鳍的方法及结构
CN106531631B (zh) * 2015-09-09 2019-07-16 中国科学院微电子研究所 一种形成鳍的方法及结构
CN109411338A (zh) * 2017-08-15 2019-03-01 台湾积体电路制造股份有限公司 制造半导体元件的方法
US10818555B2 (en) 2017-08-15 2020-10-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having planar transistor and FinFET
US11328958B2 (en) 2017-08-15 2022-05-10 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having planar transistor and FinFET
US11063003B2 (en) 2018-10-02 2021-07-13 Nanya Technology Corporation Semiconductor device with diced semiconductor chips and method for manufacturing the same
CN110993569B (zh) * 2018-10-02 2021-07-30 南亚科技股份有限公司 半导体装置及其制作方法
CN110993569A (zh) * 2018-10-02 2020-04-10 南亚科技股份有限公司 半导体装置及其制作方法

Also Published As

Publication number Publication date
TW201316514A (zh) 2013-04-16
US9806076B2 (en) 2017-10-31
US9269632B2 (en) 2016-02-23
KR101279195B1 (ko) 2013-06-26
US20160240531A1 (en) 2016-08-18
US20130082304A1 (en) 2013-04-04
US20140206156A1 (en) 2014-07-24
TWI458096B (zh) 2014-10-21
CN103035713B (zh) 2016-03-09
KR20130036694A (ko) 2013-04-12
US8723272B2 (en) 2014-05-13

Similar Documents

Publication Publication Date Title
CN103035713B (zh) FinFET器件及其制造方法
US20210184019A1 (en) Structure of a Fin Field Effect Transistor (FinFET)
US8786019B2 (en) CMOS FinFET device
CN103066123B (zh) FinFET器件及其制造方法
US10490552B2 (en) FinFET device having flat-top epitaxial features and method of making the same
CN102468235B (zh) 鳍片场效应晶体管(finfet)器件及其制造方法
CN103050530B (zh) FinFET器件及其制造方法
US8445340B2 (en) Sacrificial offset protection film for a FinFET device
US9373549B2 (en) Semiconductor device and method of forming the same
TWI625858B (zh) 鰭式場效電晶體、半導體裝置及其製造方法
US10192985B2 (en) FinFET with doped isolation insulating layer
CN103715258A (zh) 用于半导体器件的源极/漏极堆叠件压力源
CN103000506A (zh) 改进的硅化物形成方式及相关器件
CN103928517A (zh) FinFET器件及其制造方法
CN103972097A (zh) 制造FinFET器件的方法
US20230378181A1 (en) Finfet device having flat-top epitaxial features and method of making the same
CN104183496A (zh) 鳍式场效应晶体管器件的制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant