WO2020089101A1 - Verfahren zur herstellung von optoelektronischen halbleiterbauteilen - Google Patents
Verfahren zur herstellung von optoelektronischen halbleiterbauteilen Download PDFInfo
- Publication number
- WO2020089101A1 WO2020089101A1 PCT/EP2019/079242 EP2019079242W WO2020089101A1 WO 2020089101 A1 WO2020089101 A1 WO 2020089101A1 EP 2019079242 W EP2019079242 W EP 2019079242W WO 2020089101 A1 WO2020089101 A1 WO 2020089101A1
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- WIPO (PCT)
- Prior art keywords
- semiconductor
- growth substrate
- auxiliary carrier
- layer
- carrier
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 250
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 230000005693 optoelectronics Effects 0.000 title claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 230000005855 radiation Effects 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims description 70
- 239000000463 material Substances 0.000 claims description 28
- 238000001465 metallisation Methods 0.000 claims description 26
- 238000000926 separation method Methods 0.000 claims description 26
- 239000000969 carrier Substances 0.000 claims description 16
- 238000011049 filling Methods 0.000 claims description 14
- 238000007788 roughening Methods 0.000 claims description 13
- 229910002601 GaN Inorganic materials 0.000 claims description 11
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 10
- 239000003795 chemical substances by application Substances 0.000 claims description 9
- 239000000945 filler Substances 0.000 claims description 6
- 238000012545 processing Methods 0.000 claims description 6
- 229910052594 sapphire Inorganic materials 0.000 claims description 6
- 239000010980 sapphire Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 238000012360 testing method Methods 0.000 claims description 5
- 239000011787 zinc oxide Substances 0.000 claims description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000000605 extraction Methods 0.000 claims 1
- 230000001771 impaired effect Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 138
- 238000012546 transfer Methods 0.000 description 15
- 238000002161 passivation Methods 0.000 description 11
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 239000011241 protective layer Substances 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 239000011888 foil Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000001427 coherent effect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 239000007767 bonding agent Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000002745 absorbent Effects 0.000 description 1
- 239000002250 absorbent Substances 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B43/00—Operations specially adapted for layered products and not otherwise provided for, e.g. repairing; Apparatus therefor
- B32B43/006—Delaminating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
- H01L2221/68322—Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68368—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
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- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/11—Methods of delaminating, per se; i.e., separating at bonding face
- Y10T156/1153—Temperature change for delamination [e.g., heating during delaminating, etc.]
- Y10T156/1158—Electromagnetic radiation applied to work for delamination [e.g., microwave, uv, ir, etc.]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/19—Delaminating means
- Y10T156/1911—Heating or cooling delaminating means [e.g., melting means, freezing means, etc.]
- Y10T156/1917—Electromagnetic radiation delaminating means [e.g., microwave, uv, ir, etc.]
Definitions
- a method for producing optoelectronic semiconductor components is specified.
- One task to be solved is a method for
- the method is used to produce one or to produce a large number of optoelectronic semiconductor components.
- Semiconductor components are, for example
- Light-emitting diodes LEDs for short, for lights, headlights or displays.
- the semiconductor components contain a multiplicity of transferred semiconductor chips. It is possible that in the course of the procedure within a
- the method comprises the step of providing a growth substrate.
- a multiplicity of semiconductor bodies for the semiconductor components are located on the growth substrate, for example a sapphire substrate.
- the semiconductor bodies are preferably made of a continuously grown, coherent
- separation trenches are present between adjacent semiconductor bodies, which preferably only partially penetrate the semiconductor layer sequence.
- the separation trenches are produced, for example, by means of etching and preferably extend through an active zone for generating radiation.
- the semiconductor layer sequence is preferably based on a III-V compound semiconductor material.
- the semiconductor material is, for example, a nitride
- Compound semiconductor material such as Al n In ] __ nm Ga m N or a phosphide compound semiconductor material such as
- Compound semiconductor material such as Al n In ] __ nm Ga m As or like Al n Ga m In ] __ nm As P ] _-k, where 0 dn ⁇ 1, 0 dm ⁇ 1 and n + m ⁇ 1 and 0 dk ⁇ 1 is.
- Semiconductor body each provided with electrical contact structures. This means that the semiconductor bodies can in principle be electrically contacted even on the growth substrate. It is not necessary for the semiconductor bodies to be individual electrical units that can be handled separately.
- the separating layer is preferably part of the
- the separating layer particularly preferably extends continuously over all semiconductor bodies. This means that the separation layer is not affected by the separation trenches.
- the separation layer is, for example, a GaN layer, in particular an undoped GaN layer. Parts of the semiconductor layer sequence bordering on the separating layer are, for example, n-doped.
- the method comprises the step of attaching a rigid first auxiliary carrier to a side of the growth substrate facing away from the growth substrate
- the first auxiliary carrier is attached to the electrical contact structures.
- the first auxiliary carrier comprises a first release layer.
- the method comprises the step of detaching the growth substrate from the
- Semiconductor layer sequences are preferably not or not significantly affected by the laser lifting process by means of the laser radiation.
- Contact structures can already be understood as semiconductor chips. These semiconductor chips are preferably functional in principle and / or suitable for generating light.
- the method comprises the step of attaching a rigid second auxiliary carrier to a side of the first carrier which is remote from the first
- the second submount is attached where the separating layer and the
- the second auxiliary carrier is provided with a second release layer.
- the method comprises the step of detaching the first auxiliary carrier by means of laser radiation.
- the laser radiation is in the first
- the first auxiliary carrier uses the first release layer to laser lift off in a manner comparable to that of
- the permanent carrier is, for example, a printed circuit board and / or a control chip for controlling the Semiconductor body. Depending on whether additional subcarriers
- the second subcarrier is by means of
- the method for producing optoelectronic semiconductor components comprises the following steps, preferably in the order given:
- the semiconductor bodies each being provided with electrical contact structures and comprising a separating layer towards the growth substrate,
- first auxiliary carrier Attaching a rigid first auxiliary carrier to a side of the semiconductor body facing away from the growth substrate, the first auxiliary carrier being provided with a first release layer,
- small semiconductor chips in particular LED chips
- small semiconductor chips can be handled.
- the term small semiconductor chips refer in particular to semiconductor chips with lateral dimensions of at most 130 ⁇ m or of at most 500 ⁇ m.
- detachment processes that are based on foils and film carriers, such small semiconductor chips can generally not be detached with reasonable effort. Bending radii of the commonly used foils are limited by the foil thickness and thus also the detachment of a foil from small semiconductor chips. For smaller bending radii, the film would have to be made thinner, which is not possible due to the wafer sizes used and the necessary expansion and expansion of the film. The films would then no longer have sufficient strength
- a thickness of the semiconductor layer sequence below 12 ⁇ m or 8 ⁇ m and only one, for example galvanically applied, stabilizing substructure with a thickness of at least 5 ⁇ m and / or at most 60 ⁇ m.
- Laser radiation in particular with the aid of so-called laser induced forward transfer or also with the aid of stamps or pick-and-place tools, is possible, especially with a selective detachment of selected semiconductor chips.
- Semiconductor bodies seen in plan view of the growth substrate have an average edge length of at least 5 ⁇ m or 10 ⁇ m or 20 ⁇ m or 40 ⁇ m. Alternatively or additionally, the average edge length is at most 500 ym or 200 ym or 130 ym or 100 ym.
- the semiconductor bodies or the semiconductor bodies which have been detached from the growth substrate are flip chips. This means that all electrical contact structures for external electrical contacting of the semiconductor body in question are preferably located on a side of the semiconductor body facing away from the growth substrate. Alternatively, it is possible for the semiconductor body for electrical contacting on both opposite main sides of the
- the separating layer for detaching the growth substrate extends continuously over the growth substrate and over the semiconductor bodies.
- the separating layer is an epitaxially grown layer on the growth substrate, in particular made of gallium nitride, with a thickness of at least 50 nm or 100 nm.
- the separating layer has a maximum thickness of at most 0.5 ⁇ m or at most 1 ⁇ m.
- the auxiliary carriers are attached to the semiconductor bodies by means of connecting agent layers.
- the connecting agent layers are preferably reversibly removable adhesives.
- the connecting agent layers can be removed, for example, with the aid of solvents or by increasing the temperature, the semiconductor bodies and the electrical ones
- the laser radiation used for detachment does not reach the connecting agent layers, or not to a significant extent.
- auxiliary carrier Most of the auxiliary carrier concerned, or, preferably, completely removed. That is, in the finished The connecting agent layers for the auxiliary carriers are no longer present in semiconductor components.
- At least one metallization for the contact structures extends across all semiconductor bodies. This means that the metallization and / or the contact structures also bridge areas between the semiconductor bodies.
- the at least one metallization can run congruently with the separating layer.
- the at least one metallization is in the areas between the
- Separation step is preferably also a
- Laser cutting for example by means of picosecond laser pulses. It is possible that when the at least one metallization is cut through further components
- Growth substrate are also severed or that this separation step is limited to the at least one metallization.
- regions between the semiconductor bodies are free of metallization for the contact structures when the growth substrate is detached.
- a protective layer or by a passivation layer has, for example, a thickness of at most 500 nm.
- the Metallization preferably has a thickness of at least 1 ⁇ m.
- protective layers or passivations are preferably made of dielectric materials, in contrast to metallization.
- Such protective layers or passivations can be made of organic or inorganic materials.
- Semiconductor body designed as LED chips. This means that the semiconductor bodies comprise one or more active zones for generating radiation in the intended operation of the finished semiconductor components. Those are preferred
- Semiconductor body made of the material system AlInGaN or AlInGaP and set up for the generation of blue light or red light.
- the roughening is in particular opposite the first and / or a third auxiliary carrier.
- the first auxiliary carrier is preferably attached to the semiconductor bodies.
- the second auxiliary carrier is detached by means of laser radiation.
- Laser radiation is absorbed in the second release layer.
- the second becomes due to the absorption of the laser radiation
- Peeling layer decomposes, analogous to the separating layer.
- Carriers That is, as long as the semiconductor bodies are attached to the second auxiliary carrier, the semiconductor bodies are not yet to the permanent carrier.
- the transfer to the carrier is thus preferably carried out by detaching from the second auxiliary carrier.
- a rigid third auxiliary carrier is attached after the first auxiliary carrier has been detached.
- the third auxiliary carrier is located in particular on the contact structures.
- the third subcarrier is
- the second auxiliary carrier can be located on the roughening.
- the roughening is only after the
- Subcarriers are.
- a multiplicity of the semiconductor bodies are transferred from the second auxiliary carrier or from the third auxiliary carrier to the permanent carrier. This is done for example by means of laser radiation and / or by means of a stamping process. Support surfaces and / or are preferably on the permanent support
- the filling material can be produced as long as the semiconductor body is still attached to the
- the filling material is severed in regions between the semiconductor bodies after the growth substrate has been detached.
- the filling material is produced in particular as long as that
- the growth substrate is still on the semiconductor bodies and thus before the first auxiliary carrier is attached.
- laser radiation can again be used, for example picosecond laser radiation. It is possible that the filling material is in the same
- Separation step is divided like the at least one
- the filling material is in particular a plastic.
- the laser radiation is used to detach the semiconductor bodies from the growth substrate
- Growth substrate and / or scanned via the subcarrier in question can be done with a galvanic mirror, with a polygon scanner or with multiple ones simultaneously via the growth substrate and / or the
- Subcarriers or when transferring from one of the subcarriers to the permanent carrier are considered Subcarriers or when transferring from one of the subcarriers to the permanent carrier.
- the grid size can also be increased during the respective transfer, in particular by an n-fold, where n is an integer greater than or equal to 2 and preferably less than or equal to 10. Furthermore, it is possible that only semiconductor bodies which have been tested for their function and are thus found to be functional are transferred. Semiconductor components can thus be produced with a multiplicity of semiconductor bodies, the semiconductor bodies in the
- Semiconductor bodies that have been grown on the growth substrate are distributed over several different permanent carriers. Furthermore, it is possible for several growth substrates to be used per permanent carrier in order to place semiconductor bodies on the relevant permanent carrier.
- the semiconductor bodies to be placed on the permanent carrier can be identical in construction or can also be designed differently from one another, for example for production
- RGB pixels Example red-green-blue pixels, abbreviated as RGB pixels.
- a multiplicity of the semiconductor bodies are attached to each carrier.
- An average distance between adjacent semiconductor bodies on the respective carrier is preferably small. For example, this average distance is at most 0.2 mm or 50 ⁇ m or 20 ⁇ m or 10 ⁇ m.
- the semiconductor bodies are tested before the semiconductor bodies are attached to the at least one permanent carrier and / or to one of the auxiliary carriers. This testing is done
- the semiconductor bodies are located during testing
- the contact structures can, for example, be planarized and / or ground.
- Material-removing processing is preferably carried out as long as the semiconductor bodies are on the second auxiliary carrier or on the third auxiliary carrier.
- coatings can also be applied, for example for a better one
- the auxiliary carriers or at least one of the auxiliary carriers is made of sapphire
- the auxiliary carriers and the growth substrate are preferably set up so that the
- Laser radiation for detaching the growth substrate or the relevant auxiliary carrier is radiated through the growth substrate or through the relevant auxiliary carrier. This means that the growth substrate and / or the auxiliary carriers are transparent to the laser radiation used for detachment and are not significantly absorbent.
- the separation layer is still partially present in the finished semiconductor components. This means that the separation layer is only partially removed. In this case it is possible that the separation layer
- the metallization forms a mirror on the side faces of the semiconductor bodies.
- radiation emission from the semiconductor bodies on the side faces can be prevented.
- Separating layer does not metallize.
- Figures 1 to 10 are schematic sectional views of
- FIGS 11 to 14 are schematic sectional views of
- Figures 15 to 18 are schematic sectional views of
- Figure 19 is a schematic sectional view of a
- Figure 20 is a schematic sectional view of a
- Figure 21 is a schematic sectional view of a
- Figure 22 is a schematic sectional view of a
- Figure 23 is a schematic sectional view of a
- FIGS. 1 to 10 An exemplary embodiment of a method described here is illustrated in FIGS. 1 to 10.
- a growth substrate 2 is provided.
- Growth substrate 2 is in particular a
- the semiconductor layer sequence is preferably based on AlInGaN.
- a separating layer 32 extends continuously over all semiconductor bodies 3
- Separating layer 32 can be directly or near that Growth substrate 2 are.
- the first and second Growth substrate 2 are directly or near that Growth substrate 2 are.
- Separation layer 32 is an undoped GaN layer.
- the semiconductor bodies 3 are formed by structuring one
- Semiconductor layer sequence was previously preferably produced continuously on the growth substrate 2. These steps take place before the production stage shown in FIG. 1.
- Semiconductor layer sequence preferably comprises the semiconductor bodies 3 formed by the structuring and also the separating layer 32
- Semiconductor layer sequence an active zone, not shown, in which the radiation to be emitted is generated during operation, in particular by means of electroluminescence.
- the active zone is preferably arranged at a distance from the separating layer 32.
- a separating alley 91 is located between adjacent semiconductor bodies 3.
- the material of the semiconductor layer sequence from which the semiconductor bodies 3 are made became, for example by means of etching
- the isolation lanes 91 preferably penetrate the active zone (not shown), so that individual areas of the active zone are limited to the individual semiconductor bodies 3 by the isolation lanes 91. That is, the active zone lies between the separation layer 32 and the
- the separating layer 32 may be exposed through the separating lanes 91, as is also possible in all other exemplary embodiments.
- Side surfaces of the individual semiconductor bodies 3 and a side of the separating layer 32 facing away from the growth substrate 2 are preferably covered by a passivation 83.
- the passivation 83 is, for example, an oxide layer such as one
- a thickness of the passivation 83 is, for example, at least 40 nm and / or at most 300 nm.
- Semiconductor body 3 is at least one each
- the semiconductor bodies 3 are via the contact structures 4
- the contact structures 4, each of which is illustrated in a very simplified manner in the figures, preferably contain both an anode contact and a cathode contact.
- the semiconductor bodies 3 can thus be designed together with the contact structures 4 as flip chips.
- Cathode contacts of the contact structure 4 are not shown. Furthermore, it is not shown that the metallization 40 and the contact structures 4 are preferably by several
- Contact structures 4 are produced, for example, by vapor deposition in combination with electroplating.
- the contact structures 4 are, for example, electroplated layers structured by photo technology. It is possible that the contact structures 4 are only thin and
- the contact structures 4 are formed, for example, by thin solderable metallizations on the semiconductor bodies 3.
- the contact structures 4 have a maximum thickness, for example
- the contact structures 4 can also have or be formed from electrically conductive oxides such as ITO.
- a thickness of the semiconductor body 3 together with the associated contact structures 4 is, for example, at least 30 ⁇ m and / or at most 70 ⁇ m. That is, the semiconductor body
- the thickness of the separating layer 32 is preferably at least 100 nm.
- the width of the separating lanes 91 between the semiconductor bodies 3 is preferably at least 0.5 ⁇ m or 1 ⁇ m or 5 ⁇ m and / or at most 70 ⁇ m or
- first auxiliary carrier 51 is attached to the contact structures 4.
- a first release layer 61 is located on the first auxiliary carrier 51.
- the release layer 61 is set up to absorb laser radiation.
- the release layer 61 is made of ZnO or SiN, for example.
- connection layer 71 is formed by an adhesive.
- Connection medium layer 71 adheres the first auxiliary carrier 51 to the semiconductor bodies 3 and thus indirectly to the latter
- Connection middle layer 71 are pressed.
- a growth radiation 2 radiates a laser radiation L onto the separating layer 32 and is absorbed therein.
- the separating layer 32 decomposes at least partially and the growth substrate 2 can be removed. After the semiconductor bodies 3 have been detached, the growth substrate 2 can be cleaned and used as well.
- the first auxiliary carrier 51 is, for example, a rigid one
- Sapphire glass or quartz glass substrate, as in all other exemplary embodiments.
- the first is preferred
- Subcarrier 51 transparent for near ultraviolet radiation, for example for laser radiation L around 355 nm. The same can apply to all other subcarriers 52, 53.
- a roughening 81 is produced on the semiconductor bodies 3. This is done, for example, using KOH etching.
- the Contact structures 4, passivation 83 and components 51, 61, 71 preferably remain unaffected by the generation of the roughening.
- Auxiliary carrier 51 is mechanically rigid, the second auxiliary carrier 52 and can be formed from the same materials as the first auxiliary carrier 51.
- a second release layer 62 is also located on the second auxiliary carrier 52, followed by a second connecting agent layer 72.
- connection layer 71 detached.
- the first auxiliary carrier 61 is preferably detached by means of laser radiation which passes through the first auxiliary carrier 51 onto the first
- Release layer 61 is blasted and absorbed therein, whereby the first release layer 61 is decomposed.
- This detaching step is analogous to the step in FIG. 3.
- the second connection layer 72 preferably remains intact or at least functional.
- the chemical properties of the connecting means 71, 72 such that the connecting means 71, 72 can be removed independently of one another.
- a further optional method step is shown in FIG.
- the contact structures 4 can be ground, polished and / or coated in order to achieve a more efficient electrical contact. It is also possible to add additional passivation layers or
- FIG. 8 also illustrates that the semiconductor bodies 3 can optionally be tested. You can do this
- Contact needles 84 are attached to the contact structures 4.
- matrix contacts can also be used.
- the semiconductor body 3 together with the contact structures 4 thus already form functional ones
- a radiation R generated by the semiconductor bodies 3 can be detected, for example, through the second auxiliary carrier 52.
- components 52, 62, 72 are preferably transparent or at least partially transparent to the generated radiation R.
- LIFT process which stands for Laser Induced Forward Transfer. This is done, for example, using an excimer laser Laser radiation L is irradiated only on certain semiconductor chips 10a. These semiconductor chips 10a
- Semiconductor chips 10a are placed in a targeted manner from the intermediate carrier 52 onto the carrier 5.
- Other semiconductor chips 10b can initially remain on the intermediate carrier 52 and be applied to another carrier, not shown.
- a distance between adjacent semiconductor chips 10a, 10b on the intermediate carrier 52 can be different from a distance between the semiconductor chips 10a, 10c placed on the carrier 5 and is essentially freely adjustable.
- solder layer 85 on the carrier 5, such as an adhesive solder.
- Solder layer 85 is shown in Figure 9 to simplify the
- a final cleaning and / or removal of residues of the layers 62, 72 is preferably carried out.
- the detachment according to FIG. 9 takes place, for example, by means of a polygon scanner, a galvanic mirror and / or with the aid of several laser spots. Defective and / or unsuitable semiconductor chips 10a, 10b can thus remain on the intermediate carrier 52.
- FIGS. 11 to 14 A further exemplary embodiment of the production method is shown in FIGS. 11 to 14.
- the steps in FIGS. 11 to 14 preferably follow the step in FIG. 7 or also the step in FIG. 8 and in particular represent alternatives to the steps in FIGS. 9 and 10.
- a third temporary, mechanically rigid intermediate carrier 53 is attached, on which there is a third release layer 63 and a third
- Connection middle layer 73 is located.
- components 51, 61, 71 and 52, 62, 72 apply correspondingly to components 53, 63, 73.
- FIG. 12 shows that the second auxiliary carrier 52 together with the components 62, 72 has been removed. With that lie the
- the third auxiliary carrier 53 is detached again by means of laser radiation L by destroying the third one
- Peeling layer 63 The placement on the carrier 5 takes place, for example, by means of a transfer tool 86, which can be a stamp. Preferably, by means of
- FIGS. 11 to 14 can thus be summarized in particular as follows:
- a coherent GaN separating layer 32 being present and the contact structures 4 or a rear-side metallization 40 being produced. Separation takes place by means of photographic technology, see FIG. 1, or a coherent electroplating layer, for example made of nickel, is used, see FIG. 15.
- a laser lifting process also referred to as laser liftoff or LLO for short, takes place by means of the GaN layer 32.
- the first intermediate carrier 51 is laser-lifted, preferably over the entire surface, by means of the layer 61, which is preferably made of SiN or ZnO.
- test measurement and / or a
- Auxiliary carrier 53 with a thin adhesive 73 takes place via the SiN layer or ZnO layer 62.
- the side on which the third auxiliary carrier 63 was located is cleaned.
- Back-end processes can be carried out, such as a chip transfer by means of stamping or by LIFT directly onto a target substrate 5 and / or an artificial wafer 5, it being possible for individual chips 10 or groups of chips 10 to be detached and transferred in a targeted manner by means of a single chip laser removal .
- FIGS. 15 to 18 relate to method steps which can be carried out as an alternative to the steps in FIGS. 1 to 4.
- the at least one metallization 40 extends, unlike in FIG. 1, essentially over the entire growth substrate 2, specifically over the area of the singulation lanes 91.
- the first intermediate carrier 51 is applied, see FIG. 16. Then the first intermediate carrier 51 is applied, see FIG. 16.
- the growth substrate 2 is preferably detached analogously to the method step in FIG. 3.
- a further method step is illustrated in FIG.
- a laser radiation L2 preferably one
- the metallization 40 is divided. This results in further isolation lanes 92 between the
- Isolation lanes 91 which are illustrated in Figure 1.
- Isolation lanes 91 For subdivision into the semiconductor chips 10 when separating the metallization 40, optionally not shown
- Protective layers are present, which in particular cover otherwise exposed areas of the semiconductor body 3 or also the entire synthetic wafer.
- FIG. 18 The method steps following FIG. 18 can take place according to FIGS. 5 to 10 or also according to FIGS. 11 to 14.
- FIG. 19 illustrates an optional method step which can be carried out both in the method according to FIGS. 15 to 18 and in methods according to FIGS. 1 to 10 or also FIGS. 11 to 14.
- a phosphor 87 is attached to the semiconductor bodies 3.
- the attachment of the phosphor 87 is, for example, a
- the phosphor 87 can also be applied to another process step.
- FIG. 20 illustrates that, for example, the first connection means 71 can not only be applied as a thin layer, but that the first connection means 71 can embed the semiconductor chips 3 and optionally the contact structures 4 completely or almost completely.
- FIG. 21 illustrates that a filler material 82 is additionally attached.
- the filling material 82 is, for example, a plastic.
- the contact structures 4 can in the
- Filling material 82 are embedded so that the filling material 82 is molded directly onto the contact structures 4. With the attachment of the filler material 82 or with one
- the filling material 82 and the contact structures 4 in the direction away from the semiconductor bodies 3 are flush with each other.
- the filling material 82 can be divided together with the metallization 40 in a method step analogous to FIG. 17. As in the method in FIGS. 15 to 18, such a filling material 82 can also be used in the method in accordance with FIGS. 1 to 10 and correspondingly in accordance with FIGS. 11 to 14
- FIG. 22 illustrates that the filler material 82 can only be attached when the
- auxiliary carriers 51, 52, 53 Semiconductor chips 10 are located on one of the auxiliary carriers 51, 52, 53.
- the filler material 82 need not be produced if the first auxiliary carrier 51 is present, but can alternatively also be produced only on the second auxiliary carrier 52 or on the third auxiliary carrier 53.
- FIG. 23 shows an alternative contacting of the
- semiconductor chips 10 illustrated which can be used accordingly in all other embodiments.
- the semiconductor chips 10 are not flip chips, but rather semiconductor chips with electrical ones
- the invention encompasses every new feature and every combination of features, which in particular includes every combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments.
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Abstract
Description
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US17/288,430 US20210358792A1 (en) | 2018-10-29 | 2019-10-25 | Method for Producing Optoelectronic Devices |
DE112019005387.6T DE112019005387A5 (de) | 2018-10-29 | 2019-10-25 | Verfahren zur herstellung von optoelektronischen halbleiterbauteilen |
JP2021523365A JP2022506167A (ja) | 2018-10-29 | 2019-10-25 | オプトエレクトロニクス半導体コンポーネントの製造方法 |
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DE102018126936.6A DE102018126936A1 (de) | 2018-10-29 | 2018-10-29 | Verfahren zur Herstellung von optoelektronischen Halbleiterbauteilen |
DE102018126936.6 | 2018-10-29 |
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US (1) | US20210358792A1 (de) |
JP (1) | JP2022506167A (de) |
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WO2020070986A1 (ja) * | 2018-10-02 | 2020-04-09 | 株式会社フィルネックス | 半導体素子の製造方法及び半導体基板 |
DE102020111394A1 (de) | 2020-04-27 | 2021-10-28 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Verfahren zum herstellen einer halbleiterlaseranordnung und halbleiterlaseranordnung |
DE102021119155A1 (de) | 2021-07-23 | 2023-01-26 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Verfahren zum aufbringen eines elektrischen verbindungsmaterials oder flussmittels auf ein bauelement |
DE102021121026A1 (de) | 2021-08-12 | 2023-02-16 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Verfahren zur Herstellung einer Vielzahl von Halbleiterlaserchips und Halbleiterlaserchip |
DE102022102364A1 (de) * | 2022-02-01 | 2023-08-03 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Vorrichtung zum transferieren und verfahren |
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DE102009060749A1 (de) * | 2009-12-30 | 2011-07-07 | OSRAM Opto Semiconductors GmbH, 93055 | Optoelektronischer Halbleiterchip und Verwendung einer auf AIGaN basierenden Zwischenschicht |
US20150179877A1 (en) * | 2013-12-20 | 2015-06-25 | LuxVue Technology Corporation | Nanowire device |
US20160268491A1 (en) * | 2014-12-01 | 2016-09-15 | Industrial Technology Research Institute | Picking-up and placing process for electronic devices and electronic module |
DE102016124646A1 (de) * | 2016-12-16 | 2018-06-21 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines Halbleiterbauelements |
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KR100853410B1 (ko) * | 2001-04-11 | 2008-08-21 | 소니 가부시키가이샤 | 소자의 전사방법 및 이를 이용한 소자의 배열방법,화상표시장치의 제조방법 |
JP2006140398A (ja) * | 2004-11-15 | 2006-06-01 | Sony Corp | 素子転写方法 |
CN102106006B (zh) * | 2008-06-02 | 2014-12-10 | Lg伊诺特有限公司 | 用于制备半导体发光装置的支撑衬底和使用支撑衬底的半导体发光装置 |
DE102009056386B4 (de) * | 2009-11-30 | 2024-06-27 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Verfahren zur Herstellung eines Halbleiterbauelements |
JP2013211443A (ja) * | 2012-03-30 | 2013-10-10 | Toyohashi Univ Of Technology | 発光装置の製造方法 |
EP2893565B1 (de) * | 2012-09-05 | 2021-04-28 | Lumileds LLC | Laser scheidung den zwischenträger von gerätträger |
JP5986904B2 (ja) * | 2012-11-21 | 2016-09-06 | スタンレー電気株式会社 | 半導体発光素子アレイおよび車両用灯具 |
JP6384202B2 (ja) * | 2014-08-28 | 2018-09-05 | 日亜化学工業株式会社 | 発光装置の製造方法 |
JP6738802B2 (ja) * | 2015-03-30 | 2020-08-12 | ソニーセミコンダクタソリューションズ株式会社 | 電子デバイスおよび電子デバイスの製造方法 |
WO2017180693A1 (en) * | 2016-04-15 | 2017-10-19 | Glo Ab | Method of forming an array of a multi-device unit cell |
JP2018060993A (ja) * | 2016-09-29 | 2018-04-12 | 東レエンジニアリング株式会社 | 転写方法、実装方法、転写装置、及び実装装置 |
-
2018
- 2018-10-29 DE DE102018126936.6A patent/DE102018126936A1/de not_active Withdrawn
-
2019
- 2019-10-25 DE DE112019005387.6T patent/DE112019005387A5/de active Pending
- 2019-10-25 US US17/288,430 patent/US20210358792A1/en active Pending
- 2019-10-25 WO PCT/EP2019/079242 patent/WO2020089101A1/de active Application Filing
- 2019-10-25 JP JP2021523365A patent/JP2022506167A/ja active Pending
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DE102009060749A1 (de) * | 2009-12-30 | 2011-07-07 | OSRAM Opto Semiconductors GmbH, 93055 | Optoelektronischer Halbleiterchip und Verwendung einer auf AIGaN basierenden Zwischenschicht |
US20150179877A1 (en) * | 2013-12-20 | 2015-06-25 | LuxVue Technology Corporation | Nanowire device |
US20160268491A1 (en) * | 2014-12-01 | 2016-09-15 | Industrial Technology Research Institute | Picking-up and placing process for electronic devices and electronic module |
DE102016124646A1 (de) * | 2016-12-16 | 2018-06-21 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines Halbleiterbauelements |
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US20210358792A1 (en) | 2021-11-18 |
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JP2022506167A (ja) | 2022-01-17 |
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