WO2020083330A1 - 半导体器件的制造方法 - Google Patents

半导体器件的制造方法 Download PDF

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Publication number
WO2020083330A1
WO2020083330A1 PCT/CN2019/112946 CN2019112946W WO2020083330A1 WO 2020083330 A1 WO2020083330 A1 WO 2020083330A1 CN 2019112946 W CN2019112946 W CN 2019112946W WO 2020083330 A1 WO2020083330 A1 WO 2020083330A1
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hard mask
layer
mask layer
opening
etched
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PCT/CN2019/112946
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French (fr)
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刘少鹏
刘瑞盛
邵云亮
蒋信
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浙江驰拓科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • the invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a semiconductor device.
  • the general size is below 60nm, and the limitations of the general lithography machine and photoresist shape make it difficult to make semiconductor devices below 60nm. Therefore, the traditional scheme can only use a lithography machine with a higher specification during the patterning process, such as an infiltration lithography machine, resulting in a high manufacturing cost.
  • the present invention provides a method for manufacturing a semiconductor device, which can save the manufacturing cost of a small-sized device.
  • the invention provides a method for manufacturing a semiconductor device, including:
  • a substrate is provided, the substrate having a material layer to be etched formed thereon, a first hard mask layer is covered above the material layer to be etched, and a sacrificial layer is provided above the first hard mask layer;
  • the material layer to be etched is etched.
  • the material of the first hard mask layer is metal Ta.
  • the material of the sacrificial layer is SiO 2 .
  • the side wall of the opening has an angle of 0 ° to 2 ° with respect to the normal of the main surface of the substrate.
  • the backfilling insulating medium is SiO 2 or SiN, and the thickness of the insulating layer is
  • the backfilled metal is Ta or W.
  • the thickness worn away is
  • the etchant used in wet etching includes HF or BOE.
  • the material layer to be etched includes a MTJ stack layer, PRAM or PCRAM.
  • the method for manufacturing a semiconductor device uses a hole filling method to form a second hard mask layer above the first hard mask layer, and first uses the second hard mask layer as a hard mask to mask the first hard mask The film layer is etched, and then the first hard mask layer is used as a hard mask to etch the material layer to be etched. Since the general lithography machine's ability to pattern small-sized holes is better than that of lattices, Through the manufacturing method of the semiconductor device of the present invention, a general lithography machine (193 nm or more) can be used to make a pattern scheme of a small-sized semiconductor device to obtain a small-sized semiconductor device, thereby saving manufacturing costs.
  • FIG. 1 is a schematic flow chart of a method for manufacturing a semiconductor device of the present invention
  • FIGS. 2-10 respectively illustrate various intermediate stages of manufacturing a semiconductor device according to the method of the embodiment of the present invention
  • FIG. 11 is a schematic diagram of an opening angle in an embodiment of the present invention.
  • An embodiment of the present invention provides a method for manufacturing a semiconductor device. As shown in FIG. 1, the method includes:
  • a substrate having a material layer to be etched formed thereon, the material layer to be etched is covered with a first hard mask layer, and a sacrificial layer is provided above the first hard mask layer;
  • FIGS. 2 to 10 each intermediate stage of manufacturing a semiconductor device according to the method of the embodiment of the present invention is specifically shown.
  • a material layer 201 to be etched formed on a substrate is shown.
  • the material layer to be etched is covered with a first hard mask layer 202, and a sacrificial layer 203 is provided above the first hard mask layer 202.
  • the material of the first hard mask layer 202 may be metal Ta, and the thickness is generally taken
  • the sacrificial layer 203 can use SiO 2 oxide layer, the thickness is generally taken In FIG. 2, the thickness of the first hard mask layer 202 is The thickness of the sacrificial layer 203 is
  • the sacrificial layer 203 is etched to form an opening 204 until the first hard mask layer 202 is exposed.
  • the embodiment of the present invention is described by taking a 90 ° right angle opening as an example.
  • an insulating medium is backfilled in the opening 204 to form an insulating layer 205.
  • the backfilling insulating medium may be the same as or different from the material of the sacrificial layer, and may be SiO 2 or SiN.
  • the thickness of the insulating layer 205 is generally taken Figure 4 is
  • blank etch is performed to etch away the insulating layer 205 until the first hard mask layer 202 is exposed, and the thickness of the sacrificial layer 203 is
  • the opening 204 is backfilled with metal until the opening 204 is filled.
  • the backfilled metal can be Ta or W. As shown in FIG. 6, the backfilled metal forms the second hard mask layer 206.
  • the sacrificial layer 203 After profiling, the sacrificial layer 203 needs to be removed.
  • the wet etching method is used to remove the sacrificial layer 203, which has a high selectivity.
  • the etchant used includes HF or BOE. After the sacrificial layer 203 is removed, it is as shown in FIG. 8.
  • the first hard mask layer 202 is etched, using a self-aligned etching method, as shown in FIG. 9 after etching. Then, using the first hard mask layer 202 as a hard mask, the material layer to be etched 201 is etched, and a self-aligned etching method is used. After etching, as shown in FIG. 10, a small-sized semiconductor device is formed.
  • the method for manufacturing a semiconductor device uses a hole filling method to form a second hard mask layer above the first hard mask layer, and first uses the second hard mask layer as a hard mask for the first The hard mask layer is etched, and then the first hard mask layer is used as the hard mask to etch the material layer to be etched, thereby obtaining a small-sized semiconductor device.
  • a pattern scheme of a small-sized semiconductor device can be made using a general lithography machine (193 nm or more), a small-sized semiconductor device is obtained, and the manufacturing cost is saved.
  • the side wall of the opening formed relative to the normal of the main surface of the substrate may have an angle of 0 ° to 2 °, as shown by the angle ⁇ in FIG. 11, that is, in FIG. 11
  • the ⁇ angle is 88 ° to 90 °.
  • the method for manufacturing a semiconductor device according to an embodiment of the present invention is suitable for manufacturing semiconductor devices such as MTJ devices, PRAM or PCRAM, and the corresponding material layers to be etched are MTJ stacked layers, PRAM or PCRAM in sequence.

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

一种半导体器件的制造方法，包括：提供衬底，衬底具有形成在其上的待刻蚀材料层（201），待刻蚀材料层（201）上方覆盖有第一硬掩膜层（202），第一硬掩膜层（202）上方具有牺牲层（203）；在牺牲层（203）中进行刻蚀形成开口（204），直至暴露出第一硬掩膜层（202）；在开口（204）内回填绝缘介质，形成绝缘层（205）；进行无掩膜刻蚀，将绝缘层（205）刻蚀掉，直至暴露出第一硬掩膜层（202）；在开口（204）内回填金属直至填充满开口（204），形成第二硬掩膜层（206）；进行CMP剖光，使表面平整；采用湿法腐蚀的方法去除牺牲层（203）；使用第二硬掩膜层（206）作为硬掩膜，对第一硬掩膜层（202）进行刻蚀；使用第一硬掩膜层（202）作为硬掩膜，对待刻蚀材料层（201）进行刻蚀。

Description

半导体器件的制造方法 技术领域
本发明涉及半导体制造技术领域，尤其涉及一种半导体器件的制造方法。
背景技术
传统的光刻技术受到光刻胶和工艺的限制，过于小而高的光刻胶很容易坍塌、堆叠或者粘着力不够，制作小尺寸半导体器件有一定的难度。
对于小尺寸半导体器件，如MTJ器件、PRAM或者PCRAM等，一般尺寸在60nm以下，而一般的光刻机和光刻胶形貌的限制使得很难做出60nm以下的半导体器件。因此传统方案在图形化过程中只能采用规格较高的光刻机，如浸润式光刻机，造成制造成本偏高。
发明内容
针对现有技术的缺陷，本发明提供一种半导体器件的制造方法，能够节约小尺寸器件的制造成本。
本发明提供一种半导体器件的制造方法，包括：
提供衬底，所述衬底具有形成在其上的待刻蚀材料层，所述待刻蚀材料层上方覆盖有第一硬掩膜层，所述第一硬掩膜层上方具有牺牲层；
在所述牺牲层中进行刻蚀形成开口，直至暴露出所述第一硬掩膜层；
在所述开口内回填绝缘介质，形成绝缘层；
进行无掩膜刻蚀，将所述绝缘层刻蚀掉，直至暴露出所述第一硬掩膜层；
在所述开口内回填金属直至填充满所述开口，形成第二硬掩膜层；
进行CMP剖光，使表面平整；
采用湿法腐蚀的方法去除所述牺牲层；
使用所述第二硬掩膜层作为硬掩膜，对所述第一硬掩膜层进行刻蚀；
使用所述第一硬掩膜层作为硬掩膜，对所述待刻蚀材料层进行刻蚀。
可选地，所述第一硬掩膜层的材料为金属Ta。
可选地，所述牺牲层的材料为SiO 2。
可选地，相对于所述衬底的主表面的法线，所述开口的侧壁具有0°至2°的角度。
可选地，回填的绝缘介质为SiO 2或者SiN，所述绝缘层的厚度为
Figure PCTCN2019112946-appb-000001
可选地，回填的金属为Ta或者W。
可选地，进行CMP剖光时，磨掉的厚度为
Figure PCTCN2019112946-appb-000002
可选地，湿法腐蚀使用的腐蚀剂包括HF或者BOE。
可选地，所述待刻蚀材料层包括MTJ堆叠层、PRAM或者PCRAM。
本发明提供的半导体器件的制造方法，采用孔填充的方法，在第一硬掩膜层的上方形成第二硬掩膜层，先使用第二硬掩膜层作为硬掩膜对第一硬掩膜层进行刻蚀，再使用第一硬掩膜层作为硬掩膜对待刻蚀材料层进行刻蚀，由于一般光刻机对小尺寸孔的图形化能力要好于对点阵的图形化能力，通过本发明的半导体器件的制造方法，使用一般的光刻机(193nm以上)就可以做出小尺寸半导体器件的图形方案，得到小尺寸的半导体器件，节约了制造成本。
附图说明
图1为本发明的一种半导体器件的制造方法的流程示意图；
图2-图10分别示出了根据本发明实施例的方法制造半导体器件的各个中间阶段；
图11为本发明实施例中的开口角度的示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明实施例提供一种半导体器件的制造方法，如图1所示，所述方法包括：
S101、提供衬底，衬底具有形成在其上的待刻蚀材料层，待刻蚀材料层上方覆盖有第一硬掩膜层，第一硬掩膜层上方具有牺牲层；
S102、在牺牲层中进行刻蚀形成开口，直至暴露出第一硬掩膜层；
S103、在开口内回填绝缘介质，形成绝缘层；
S104、进行无掩膜刻蚀，将绝缘层刻蚀掉，直至暴露出第一硬掩膜层；
S105、在开口内回填金属直至填充满开口，形成第二硬掩膜层；
S106、进行CMP剖光，使表面平整；
S107、采用湿法腐蚀的方法去除牺牲层；
S108、使用第二硬掩膜层作为硬掩膜，对第一硬掩膜层进行刻蚀；
S109、使用第一硬掩膜层作为硬掩膜，对待刻蚀材料层进行刻蚀。
为了更加清楚，参考图2至图10，具体示出了根据本发明实施例的方法制造半导体器件的各个中间阶段。首先如图2，示出了形成在衬底上的待刻蚀材料层201，待刻蚀材料层上方覆盖有第一硬掩膜层202，第一硬掩膜层202上方具有牺牲层203。第一硬掩膜层202的材料可以为金属Ta，厚度一般取
Figure PCTCN2019112946-appb-000003
牺牲层203可以采用SiO 2氧化层，厚度一般取
Figure PCTCN2019112946-appb-000004
图 2中，第一硬掩膜层202厚度为
Figure PCTCN2019112946-appb-000005
牺牲层203厚度为
Figure PCTCN2019112946-appb-000006
如图3所示，在牺牲层203中进行刻蚀形成开口204，直至暴露出第一硬掩膜层202。本发明实施例以90°直角开口为例进行说明。
进一步地，如图4所示，在开口204内回填绝缘介质，形成绝缘层205。回填的绝缘介质可以和牺牲层材料相同或者不同，可以为SiO 2或者SiN，绝缘层205的厚度一般取
Figure PCTCN2019112946-appb-000007
图4中为
Figure PCTCN2019112946-appb-000008
接着，如图5所示，进行无掩膜刻蚀(blanket etch)，将绝缘层205刻蚀掉，直至暴露出第一硬掩膜层202，此时牺牲层203的厚度为
Figure PCTCN2019112946-appb-000009
之后，在开口204内回填金属直至填充满开口204，回填的金属可以选择Ta或者W，如图6所示，回填的金属形成第二硬掩膜层206。
再进行CMP剖光，使表面平整。进行CMP剖光时，磨掉的厚度为
Figure PCTCN2019112946-appb-000010
剖光后如图7所示，图7中磨掉
Figure PCTCN2019112946-appb-000011
剖光之后，需要进行牺牲层203的去除。采用湿法腐蚀的方法去除牺牲层203，具有高选择比，使用的腐蚀剂包括HF或者BOE等。去除牺牲层203后如图8所示。
接下来，使用第二硬掩膜层206作为硬掩膜，对第一硬掩膜层202进行刻蚀，使用自对准刻蚀方法，刻蚀后如图9所示。再使用第一硬掩膜层202作为硬掩膜，对待刻蚀材料层201进行刻蚀，使用自对准刻蚀方法，刻蚀后如图10所示，也就形成了小尺寸半导体器件。
本发明实施例提供的半导体器件的制造方法，采用孔填充的方法，在第一硬掩膜层的上方形成第二硬掩膜层，先使用第二硬掩膜层作为硬掩膜对第一硬掩膜层进行刻蚀，再使用第一硬掩膜层作为硬掩膜对待刻蚀材料层进行刻蚀，从而得到小尺寸的半导体器件。通过本发明的半导体器件的制造方法，使用一 般的光刻机(193nm以上)就可以做出小尺寸半导体器件的图形方案，得到小尺寸的半导体器件，节约了制造成本。
需要说明的是，实际制造过程中，形成的开口相对于衬底的主表面的法线，其侧壁可以具有0°至2°的角度，如图11中的α角，即图11中的β角为88°至90°。
另外，本发明实施例的半导体器件的制造方法适用于制造MTJ器件、PRAM或者PCRAM等半导体器件，对应的待刻蚀材料层依次为MTJ堆叠层、PRAM或者PCRAM。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求的保护范围为准。

Claims (9)

  1. 一种半导体器件的制造方法，其特征在于，包括：
    提供衬底，所述衬底具有形成在其上的待刻蚀材料层，所述待刻蚀材料层上方覆盖有第一硬掩膜层，所述第一硬掩膜层上方具有牺牲层；
    在所述牺牲层中进行刻蚀形成开口，直至暴露出所述第一硬掩膜层；
    在所述开口内回填绝缘介质，形成绝缘层；
    进行无掩膜刻蚀，将所述绝缘层刻蚀掉，直至暴露出所述第一硬掩膜层；
    在所述开口内回填金属直至填充满所述开口，形成第二硬掩膜层；
    进行CMP剖光，使表面平整；
    采用湿法腐蚀的方法去除所述牺牲层；
    使用所述第二硬掩膜层作为硬掩膜，对所述第一硬掩膜层进行刻蚀；
    使用所述第一硬掩膜层作为硬掩膜，对所述待刻蚀材料层进行刻蚀。
  2. 根据权利要求1所述的方法，其特征在于，所述第一硬掩膜层的材料为金属Ta。
  3. 根据权利要求1所述的方法，其特征在于，所述牺牲层的材料为SiO 2。
  4. 根据权利要求1所述的方法，其特征在于，相对于所述衬底的主表面的法线，所述开口的侧壁具有0°至2°的角度。
  5. 根据权利要求1所述的方法，其特征在于，回填的绝缘介质为SiO 2或者SiN，所述绝缘层的厚度为
    Figure PCTCN2019112946-appb-100001
  6. 根据权利要求1所述的方法，其特征在于，回填的金属为Ta或者W。
  7. 根据权利要求1所述的方法，其特征在于，进行CMP剖光时，磨掉的厚度为
    Figure PCTCN2019112946-appb-100002
  8. 根据权利要求1所述的方法，其特征在于，湿法腐蚀使用的腐蚀剂包括HF或者BOE。
  9. 根据权利要求1所述的方法，其特征在于，所述待刻蚀材料层包括MTJ堆叠层、PRAM或者PCRAM。
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