WO2020082531A1 - 阵列基板、该阵列基板的制备方法及显示面板 - Google Patents

阵列基板、该阵列基板的制备方法及显示面板 Download PDF

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Publication number
WO2020082531A1
WO2020082531A1 PCT/CN2018/120402 CN2018120402W WO2020082531A1 WO 2020082531 A1 WO2020082531 A1 WO 2020082531A1 CN 2018120402 W CN2018120402 W CN 2018120402W WO 2020082531 A1 WO2020082531 A1 WO 2020082531A1
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Prior art keywords
metal trace
array substrate
insulating layer
orthographic projection
layer
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PCT/CN2018/120402
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English (en)
French (fr)
Inventor
方宏
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/333,239 priority Critical patent/US11139361B2/en
Publication of WO2020082531A1 publication Critical patent/WO2020082531A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
    • H10K71/236—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers using printing techniques, e.g. applying the etch liquid using an ink jet printer

Definitions

  • the present invention relates to the field of display technology, and in particular, to an array substrate, a preparation method of the array substrate, and a display panel.
  • LCD liquid crystal displays
  • OLED Organic Light Flat panel display technologies such as Emitting Diode
  • OLED has many advantages such as self-luminescence, low driving voltage, high luminous efficiency, short response time, high clarity and contrast, nearly 180 degrees viewing angle, wide temperature range, flexible display and large-area full-color display.
  • the industry is recognized as the most promising display device.
  • OLED can be divided into passive OLED (PMOLED) and active OLED (AMOLED) according to the driving type.
  • AMOLED is usually made of low temperature polysilicon (Low Temperature Poly-Silicon (LTPS) drives the backplane and electrically excited light layer to form a self-luminous component.
  • Low temperature polysilicon has a higher electron mobility.
  • the use of low temperature polysilicon material has the advantages of high resolution, fast reaction speed, high brightness, high aperture ratio, low energy consumption and so on.
  • the technical problem to be solved by the present invention is to provide an array substrate, a preparation method of the array substrate, and a display panel, which can prevent metal traces from being broken during bending and stretching, and improve the bending and stretching process of the array substrate
  • the reliability of medium metal wiring improves the bending and stretching performance of the array substrate.
  • the present invention provides an array substrate including at least one first metal trace and at least one second metal trace above the first metal trace, the first metal trace and all The second metal traces are insulated from each other, the first metal trace has a plurality of first concave portions and a plurality of first convex portions arranged alternately, and the second metal trace has a plurality of second concave portions arranged alternately And a plurality of second convex portions.
  • an orthographic projection of the first metal trace crosses an orthographic projection of the second metal trace.
  • the array substrate further includes at least one third metal trace, the third metal trace is located above the first metal trace and below the second metal trace, the first Three metal traces are insulated from the first metal trace and the second metal trace.
  • the third metal trace has a plurality of third concave portions and a plurality of third convex portions arranged alternately. In the direction of the array substrate, the orthographic projection of the first metal trace coincides with the orthographic projection of the third metal trace, the orthographic projection of the first concave portion coincides with the orthographic projection of the third concave part The orthographic projection of the first convex portion coincides with the orthographic projection of the third convex portion.
  • the first metal trace is a first gate scan line
  • the second metal trace is a data line
  • the third metal trace is a second gate scan line
  • the orthographic projection of the first metal trace coincides with the orthographic projection of the second metal trace, and the orthographic projection of the first concave portion and the first The orthographic projections of the two concave portions coincide, and the orthographic projections of the first convex portion coincide with the orthographic projections of the second convex portion.
  • the first metal trace is a first gate scan line
  • the second metal trace is a second gate scan line
  • first concave portions and the first convex portions are alternately arranged along the length of the first metal trace, and the second concave portions and the second convex portions are along the second metal The lengths of the traces are arranged alternately.
  • the first metal trace is a composite layer of Ti / Cu / Ti and Cu
  • the second metal trace is a composite layer of Ti / Cu / Ti and Cu.
  • the array substrate further includes a substrate, an active layer disposed on the substrate, a first insulating layer covering the active layer and an organic light-emitting layer, and a first metal
  • the wiring is disposed on the first insulating layer, a second insulating layer is disposed between the first metal wiring and the second metal wiring, and the organic light emitting layer is disposed on the second metal wiring Online and electrically connected to the second metal trace.
  • the invention also provides a method for preparing the above array substrate, comprising the following steps: providing a substrate, a surface of the substrate having an active layer; a surface of the active layer and the substrate The surface is covered with a first insulating layer, the first insulating layer includes a plurality of first regions having a first thickness and a plurality of second regions having a second thickness, the first thickness is smaller than the second Thickness, the first regions and the second regions are alternately arranged; the first metal trace is formed on the first insulating layer, and the first region of the first insulating layer, the first A metal trace forms the first concave portion, and in the second region of the first insulating layer, the first metal trace forms the first convex portion; it is formed on the first metal trace A second insulating layer, the second insulating layer includes a plurality of first regions having a first thickness and a plurality of second regions having a second thickness, the first thickness is less than the second thickness, the first A region alternates with the second region; formed on the
  • the orthographic projection of the first region of the second insulating layer is offset from the orthographic projection of the first concave portion of the first metal trace.
  • the orthographic projection of the first region of the second insulating layer coincides with the orthographic projection of the first concave portion of the first metal trace.
  • the method further includes the following steps: forming a third insulating layer on the second metal trace, the first The three insulating layers include a plurality of first regions having a first thickness and a plurality of second regions having a second thickness, the first thickness is smaller than the second thickness, the first regions alternate with the second regions Arranged, the orthographic projection of the first region of the third insulating layer is offset from the orthographic projection of the first concave portion of the second metal trace; a third metal is formed on the third insulating layer In the first area, the third metal trace forms a third concave portion, and in the second area, the third metal trace forms a third convex portion.
  • the preparation method further includes the steps of: covering a planarization layer on the second metal trace; forming an organic light-emitting layer on the planarization layer, one of the organic light-emitting layers The anode is electrically connected to a drain in the second metal trace.
  • the invention also provides a display panel, comprising the above array substrate and a cover plate provided on the array substrate.
  • the advantage of the present invention is that the wiring space of the metal traces is increased in the longitudinal direction, the length of the metal traces is extended, the metal traces are prevented from being broken during the bending and stretching process, and the array substrate is improved during the bending and stretching process The reliability of the metal wiring improves the bending and stretching performance of the array substrate.
  • 1 is a schematic plan view of the first embodiment of the array substrate of the present invention.
  • FIG. 2 is a schematic cross-sectional view taken along line A-A in FIG. 1;
  • FIG. 3 is a schematic cross-sectional view taken along line B-B in FIG. 1;
  • FIG. 4 is a schematic cross-sectional view of the first embodiment of the array substrate of the present invention.
  • 5A is a schematic top view of a second embodiment of the array substrate of the present invention.
  • 5B is a schematic cross-sectional view taken along line A-A in FIG. 5A;
  • 6A is a schematic top view of a third embodiment of the array substrate of the present invention.
  • 6B is a schematic cross-sectional view taken along line A-A in FIG. 6A;
  • FIGS. 7A-7L are process flow diagrams of the first embodiment of the method for manufacturing an array substrate of the present invention.
  • 8A-8P are process flow diagrams of the second embodiment of the method for manufacturing an array substrate of the present invention.
  • FIG. 9 is a schematic diagram of the structure of the display panel of the present invention.
  • FIG. 1 is a schematic top view of a first embodiment of an array substrate of the present invention
  • FIG. 2 is a schematic cross-sectional view taken along line AA in FIG. 1
  • FIG. 3 is a schematic cross-sectional view taken along line BB in FIG. 1, please refer to FIGS. 1, 2 and 3
  • the array substrate 100 of the present invention includes at least one first metal trace 1 and at least one second metal trace 2 located above the first metal trace 1.
  • two first metal traces 1 and two second metal traces 2 are schematically shown in the drawings.
  • the present invention is not limited to this. In other embodiments, all The number of the first metal traces 1 and the second metal traces 2 can be set according to actual needs.
  • the “above” refers to not the vertical above, but the positional relationship between the two layers.
  • the second metal trace 2 is located above the first metal trace 1 means that the layer where the second metal trace 2 is located is above the layer where the first metal trace 1 is located .
  • the relationship between the first metal trace 1 and the second metal trace 2 includes but is not limited to the intersection of the orthographic projection of the first metal trace 1 and the orthographic projection of the second metal trace 2 Or, the orthographic projection of the first metal trace 1 coincides with the orthographic projection of the second metal trace 2.
  • the orthographic projection of the first metal trace 1 and the second metal trace 2 The orthographic projection crosses.
  • the second metal trace 2 is a data line, which is connected to the source electrode 108 (see FIG. 4) of the thin film transistor of the array substrate 100.
  • the first metal trace 1 and the second metal trace 2 are insulated from each other.
  • a second insulating layer 105 is provided at and around the position where the first metal trace 1 and the second metal trace 2 intersect, so that the first metal trace 1 and all The second metal traces 2 are insulated from each other. Since the first metal trace 1 is blocked by the second insulating layer 105, in FIG. 1, the first metal trace 1 is depicted by a dotted line.
  • the first metal trace 1 has a plurality of first concave portions 10 and a plurality of first convex portions 11 arranged alternately, so that the first metal trace 1 forms a concave-convex structure.
  • the advantage is that the wiring space of the first metal trace 1 is raised in the longitudinal direction, the length of the first metal trace 1 is extended, and the first metal trace 1 is prevented from being broken during stretching during the bending process.
  • the reliability of the first metal trace 1 during the bending and stretching of the array substrate 100 is improved, and the bending and stretching performance of the array substrate 100 is improved.
  • the first concave portions 10 and the first convex portions 11 are alternately arranged along the length direction of the first metal trace 1.
  • the first concave portion 10 is schematically depicted by hatching to distinguish it from the first convex portion 11.
  • the second metal trace 2 has a plurality of second concave portions 20 and a plurality of second convex portions 21 arranged alternately, so that the second metal trace 2 forms a concave-convex structure.
  • the advantage is that the wiring space of the second metal trace 2 is raised in the longitudinal direction, the length of the second metal trace 2 is extended, and the second metal trace 2 is prevented from being broken during the bending and stretching process.
  • the reliability of the first metal trace 1 during the bending and stretching of the array substrate 100 is improved, and the bending and stretching performance of the array substrate 100 is improved.
  • the second concave portions 20 and the second convex portions 21 are alternately arranged along the length direction of the second metal trace 2.
  • the second concave portion 20 is schematically depicted by hatching to distinguish it from the second convex portion 21.
  • the first metal trace 1 and the second metal trace 2 may use a metal or a composite metal with good ductility, for example, a composite layer of Ti / Cu / Ti and Cu to improve the first
  • the bending performance of the metal trace 1 and the second metal trace 2 further provides the bending performance of the array substrate 100.
  • the array substrate 100 further includes a substrate 101, An active layer 102 disposed on the substrate 101, a first insulating layer 103 covering the active layer 102, and an organic light emitting layer 104.
  • the first metal trace 1 is connected to the gate 107 and is disposed on the first insulating layer 103.
  • the second insulating layer 105 is provided on the first metal trace 1, the second metal trace 2 is connected to the source 108, and is provided on the second insulator 105, so that the The first metal trace 1 is insulated from the second metal trace 2.
  • the organic light emitting layer 104 is disposed on the second metal trace 2 and is electrically connected to the second metal trace 2.
  • a flat layer 106 is provided between the organic light emitting layer 104 and the second metal trace 2.
  • the organic light-emitting layer 104 is a conventional structure in the art, which includes conventional structures such as an anode, an organic layer, and a cathode layer, which will not be repeated here.
  • FIG. 5A is a schematic top view of a second embodiment of the array substrate of the present invention
  • FIG. 5B is a schematic cross-sectional view taken along line A ⁇ A in FIG. 5A.
  • the difference between the second embodiment of the array substrate of the present invention and the first embodiment is that the array substrate 100 further includes a third metal trace 3.
  • the present invention is not limited to this. In other embodiments, the number of the third metal traces 3 can be set according to actual requirements.
  • the third metal trace 3 is located above the first metal trace 1 and below the second metal trace 2.
  • “Upper” refers to not the vertical upper position, but the positional relationship between the two layers. Specifically, the third metal trace 3 is located above the first metal trace 1
  • the layer where the third metal trace 3 is located is above the layer where the first metal trace 1 is located; where "below” does not mean vertically below, but refers to the positional relationship between the layers where the two are located
  • the third metal trace 3 is located below the second metal trace 2 means that the layer where the third metal trace 3 is located is located on the layer where the second metal trace 2 is located Below.
  • the orthographic projection of the third metal trace 3 coincides with the orthographic projection of the first metal trace 1, and the orthographic projection of the first metal trace 1 and the first
  • the orthographic projections of the three metal traces 2 cross, and the corresponding relationship can refer to FIG. 5A.
  • FIG. 5A since the orthographic projection of the third metal trace 3 coincides with the orthographic projection of the first metal trace 1, the first metal trace 1 is blocked by the third metal trace 3, The first metal trace 1 is not shown.
  • the third metal trace 3 is insulated from the first metal trace 1 and the second metal trace 2.
  • a gate insulating layer 109 is provided at and around the position where the first metal trace 1 and the third metal trace 3 intersect, so that the first metal trace 1 and all
  • the third metal trace 3 is insulated;
  • a second insulating layer 105 is provided at and around the position where the second metal trace 2 intersects with the third metal trace 3, so that the second metal trace 2 insulated from the third metal trace 3.
  • the third metal trace 3 has a plurality of third concave portions 30 and a plurality of third convex portions 31 arranged alternately.
  • the orthographic projection of the first concave portion 10 coincides with the orthographic projection of the third concave portion 30, and the orthographic projection of the first convex portion 11 and the third convex portion
  • the orthographic projections of 31 coincide.
  • the third concave portions 30 and the third convex portions 31 are alternately arranged along the length direction of the third metal trace 3.
  • the third concave portion 30 is schematically depicted by hatching to distinguish it from the third convex portion 31.
  • the first metal trace 1 is a first gate scan line
  • the second metal trace 2 is a data line
  • the third metal trace 3 is a second gate scan line
  • the first metal trace 1 is connected to the first gate of the thin film transistor of the array substrate
  • the second metal trace 2 is connected to the data line of the thin film transistor of the array substrate
  • the third metal trace 3 It is connected to the second gate of the thin film transistor of the array substrate.
  • a storage capacitor is formed between the first metal trace 1 and the third metal trace 3, and the orthographic projection of the first concave portion 10 coincides with the orthographic projection of the third concave portion 30 ,
  • the orthographic projection of the first convex portion 11 coincides with the orthographic projection of the third convex portion 31, which increases the area directly facing the storage capacitor, thereby increasing the capacity of the storage capacitor and increasing the storage capacitor
  • the capacity to store charge improves the leakage problem of the array substrate 100 during the bending and stretching process, and ensures the uniformity of the display brightness.
  • the invention also provides a third embodiment.
  • 6A is a schematic top view of a third embodiment of the array substrate of the present invention
  • FIG. 6B is a schematic cross-sectional view taken along line A-A in FIG. 6A.
  • the first metal trace 1 is the first gate scan line
  • the second metal trace 2 is the data line.
  • the first The metal trace 1 is a first gate scan line
  • the second metal trace 2 is a second gate scan line.
  • the orthographic projection of the first metal trace 1 and the orthographic projection of the second metal trace 2 coincide, so The orthographic projection of the first concave portion 10 coincides with the orthographic projection of the second concave portion 20, and the orthographic projection of the first convex portion 11 coincides with the orthographic projection of the second convex portion 21.
  • a storage capacitor is formed between the first metal trace 1 and the second metal trace 2, and since the orthographic projection of the first concave portion 10 coincides with the orthographic projection of the second concave portion 20, the first The orthographic projection of the convex portion 11 coincides with the orthographic projection of the second convex portion 21, which increases the area directly facing the storage capacitor, thereby increasing the capacity of the storage capacitor and increasing the storage capacity of the storage capacitor, The leakage problem of the array substrate 100 during the bending and stretching process is improved, and the uniformity of display brightness is ensured.
  • the wiring space of the first metal trace 1 and the second metal trace 2 is raised in the longitudinal direction to extend the first metal trace 1 and the second metal trace 2 To prevent the first metal trace 1 and the second metal trace 2 from breaking during bending and stretching, and to increase the first metal trace 1 during bending and stretching of the array substrate 100 And the reliability of the second metal trace 2 improves the bending and stretching performance of the array substrate 100.
  • the invention also provides a preparation method of the array substrate 100.
  • 7A-7L are process flow diagrams of the first embodiment of the method for manufacturing an array substrate of the present invention.
  • FIGS. 7A and 7B wherein FIG. 7A is a cross-sectional view, and FIG. 7B is a top view, providing a substrate 700.
  • One surface of the substrate 700 has an active layer 701.
  • the substrate 700 further includes a substrate 702, a flexible film layer 703 disposed on the substrate 702, and an isolation layer 704 and a buffer layer 705 disposed on the flexible film layer 703.
  • the active layer 701 is disposed on the buffer layer 705.
  • the active layer 701, the substrate 702, the flexible thin film layer 703, the isolation layer 704, and the buffer layer 705 are all conventional structures of flexible display panels.
  • the substrate 702 is a glass substrate on which a PI layer is deposited as a flexible thin film layer 703, and an isolation layer 704 (barrier) is deposited on the flexible thin film layer 703, wherein the isolation
  • the layer 704 is SiNx / SiOx.
  • a buffer layer 705 is deposited on the isolation layer 704.
  • the buffer layer 705 includes but is not limited to SiNx / SiOx.
  • a polysilicon is formed on the buffer layer 705 as the active layer 701.
  • FIGS. 7C and 7D wherein FIG. 7C is a top view, and FIG. 7D is a cross-sectional view taken along line AA in FIG. 7C.
  • a surface of the active layer 701 and the surface of the substrate 700 are covered with a first One insulating layer 706.
  • the first insulating layer 706 includes a plurality of first regions A1 having a first thickness and a plurality of second regions B1 having a second thickness, the first thickness is smaller than the second thickness, the first region A1
  • the second regions B1 are alternately arranged.
  • FIG. 7C only a part of the first area A1 and the second area B1 are schematically shown.
  • the method for forming the first insulating layer 706 with different thicknesses includes but is not limited to mask etching, etc.
  • the method for forming the first insulating layer 706 with different thicknesses is A surface of the active layer 701 and the surface of the substrate 700 are covered with an insulating layer, and part of the first insulating layer 706 is removed by etching with an etching solution to form a plurality of first regions having a first thickness A1 and a plurality of second regions B1 having a second thickness, wherein the etching solution includes but is not limited to HF solution.
  • FIGS. 7E and 7F wherein FIG. 7E is a top view, and FIG. 7F is a cross-sectional view taken along line A-A in FIG. 7E.
  • the first metal trace 707 is formed on the first insulating layer 706. In the first region A1 of the first insulating layer 706, the first metal trace 707 forms a first recess 7071. In the second region B1 of the first insulating layer 706, the first A metal trace 707 forms the first convex portion 7072, so that the first metal trace 707 forms a concave-convex shape.
  • the method for forming the first metal trace 707 may be to deposit a metal layer on the first insulating layer 706, pattern the metal layer, and form the first metal trace 707. This method is an existing technology and will not be described in detail.
  • FIGS. 7G and 7H where FIG. 7G is a top view, and FIG. 7H is a cross-sectional view taken along line BB in FIG. 7G.
  • a second insulating layer 708 is formed on the first metal trace 707.
  • the second insulating layer 708 also covers the first insulating layer 706.
  • the second insulating layer 708 includes a plurality of first regions A2 having a first thickness and a plurality of second regions B2 having a second thickness, the first thickness is smaller than the second thickness, the first region A2 It is arranged alternately with the second area B2.
  • the method of forming the second insulating layer 708 having a different thickness is the same as the method of forming the first insulating layer 707, and is not repeated here. Since the first metal trace 707 is blocked by the second insulating layer 708, in FIG. 7G, the first metal trace 707 is schematically depicted by a broken line.
  • the orthographic projection of the first area A2 of the second insulating layer 708 is offset from the orthographic projection of the first concave portion 7071 of the first metal trace 707.
  • the orthographic projection of the alignment formed by the first region A2 of the plurality of second insulating layers 708 is offset from the orthographic projection of the alignment formed by the first recess 7071 of the first metal trace 707, namely The first area A2 does not coincide with the first recess 7071.
  • the method of forming the second insulating layer 708 may be to deposit a flat second insulating layer 708 on the first metal trace 707, and remove a portion of the second insulating layer 708 to form a first thickness A plurality of first regions A2 and a plurality of second regions B2 having a second thickness.
  • FIG. 7I and FIG. 7J are cross-sectional views taken along line B-B in FIG.
  • the second metal trace 709 forms the second recess 7091
  • the second region B2 of the second insulating layer 708 the The second metal trace 709 forms the second convex portion 7092 so that the second metal trace 709 forms a concave-convex shape.
  • the method for forming the second metal trace 709 may be to deposit a metal layer on the second insulating layer 708, pattern the metal layer, and form the second metal trace 709. This method is an existing technology and will not be described in detail.
  • the first metal trace 707 is a first gate scan line connected to the gate 712 of the TFT (shown in FIG. 7K), and the second metal trace 709 is a data line. Connected to the source and drain 713 (shown in FIG. 7K).
  • the first metal trace 707 and the second metal trace 709 are both concave-convex shapes, which vertically raise the wiring space of the first metal trace 707 and the second metal trace 709, and extend the first Lengths of a metal trace 707 and the second metal trace 709 to prevent the first metal trace 707 and the second metal trace 709 from being broken during the bending and stretching process, and improve the bending of the array substrate
  • the reliability of the first metal trace 707 and the second metal trace 709 during the folding and stretching process improves the bending and stretching performance of the array substrate.
  • FIGS. 7K and 7L where FIG. 7K is a cross-sectional view, and FIG. 7L is a top view.
  • a planarization layer 710 is covered on the second metal trace 709; an organic light-emitting layer is formed on the planarization layer 710 711.
  • An anode of the organic light-emitting layer 711 is electrically connected to a drain in the second metal trace 709. This step is a normal step and will not be repeated here.
  • the invention also provides another preparation method of the array substrate.
  • 8A-8P are process flow diagrams of the second embodiment of the method for manufacturing an array substrate of the present invention.
  • FIGS. 8A and 8B wherein FIG. 8A is a cross-sectional view, and FIG. 8B is a top view, providing a substrate 800.
  • One surface of the substrate 800 has an active layer 801.
  • the substrate 800 further includes a substrate 802, a flexible film layer 803 disposed on the substrate 802, and an isolation layer 804 and a buffer layer 805 disposed on the flexible film layer 803.
  • the active layer 801 is disposed on the buffer layer 805.
  • the active layer 801, the substrate 802, the flexible thin film layer 803, the isolation layer 804, and the buffer layer 805 are all conventional structures of flexible display panels.
  • a PI layer is deposited as a flexible thin film layer 803 on a glass substrate 802, and an isolation layer 804 (barrier) is deposited on the flexible thin film layer 803, wherein the isolation layer 804 is SiNx / SiOx, a buffer layer 805 is deposited on the isolation layer 804, the buffer layer 805 includes but is not limited to SiNx / SiOx, a polysilicon is formed on the buffer layer 805 as the active layer 801.
  • FIGS. 8C and 8D wherein FIG. 8C is a top view, and FIG. 8D is a cross-sectional view taken along line AA in FIG. 8C.
  • One insulating layer 806 The first insulating layer 806 includes a plurality of first regions A1 having a first thickness and a plurality of second regions B1 having a second thickness, the first thickness is smaller than the second thickness, the first region A1 The second regions B1 are alternately arranged.
  • FIG. 8C only a part of the first area A1 and the second area B1 are schematically shown.
  • the method for forming the first insulating layer 806 with different thicknesses includes but is not limited to mask etching, etc.
  • the method for forming the first insulating layer 806 with different thicknesses is A surface of the active layer 801 and the surface of the substrate 800 are covered with an insulating layer, and part of the first insulating layer 806 is removed by etching with an etching solution to form a plurality of first regions having a first thickness A1 and a plurality of second regions B1 having a second thickness, wherein the etching solution includes but is not limited to HF solution.
  • FIGS. 8E and 8F wherein FIG. 8E is a top view, and FIG. 8F is a cross-sectional view taken along line A-A in FIG. 8E.
  • the first metal trace 807 is formed on the first insulating layer 806. In the first region A1 of the first insulating layer 806, the first metal trace 807 forms a first recess 8071, and in the second region B1 of the first insulating layer 806, the first A metal trace 807 forms the first convex portion 8072, so that the first metal trace 807 forms a concave-convex shape.
  • the method for forming the first metal trace 807 may be to deposit a metal layer on the first insulating layer 806, pattern the metal layer, and form the first metal trace 807. This method is an existing technology and will not be described in detail.
  • FIGS. 8G and 8H where FIG. 8G is a top view, and FIG. 8H is a cross-sectional view taken along the line AA in FIG.
  • the second insulating layer 808 also covers the first insulating layer 806.
  • the second insulating layer 808 includes a plurality of first regions A2 having a first thickness and a plurality of second regions B2 having a second thickness, the first thickness is smaller than the second thickness, the first region A2 It is arranged alternately with the second area B2.
  • the method of forming the second insulating layer 808 having a different thickness is the same as the method of forming the first insulating layer 807, and will not be described again. Since the first metal trace 807 is blocked by the second insulating layer 808, in FIG. 8G, the first metal trace 807 is schematically depicted by a broken line.
  • the orthographic projection of the first region A2 of the second insulating layer 808 coincides with the orthographic projection of the first concave portion 8071 of the first metal trace 807.
  • a plurality of first regions A2 having a first thickness can be directly formed by using the uneven shape of the first metal trace 807 and having A plurality of second regions B2 of a second thickness.
  • a flat second insulating layer 808 may also be deposited on the first metal trace 807, and a portion of the second insulating layer 808 may be removed to form multiple first layers with a first thickness A region A2 and a plurality of second regions B2 having a second thickness.
  • FIGS. 8I and 8J wherein FIG. 8I is a top view, and FIG. 8J is a cross-sectional view taken along line A-A in FIG. 8I.
  • the second metal trace 809 is formed on the second insulating layer 808. In the first region A2 of the second insulating layer 808, the second metal trace 809 forms the second recess 8091, and in the second region B2 of the second insulating layer 808, the The second metal trace 809 forms the second convex portion 8092 so that the second metal trace 809 forms a concave-convex shape.
  • the method for forming the second metal trace 809 may be to deposit a metal layer on the second insulating layer 808, pattern the metal layer, and form the second metal trace 809. This method is an existing technology and will not be described in detail.
  • the second metal trace 809 is a second gate scan line.
  • the orthographic projection of the first metal trace 807 coincides with the orthographic projection of the second metal trace 809.
  • the orthographic projection of a concave portion 8071 coincides with the orthographic projection of the second concave portion 8091, and the orthographic projection of the first convex portion 8072 coincides with the orthographic projection of the second convex portion 8092.
  • a storage capacitor is formed between the first metal trace 807 and the second metal trace 809, and since the orthographic projection of the first concave portion 8071 coincides with the orthographic projection of the second concave portion 8091, the first The orthographic projection of the convex portion 8072 coincides with the orthographic projection of the second convex portion 8092, which increases the area directly facing the storage capacitor, thereby increasing the capacity of the storage capacitor and increasing the storage capacity of the storage capacitor.
  • the leakage problem of the array substrate during the bending and stretching process is improved, and the uniformity of display brightness is ensured.
  • the wiring space of the first metal trace 807 and the second metal trace 809 is raised in the longitudinal direction to extend the first metal trace 807 and the second metal trace 809 to prevent the first metal trace 807 and the second metal trace 809 from being broken during bending and stretching, and to increase the first metal trace 807 and the first metal trace during the bending and stretching of the array substrate
  • the reliability of the second metal trace 809 improves the bending and stretching performance of the array substrate.
  • FIGS. 8K and 8L where FIG. 8K is a top view, and FIG. 8L is a cross-sectional view taken along the line B-B in FIG. 8K.
  • a third insulating layer 810 is formed on the second metal trace 809, and the third insulating layer 810 also covers the second insulating layer 808.
  • the third insulating layer 810 includes a plurality of first regions A3 having a first thickness and a plurality of second regions B3 having a second thickness, the first thickness is smaller than the second thickness, the first region A3
  • the second regions B3 are alternately arranged.
  • the method of forming the third insulating layer 810 having a different thickness is the same as the method of forming the first insulating layer 807, and is not repeated here.
  • the method of forming the third insulating layer 810 having a different thickness is the same as the method of forming the second insulating layer 808, and is not repeated here. Since the second metal trace 809 is blocked by the third insulating layer 810, in FIG. 8K, the second metal trace 809 is schematically depicted by a dotted line.
  • the orthographic projection of the first area A3 of the third insulating layer 810 is offset from the orthographic projection of the first concave portion 8091 of the second metal trace 809, and the third insulating layer 810
  • the orthographic projection of the second area B3 is offset from the orthographic projection of the first convex portion 8091 of the second metal trace 809, that is, the first area A3 and the first concave portion 8091 do not coincide.
  • the second area B3 does not overlap with the first convex portion 8092.
  • the method of forming the third insulating layer 810 may be to deposit a flat second insulating layer 810 on the second metal trace 809, and remove a portion of the third insulating layer 810 to form a first thickness A plurality of first regions A3 and a plurality of second regions B3 having a second thickness.
  • FIGS. 8M and 8N wherein FIG. 8M is a top view, and FIG. 8N is a cross-sectional view taken along the line B-B in FIG. 8M.
  • a third metal trace 811 is formed on the third insulating layer 810. In the first area A3, the third metal trace 811 forms a third recess 8111. In the second area B3, the The third metal trace 811 forms a third convex portion 8112.
  • the method of forming the third metal trace 811 may be to deposit a metal layer on the third insulating layer 810, pattern the metal layer, and form the third metal trace 811. There is technology, no more details.
  • the first metal trace 807 is the first gate scan line, which is connected to the first gate 812 of the TFT (shown in FIG. 8O), and the second metal trace 809 is the first The two-gate scanning line is connected to the second gate 813 (shown in FIG. 8O) of the TFT, and the third metal trace 811 is a data line connected to the source and drain 814 (shown in FIG. 8O).
  • the first metal trace 807, the second metal trace 809, and the third metal trace 811 are all concave and convex shapes, which lift the first metal trace 807, the second metal trace 809, and the The wiring space of the third metal trace 811 extends the lengths of the first metal trace 807, the second metal trace 809 and the third metal trace 811 to avoid the first metal trace 807,
  • the second metal trace 809 and the third metal trace 811 are broken during the bending and stretching process to improve the first metal trace 807 and the second metal trace 809 during the bending and stretching of the array substrate And the reliability of the third metal trace 811 improves the bending and stretching performance of the array substrate.
  • a storage capacitor is formed between the first metal trace 807 and the second metal trace 809, and since the orthographic projection of the first concave portion 8071 coincides with the orthographic projection of the second concave portion 8091, the first The orthographic projection of a convex portion 8072 coincides with the orthographic projection of the second convex portion 8092, which increases the area directly facing the storage capacitor, thereby increasing the capacity of the storage capacitor and increasing the storage capacity of the storage capacitor It improves the leakage problem of the array substrate during the bending and stretching process, and ensures the uniformity of the display brightness.
  • a planarization layer 815 is covered on the third metal trace 811; an organic light-emitting layer 816 is formed on the planarization layer 815, an anode of the organic light-emitting layer 816 and A drain in the third metal trace 811 is electrically connected.
  • This step is a normal step and will not be repeated here.
  • the invention also provides a display panel.
  • 9 is a schematic diagram of the structure of the display panel.
  • the display panel includes the array substrate 100 and a cover plate 900 disposed on the array substrate 100.
  • the cover plate 900 includes but is not limited to a glass cover plate.
  • a structure such as a polarizer (not shown in the drawings) may also be included between the cover plate 900 and the array substrate 100.

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Abstract

本发明提供阵列基板、该阵列基板的制备方法及显示面板，本发明的优点在于，在纵向上提升所述金属走线的布线空间，延长金属走线的长度，避免金属走线在弯折拉伸过程中折断，提高所述阵列基板弯折拉伸过程中金属走线的可靠性，提高阵列基板的弯折拉伸性能。

Description

阵列基板、该阵列基板的制备方法及显示面板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板、该阵列基板的制备方法及显示面板。
 背景技术
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED)等平板显示技术已经逐步取代CRT显示器。其中，OLED具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180度视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。
OLED按照驱动类型可分为无源OLED(PMOLED)和有源OLED(AMOLED)。其中，AMOLED通常是由低温多晶硅(Low Temperature Poly-Silicon，LTPS)驱动背板和电激发光层组成自发光组件。低温多晶硅具有较高的电子迁移率，对AMOLED而言，采用低温多晶硅材料具有高分辨率、反应速度快、高亮度、高开口率、低能耗等优点。
目前市场上小尺寸手机显示屏的主流方向是全面屏显示，随着人们对手机减薄可使用形态多元化的需求不断增强，可折叠手机会是显示产业发展的新方向和产能突破点。相对于目前我们所使用背板技术，可折叠手机提出的技术需求以及对产品的信赖性要求会更高。
 技术问题
LTPS背板技术直接转移到可折叠（foldable ）产品上会产生背板脆裂、走线断裂的问题，且在弯折过程中还可能会出现漏电的情况，产品的可靠性较低。
 技术解决方案
本发明所要解决的技术问题是，提供一种阵列基板、该阵列基板的制备方法及显示面板，其能够避免金属走线在弯折拉伸过程中折断，提高所述阵列基板弯折拉伸过程中金属走线的可靠性，提高阵列基板的弯折拉伸性能。
为了解决上述问题，本发明提供了一种阵列基板，包括至少一第一金属走线及位于所述第一金属走线上方的至少一第二金属走线，所述第一金属走线与所述第二金属走线彼此绝缘隔离，所述第一金属走线具有交替排列的多个第一凹部及多个第一凸部，所述第二金属走线具有交替排列的多个第二凹部及多个第二凸部。
在一实施例中，在垂直所述阵列基板的方向，所述第一金属走线的正投影与所述第二金属走线的正投影交叉设置。
在一实施例中，所述阵列基板还包括至少一第三金属走线，所述第三金属走线位于所述第一金属走线上方及所述第二金属走线的下方，所述第三金属走线与所述第一金属走线及所述第二金属走线绝缘隔离，所述第三金属走线具有交替排列的多个第三凹部及多个第三凸部，在垂直所述阵列基板的方向，所述第一金属走线的正投影与所述第三金属走线的正投影重合，所述第一凹部的正投影与所述第三凹部的正投影重合，所述第一凸部的正投影与所述第三凸部的正投影重合。
在一实施例中，所述第一金属走线为第一栅极扫描线，所述第二金属走线为数据线，所述第三金属走线为第二栅极扫描线。
在一实施例中，在垂直所述阵列基板的方向，所述第一金属走线的正投影与所述第二金属走线的正投影重合，所述第一凹部的正投影与所述第二凹部的正投影重合，所述第一凸部的正投影与所述第二凸部的正投影重合。
在一实施例中，所述第一金属走线为第一栅极扫描线，所述第二金属走线为第二栅极扫描线。
在一实施例中，所述第一凹部及所述第一凸部沿所述第一金属走线的长度方向交替排列，所述第二凹部及所述第二凸部沿所述第二金属走线的长度方向交替排列。
在一实施例中，所述第一金属走线为Ti/Cu/Ti与Cu的复合层，所述第二金属走线为Ti/Cu/Ti与Cu的复合层。
在一实施例中，所述阵列基板还包括一衬底、设置在所述衬底上的一有源层、覆盖所述有源层的一第一绝缘层及一有机发光层，第一金属走线设置在所述第一绝缘层上，在所述第一金属走线与所述第二金属走线之间设置有一第二绝缘层，所述有机发光层设置在所述第二金属走线上，并与所述第二金属走线电连接。
本发明还提供一种上述的阵列基板的制备方法，包括如下步骤：提供一衬底，所述衬底的一表面具有一有源层；在所述有源层的一表面及所述衬底的所述表面覆盖一第一绝缘层，所述第一绝缘层包括具有第一厚度的多个第一区域及具有第二厚度的多个第二区域，所述第一厚度小于所述第二厚度，所述第一区域与所述第二区域交替排列；在所述第一绝缘层上形成所述第一金属走线，在所述第一绝缘层的所述第一区域，所述第一金属走线形成所述第一凹部，在所述第一绝缘层的所述第二区域，所述第一金属走线形成所述第一凸部；在所述第一金属走线上形成一第二绝缘层，所述第二绝缘层包括具有第一厚度的多个第一区域及具有第二厚度的多个第二区域，所述第一厚度小于所述第二厚度，所述第一区域与所述第二区域交替排列；在所述第二绝缘层上形成所述第二金属走线，在所述第二绝缘层的所述第一区域，所述第二金属走线形成所述第二凹部，在所述第二绝缘层的所述第二区域，所述第二金属走线形成所述第二凸部。
在一实施例中，所述第二绝缘层的所述第一区域的正投影与所述第一金属走线的所述第一凹部的正投影错开设置。
在一实施例中，所述第二绝缘层的所述第一区域的正投影与所述第一金属走线的所述第一凹部的的正投影重合。
在一实施例中，在所述第二绝缘层上形成所述第二金属走线的步骤之后，还包括如下步骤：在所述第二金属走线上形成一第三绝缘层，所述第三绝缘层包括具有第一厚度的多个第一区域及具有第二厚度的多个第二区域，所述第一厚度小于所述第二厚度，所述第一区域与所述第二区域交替排列，所述第三绝缘层的所述第一区域的正投影与所述第二金属走线的所述第一凹部的正投影错开设置；在所述第三绝缘层上形成一第三金属走线，，在所述第一区域，所述第三金属走线形成一第三凹部，在所述第二区域，所述第三金属走线形成一第三凸部。
在一实施例中，所述制备方法还包括如下步骤：在所述第二金属走线上覆盖一平坦化层；在所述平坦化层上形成一有机发光层，所述有机发光层的一阳极与所述第二金属走线中的一漏极电连接。
本发明还提供一种显示面板，包括上述的阵列基板及设置在所述阵列基板上的盖板。
 有益效果
本发明的优点在于，在纵向上提升所述金属走线的布线空间，延长金属走线的长度，避免金属走线在弯折拉伸过程中折断，提高所述阵列基板弯折拉伸过程中金属走线的可靠性，提高阵列基板的弯折拉伸性能。
 附图说明
图1是本发明阵列基板的第一实施例的俯视示意图；
图2是沿图1中A-A线的截面示意图；
图3是沿图1中B-B线的截面示意图；
图4是本发明阵列基板的第一实施例的一截面示意图；
图5A是本发明阵列基板的第二实施例的俯视示意图；
图5B是沿图5A中A-A线的截面示意图；
图6A是本发明阵列基板的第三实施例的俯视示意图；
图6B是沿图6A中A-A线的截面示意图；
图7A~图7L是本发明阵列基板的制备方法的第一实施例工艺流程图；
图8A~图8P是本发明阵列基板的制备方法的第二实施例工艺流程图；
图9是本发明显示面板的结构示意图。
 本发明的实施方式
下面结合附图对本发明提供的阵列基板、该阵列基板的制备方法及显示面板的具体实施方式做详细说明。
图1是本发明阵列基板的第一实施例的俯视示意图，图2是沿图1中A-A线的截面示意图，图3是沿图1中B-B线的截面示意图，请参阅图1、图2及图3，本发明阵列基板100包括至少一第一金属走线1及位于所述第一金属走线1上方的至少一第二金属走线2。为了清楚说明本发明技术方案，在附图中示意性地绘示两条第一金属走线1及两条第二金属走线2，当然本发明并不限于此，在其他实施例中，所述第一金属走线1及所述第二金属走线2的数量可根据实际需求设置。
其中所述“上方”指的并不是垂直上方，而是指两者所在的层之间的位置关系。具体地说，所述第二金属走线2位于所述第一金属走线1上方指的是所述第二金属走线2所在的层位于所述第一金属走线1所在的层的上方，所述第一金属走线1与所述第二金属走线2之间的关系包括但不限于所述第一金属走线1的正投影与所述第二金属走线2的正投影交叉，或者所述第一金属走线1的正投影与所述第二金属走线2的正投影重合。在本实施例中，在垂直所述阵列基板100的方向上，即在所述阵列基板100的俯视方向上，所述第一金属走线1的正投影与所述第二金属走线2的正投影交叉，其对应关系可参考图1所示的所述阵列基板100的俯视图，其中，所述第一金属走线1为第一栅极扫描线，其与阵列基板100的薄膜晶体管的栅极107（见图4）连接，所述第二金属走线2为数据线，其与阵列基板100的薄膜晶体管的源极108（见图4）连接。
所述第一金属走线1与所述第二金属走线2彼此绝缘隔离。在本实施例中，在所述第一金属走线1与所述第二金属走线2相交的位置及其周围设置有第二绝缘层105，以使得所述第一金属走线1与所述第二金属走线2彼此绝缘隔离。由于所述第一金属走线1被所述第二绝缘层105遮挡，所以在图1中，采用虚线绘示所述第一金属走线1。
请参阅图1及图2，所述第一金属走线1具有交替排列的多个第一凹部10及多个第一凸部11，使得所述第一金属走线1形成凹凸形状的结构。其优点在于，在纵向上提升所述第一金属走线1的布线空间，延长所述第一金属走线1的长度，避免所述第一金属走线1在弯折过程拉伸中折断，提高所述阵列基板100弯折拉伸过程中所述第一金属走线1的可靠性，提高阵列基板100的弯折拉伸性能。在本实施例中，所述第一凹部10及所述第一凸部11沿所述第一金属走线1的长度方向交替排列。其中，在图1中采用阴影线示意性绘示所述第一凹部10，以与所述第一凸部11进行区分。
请参阅图1及图3，所述第二金属走线2具有交替排列的多个第二凹部20及多个第二凸部21，使得所述第二金属走线2形成凹凸形状的结构。其优点在于，在纵向上提升所述第二金属走线2的布线空间，延长所述第二金属走线2的长度，避免所述第二金属走线2在弯折拉伸过程中折断，提高所述阵列基板100弯折拉伸过程中所述第一金属走线1的可靠性，提高阵列基板100的弯折拉伸性能。在本实施例中，所述第二凹部20及所述第二凸部21沿所述第二金属走线2的长度方向交替排列。其中，在图1中采用阴影线示意性绘示所述第二凹部20，以与所述第二凸部21进行区分。
其中，所述第一金属走线1及所述第二金属走线2可采用延展性较好的金属或复合金属，例如，Ti/Cu/Ti与Cu的复合层，以提高所述第一金属走线1及所述第二金属走线2的弯折性能，进而提供所述阵列基板100的弯折性能。
图4是本发明阵列基板的第一实施例的一截面示意图，请继续参阅图1、图2、图3及图4，在本实施例中，所述阵列基板100还包括一衬底101、设置在所述衬底101上的一有源层102、覆盖所述有源层102的一第一绝缘层103及一有机发光层104。为了清楚说明本发明阵列基板100的结构，在图1、图2及图3中仅示意性绘示相关结构。第一金属走线1与所述栅极107连接，并设置在所述第一绝缘层103上。所述第二绝缘层105设置在所述第一金属走线1上，所述第二金属走线2与所述源极108连接，并设置在所述第二绝缘体105上，以使所述第一金属走线1与所述第二金属走线2绝缘。所述有机发光层104设置在所述第二金属走线2上，并与所述第二金属走线2电连接。在所述有机发光层104与所述第二金属走线2之间设置有一平坦层106。其中，所述有机发光层104为本领域常规结构，其包括阳极、有机层及阴极层等常规结构，在此不再赘述。
图5A是本发明阵列基板的第二实施例的俯视示意图，图5B是沿图5A中A~A线的截面示意图。请参阅图5A及图5B，本发明阵列基板的第二实施例与第一实施例的区别在于，所述阵列基板100还包括一第三金属走线3。在附图中示意性地绘示两条第三金属走线3，当然本发明并不限于此，在其他实施例中，所述第三金属走线3的数量可根据实际需求设置。
所述第三金属走线3位于所述第一金属走线1上方及所述第二金属走线2的下方。其中“上方”指的并不是垂直上方，而是指两者所在的层之间的位置关系，具体地说，所述第三金属走线3位于所述第一金属走线1上方指的是所述第三金属走线3所在的层位于所述第一金属走线1所在的层的上方；其中“下方”指的并不是垂直下方，而是指两者所在的层之间的位置关系，具体地说，所述第三金属走线3位于所述第二金属走线2的下方指的是所述第三金属走线3所在的层位于所述第二金属走线2所在的层的下方。
在垂直所述阵列基板100的方向，所述第三金属走线3的正投影与所述第一金属走线1的正投影重合，所述第一金属走线1的正投影与所述第三金属走线2的正投影交叉，其对应关系可参考图5A。在图5A中，由于所述第三金属走线3的正投影与所述第一金属走线1的正投影重合，所述第一金属走线1被所述第三金属走线3遮挡，则并未绘示所述第一金属走线1。
所述第三金属走线3与所述第一金属走线1及所述第二金属走线2绝缘。在本实施例中，在所述第一金属走线1与所述第三金属走线3相交的位置及其周围设置有栅极绝缘层109，以使得所述第一金属走线1与所述第三金属走线3绝缘；在所述第二金属走线2与所述第三金属走线3相交的位置及其周围设置有第二绝缘层105，以使得所述第二金属走线2与所述第三金属走线3绝缘。
所述第三金属走线3具有交替排列的多个第三凹部30及多个第三凸部31。其中，在垂直所述阵列基板100的方向，所述第一凹部10的正投影与所述第三凹部30的正投影重合，所述第一凸部11的正投影与所述第三凸部31的正投影重合。在本实施例中，所述第三凹部30及所述第三凸部31沿所述第三金属走线3的长度方向交替排列。其中，在图5A中采用阴影线示意性绘示所述第三凹部30，以与所述第三凸部31进行区分。
在本实施例中，所述第一金属走线1为第一栅极扫描线，所述第二金属走线2为数据线，所述第三金属走线3为第二栅极扫描线，其中，所述第一金属走线1与阵列基板的薄膜晶体管的第一栅极连接，所述第二金属走线2与阵列基板的薄膜晶体管的数据线连接，所述第三金属走线3与与阵列基板的薄膜晶体管的第二栅极连接。请参阅图5B，所述第一金属走线1与所述第三金属走线3之间形成存储电容，而由于所述第一凹部10的正投影与所述第三凹部30的正投影重合，所述第一凸部11的正投影与所述第三凸部31的正投影重合，则使所述存储电容的正对面积增大，进而增大了该存储电容的容量，提高存储电容储存电荷的容量，改善了在弯折拉伸过程中阵列基板100所发生的漏电问题，保证了显示亮度的均一性。
本发明还提供一第三实施例。图6A是本发明阵列基板的第三实施例的俯视示意图，图6B是沿图6A中A-A线的截面示意图。其中，在第一实施例中，所述第一金属走线1为第一栅极扫描线，所述第二金属走线2为数据线，则在该第三实施例中，所述第一金属走线1为第一栅极扫描线，所述第二金属走线2为第二栅极扫描线。请参阅图6A及图6B，在该实施例中，在垂直所述阵列基板100的方向，所述第一金属走线1的正投影与所述第二金属走线2的正投影重合，所述第一凹部10的正投影与所述第二凹部20的正投影重合，所述第一凸部11的正投影与所述第二凸部21的正投影重合。
所述第一金属走线1与所述第二金属走线2之间形成存储电容，而由于所述第一凹部10的正投影与所述第二凹部20的正投影重合，所述第一凸部11的正投影与所述第二凸部21的正投影重合，则使所述存储电容的正对面积增大，进而增大了该存储电容的容量，提高存储电容储存电荷的容量，改善了在弯折拉伸过程中阵列基板100所发生的漏电问题，保证了显示亮度的均一性。且在该实施例中，在纵向上提升所述第一金属走线1及所述第二金属走线2的布线空间，延长所述第一金属走线1及所述第二金属走线2的长度，避免所述第一金属走线1及所述第二金属走线2在弯折拉伸过程中折断，提高所述阵列基板100弯折拉伸过程中所述第一金属走线1及所述第二金属走线2的可靠性，提高阵列基板100的弯折拉伸性能。
本发明还提供一种所述阵列基板100的制备方法。其中图7A~图7L是本发明阵列基板的制备方法的第一实施例工艺流程图。
请参阅图7A及图7B，其中图7A为截面视图，图7B为俯视图，提供一衬底700。所述衬底700的一表面具有一有源层701。具体地说，所述衬底700还包括一基板702、设置在所述基板702上的柔性薄膜层703及设置在所述柔性薄膜层703上的隔离层704及缓冲层705。所述有源层701设置在所述缓冲层705上。其中，所述有源层701、所述基板702、柔性薄膜层703、隔离层704及缓冲层705均为柔性显示面板的常规结构。例如，在本实施例中，所述基板702为一玻璃基板，其上沉积一层PI层作为柔性薄膜层703，在所述柔性薄膜层703上沉积隔离层704（barrier），其中所述隔离层704 为SiNx/SiOx，在所述隔离层704上沉积缓冲层705，所述缓冲层705包括但不限于SiNx/SiOx，在所述缓冲层705上形成一多晶硅作为有源层701。
请参阅图7C及图7D，其中图7C为俯视图，图7D为沿图7C中A-A线的截面图，在所述有源层701的一表面及所述衬底700的所述表面覆盖一第一绝缘层706。所述第一绝缘层706包括具有第一厚度的多个第一区域A1及具有第二厚度的多个第二区域B1，所述第一厚度小于所述第二厚度，所述第一区域A1与所述第二区域B1交替排列。为了清楚描述本发明技术方案，在图7C中，仅示意性地绘示部分第一区域A1及第二区域B1。形成具有不同厚度的所述第一绝缘层706的方法包括但不限于掩膜刻蚀等，例如，在一实施例中，形成具有不同厚度的所述第一绝缘层706的方法为在所述有源层701的一表面及所述衬底700的所述表面覆盖一绝缘层，采用刻蚀液进行刻蚀去除部分所述第一绝缘层706，形成具有第一厚度的多个第一区域A1及具有第二厚度的多个第二区域B1，其中，所述刻蚀液包括但不限于HF溶液。
请参阅图7E及图7F，其中图7E为俯视图，图7F为沿图7E中A-A线的截面图，在所述第一绝缘层706上形成所述第一金属走线707。在所述第一绝缘层706的所述第一区域A1，所述第一金属走线707形成一第一凹部7071，在所述第一绝缘层706的所述第二区域B1，所述第一金属走线707形成所述第一凸部7072，使得所述第一金属走线707形成凹凸形状。其中，形成所述第一金属走线707的方法可以为在所述第一绝缘层706上沉积一金属层，图形化所述金属层，形成所述第一金属走线707。该方法为现有技术，不再赘述。
请参阅图7G及图7H，其中图7G为俯视图，图7H为沿图7G中B-B线的截面图，在所述第一金属走线707上形成一第二绝缘层708，其中，在本实施例中，所述第二绝缘层708也覆盖所述第一绝缘层706。所述第二绝缘层708包括具有第一厚度的多个第一区域A2及具有第二厚度的多个第二区域B2，所述第一厚度小于所述第二厚度，所述第一区域A2与所述第二区域B2交替排列。形成具有不同厚度的所述第二绝缘层708的方法与形成所述第一绝缘层707的方法相同，不再赘述。由于所述第一金属走线707被第二绝缘层708遮挡，所以在图7G中，采用虚线示意性绘示所述第一金属走线707。
在本实施例中，所述第二绝缘层708的所述第一区域A2的正投影与所述第一金属走线707的第一凹部7071的正投影错开设置。具体地说，多个所述第二绝缘层708的所述第一区域A2形成的队列的正投影与所述第一金属走线707的第一凹部7071形成的队列的正投影错开设置，即所述第一区域A2与所述第一凹部7071不重合。形成所述第二绝缘层708的方法可以为在所述第一金属走线707上沉积一平坦的第二绝缘层708，在去除部分所述第二绝缘层708，进而形成具有第一厚度的多个第一区域A2及具有第二厚度的多个第二区域B2。
请参阅图7I及图7J，其中图7I为俯视图，图7J为沿图7I中B-B线的截面图，在所述第二绝缘层708上形成所述第二金属走线709。在所述第二绝缘层708的所述第一区域A2，所述第二金属走线709形成所述第二凹部7091，在所述第二绝缘层708的所述第二区域B2，所述第二金属走线709形成所述第二凸部7092，使得所述第二金属走线709形成凹凸形状。其中，形成所述第二金属走线709的方法可以为在所述第二绝缘层708上沉积一金属层，图形化所述金属层，形成所述第二金属走线709。该方法为现有技术，不再赘述。
在本实施例中，所述第一金属走线707为第一栅极扫描线，与TFT的栅极712（绘示在图7K中）连接，所述第二金属走线709为数据线，与源漏极713（绘示在图7K中）连接。所述第一金属走线707与第二金属走线709均为凹凸形状，其在纵向上提升所述第一金属走线707及所述第二金属走线709的布线空间，延长所述第一金属走线707及所述第二金属走线709的长度，避免所述第一金属走线707及所述第二金属走线709在弯折拉伸过程中折断，提高所述阵列基板弯折拉伸过程中所述第一金属走线707及所述第二金属走线709的可靠性，提高阵列基板的弯折拉伸性能。
请参阅图7K及图7L，其中图7K为截面视图，图7L为俯视图，在所述第二金属走线709上覆盖一平坦化层710；在所述平坦化层710上形成一有机发光层711，所述有机发光层711的一阳极与所述第二金属走线709中的一漏极电连接。该步骤为常规步骤，不再赘述。
本发明还提供一种所述阵列基板的另一制备方法。其中图8A~图8P是本发明阵列基板的制备方法的第二实施例工艺流程图。
请参阅图8A及图8B，其中图8A为截面视图，图8B为俯视图，提供一衬底800。所述衬底800的一表面具有一有源层801。具体地说，所述衬底800还包括一基板802、设置在所述基板802上的柔性薄膜层803及设置在所述柔性薄膜层803上的隔离层804及缓冲层805。所述有源层801设置在所述缓冲层805上。其中，所述有源层801、所述基板802、柔性薄膜层803、隔离层804及缓冲层805均为柔性显示面板的常规结构。例如，在本实施例中，在一玻璃基板802上沉积一层PI层作为柔性薄膜层803，在所述柔性薄膜层803上沉积隔离层804（barrier），其中所述隔离层804 为SiNx/SiOx，在所述隔离层804上沉积缓冲层805，所述缓冲层805包括但不限于SiNx/SiOx，在所述缓冲层805上形成一多晶硅作为有源层801。
请参阅图8C及图8D，其中图8C为俯视图，图8D为沿图8C中A-A线的截面图，在所述有源层801的一表面及所述衬底800的所述表面覆盖一第一绝缘层806。所述第一绝缘层806包括具有第一厚度的多个第一区域A1及具有第二厚度的多个第二区域B1，所述第一厚度小于所述第二厚度，所述第一区域A1与所述第二区域B1交替排列。为了清楚描述本发明技术方案，在图8C中，仅示意性地绘示部分第一区域A1及第二区域B1。形成具有不同厚度的所述第一绝缘层806的方法包括但不限于掩膜刻蚀等，例如，在一实施例中，形成具有不同厚度的所述第一绝缘层806的方法为在所述有源层801的一表面及所述衬底800的所述表面覆盖一绝缘层，采用刻蚀液进行刻蚀去除部分所述第一绝缘层806，形成具有第一厚度的多个第一区域A1及具有第二厚度的多个第二区域B1，其中，所述刻蚀液包括但不限于HF溶液。
请参阅图8E及图8F，其中图8E为俯视图，图8F为沿图8E中A-A线的截面图，在所述第一绝缘层806上形成所述第一金属走线807。在所述第一绝缘层806的所述第一区域A1，所述第一金属走线807形成一第一凹部8071，在所述第一绝缘层806的所述第二区域B1，所述第一金属走线807形成所述第一凸部8072，使得所述第一金属走线807形成凹凸形状。其中，形成所述第一金属走线807的方法可以为在所述第一绝缘层806上沉积一金属层，图形化所述金属层，形成所述第一金属走线807。该方法为现有技术，不再赘述。
请参阅图8G及图8H，其中图8G为俯视图，图8H为图8G中A-A向的截面图，在所述第一金属走线807上形成一第二绝缘层808，其中，在本实施例中，所述第二绝缘层808也覆盖所述第一绝缘层806。所述第二绝缘层808包括具有第一厚度的多个第一区域A2及具有第二厚度的多个第二区域B2，所述第一厚度小于所述第二厚度，所述第一区域A2与所述第二区域B2交替排列。形成具有不同厚度的所述第二绝缘层808的方法与形成所述第一绝缘层807的方法相同，不再赘述。由于所述第一金属走线807被第二绝缘层808遮挡，所以在图8G中，采用虚线示意性绘示所述第一金属走线807。
在本实施例中，所述第二绝缘层808的所述第一区域A2的正投影与所述第一金属走线807的第一凹部8071的正投影重合。其中，在所述第一金属走线807上沉积所述第二绝缘层808时，利用所述第一金属走线807的凹凸形状可直接形成具有第一厚度的多个第一区域A2及具有第二厚度的多个第二区域B2。在其他实施方式中，也可以在所述第一金属走线807上沉积一平坦的第二绝缘层808，在去除部分所述第二绝缘层808，进而形成具有第一厚度的多个第一区域A2及具有第二厚度的多个第二区域B2。
请参阅图8I及图8J，其中图8I为俯视图，图8J为沿图8I中A-A线的截面图，在所述第二绝缘层808上形成所述第二金属走线809。在所述第二绝缘层808的所述第一区域A2，所述第二金属走线809形成所述第二凹部8091，在所述第二绝缘层808的所述第二区域B2，所述第二金属走线809形成所述第二凸部8092，使得所述第二金属走线809形成凹凸形状。其中，形成所述第二金属走线809的方法可以为在所述第二绝缘层808上沉积一金属层，图形化所述金属层，形成所述第二金属走线809。该方法为现有技术，不再赘述。
在本实施例中，所述第二金属走线809为第二栅极扫描线，所述第一金属走线807的正投影与所述第二金属走线809的正投影重合，所述第一凹部8071的正投影与所述第二凹部8091的正投影重合，所述第一凸部8072的正投影与所述第二凸部8092的正投影重合。所述第一金属走线807与所述第二金属走线809之间形成存储电容，而由于所述第一凹部8071的正投影与所述第二凹部8091的正投影重合，所述第一凸部8072的正投影与所述第二凸部8092的正投影重合，则使所述存储电容的正对面积增大，进而增大了该存储电容的容量，提高存储电容储存电荷的容量，改善了在弯折拉伸过程中阵列基板所发生的漏电问题，保证了显示亮度的均一性。且在该实施例中，在纵向上提升所述第一金属走线807及所述第二金属走线809的布线空间，延长所述第一金属走线807及所述第二金属走线809的长度，避免所述第一金属走线807及所述第二金属走线809在弯折拉伸过程中折断，提高所述阵列基板弯折拉伸过程中所述第一金属走线807及所述第二金属走线809的可靠性，提高阵列基板的弯折拉伸性能。
进一步，在本实施例中，请参阅图8K及图8L，其中图8K为俯视图，图8L为图8K中B-B向的截面图。在所述第二金属走线809上形成一第三绝缘层810，所述第三绝缘层810也覆盖所述第二绝缘层808。所述第三绝缘层810包括具有第一厚度的多个第一区域A3及具有第二厚度的多个第二区域B3，所述第一厚度小于所述第二厚度，所述第一区域A3与所述第二区域B3交替排列。形成具有不同厚度的所述第三绝缘层810的方法与形成所述第一绝缘层807的方法相同，不再赘述。形成具有不同厚度的所述第三绝缘层810的方法与形成所述第二绝缘层808的方法相同，不再赘述。由于所述第二金属走线809被第三绝缘层810遮挡，所以在图8K中，采用虚线示意性绘示所述第二金属走线809。
在本实施例中，所述第三绝缘层810的所述第一区域A3的正投影与所述第二金属走线809的第一凹部8091的正投影错开设置，所述第三绝缘层810的所述第二区域B3的正投影与所述第二金属走线809的第一凸部8091的正投影错开设置，即所述第一区域A3与所述第一凹部8091不重合，所述第二区域B3与所述第一凸部8092不重合。形成所述第三绝缘层810的方法可以为在所述第二金属走线809上沉积一平坦的第二绝缘层810，在去除部分所述第三绝缘层810，进而形成具有第一厚度的多个第一区域A3及具有第二厚度的多个第二区域B3。
请参阅图8M及图8N，其中图8M为俯视图，图8N为图8M中B-B向的截面图。在所述第三绝缘层810上形成一第三金属走线811，在所述第一区域A3，所述第三金属走线811形成一第三凹部8111，在所述第二区域B3，所述第三金属走线811形成一第三凸部8112。其中，形成所述第三金属走线811的方法可以为在所述第三绝缘层810上沉积一金属层，图形化所述金属层，形成所述第三金属走线811，该方法为现有技术，不再赘述。
在本实施例中，所述第一金属走线807为第一栅极扫描线，与TFT的第一栅极812（绘示在图8O中）连接，所述第二金属走线809为第二栅极扫描线，与TFT的第二栅极813（绘示在图8O中）连接，所述第三金属走线811为数据线，与源漏极814（绘示在图8O中）连接。所述第一金属走线807、第二金属走线809及所述第三金属走线811均为凹凸形状，其在纵向上提升所述第一金属走线807、第二金属走线809及所述第三金属走线811的布线空间，延长所述第一金属走线807、第二金属走线809及所述第三金属走线811的长度，避免所述第一金属走线807、第二金属走线809及所述第三金属走线811在弯折拉伸过程中折断，提高所述阵列基板弯折拉伸过程中所述第一金属走线807、第二金属走线809及所述第三金属走线811的可靠性，提高阵列基板的弯折拉伸性能。且所述第一金属走线807与所述第二金属走线809之间形成存储电容，而由于所述第一凹部8071的正投影与所述第二凹部8091的正投影重合，所述第一凸部8072的正投影与所述第二凸部8092的正投影重合，则使所述存储电容的正对面积增大，进而增大了该存储电容的容量，提高存储电容储存电荷的容量，改善了在弯折拉伸过程中阵列基板所发生的漏电问题，保证了显示亮度的均一性。
请参阅图8O及图8P，在所述第三金属走线811上覆盖一平坦化层815；在所述平坦化层815上形成一有机发光层816，所述有机发光层816的一阳极与所述第三金属走线811中的一漏极电连接。该步骤为常规步骤，不再赘述。
本发明还提供一种显示面板。图9是所述显示面板的结构示意图。请参阅图9，所述显示面板包括所述阵列基板100及设置在所述阵列基板100上的盖板900。所述盖板900包括但不限于玻璃盖板。其中，在所述盖板900与所述阵列基板100之间还可以包括偏光片（附图中未绘示）等结构。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。
 工业实用性
本申请的主题可以在工业中制造和使用，具备工业实用性。

Claims (15)

  1.   一种阵列基板，其包括至少一第一金属走线及位于所述第一金属走线上方的至少一第二金属走线，所述第一金属走线与所述第二金属走线彼此绝缘隔离，所述第一金属走线具有交替排列的多个第一凹部及多个第一凸部，所述第二金属走线具有交替排列的多个第二凹部及多个第二凸部。
  2.   根据权利要求1所述的阵列基板，其中在垂直所述阵列基板的方向，所述第一金属走线的一正投影与所述第二金属走线的一正投影交叉设置。
  3.   根据权利要求2所述的阵列基板，其中所述阵列基板还包括至少一第三金属走线，所述第三金属走线位于所述第一金属走线上方及所述第二金属走线的下方，所述第三金属走线与所述第一金属走线及所述第二金属走线绝缘隔离，所述第三金属走线具有交替排列的多个第三凹部及多个第三凸部，在垂直所述阵列基板的方向，所述第一金属走线的所述正投影与所述第三金属走线的一正投影重合，所述第一凹部的一正投影与所述第三凹部的一正投影重合，所述第一凸部的一正投影与所述第三凸部的一正投影重合。
  4.   根据权利要求3所述的阵列基板，其中所述第一金属走线为一第一栅极扫描线，所述第二金属走线为一数据线，所述第三金属走线为一第二栅极扫描线。
  5.   根据权利要求1所述的阵列基板，其中在垂直所述阵列基板的方向，所述第一金属走线的一正投影与所述第二金属走线的一正投影重合，所述第一凹部的一正投影与所述第二凹部的一正投影重合，所述第一凸部的一正投影与所述第二凸部的一正投影重合。
  6.   根据权利要求5所述的阵列基板，其中所述第一金属走线为一第一栅极扫描线，所述第二金属走线为一第二栅极扫描线。
  7.   根据权利要求1所述的阵列基板，其中所述第一凹部及所述第一凸部沿所述第一金属走线的长度方向交替排列，所述第二凹部及所述第二凸部沿所述第二金属走线的长度方向交替排列。
  8.   根据权利要求1所述的阵列基板，其中所述第一金属走线为Ti/Cu/Ti与Cu的复合层，所述第二金属走线为Ti/Cu/Ti与Cu的复合层。
  9.   根据权利要求1所述的阵列基板，其中所述阵列基板还包括一衬底、设置在所述衬底上的一有源层、覆盖所述有源层的一第一绝缘层及一有机发光层，第一金属走线设置在所述第一绝缘层上，在所述第一金属走线与所述第二金属走线之间设置有一第二绝缘层，所述有机发光层设置在所述第二金属走线上，并与所述第二金属走线电连接。
  10. 一种根据权利要求1所述的阵列基板的制备方法，其中包括如下步骤：
    提供一衬底，所述衬底的一表面具有一有源层；
    在所述有源层的一表面及所述衬底的所述表面覆盖一第一绝缘层，所述第一绝缘层包括具有第一厚度的多个第一区域及具有第二厚度的多个第二区域，所述第一厚度小于所述第二厚度，所述第一区域与所述第二区域交替排列；
    在所述第一绝缘层上形成所述第一金属走线，在所述第一绝缘层的所述第一区域，所述第一金属走线形成所述第一凹部，在所述第一绝缘层的所述第二区域，所述第一金属走线形成所述第一凸部；
    在所述第一金属走线上形成一第二绝缘层，所述第二绝缘层包括具有第一厚度的多个第一区域及具有第二厚度的多个第二区域，所述第一厚度小于所述第二厚度，所述第一区域与所述第二区域交替排列；
    在所述第二绝缘层上形成所述第二金属走线，在所述第二绝缘层的所述第一区域，所述第二金属走线形成所述第二凹部，在所述第二绝缘层的所述第二区域，所述第二金属走线形成所述第二凸部。
  11. 根据权利要求10所述的阵列基板的制备方法，其中所述第二绝缘层的所述第一区域的一正投影与所述第一金属走线的所述第一凹部的一正投影错开设置。
  12. 根据权利要求10所述的阵列基板的制备方法，其中所述第二绝缘层的所述第一区域的一正投影与所述第一金属走线的所述第一凹部的的一正投影重合。
  13. 根据权利要求12所述的阵列基板的制备方法，其中在所述第二绝缘层上形成所述第二金属走线的步骤之后，还包括如下步骤：
    在所述第二金属走线上形成一第三绝缘层，所述第三绝缘层包括具有第一厚度的多个第一区域及具有第二厚度的多个第二区域，所述第一厚度小于所述第二厚度，所述第一区域与所述第二区域交替排列，所述第三绝缘层的所述第一区域的一正投影与所述第二金属走线的所述第一凹部的一正投影错开设置；
    在所述第三绝缘层上形成一第三金属走线，，在所述第一区域，所述第三金属走线形成一第三凹部，在所述第二区域，所述第三金属走线形成一第三凸部。
  14. 根据权利要求10所述的阵列基板的制备方法，其中所述制备方法还包括如下步骤：
    在所述第二金属走线上覆盖一平坦化层；
    在所述平坦化层上形成一有机发光层，所述有机发光层的一阳极与所述第二金属走线中的一漏极电连接。
  15. 一种显示面板，其中包括一如权利要求1所述的阵列基板及一设置在所述阵列基板上的盖板。
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