WO2020062808A1 - 阵列基板及其驱动方法、显示面板 - Google Patents

阵列基板及其驱动方法、显示面板 Download PDF

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Publication number
WO2020062808A1
WO2020062808A1 PCT/CN2019/079144 CN2019079144W WO2020062808A1 WO 2020062808 A1 WO2020062808 A1 WO 2020062808A1 CN 2019079144 W CN2019079144 W CN 2019079144W WO 2020062808 A1 WO2020062808 A1 WO 2020062808A1
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Prior art keywords
transistor
signal
signal line
initialization
data
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PCT/CN2019/079144
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English (en)
French (fr)
Inventor
范龙飞
朱晖
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昆山国显光电有限公司
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Priority to US16/838,040 priority Critical patent/US11056061B2/en
Publication of WO2020062808A1 publication Critical patent/WO2020062808A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD

Definitions

  • the present application relates to the field of display technology, and particularly to an array substrate, a driving method thereof, and a display panel.
  • Organic light-emitting display panels are increasingly used in the display field because of their advantages such as high contrast, low power consumption, wide viewing angle, and fast response speed.
  • the organic light emitting display panel includes pixel circuits arranged in an array.
  • the size of the pixel circuit is reduced, and the data signal line and the initialization signal line are combined, that is, the data signal and the initialization signal are input into the pixel circuit through the same signal line.
  • the driving chip outputs different signals through the same signal line to control the operation of the pixel circuit, which is prone to the problem of control failure, thereby causing the display panel display to fail.
  • Various embodiments disclosed in the present application provide an array substrate, a driving method thereof, and a display panel.
  • the present application provides an array substrate including a display area and a non-display area provided around the display area.
  • the display area includes a plurality of pixel circuits arranged in an array and a first signal line connected to the pixel circuits.
  • the non-display area includes: a plurality of common circuits and a data driving chip. Each of the common circuits is connected to the pixel circuit through the first signal line, and is configured to provide an initialization signal and a data signal to the pixel circuit.
  • the data driving chip is connected to the common circuit through a second signal line and a third signal line.
  • the data driving chip provides the initialization signal to the common circuit through the second signal line, the common circuit receives the initialization signal and initializes the pixel circuit through the first signal line, And the data driving chip provides the data signal to the common circuit through the third signal line, the common circuit receives the data signal and writes data to the pixel circuit through the first signal line .
  • the common circuit includes an initialization circuit and a data writing circuit.
  • the initialization circuit is connected to the data driving chip through the second signal line, and is configured to receive an initialization signal output by the data driving chip and transmit the initialization signal to the pixel circuit through the first signal line.
  • the data writing circuit is connected to the data driving chip through the third signal line, and is configured to receive a data signal output by the data driving chip and transmit the data signal to the pixel through the first signal line. Circuit.
  • the non-display area further includes a scan driving chip and a first control signal line and a second control signal line connected to the scan driving chip.
  • the scan driving chip provides a first control signal to the initialization circuit through the first control signal line, so that the initialization circuit provides the initialization signal to the pixel circuit when the first control signal is valid.
  • the scan driving chip provides a second control signal to the data writing circuit through the second control signal line, so that the data writing circuit provides the data signal to the data writing circuit when the second control signal is valid.
  • the pixel circuit is a scan driving chip and a first control signal line and a second control signal line connected to the scan driving chip.
  • the scan driving chip is connected to the pixel circuit through a scan signal line, and is configured to provide a scan signal for the pixel circuit.
  • the array substrate further includes a light emission control chip, and the light emission control chip is connected to the pixel circuit through a light emission control signal line, and is configured to provide the pixel circuit with a light emission control signal.
  • the initialization circuit includes an initialization transistor
  • the data writing circuit includes a data writing transistor.
  • a control terminal of the initialization transistor is connected to the scan driving chip through the first control signal line, a first pole of the initialization transistor is connected to the pixel circuit through the first signal line, and a second terminal of the initialization transistor is The pole is connected to the data driving chip through the second signal line.
  • a control terminal of the data writing transistor is connected to the scan driving chip through the second control signal line, a first pole of the data writing transistor is connected to the pixel circuit through the first signal line, and the data The second pole of the write transistor is connected to the data driving chip through the second signal line.
  • the pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a capacitor, and a light emitting diode.
  • a control terminal of the first transistor is connected to a first pole plate of the capacitor, a second pole of the second transistor, and a first pole of the sixth transistor, and the first pole of the first transistor is connected to the A first power source, a second pole of the first transistor is connected to a first pole of the second transistor and a first pole of the third transistor T 3 .
  • a control terminal of the second transistor is connected to a second scanning signal line.
  • a control terminal of the third transistor is connected to a light emitting control signal line, a second pole of the third transistor is connected to a first pole of the fifth transistor and an anode of the light emitting diode, and a cathode of the light emitting diode is connected to a second power supply.
  • the control terminal of the fifth transistor is connected to the control terminal of the sixth transistor and the first scanning signal line, and the second electrode of the fifth transistor is connected to the second electrode of the sixth transistor and the fourth transistor.
  • a control terminal of the fourth transistor is connected to a third scanning signal line, and a first pole of the fourth transistor is connected to a second plate of the capacitor.
  • the first control signal controls the initialization transistor to be turned on, and the first scan signal controls the fifth transistor.
  • the sixth transistor is turned on, and the initialization signal initializes the first plate of the capacitor, the control terminal of the first transistor, and the anode of the light emitting diode.
  • a voltage of the initialization signal is lower than a power supply voltage of the second power source.
  • the third scan signal controls the fourth transistor to be turned on, and the second control signal controls the data writing.
  • the input transistor is turned on, and the data signal is written into the second plate of the capacitor through the data writing transistor and the fourth transistor.
  • the third scan signal controls the fourth transistor to be turned on, and the first control signal controls the initialization transistor.
  • the initialization signal is applied to the control terminal of the first transistor through the capacitor, and the power supply voltage provided by the first power supply is compensated.
  • the light emission control signal when the light emission control signal is valid, the light emission control signal controls the third transistor to be turned on, and the light emitting diode emits light.
  • the present application provides a display panel including the aforementioned array substrate.
  • the present application provides a driving method of the foregoing array substrate.
  • the method includes: a data driving chip providing an initialization signal to a common circuit through a second signal line, the common circuit receiving the initialization signal and the pixel circuit through the first signal line Perform initialization; and the data driving chip provides a data signal to the common circuit through a third signal line, the common circuit receives the data signal and writes data to the pixel circuit through the first signal line.
  • the common circuit includes an initialization circuit and a data writing circuit.
  • the initialization circuit is connected to the data driving chip through the second signal line, and the data writing circuit is connected to the third signal through the third signal.
  • Connecting the data driving chip with a line wherein the method further comprises: the initialization circuit receiving an initialization signal output by the data driving chip and transmitting the initialization signal to the pixel circuit through the first signal line;
  • the data writing circuit receives a data signal output from the data driving chip and transmits the data signal to the pixel circuit through the first signal line.
  • the non-display area further includes a scan driving chip and a first control signal line and a second control signal line connected to the scan driving chip, wherein the method further includes: the scan driving chip A first control signal is provided to the initialization circuit through the first control signal line, and the initialization circuit provides the initialization signal to the pixel circuit when the first control signal is valid; the scan driving chip passes The second control signal line provides a second control signal to the data writing circuit, and the data writing circuit provides the data signal to the pixel circuit when the second control signal is valid.
  • the scan driving chip is connected to the pixel circuit through a scan signal line, and the method further includes: the scan driving chip provides a scan signal to the pixel circuit through a scan signal line.
  • the array substrate further includes a light-emitting control chip, and the light-emitting control chip is connected to the pixel circuit through a light-emitting control signal line, and the method further includes: the light-emitting control chip uses a light-emitting control signal The line provides a light emission control signal to the pixel circuit.
  • the array substrate and the display panel are provided with a common circuit in a non-display area.
  • the data driving chip is connected to the common circuit through the second signal line and the third signal line.
  • the data driving chip outputs different signals in different periods, and can provide an initialization signal to the common circuit through the second signal line, and a data signal to the common circuit through the third signal line.
  • the common circuit outputs the received signal to the pixel circuit through the first signal line.
  • the shared circuit transmits the data signal and the initialization signal to the pixel circuit through the first signal line at different times, that is, the data signal and the initialization signal share the same signal line in the display area, which reduces the screen body routing. Density, which can increase the aperture ratio and achieve high-resolution display.
  • FIG. 1 is a schematic diagram of an array substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a pixel circuit provided by an embodiment of the application.
  • FIG. 3 is a timing signal diagram of a pixel circuit provided by an embodiment of the application.
  • An embodiment of the present application provides an array substrate including a display area 100 and a non-display area 200 provided around the display area 100.
  • the display area 100 includes pixel circuits 110 arranged in an array and first signal lines 120 connected to the pixel circuits 110.
  • the non-display area 200 includes a common circuit 210, and each common circuit 210 is connected to the pixel circuit 110 through a first signal line 120, respectively, and is configured to provide an initialization signal and a data signal to the pixel circuit 110.
  • the non-display area 200 further includes a data driving chip 220, and the data driving chip 220 is connected to the common circuit 210 through the second signal line 221 and the third signal line 222.
  • the data driving chip 220 provides an initialization signal to the common circuit 210 through the second signal line 221. After receiving the initialization signal, the common circuit 210 initializes the pixel circuit 110 through the first signal line 120. The data driving chip 220 provides a data signal to the common circuit 210 through the third signal line 222. After receiving the data signal, the common circuit 210 writes data to the pixel circuit 110 through the first signal line 120. In this embodiment, the data driving chip 220 may output different signals in different periods, and transmit the signals to the common circuit 210 through the second signal line 221 or the third signal line 222, respectively. It should be noted that the first signal line 120 is located in the display area 100, and the second signal line 221 and the third signal line 222 are located in the non-display area 200.
  • the array substrate provided in the above embodiment is provided with a common circuit 210 in the non-display area 200.
  • the data driving chip 220 is connected to the common circuit 210 through the second signal line 221 and the third signal line 222.
  • the data driving chip 220 outputs different signals in different periods, and can provide an initialization signal to the common circuit 210 through the second signal line 221 and a data signal to the common circuit 210 through the third signal line 222.
  • the common circuit 210 outputs the received signal to the pixel circuit 110 through the first signal line 120.
  • different traces are used to output different signals to facilitate the control of the data driving chip 220, and the problem of display failure that may be caused by using the same trace to output different signals is solved.
  • the common circuit 210 transmits the data signal and the initialization signal to the pixel circuit 110 through the first signal line 120 at different periods, that is, the data signal and the initialization signal share a signal line in the display area 100, which reduces the The density of the screen body traces can increase the aperture ratio and achieve high-resolution display.
  • the common circuit 210 includes an initialization circuit 211 and a data writing circuit 212.
  • the initialization circuit 211 is connected to the data driving chip 220 through the second signal line 221, and is used for receiving the initialization signal output from the data driving chip 220, and transmits the initialization signal to the pixel circuits 110 in each column through the first signal line 120.
  • the data writing circuit 212 is connected to the data driving chip 220 through the third signal line 222, and is used for receiving the data signals output by the data driving chip 220 and transmitting the data signals to the pixel circuits 110 in each column through the first signal line 120.
  • the output terminals of each group of the initialization circuit 211 and the data writing circuit 212 are commonly connected to the same first signal line 120, and a row of pixel units are correspondingly connected through the first signal line 120.
  • the initialization circuit 211 and the data writing circuit 212 operate in different periods, respectively. When the initialization circuit 211 works, the data writing circuit 212 does not work.
  • the initialization circuit 211 receives the initialization signal and transmits it to the pixel circuit 110 through the first signal line 120.
  • the data writing circuit 212 works, the initialization circuit 211 does not work.
  • the data writing circuit 212 receives the data signal and transmits it to the pixel circuit 110 through the first signal line 120.
  • the data driving chip 220 transmits two signals respectively through different signal lines, which is convenient for control, and reduces the risk of display failure that may be caused by using the same trace to output different signals.
  • the non-display area 200 of the array substrate further includes a scan driving chip 230 and first and second control signal lines 231 and 232 connected to the scan driving chip 230.
  • the scan driving chip 230 provides a first control signal to the initialization circuit 211 through the first control signal line 231, so that the initialization circuit 211 provides the initialization signal to each column of the pixel circuits 110 when the first control signal is valid.
  • the scan driving chip 230 provides a second control signal to the data writing circuit 212 through the second control signal line 232, so that the data writing circuit 212 provides the data signal to each column of the pixel circuits 110 when the second control signal is valid.
  • the scan driving chip 230 is connected to the control terminal of the initialization circuit 211 through a first control signal line 231, and is connected to the control terminal of the data writing circuit 212 through a second control signal line 232.
  • the scan driving chip 230 outputs a first control signal and transmits the first control signal to the control terminal of the initialization circuit 211 through the first control signal line 231, so that the initialization circuit 211 is turned on, and the initialization signal can be transmitted to the pixel circuit 110 through the initialization circuit 211.
  • the scan driving chip 230 outputs a second control signal and transmits it to the control terminal of the data writing circuit 212 through the second control signal line 232, so that the data writing circuit 212 is turned on, and then the data signal can be transmitted to the pixels through the data writing circuit 212.
  • the circuit 110 writes a data signal to the pixel circuit 110.
  • the scan driving chip 230 is also connected to each row of pixel circuits 110 through a scan signal line, and is configured to provide a scan signal for each row of pixel circuits 110.
  • the array substrate further includes a light emitting control chip 240, which is connected to each row of pixel circuits 110 through a light emitting control signal line, and is configured to provide a light emitting control signal for each row of pixel circuits 110.
  • a plurality of pixel circuits 110 are arranged in an array of rows and columns.
  • PX 11 , PX 21 ,..., PX nm show).
  • the array arrangement of the pixel circuits 110 described above may also be in other forms.
  • the data driving chip 220, the scanning driving chip 230, and the light emitting control chip 240 may be independent control chips, or may be integrated on the same control chip.
  • the initialization circuit 211 includes an initialization transistor T 7
  • the data writing circuit 212 includes a data writing transistor T 8 .
  • the control terminal of the initialization transistor T 7 is connected to the scan driving chip 230 through a first control signal line 231
  • the first pole of the initialization transistor T 7 is connected to the pixel circuit 110 through a first signal line 120
  • the second pole of the initialization transistor T 7 is connected through a second
  • the signal line 221 is connected to the data driving chip 220.
  • Data write control terminal of the transistor T 8 is connected to chip 230 through the second scan driver control signal line 232, a first data writing transistor T 8 is connected via a first pixel circuit of the signal lines 120 110, a data writing transistor T 8 The second pole is connected to the data driving chip 220 through a second signal line 221.
  • the initialization circuit 211 and the data writing circuit 212 may also be other circuits capable of transmitting initialization signals and data signals, which are not limited herein.
  • the initialization transistor T 7 and the data writing transistor T 8 may both be P-type transistors.
  • the first control signal and the second control signal output by the scan driving chip 230 may be low-level signals, and the first control signal and the second control signal may control the initialization transistor T 7 and the data writing transistor T 8 to be turned on, respectively.
  • the initialization signal or data signal can be written into the pixel circuit 110 through the initialization transistor T 7 or the data writing transistor T 8 .
  • the pixel circuit 110 includes a first transistor T 1 , a second transistor T 2 , a third transistor T 3 , a fourth transistor T 4 , a fifth transistor T 5 , and a sixth transistor.
  • T 6 capacitor C 1 and light emitting diode D 1 .
  • the control terminal of the first transistor T 1 is connected to the first electrode plate of the capacitor C 1 , the second electrode of the second transistor T 2 and the first electrode of the sixth transistor T 6 , and the first electrode of the first transistor T 1 is connected
  • the first power source V DD the second pole of the first transistor T 1 is connected to the first pole of the second transistor T 2 and the first pole of the third transistor T 3 .
  • the control terminal of the second transistor T 2 is connected to the second scanning signal line.
  • the control terminal of the third transistor T 3 is connected to the light-emitting control signal line, and the second pole of the third transistor T 3 is connected to the first pole of the fifth transistor T 5 and the D 1 anode of the light-emitting diode.
  • the cathode of the light-emitting diode D 1 is connected to the second power source V SS .
  • the control terminal of the fifth transistor T 5 is connected to the control terminal of the sixth transistor T 6 and the first scanning signal line, and the second electrode of the fifth transistor T 5 is connected to the second electrode of the sixth transistor T 6 and the fourth transistor T 4.
  • the control terminal of the fourth transistor T 4 is connected to the third scanning signal line, and the first electrode of the fourth transistor T 4 is connected to the second plate of the capacitor C 1 .
  • the second transistor T 2 , the third transistor T 3 , the fourth transistor T 4 , the fifth transistor T 5 , and the sixth transistor T 6 of the pixel circuit 110 are all switching transistors, and the first transistor T 1 is a driving transistor.
  • the capacitor C 1 is an energy storage capacitor, and the light emitting diode D 1 is an OLED (Organic Light-Emitting Diode).
  • the transistors in this embodiment are all P-type transistors.
  • the control terminal is the gate of the transistor, the source of the first electrode and the drain of the second transistor. A low level is applied to the control terminal of the transistor to make the transistor conductive. . Since the thin film transistor is a symmetrical device, the first pole and the second pole can be interchanged.
  • the transistor may also be an N-type transistor. When an N-type transistor is used as the transistor in the pixel circuit 110, a high-level signal is input to the control terminal of the transistor to make it conductive.
  • the first power source V DD may be a positive voltage and is used to provide a power source voltage for the first transistor T 1 .
  • the first transistor T 1 outputs a current under the action of the first power source V DD . This current flows into the light emitting diode D 1 , so that the light emitting diode D 1 emits light.
  • the current flows into the second power source V SS , and the second power source V SS may be a negative voltage.
  • S 1 is the first scan signal transmitted by the first scan signal line
  • S 2 is the second scan signal transmitted by the second scan signal line
  • S 3 is the third scan transmitted by the third scan signal line.
  • Signal, EM is a light emission control signal transmitted by the light emission control signal line
  • X 1 is a first control signal transmitted by the first control signal line 231
  • X 2 is a second control signal transmitted by the second control signal line 232.
  • a first scanning signal line a control terminal of the fifth transistor and the sixth transistor T T. 5. 6 for a first scan signal input to the control terminal of the fifth transistor and the sixth transistor T T. 5. 6 to control the fifth transistor T 5 and the sixth transistor T 6 are turned on and off.
  • a second scanning signal line connected to the control terminal of the second transistor T 2, a second scan signal input to the control terminal of the second transistor T 2, to control the second transistor T 2 is turned on and off.
  • the third control terminal of the scanning signal line is connected to the fourth transistor T 4, a third scan signal input to the control terminal of the fourth transistor T 4 to control the fourth transistor T 4 is turned on and off.
  • a first control signal line 231 connected to the control terminal of the initialization transistor T 7, a first control signal input terminal of the control transistor T 7 to initialization, to control the initialization transistor T 7 is turned on and off.
  • a second control signal line 232 connected to the data write control terminal of the transistor T 8, a write control signal input terminal of the second control transistor T 8 to the data, control data writing transistor T 8 is turned on and off.
  • the first scan signal controls the fifth transistor T 5 and the sixth transistor T 6 to be in an on state
  • the first control signal controls the initialization transistor T 7 to be in an on state
  • the initialization signal is transmitted to the pixel circuit 110 through the initialization transistor T 7 , and the first electrode plate of the capacitor C 1 and the control terminal of the first transistor T 1 are initialized by the sixth transistor T 6 so that data can be written into the capacitor C 1 .
  • the initialization signal initializes the anode of the light emitting diode D 1 through the fifth transistor T 5 .
  • the voltage of the initialization signal is smaller than the power supply voltage of the second power source V SS to prevent the light-emitting diode D 1 from emitting light during the initialization phase.
  • the second scan signal controls the second transistor T 2 to be in an on state
  • the third scan signal controls the fourth transistor T 4 to be in an on state.
  • the two control signals control the data writing transistor T 8 to be in an on state, and the data signals are written to the second plate of the capacitor C 1 through the data writing transistor T 8 and the fourth transistor T 4 .
  • the third scan signal controls the fourth transistor T 4 to be in an on state
  • the first control signal controls the initialization transistor T 7 to be in an on state
  • the initialization signal is applied through the capacitor C 1 Go to the control terminal of the first transistor T 1 and compensate the power supply voltage provided by the first power supply V DD so that the current flowing through the first transistor T 1 is independent of the power supply voltage of the first power supply V DD .
  • the light emitting control signal When the light emitting control signal is valid, the light emitting control signal controls the third transistor T 3 to be in an on state, and a current flows through the light emitting diode D 1 to make the light emitting diode D 1 emit light.
  • FIG. 3 is a working timing diagram of the pixel circuit 110 according to an embodiment of the present application. Based on FIG. 2 and FIG. 3, the working principle of the pixel circuit 110 is:
  • the first scan signal and the first control signal are low-level signals
  • the second scan signal, the third scan signal, the light-emission control signal, and the second control signal are high-level signals.
  • the initialization transistor T 7 , the fifth transistor T 5 , and the sixth transistor T 6 are turned on, and the data writing transistor T 8 , the second transistor T 2 , the third transistor T 3 , and the fourth transistor T 4 are turned off.
  • the initialization signal Since the initialization transistor T 7 is turned on, the initialization signal enters the pixel circuit 110 through the transistor T 7 and the first signal line 120 connected to the transistor T 7 .
  • the initialization signal initializes the control terminal of the first transistor T 1 and the first plate of the capacitor C 1 through the sixth transistor T 6 .
  • the initialization signal may be, for example, the first reference voltage V ref .
  • the first reference voltage V ref may be a negative voltage.
  • a first reference voltage V ref applied to the control terminal of the first transistor T 1 as the first transistor T 1 may be turned on. Since the fifth transistor T 5 is turned on, the initialization signal can initialize the anode of the light emitting diode D 1 .
  • the second scan signal, the third scan signal, and the second control signal are low-level signals, and the first scan signal, the first control signal, and the light-emission control signal are high-level signals.
  • the data writing transistor T 8 , the second transistor T 2 and the fourth transistor T 4 are turned on, and in the initialization phase, the first transistor T 1 is turned on.
  • the third transistor T 3 , the fifth transistor T 5 , the sixth transistor T 6 , and the initialization transistor T 7 are turned off.
  • the power source voltage of the first power source V DD is written into the first pole of the first transistor T 1 .
  • the voltage of the first electrode of the first transistor T 1 continues to increase until the first transistor T 1 is in a critical state of being turned off and turned on. At this time, the potential of the first pole of the first transistor T 1 is V DD , and the potential of the control terminal is V DD-
  • the data writing transistor T 8 is turned on, the data signal enters the pixel circuit 110 through the data writing transistor T 8 . Since the fourth transistor T 4 is turned on, the data signal is written into the second plate of the capacitor C 1 through the fourth transistor T 4 , so that the potential of the second plate of the capacitor C 1 is V data .
  • the third scanning signal and the first control signal are low-level signals
  • the first scanning signal, the second scanning signal, the light emission control signal, and the second control signal are high-level signals.
  • the fourth transistor T 4 The initialization transistor T 7 is turned on, and the second transistor T 2 , the third transistor T 3 , the sixth transistor T 6 , the fifth transistor T 5 , and the data writing transistor T 8 are turned off.
  • the initialization transistor T 7 Since the initialization transistor T 7 is turned on, the initialization voltage is written into the second plate of the capacitor C 1 through the initialization transistor T 7 and the fourth transistor T 4. Therefore, the potential of the second plate of the capacitor C 1 is changed from V data to V ref . Since the second transistor T 2 and the sixth transistor T 6 are turned off, the voltage difference across the capacitor C 1 is unchanged. According to the capacitive coupling principle, the first pole of the capacitor C 1 is maintained under the condition that the voltage difference of the capacitor C 1 remains unchanged. The potential of the plate also changes with the change of the potential of the second plate, so the potential change of the first plate of the capacitor C 1 is V ref -V data .
  • the control terminal of the first transistor T 1 Since the control terminal of the first transistor T 1 is connected to the first plate of the capacitor C 1 , further, the amount of change in the potential of the control terminal of the first transistor T 1 is V ref -V data . Therefore, the potential of the control terminal of the first transistor T 1 is V DD-
  • the light-emitting control signal is a low-level signal
  • the first scan signal, the second scan signal, the third scan signal, the first control signal, and the second control signal are all high-level signals.
  • the third transistor T 3 is turned on, and the second transistor T 2 , the fourth transistor T 4 , the sixth transistor T 6 , the fifth transistor T 5 , the initialization transistor T 7 , and the data writing transistor T 8 are turned off. Since the third transistor T 3 is turned on, the loop from the first power source V DD , the first transistor T 1 , the third transistor T 3 , and the light emitting diode D 1 to the second power source V SS is turned on.
  • the current flowing through the first transistor T 1 is:
  • K 1/2 * ⁇ * C ox * W / L.
  • ⁇ is the electron mobility of the first transistor T 1
  • C ox is the gate oxide capacitance per unit area of the first transistor T 1 is
  • W is the channel width of the first transistor T 1
  • L is a channel of a first transistor T length.
  • the driving current flowing through the first transistor T 1 is the light emitting current flowing through the light emitting diode D 1 . It can be seen from the above formula that the light-emitting current flowing through the light-emitting diode D 1 has nothing to do with the voltage of the first power source V DD , nor has it a threshold voltage of the transistor, but has a relationship with the voltage value of the initialization signal.
  • the circuit structure of the array substrate can compensate the current-resistance voltage drop on the first power line by using the initialization signal.
  • the circuit structure and the control method thereof also compensate for the threshold voltage to the light-emitting current The effect of this can improve the uniformity of the screen's luminescence.
  • the data driving chip 220 of the array substrate is connected to the initialization transistor T 7 and the data writing transistor T 8 through the second signal line 221 and the third signal 222 line, respectively. Different signals are transmitted through different signal lines to facilitate control and prevent display. The problem of failure.
  • initializing transistor T 7 and transistor T 8 each data write by the first signal line 120 to the circuit 110 inputs the pixel signal, thereby reducing the routing density matrix screen, to further improve the resolution of the screen body.
  • the data driving chip 220, the scan driving chip 230, and the light emitting control chip 240 may include at least one memory storing a computer program and at least one processor executing the computer program.
  • the implementation of all or part of the processes in the methods of the above embodiments can be completed by hardware indicated by a computer program that can be stored in a non-transitory computer-readable storage medium.
  • a computer program is executed, embodiments of all the methods described above may be executed. Any reference to a memory, database, or other medium used in the embodiments provided herein may include non-transitory and / or temporary storage.
  • Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory.
  • Volatile memory can include random access memory (RAM) or external cache memory.
  • RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous chain (Synchlink), DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

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Abstract

本申请涉及一种阵列基板，包括显示区和围绕显示区设置的非显示区；显示区包括阵列排布的像素电路和连接每列像素电路的第一信号线；非显示区包括共用电路，每个共用电路分别通过第一信号线连接每列像素电路，用于为像素电路提供初始化信号和数据信号；非显示区还包括数据驱动芯片，数据驱动芯片通过第二信号线和第三信号线连接共用电路；数据驱动芯片通过第二信号线提供初始化信号至共用电路，共用电路接收初始化信号并通过第一信号线对像素电路进行初始化；数据驱动芯片通过第三信号线提供数据信号至共用电路，共用电路接收数据信号并通过第一信号线对像素电路进行数据写入。

Description

阵列基板及其驱动方法、显示面板
援引加入
本申请要求将于2018年09月28日提交中国专利局、申请号为201811137492.3、发明名称为“阵列基板及显示面板”的中国专利申请的优先权，其全部内容通过引用并入在本申请中。
技术领域
本申请涉及显示技术领域，特别是涉及阵列基板及其驱动方法、显示面板。
背景技术
有机发光显示面板因其具有对比度高、低功耗、视角广、反应速度快等优点，被越来越多地应用到显示领域。有机发光显示面板中包含阵列排布的像素电路。通常，为了实现高分辨率，会降低像素电路的尺寸，并且将数据信号线和初始化信号线合并，即数据信号和初始化信号通过同一信号线输入至像素电路中。申请人发现，驱动芯片通过同一条信号线输出不同信号以控制像素电路工作，容易产生控制失效的问题，进而导致显示面板显示失效。
发明内容
本申请公开的各种实施例，提供一种阵列基板及其驱动方法、显示面板。
本申请提供一种阵列基板，包括：显示区以及围绕所述显示区设置的非显示区。所述显示区包括若干阵列排布的像素电路和连接所述像素电路的第一信号线。所述非显示区包括：若干共用电路和数据驱动芯片。每个所述共用电路 通过所述第一信号线连接所述像素电路，用于为所述像素电路提供初始化信号和数据信号。所述数据驱动芯片通过第二信号线和第三信号线连接所述共用电路。其中，所述数据驱动芯片通过所述第二信号线提供所述初始化信号至所述共用电路，所述共用电路接收所述初始化信号并通过所述第一信号线对所述像素电路进行初始化，以及所述数据驱动芯片通过所述第三信号线提供所述数据信号至所述共用电路，所述共用电路接收所述数据信号并通过所述第一信号线对所述像素电路进行数据写入。
在其中一个实施例中，所述共用电路包括初始化电路和数据写入电路。所述初始化电路通过所述第二信号线连接所述数据驱动芯片，用于接收所述数据驱动芯片输出的初始化信号并通过所述第一信号线将所述初始化信号传输至所述像素电路。所述数据写入电路通过所述第三信号线连接所述数据驱动芯片，用于接收所述数据驱动芯片输出的数据信号并通过所述第一信号线将所述数据信号传输至所述像素电路。
在其中一个实施例中，所述非显示区还包括扫描驱动芯片和连接所述扫描驱动芯片的第一控制信号线和第二控制信号线。所述扫描驱动芯片通过所述第一控制信号线提供第一控制信号至所述初始化电路，以使所述初始化电路在所述第一控制信号有效时将所述初始化信号提供至所述像素电路。所述扫描驱动芯片通过所述第二控制信号线提供第二控制信号至所述数据写入电路，以使所述数据写入电路在所述第二控制信号有效时将所述数据信号提供至所述像素电路。
在其中一个实施例中，所述扫描驱动芯片通过扫描信号线连接所述像素电路，用于为所述像素电路提供扫描信号。
在其中一个实施例中，所述阵列基板还包括发光控制芯片，所述发光控制 芯片通过发光控制信号线连接所述像素电路，用于为所述像素电路提供发光控制信号。
在其中一个实施例中，所述初始化电路包括初始化晶体管，所述数据写入电路包括数据写入晶体管。所述初始化晶体管的控制端通过所述第一控制信号线连接所述扫描驱动芯片，所述初始化晶体管的第一极通过所述第一信号线连接所述像素电路，所述初始化晶体管的第二极通过所述第二信号线连接所述数据驱动芯片。所述数据写入晶体管的控制端通过所述第二控制信号线连接所述扫描驱动芯片，所述数据写入晶体管的第一极通过所述第一信号线连接所述像素电路，所述数据写入晶体管的第二极通过所述第二信号线连接所述数据驱动芯片。
在其中一个实施例中，所述像素电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、电容和发光二极管。所述第一晶体管的控制端连接所述电容的第一极板、所述第二晶体管的第二极和所述第六晶体管的第一极，所述第一晶体管的第一极连接所述第一电源，所述第一晶体管的第二极连接所述第二晶体管的第一极和所述第三晶体管T 3的第一极。所述第二晶体管的控制端连接第二扫描信号线。所述第三晶体管的控制端连接发光控制信号线，所述第三晶体管的第二极连接所述第五晶体管的第一极和所述发光二极管的阳极，所述发光二极管的阴极连接第二电源。所述第五晶体管的控制端分别连接所述第六晶体管的控制端和第一扫描信号线，所述第五晶体管的第二极连接所述第六晶体管的第二极、所述第四晶体管的第二极、所述初始化晶体管的第一极和所述数据写入晶体管的第一极。所述第四晶体管的控制端连接第三扫描信号线，所述第四晶体管的第一极连接所述电容的第二极板。
在其中一个实施例中，所述第一控制信号和所述第一扫描信号同时有效时， 所述第一控制信号控制所述初始化晶体管导通，所述第一扫描信号控制所述第五晶体管和所述第六晶体管导通，所述初始化信号对所述电容的第一极板、所述第一晶体管的控制端和所述发光二极管的阳极进行初始化。
在其中一个实施例中，所述初始化信号的电压小于所述第二电源的电源电压。
在其中一个实施例中，所述第三扫描信号和所述第二控制信号同时有效时，所述第三扫描信号控制所述第四晶体管导通，所述第二控制信号控制所述数据写入晶体管导通，所述数据信号通过所述数据写入晶体管和所述第四晶体管写入所述电容的第二极板。
在其中一个实施例中，所述第三扫描信号和所述第一控制信号同时有效时，所述第三扫描信号控制所述第四晶体管导通，所述第一控制信号控制所述初始化晶体管导通，所述初始化信号通过所述电容施加至所述第一晶体管的控制端，对第一电源提供的电源电压进行补偿。
在其中一个实施例中，在所述发光控制信号有效时，所述发光控制信号控制所述第三晶体管导通，所述发光二极管发光。
本申请提供一种显示面板，包括前述阵列基板。
本申请提供一种前述阵列基板的驱动方法，所述方法包括：数据驱动芯片通过第二信号线提供初始化信号至共用电路，所述共用电路接收所述初始化信号并通过第一信号线对像素电路进行初始化；以及所述数据驱动芯片通过第三信号线提供数据信号至所述共用电路，所述共用电路接收所述数据信号并通过所述第一信号线对所述像素电路进行数据写入。
在其中一个实施例中，所述共用电路包括初始化电路和数据写入电路，所述初始化电路通过所述第二信号线连接所述数据驱动芯片，所述数据写入电路 通过所述第三信号线连接所述数据驱动芯片，其中，所述方法还包括：所述初始化电路接收所述数据驱动芯片输出的初始化信号并通过所述第一信号线将所述初始化信号传输至所述像素电路；所述数据写入电路接收所述数据驱动芯片输出的数据信号并通过所述第一信号线将所述数据信号传输至所述像素电路。
在其中一个实施例中，所述非显示区还包括扫描驱动芯片和连接所述扫描驱动芯片的第一控制信号线和第二控制信号线，其中，所述方法还包括：所述扫描驱动芯片通过所述第一控制信号线提供第一控制信号至所述初始化电路，所述初始化电路在所述第一控制信号有效时将所述初始化信号提供至所述像素电路；所述扫描驱动芯片通过所述第二控制信号线提供第二控制信号至所述数据写入电路，所述数据写入电路在所述第二控制信号有效时将所述数据信号提供至所述像素电路。
在其中一个实施例中，所述扫描驱动芯片通过扫描信号线连接所述像素电路，其中，所述方法还包括：所述扫描驱动芯片通过扫描信号线为所述像素电路提供扫描信号。
在其中一个实施例中，所述阵列基板还包括发光控制芯片，所述发光控制芯片通过发光控制信号线连接所述像素电路，其中，所述方法还包括：所述发光控制芯片通过发光控制信号线为所述像素电路提供发光控制信号。
上述阵列基板及显示面板在非显示区设置有共用电路。数据驱动芯片通过第二信号线和第三信号线连接该共用电路。此外，数据驱动芯片在不同的时段输出不同的信号，并且可通过第二信号线提供初始化信号至共用电路，通过第三信号线提供数据信号至共用电路。共用电路将接收到的信号通过第一信号线输出至像素电路。本申请通过采用不同的走线来输出不同的信号，以便于数据驱动芯片的控制，解决了采用同一走线输出不同信号可能导致的显示失效的问 题。同时，在显示区内，共用电路通过第一信号线在不同时段分别传输数据信号和初始化信号至像素电路，即在显示区内数据信号和初始化信号共用一条信号线，降低了屏体走线的密度，从而可以增大开口率，实现高分辨率显示。
附图说明
图1为本申请的一个实施例提供的阵列基板示意图；
图2为申请的一个实施例提供的像素电路示意图；
图3为申请的一个实施例提供的像素电路的时序信号图。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本申请。但是本申请能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似改进，因此本申请不受下面公开的具体实施例的限制。
需要说明的是，当元件被称为“设置于”另一个元件，它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“垂直的”、“水平的”、“左”、“右”以及类似的表述只是为了说明的目的，并不表示是唯一的实施方式。
本申请的一个实施例提供一种阵列基板，包括显示区100和围绕显示区100设置的非显示区200。显示区100包括阵列排布的像素电路110和连接像素电路110的第一信号线120。非显示区200包括共用电路210，每个共用电路210分 别通过第一信号线120连接像素电路110，用于为像素电路110提供初始化信号和数据信号。非显示区200还包括数据驱动芯片220，数据驱动芯片220通过第二信号线221和第三信号线222连接共用电路210。进一步的，数据驱动芯片220通过第二信号线221提供初始化信号至共用电路210。共用电路210接收到初始化信号后通过第一信号线120对像素电路110进行初始化。数据驱动芯片220通过第三信号线222提供数据信号至共用电路210。共用电路210接收到数据信号后通过第一信号线120对像素电路110进行数据写入。本实施例中，数据驱动芯片220可在不同时段输出不同的信号，并分别通过第二信号线221或第三信号线222传输至共用电路210。需要说明的是，第一信号线120位于显示区100内，第二信号线221和第三信号线222位于非显示区200内。
上述实施例提供的阵列基板在非显示区200设置有共用电路210。数据驱动芯片220通过第二信号线221和第三信号线222连接共用电路210。此外，数据驱动芯片220在不同的时段输出不同的信号，并且可通过第二信号线221提供初始化信号至共用电路210，通过第三信号线222提供数据信号至共用电路210。共用电路210将接收到的信号通过第一信号线120输出至像素电路110。本实施例通过采用不同的走线来输出不同的信号，以便于数据驱动芯片220的控制，解决了采用同一走线输出不同信号可能导致的显示失效的问题。同时，在显示区100内，共用电路210通过第一信号线120在不同时段分别传输数据信号和初始化信号至像素电路110，即在显示区100内数据信号和初始化信号共用一条信号线，降低了屏体走线的密度，从而可以增大开口率，实现高分辨率显示。
在其中一个实施例中，请继续参见图1，共用电路210包括初始化电路211和数据写入电路212。初始化电路211通过第二信号线221连接数据驱动芯片220，用于接收数据驱动芯片220输出的初始化信号，并通过第一信号线120将 初始化信号传输至每列像素电路110。数据写入电路212通过第三信号线222连接数据驱动芯片220，用于接收数据驱动芯片220输出的数据信号并通过第一信号线120将数据信号传输至每列像素电路110。
本实施例中，每组初始化电路211和数据写入电路212的输出端共同连接同一条第一信号线120，并通过该第一信号线120对应连接一列像素单元。初始化电路211和数据写入电路212分别在不同时段工作。当初始化电路211工作时，数据写入电路212不工作，初始化电路211接收初始化信号并通过第一信号线120传输至像素电路110。当数据写入电路212工作时，初始化电路211不工作，数据写入电路212接收数据信号并通过第一信号线120传输至像素电路110。因此，本实施例中数据驱动芯片220分别通过不同的信号线传输两种信号，便于控制，且降低了采用同一走线输出不同信号可能导致的显示失效的风险。在其中一个实施例中，阵列基板的非显示区200还包括扫描驱动芯片230和连接所述扫描驱动芯片230的第一控制信号线231和第二控制信号线232。扫描驱动芯片230通过第一控制信号线231提供第一控制信号至初始化电路211，以使初始化电路211在第一控制信号有效时将初始化信号提供至每列像素电路110。扫描驱动芯片230通过第二控制信号线232提供第二控制信号至数据写入电路212，以使数据写入电路212在第二控制信号有效时将所述数据信号提供至每列像素电路110。
具体的，扫描驱动芯片230通过第一控制信号线231连接初始化电路211的控制端，通过第二控制信号线232连接数据写入电路212的控制端。扫描驱动芯片230输出第一控制信号并通过第一控制信号线231传输至初始化电路211的控制端，以使初始化电路211打开，进而初始化信号可通过初始化电路211传输至像素电路110。扫描驱动芯片230输出第二控制信号并通过第二控制信号 线232传输至数据写入电路212的控制端，以使数据写入电路212打开，进而数据信号可通过数据写入电路212传输至像素电路110以将数据信号写入像素电路110。
进一步的，扫描驱动芯片230还通过扫描信号线连接每行像素电路110，用于为每行像素电路110提供扫描信号。阵列基板还包括发光控制芯片240，通过发光控制信号线连接每行像素电路110，用于为每行像素电路110提供发光控制信号。
还需要注意的是，在如图1的上述实施例中，若干像素电路110是以行列形式的阵列进行排布，例如，PX 11、PX 21、...、PX nm(图1中未全部示出)。但是应当理解的是，只要不脱离发明的构思，上述像素电路110的阵列排布也可以是其他的形式。
数据驱动芯片220、扫描驱动芯片230和发光控制芯片240可以是相互独立的控制芯片，也可以集成于同一控制芯片上。
在其中一个实施例中，参见图2，初始化电路211包括初始化晶体管T 7，数据写入电路212包括数据写入晶体管T 8。初始化晶体管T 7的控制端通过第一控制信号线231连接扫描驱动芯片230，初始化晶体管T 7的第一极通过第一信号线120连接像素电路110，初始化晶体管T 7的第二极通过第二信号线221连接数据驱动芯片220。数据写入晶体管T 8的控制端通过第二控制信号线232连接扫描驱动芯片230，数据写入晶体管T 8的第一极通过第一信号线120连接像素电路110，数据写入晶体管T 8的第二极通过第二信号线221连接数据驱动芯片220。在其他实施例中，初始化电路211和数据写入电路212还可以是其他能够分别传输初始化信号与数据信号的电路，在此不做限定。
本实施例中，初始化晶体管T 7和数据写入晶体管T 8可以均为P型晶体管。 扫描驱动芯片230输出的第一控制信号和第二控制信号可以是低电平信号，进而第一控制信号和第二控制信号可以分别控制初始化晶体管T 7和数据写入晶体管T 8导通，以使初始化信号或数据信号可通过初始化晶体管T 7或数据写入晶体管T 8写入像素电路110中。
请继续参见图2，在其中一个实施例中，像素电路110包括第一晶体管T 1、第二晶体管T 2、第三晶体管T 3、第四晶体管T 4、第五晶体管T 5、第六晶体管T 6、电容C 1和发光二极管D 1。
其中，第一晶体管T 1的控制端连接电容C 1的第一极板、第二晶体管T 2的第二极和第六晶体管T 6的第一极，第一晶体管T 1的第一极连接第一电源V DD，第一晶体管T 1的第二极连接第二晶体管T 2的第一极和第三晶体管T 3的第一极。第二晶体管T 2的控制端连接第二扫描信号线。第三晶体管T 3的控制端连接发光控制信号线，第三晶体管T 3的第二极连接第五晶体管T 5的第一极和发光二极管的D 1阳极。发光二极管D 1的阴极连接第二电源V SS。第五晶体管T 5的控制端分别连接第六晶体管T 6的控制端和第一扫描信号线，第五晶体管T 5的第二极连接第六晶体管T 6的第二极、第四晶体管T 4的第二极、初始化晶体管T 7的第一极和数据写入晶体管T 8的第一极。第四晶体管T 4的控制端连接第三扫描信号线，第四晶体管T 4的第一极连接电容C 1的第二极板。
本实施例中，像素电路110的第二晶体管T 2、第三晶体管T 3、第四晶体管T 4、第五晶体管T 5、第六晶体管T 6均为开关晶体管，第一晶体管T 1为驱动晶体管。电容C 1为储能电容，发光二极管D 1为OLED(Organic Light-Emitting Diode,有机发光二极管)。本实施例中的晶体管均采用P型晶体管，控制端为晶体管的栅极，第一极为晶体管的源极，第二极为晶体管的漏极，对晶体管的控制端施加低电平以使晶体管导通。由于该薄膜晶体管为对称器件，故第一极和第二极 可以互换。当然，在其他实施例中，晶体管也可以是N型晶体管，在采用N型晶体管作为像素电路110中的晶体管时，对晶体管的控制端输入高电平信号以使其导通。
第一电源V DD可以是正电压，并用于为第一晶体管T 1提供电源电压。第一晶体管T 1在第一电源V DD的作用下，输出电流。该电流流入发光二极管D 1，使得发光二极管D 1发光。在发光二极管D 1发光时，该电流流入第二电源V SS，第二电源V SS可以是负电压。
图2所示电路中，S 1为第一扫描信号线传输的第一扫描信号，S 2为第二扫描信号线传输的第二扫描信号，S 3为第三扫描信号线传输的第三扫描信号，EM为发光控制信号线传输的发光控制信号，X 1为第一控制信号线231传输的第一控制信号，X 2为第二控制信号线232传输的第二控制信号。
第一扫描信号线连接第五晶体管T 5和第六晶体管T 6的控制端，用于向第五晶体管T 5和第六晶体管T 6的控制端输入第一扫描信号，以控制第五晶体管T 5和第六晶体管T 6的导通与断开。第二扫描信号线连接第二晶体管T 2的控制端，用于向第二晶体管T 2的控制端输入第二扫描信号，以控制第二晶体管T 2的导通与断开。第三扫描信号线连接第四晶体管T 4的控制端，用于向第四晶体管T 4的控制端输入第三扫描信号，以控制第四晶体管T 4的导通与断开。第一控制信号线231连接初始化晶体管T 7的控制端，用于向初始化晶体管T 7的控制端输入第一控制信号，以控制初始化晶体管T 7的导通与断开。第二控制信号线232连接数据写入晶体管T 8的控制端，用于向数据写入晶体管T 8的控制端输入第二控制信号，以控制数据写入晶体管T 8的导通与断开。
当第一控制信号和第一扫描信号同时有效时，第一扫描信号控制第五晶体管T 5和第六晶体管T 6处于导通状态，且第一控制信号控制初始化晶体管T 7处 于导通状态，初始化信号通过初始化晶体管T 7传输至像素电路110中，并通过第六晶体管T 6对电容C 1的第一极板和第一晶体管T 1的控制端进行初始化，以使数据能够写入电容C 1。同时，初始化信号通过第五晶体管T 5对发光二极管D 1的阳极进行初始化。需要说明的是，初始化信号的电压小于第二电源V SS的电源电压，以防止在初始化阶段发光二极管D 1发光。
当第二扫描信号、第三扫描信号和第二控制信号同时有效时，第二扫描信号控制第二晶体管T 2处于导通状态，第三扫描信号控制第四晶体管T 4处于导通状态，第二控制信号控制数据写入晶体管T 8处于导通状态，数据信号通过数据写入晶体管T 8和第四晶体管T 4写入电容C 1的第二极板。
当第三扫描信号和第一控制信号同时有效时，第三扫描信号控制第四晶体管T 4处于导通状态，第一控制信号控制初始化晶体管T 7处于导通状态，初始化信号通过电容C 1施加至第一晶体管T 1的控制端，并对第一电源V DD提供的电源电压进行补偿，以使流过所述第一晶体管T 1的电流与所述第一电源V DD的电源电压无关。
当发光控制信号有效时，发光控制信号控制第三晶体管T 3处于导通状态，电流流经所述发光二极管D 1以使所述发光二极管D 1发光。
图3为本申请的一个实施例提供的所述像素电路110的工作时序图。基于图2与图3，所述像素电路110的工作原理为：
在初始化阶段t1，第一扫描信号和第一控制信号为低电平信号，第二扫描信号、第三扫描信号、发光控制信号和第二控制信号为高电平信号。初始化晶体管T 7、第五晶体管T 5、第六晶体管T 6导通，数据写入晶体管T 8、第二晶体管T 2、第三晶体管T 3、第四晶体管T 4截止。
由于初始化晶体管T 7导通，初始化信号通过晶体管T 7和连接晶体管T 7的 第一信号线120进入像素电路110。初始化信号通过第六晶体管T 6对第一晶体管T 1的控制端和电容C 1的第一极板进行初始化。初始化信号例如可以是第一参考电压V ref。第一参考电压V ref可以是负电压。第一参考电压V ref作用于第一晶体管T 1的控制端可以使第一晶体管T 1导通。由于第五晶体管T 5导通，初始化信号可以对发光二极管D 1的阳极进行初始化。
在数据写入阶段t2，第二扫描信号、第三扫描信号和第二控制信号为低电平信号，第一扫描信号、第一控制信号和发光控制信号为高电平信号。数据写入晶体管T 8、第二晶体管T 2和第四晶体管T 4导通，在初始化阶段，第一晶体管T 1已导通。第三晶体管T 3、第五晶体管T 5、第六晶体管T 6、初始化晶体管T 7截止。
由于第一晶体管T 1导通，第一电源V DD的电源电压写入第一晶体管T 1的第一极。第一晶体管T 1的第一极电压不断升高，直至第一晶体管T 1处于截止与导通的临界状态。此时，第一晶体管T 1的第一极的电位为V DD，控制端电位为V DD-|V th|,实现了对第一晶体管T 1的阈值电压的补偿。由于数据写入晶体管T 8导通，数据信号经过数据写入晶体管T 8进入像素电路110内。由于第四晶体管T 4导通，数据信号通过第四晶体管T 4写入电容C 1的第二极板，以使电容C 1的第二极板的电位为V data。
在补偿阶段t3，第三扫描信号和第一控制信号为低电平信号，第一扫描信号、第二扫描信号、发光控制信号和第二控制信号为高电平信号，第四晶体管T 4、初始化晶体管T 7导通，第二晶体管T 2、第三晶体管T 3、第六晶体管T 6、第五晶体管T 5、数据写入晶体管T 8截止。
由于初始化晶体管T 7导通，初始化电压通过初始化晶体管T 7和第四晶体管T 4写入电容C 1的第二极板，因此，电容C 1的第二极板的电位由V data变为V ref。 由于第二晶体管T 2和第六晶体管T 6截止，电容C 1两端的电压差不变，根据电容耦合原理，在电容C 1的电压差保持不变的情况下，电容C 1的第一极板的电位也会随第二极板电位的变化而变化，故电容C 1的第一极板的电位变化量为V ref-V data。由于第一晶体管T 1的控制端连接电容C 1的第一极板，进而，第一晶体管T 1的控制端电位变化量为V ref-V data。因此，第一晶体管T 1的控制端的电位为V DD-|V th|+V ref-V data。
在发光阶段t4，发光控制信号为低电平信号，第一扫描信号、第二扫描信号、第三扫描信号、第一控制信号和第二控制信号均为高电平信号。第三晶体管T 3导通，第二晶体管T 2、第四晶体管T 4、第六晶体管T 6、第五晶体管T 5、初始化晶体管T 7、数据写入晶体管T 8截止。由于第三晶体管T 3导通，则从第一电源V DD、第一晶体管T 1、第三晶体管T 3、发光二极管D 1至第二电源V SS的回路导通。流过第一晶体管T 1的电流为：
I＝K*(V gs-V th) 2＝K*(V DD-|V th|+V ref-V data-V DD+|V th|) 2＝K*(V ref-V data) 2
其中，K＝1/2*μ*C ox*W/L。μ是第一晶体管T 1的电子迁移率，C ox是第一晶体管T 1单位面积的栅氧化层电容，W是第一晶体管T 1的沟道宽度，L是第一晶体管T 1的沟道长度。流过第一晶体管T 1的驱动电流即为流过发光二极管D 1的发光电流。由上述公式可以看出，流过发光二极管D 1的发光电流与第一电源V DD的电压无关，与晶体管的阈值电压也无关，而与初始化信号的电压值有关。因此，本申请的实施例提供的阵列基板，其中的电路结构可利用初始化信号补偿第一电源线上的电流-电阻压降，同时，上述电路结构及其控制方法也补偿了阈值电压对发光电流的影响，因此可以提高屏体发光的均一性。且阵列基板的数据驱动芯片220分别通过第二信号线221和第三信号222线连接初始化晶体 管T 7和数据写入晶体管T 8，通过不同的信号线传输不同的信号，便于控制，防止产生显示失效的问题。在显示区100内，初始化晶体管T 7和数据写入晶体管T 8均通过第一信号线120向像素电路110输入信号，因此降低了屏体的走线密度，进一步提高屏体的分辨率。
可以理解的是，数据驱动芯片220、扫描驱动芯片230以及发光控制芯片240可以包括至少一个存储有计算机程序的存储器和至少一个执行所述计算机程序的处理器。在上述实施例的方法中的全部或部分过程的实现可以由可以存储在一个非暂时性计算机可读存储介质中的计算机程序指示的硬件完成。当执行计算机程序时，可以执行上述所有方法的实施例。在本申请提供的实施例中使用的存储器、数据库或其他介质的任何引用都可以包括非暂时和/或暂时存储器。非易失性存储器可包括只读存储器(ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦除可编程ROM(EEPROM)或闪存。易失性存储器可包括随机存取存储器(RAM)或者外部高速缓冲存储器。作为说明而非局限，RAM以多种形式可得，诸如静态RAM(SRAM)、动态RAM(DRAM)、同步DRAM(SDRAM)、双数据率SDRAM(DDRSDRAM)、增强型SDRAM(ESDRAM)、同步链路(Synchlink)、DRAM(SLDRAM)、存储器总线(Rambus)直接RAM(RDRAM)、直接存储器总线动态RAM(DRDRAM)、以及存储器总线动态RAM(RDRAM)等。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请保护范围的限制。应当指出的是，本领域的普通 技术人员在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种阵列基板，包括：
    显示区，包括若干阵列排布的像素电路和连接所述像素电路的第一信号线；以及
    围绕所述显示区设置的非显示区，包括：
    若干共用电路，每个所述共用电路通过所述第一信号线连接所述像素电路，用于为所述像素电路提供初始化信号和数据信号；和
    数据驱动芯片，所述数据驱动芯片通过第二信号线和第三信号线连接所述共用电路，用于为所述共用电路提供所述初始化信号和所述数据信号。
  2. 根据权利要求1所述的阵列基板，其中，所述共用电路包括初始化电路和数据写入电路；
    所述初始化电路通过所述第二信号线连接所述数据驱动芯片，用于接收所述数据驱动芯片输出的初始化信号并通过所述第一信号线将所述初始化信号传输至所述像素电路；
    所述数据写入电路通过所述第三信号线连接所述数据驱动芯片，用于接收所述数据驱动芯片输出的数据信号并通过所述第一信号线将所述数据信号传输至所述像素电路。
  3. 根据权利要求2所述的阵列基板，其中，所述非显示区还包括扫描驱动芯片和连接所述扫描驱动芯片的第一控制信号线和第二控制信号线；
    所述扫描驱动芯片通过所述第一控制信号线提供第一控制信号至所述初始化电路，以使所述初始化电路在所述第一控制信号有效时将所述初始化信号提供至所述像素电路；
    所述扫描驱动芯片通过所述第二控制信号线提供第二控制信号至所述数据写入电路，以使所述数据写入电路在所述第二控制信号有效时将所述数据信号提供至所述像素电路。
  4. 根据权利要求3所述的阵列基板，其中，所述扫描驱动芯片通过扫描信号线连接所述像素电路，用于为所述像素电路提供扫描信号。
  5. 根据权利要求3所述的阵列基板，还包括发光控制芯片，所述发光控制芯片通过发光控制信号线连接所述像素电路，用于为所述像素电路提供发光控制信号。
  6. 根据权利要求3所述的阵列基板，其中，所述初始化电路包括初始化晶体管，所述数据写入电路包括数据写入晶体管；
    所述初始化晶体管的控制端通过所述第一控制信号线连接所述扫描驱动芯片，所述初始化晶体管的第一极通过所述第一信号线连接所述像素电路，所述初始化晶体管的第二极通过所述第二信号线连接所述数据驱动芯片；
    所述数据写入晶体管的控制端通过所述第二控制信号线连接所述扫描驱动芯片，所述数据写入晶体管的第一极通过所述第一信号线连接所述像素电路，所述数据写入晶体管的第二极通过所述第二信号线连接所述数据驱动芯片。
  7. 根据权利要求6所述的阵列基板，其中，所述像素电路包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、电容和发光二极管；
    所述第一晶体管的控制端连接所述电容的第一极板、所述第二晶体管的第二极和所述第六晶体管的第一极，所述第一晶体管的第一极连接所述第一电源，所述第一晶体管的第二极连接所述第二晶体管的第一极和所述第三晶体管的第一极；
    所述第二晶体管的控制端连接第二扫描信号线；
    所述第三晶体管的控制端连接发光控制信号线，所述第三晶体管的第二极连接所述第五晶体管的第一极和所述发光二极管的阳极，所述发光二极管的阴极连接第二电源；
    所述第五晶体管的控制端分别连接所述第六晶体管的控制端和第一扫描信号线，所述第五晶体管的第二极连接所述第六晶体管的第二极、所述第四晶体管的第二极、所述初始化晶体管的第一极和所述数据写入晶体管的第一极；
    所述第四晶体管的控制端连接第三扫描信号线，所述第四晶体管的第一极连接所述电容的第二极板。
  8. 根据权利要求7所述的阵列基板，其中，所述第一控制信号和所述第一扫描信号同时有效时，所述第一控制信号控制所述初始化晶体管导通，所述第一扫描信号控制所述第五晶体管和所述第六晶体管导通，所述初始化信号对所述电容的第一极板、所述第一晶体管的控制端和所述发光二极管的阳极进行初始化。
  9. 根据权利要求8所述的阵列基板，其中，所述初始化信号的电压小于所述第二电源的电源电压。
  10. 根据权利要求9所述的阵列基板，其中，所述第三扫描信号和所述第二控制信号同时有效时，所述第三扫描信号控制所述第四晶体管导通，所述第二控制信号控制所述数据写入晶体管导通，所述数据信号通过所述数据写入晶体管和所述第四晶体管写入所述电容的第二极板。
  11. 根据权利要求10所述的阵列基板，其中，所述第三扫描信号和所述第一控制信号同时有效时，所述第三扫描信号控制所述第四晶体管导通，所述第一控制信号控制所述初始化晶体管导通，所述初始化信号通过所述电容施加至 所述第一晶体管的控制端，对第一电源提供的电源电压进行补偿。
  12. 根据权利要求11所述的阵列基板，其中，在所述发光控制信号有效时，所述发光控制信号控制所述第三晶体管导通，所述发光二极管发光。
  13. 一种显示面板，包括权利要求1-12中任一项所述的阵列基板。
  14. 一种阵列基板的驱动方法，所述阵列基板为权利要求1所述的阵列基板，所述方法包括：
    数据驱动芯片通过第二信号线提供初始化信号至共用电路，所述共用电路接收所述初始化信号并通过第一信号线对像素电路进行初始化；以及
    所述数据驱动芯片通过第三信号线提供数据信号至所述共用电路，所述共用电路接收所述数据信号并通过所述第一信号线对所述像素电路进行数据写入。
  15. 根据权利要求14所述的方法，所述共用电路包括初始化电路和数据写入电路，所述初始化电路通过所述第二信号线连接所述数据驱动芯片，所述数据写入电路通过所述第三信号线连接所述数据驱动芯片，其中，所述方法还包括：
    所述初始化电路接收所述数据驱动芯片输出的初始化信号并通过所述第一信号线将所述初始化信号传输至所述像素电路；
    所述数据写入电路接收所述数据驱动芯片输出的数据信号并通过所述第一信号线将所述数据信号传输至所述像素电路。
  16. 根据权利要求15所述的方法，所述非显示区还包括扫描驱动芯片和连接所述扫描驱动芯片的第一控制信号线和第二控制信号线，其中，所述方法还包括：
    所述扫描驱动芯片通过所述第一控制信号线提供第一控制信号至所述初始 化电路，所述初始化电路在所述第一控制信号有效时将所述初始化信号提供至所述像素电路；
    所述扫描驱动芯片通过所述第二控制信号线提供第二控制信号至所述数据写入电路，所述数据写入电路在所述第二控制信号有效时将所述数据信号提供至所述像素电路。
  17. 根据权利要求16所述的阵列基板，所述扫描驱动芯片通过扫描信号线连接所述像素电路，其中，所述方法还包括：
    所述扫描驱动芯片通过扫描信号线为所述像素电路提供扫描信号。
  18. 根据权利要求16所述的阵列基板，所述阵列基板还包括发光控制芯片，所述发光控制芯片通过发光控制信号线连接所述像素电路，其中，所述方法还包括：
    所述发光控制芯片通过发光控制信号线为所述像素电路提供发光控制信号。
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