WO2020062460A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2020062460A1
WO2020062460A1 PCT/CN2018/114456 CN2018114456W WO2020062460A1 WO 2020062460 A1 WO2020062460 A1 WO 2020062460A1 CN 2018114456 W CN2018114456 W CN 2018114456W WO 2020062460 A1 WO2020062460 A1 WO 2020062460A1
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WO
WIPO (PCT)
Prior art keywords
base plate
data line
pixel electrode
electrically connected
electrode
Prior art date
Application number
PCT/CN2018/114456
Other languages
English (en)
French (fr)
Inventor
刘忠念
Original Assignee
惠科股份有限公司
重庆惠科金渝光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 惠科股份有限公司, 重庆惠科金渝光电科技有限公司 filed Critical 惠科股份有限公司
Priority to US16/245,401 priority Critical patent/US10847099B2/en
Publication of WO2020062460A1 publication Critical patent/WO2020062460A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a display panel, and a display device.
  • the structure on the array substrate is affected, and defects such as bright spots and bright lines are formed. Some of these defects can be repaired, for example, caused by film residues and foreign particles. Some can be repaired to normal points through repair processes, while others that are more serious or cannot be repaired are repaired into dark spots. However, the dark spot still has a great impact on the overall yield of the array substrate and the quality of the finished liquid crystal display module, which significantly reduces the performance and quality of the product.
  • the main purpose of this application is to provide an array substrate, which aims to improve product performance.
  • the array substrate provided in the present application includes a base plate, a plurality of scan lines and a plurality of data lines formed on the base plate, and the plurality of scan lines and the plurality of data lines are insulated to define a plurality of pixel units. ;
  • Each pixel unit includes a switching element and a pixel electrode electrically connected to the switching element.
  • the pixel electrode is electrically connected to a corresponding scanning line and a data line through the switching element.
  • At least one spare element is provided between two adjacent pixel electrodes. The two adjacent pixel electrodes are separated by a data line, and the spare element crosses the data line and is insulated and connected to at least one pixel electrode.
  • the spare element is provided on a different layer from the data line and is at least partially provided on the bottom plate, and a first insulation layer is provided between a portion of the spare element provided on the back plate and the data line. .
  • a second insulating layer is provided between two adjacent pixel electrodes and the data line, and each pixel electrode is electrically connected to the data line through a corresponding switching element.
  • the spare element includes a suspended metal piece provided on the base plate, and a projection area of each pixel electrode on the base plate and a projection area of the suspended metal piece on the base plate are at least Partial overlap.
  • the spare element includes a suspended metal block and an electrode bar which are disposed at a distance, the suspended metal block is provided on the bottom plate, and the electrode bar is electrically connected to a pixel electrode and straddles the data line. Spaced from adjacent pixel electrodes;
  • the projection area of the suspended metal block on the base plate at least partially overlaps with the projection area of the pixel electrode without an electrode strip on the base plate, and the projection area of the electrode strip on the base plate and the base plate
  • the projection area of the suspended metal block on the bottom plate at least partially overlaps.
  • the spare element is disposed at an end of two adjacent pixel electrodes away from the switching element.
  • the pixel unit further includes a common electrode which is insulated from the corresponding pixel electrode.
  • the switching element includes a control terminal, an input terminal, and an output terminal, the control terminal is electrically connected to a corresponding scanning line, the input terminal is electrically connected to a corresponding data line, and the output terminal is corresponding to a pixel
  • the electrodes are electrically connected.
  • the present application also provides a display panel including an array substrate, the array substrate including a base plate, a plurality of scan lines and a plurality of data lines formed on the base plate, and the plurality of scan lines and a plurality of data lines.
  • Data lines insulated crossing define multiple pixel units;
  • Each pixel unit includes a thin film transistor and a pixel electrode electrically connected to the thin film transistor.
  • the pixel electrode is electrically connected to a corresponding scan line and a data line through the thin film transistor.
  • At least one spare element is provided between two adjacent pixel electrodes. The two adjacent pixel electrodes are separated by a data line, and the spare element crosses the data line and is insulated and connected to at least one pixel electrode.
  • the present application also proposes a display device including a display panel, the display panel including an array substrate, the array substrate including a base plate, a plurality of scan lines and a plurality of data lines formed on the base plate, The plurality of scanning lines and the plurality of data lines are insulated from each other to define a plurality of pixel units;
  • Each pixel unit includes a thin film transistor and a pixel electrode electrically connected to the thin film transistor.
  • the pixel electrode is electrically connected to a corresponding scan line and a data line through the thin film transistor.
  • At least one spare element is provided between two adjacent pixel electrodes. The two adjacent pixel electrodes are separated by a data line, and the spare element crosses the data line and is insulated and connected to at least one pixel electrode.
  • At least one spare element is provided between two adjacent pixel units.
  • the spare element crosses the data line and is at least insulated from one pixel unit.
  • the corresponding element is provided through the switching element.
  • the pixel electrode is charged, and the brightness of two adjacent pixel electrodes remains the same; when a defect occurs in one of the pixel units, the adjacent two pixel electrodes are electrically connected through a spare element, and the brightness of the two pixel electrodes is the same to achieve the defect. Repairing can not only repair bright points, but also dark points, thus improving product performance, and the spare parts occupy a small space, are easy to set up, and greatly improve the repair efficiency.
  • FIG. 1 is a schematic plan view of an array substrate according to an embodiment of the present application.
  • FIG. 2 is a partial cross-sectional view before laser cutting at A-A in FIG. 1;
  • FIG. 3 is a partial cross-sectional view after laser cutting at A-A in FIG. 1;
  • FIG. 4 is a partial cross-sectional view before laser melting at B-B in FIG. 1;
  • FIG. 5 is a partial cross-sectional view after laser melting at B-B in FIG. 1;
  • FIG. 6 is a schematic plan view of another embodiment of an array substrate of the present application.
  • FIG. 7 is a partial cross-sectional view before laser melting at C-C in FIG. 6;
  • Fig. 8 is a partial cross-sectional view after laser melting at C-C in Fig. 6.
  • Label name Label name 100 Array substrate 50 Spare component 10 Floor 51 Suspension metal parts 20 Scan line 52 Suspended metal block 30 Data line 53 Electrode strip 40 Pixel unit 60 First insulation layer 41 Switching element 70 Second insulation layer 42 Pixel electrode 80 Common electrode
  • fixed may be a fixed connection, a detachable connection, or a whole; It is a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. It can be the internal connection of two elements or the interaction relationship between two elements, unless it is clearly defined otherwise.
  • fixed may be a fixed connection, a detachable connection, or a whole; It is a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. It can be the internal connection of two elements or the interaction relationship between two elements, unless it is clearly defined otherwise.
  • the present application proposes an array substrate 100.
  • the array substrate 100 includes a base plate 10, a plurality of scan lines 20 and a plurality of data lines 30 formed on the base plate 10, and the plurality of scan lines 20 Insulate and cross a plurality of data lines 30 to define a plurality of pixel units 40;
  • Each pixel unit 40 includes a switching element 41 and a pixel electrode 42 electrically connected to the switching element 41.
  • the pixel electrode 42 is electrically connected to the corresponding scanning line 20 and data line 30 through the switching element 41.
  • Two adjacent pixel electrodes At least one spare element 50 is provided between 42 and two adjacent pixel electrodes 42 are separated by a data line 30.
  • the spare element 50 crosses the data line 30 and is insulated from at least one pixel electrode 42 connection.
  • the bottom plate 10 is a transparent substrate, such as a glass substrate, a quartz substrate, or the like.
  • the scanning lines 20 and the data lines 30 are formed of a conductive material, such as aluminum alloy, chrome metal, and the like.
  • the array substrate 100 includes a plurality of pixel units 40 arranged in an array.
  • the scan lines 20 and the data lines 30 are insulated and cross to define a plurality of pixel units 40.
  • the scan lines 20 and the data lines 30 are arranged perpendicular to each other, and the plurality of scan lines 20 are parallel.
  • the plurality of data lines 30 are arranged at intervals.
  • the two adjacent data lines 30 and the two adjacent scanning lines 20 surround one another to define a pixel unit 40.
  • Each pixel unit 40 includes a switching element 41 and a pixel electrode 42.
  • the pixel electrode 42 is electrically connected to the corresponding scanning line 20 and data line 30 through the switching element 41.
  • the switching element 41 includes a control terminal (not shown), an input terminal (not shown), and an output terminal (not shown).
  • the control terminal is electrically connected to the corresponding scanning line 20, and the input terminal It is electrically connected to the corresponding data line 30, and the output terminal is electrically connected to the corresponding pixel electrode 42.
  • the optional switching element 41 is a thin film transistor.
  • the thin film transistor includes a gate, a source, and a drain. The gate is electrically connected to the corresponding scan line 20.
  • the gate and the scan line 20 are generally formed at the same time using the same material; the source and the corresponding The data line 30 is electrically connected, and the drain is electrically connected to the corresponding pixel electrode 42. Usually, the source and drain electrodes are formed simultaneously with the data line 30 using the same material.
  • the thin film transistor also includes an active layer (not shown).
  • the active layer may include a semiconductor layer and a doped semiconductor layer, which are located below the source and drain electrodes, and are located above the gate electrode, between the source electrode and the drain electrode. The entire doped semiconductor layer and a part of the semiconductor layer are etched away to form a TFT channel.
  • the gate When the gate is turned on, the source and drain are turned on through the active layer, and the image signal voltage in the data line 30 is passed to the pixel electrode 42.
  • the insulating layer covered on the scanning line 20 and the gate is a gate insulating layer, and the insulating layer covered on the data line 30, the active layer, the source, and the drain is passivated.
  • the pixel electrode 42 is formed on the passivation layer, and the pixel electrode 42 is connected to the drain through a via hole on the passivation layer.
  • the pixel electrode 42 may be a translucent electrode or a reflective electrode.
  • the pixel electrode 42 may include a transparent conductive layer.
  • the transparent conductive layer may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). At least one.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • IGO indium gallium oxide
  • AZO zinc aluminum oxide
  • the pixel electrode 42 may include a semi-transmissive reflective layer configured to improve light emission efficiency.
  • the transflective layer may be a thin layer (e.g., several nanometers to several tens of nanometers thick), and may include at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, and Yb One.
  • At least one spare element 50 is provided between two adjacent pixel electrodes 42.
  • the two adjacent pixel electrodes 42 are separated by a data line 30.
  • the spare element 50 crosses the data line 30 and is insulated and connected to at least one pixel electrode 42. .
  • the spare element 50 is a conductive material, and may be a metal having a low resistance. Since the pixel electrode 42 cannot directly cross the data line 30 and is connected by setting a spare element 50, compared with the scanning line 20, the occupied space is small and the installation is convenient.
  • the spare element 50 is provided integrally, the spare element 50 and the two pixel electrodes 42 are insulated and connected.
  • the spare element 50 is provided separately, a part of the spare element 50 is insulated and connected to a pixel electrode 42, and the other part is The other pixel electrode 42 is electrically connected.
  • the spare element 50 is insulated from the at least one pixel electrode 42 so that signals between two adjacent pixel electrodes 42 do not interfere with each other.
  • the spare element 50 It is also not connected to other conductive structures. At this time, the spare element 50 has no influence on the production process and the display characteristics of the array substrate 100.
  • at least one of the connection between the switching element 41 and the scanning line 20, the connection between the switching element 41 and the data line 30, or the connection between the switching element 41 and the pixel electrode 42 is performed. Cut off. In this embodiment, the connection between the switching element 41 and the pixel electrode 42 may be cut off, so that the switching element 41 and the pixel electrode 42 are electrically insulated.
  • the array substrate 100 of the present application is provided with at least one spare element 50 between two adjacent pixel units 40.
  • the spare element 50 crosses the data line 30 and is connected to at least one pixel unit 40.
  • the array substrate 100 works normally
  • the corresponding pixel electrode 42 is charged by the switching element 41, the brightness of two adjacent pixel electrodes 42 remains the same; when a defect occurs in one of the pixel units 40, the adjacent two pixel electrodes 42 are processed by the spare element 50 Electrically connected, the brightness of the two pixel electrodes 42 is the same, and defect repair can be performed, which can not only repair bright spots but also dark spots, thereby improving product performance, and the space occupied by the spare component 50 is small, which facilitates installation and greatly improves repair efficiency.
  • the backup element 50 is disposed on a different layer from the data line 30 and is at least partially disposed on the base plate 10.
  • the backup element 50 is disposed on the bottom plate 10.
  • a first insulating layer 60 is provided between a portion and the data line 30.
  • the spare element 50 and the data line 30 are arranged at different layers. It can be understood that the spare element 50 and the data line 30 are stacked or interposed with an insulating material, so that the spare element 50 can cross the data line 30, differently.
  • the layer setting can realize the cross-line between different metal layers and avoid signal short circuit.
  • the spare element 50 is provided as a whole, the spare elements 50 are all disposed on the base plate 10.
  • a first insulating layer 60 is provided between the spare element 50 and the data line 30, and the first insulating layer 60 is provided to the spare element 50 and the data.
  • the wire 30 is electrically insulated.
  • the spare element 50 When the spare element 50 is provided separately, a part of the spare element 50 is provided on the base plate 10, and another part is electrically connected to another pixel electrode 42. A portion provided on the base plate 10 and the data line 30 passes through the first insulating layer 60.
  • the first insulating layer 60 is a gate insulating layer.
  • a second insulating layer 70 is provided between two adjacent pixel electrodes 42 and the data line 30, and each pixel electrode 42 is electrically connected to the data line 30 through a corresponding switching element 41.
  • a second insulating layer 70 is provided between two adjacent pixel electrodes 42 and the data line 30.
  • the second insulating layer 70 is provided to electrically insulate the pixel electrode 42 and the data line 30, and the pixel electrode 42 passes the corresponding
  • the switching element 41 is electrically connected to the data line 30, wherein the second insulating layer 70 is a polyvinyl chloride insulating layer, which has resistance to sunlight and low temperature flexibility, a thick insulating layer, and a flame resistance level.
  • the spare element 50 includes a suspended metal piece 51 provided on the base plate 10.
  • the projection area of each pixel electrode 42 on the base plate 10 is the same as the projection area of the pixel electrode 42.
  • the projection area of the suspension metal piece 51 on the bottom plate 10 at least partially overlaps.
  • the spare element 50 is provided integrally.
  • the spare element 50 is a suspended metal piece 51 provided on the base plate 10, and the projection area of each pixel electrode 42 on the base plate 10 and the suspended metal piece 51 on the base plate 10
  • the projected area on the screen at least partially overlaps, so that when a pixel unit 40 displays abnormally, the overlapped portion of the pixel electrode 42 and the suspended metal piece 51 can be processed by laser melting or chemical vapor deposition to realize the pixel electrode.
  • the electrical connection between 42 and the suspended metal piece 51 makes the brightness between two adjacent pixel electrodes 42 consistent, thereby eliminating defects, and enabling the abnormally displayed pixel unit 40 to display normally.
  • the spare element 50 includes a suspended metal block 52 and an electrode bar 53 which are disposed at intervals.
  • the suspended metal block 52 is provided on the bottom plate 10 and the electrode bar 53. Electrically connected to one of the pixel electrodes 42 and spaced apart from adjacent pixel electrodes 42 across the data line 30;
  • the projection area of the floating metal block 52 on the base plate 10 at least partially overlaps the projection area of the pixel electrode 42 on the base plate 10 without the electrode strip 53, and the electrode strip 53 is on the base plate 10.
  • the projected area on the surface at least partially overlaps the projected area of the suspended metal block 52 on the bottom plate 10.
  • the spare element 50 is provided separately.
  • the spare element 50 includes a suspended metal block 52 and an electrode bar 53, which are separately provided.
  • the suspended metal block 52 is provided on the bottom plate 10 and is separated from the data line 30.
  • the first insulating layer 60 is used for insulation.
  • the electrode strip 53 is electrically connected to the pixel electrode 42 and is spaced apart from the adjacent pixel electrode 42 across the data line 30.
  • the electrode strip 53 may be optionally disposed on the edge of a pixel electrode 42.
  • the electrode strip 53 The material of 53 is the same as that of the pixel electrode 42, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), and indium gallium oxide (IGO). And at least one of aluminum zinc oxide (AZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • IGO indium gallium oxide
  • AZO aluminum zinc oxide
  • a transflective layer is provided to improve the luminous efficiency.
  • the transflective layer may be a thin layer (e.g., several nanometers to several tens of nanometers thick), and may include at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, and Yb One.
  • the projected area of the floating metal block 52 on the base plate 10 and the projected area of the pixel electrode 42 without the electrode strip 53 on the base plate 10 at least partially overlap, and the projected area of the electrode bar 53 on the base plate 10 and the suspended metal block 52 are The projected area on the base plate 10 at least partially overlaps, so that when an abnormal display occurs in a certain pixel unit 40, the overlapping portion of the pixel electrode 42 and the suspended metal block 52 can be processed by laser melting or chemical vapor deposition, and the electrode The overlapping portion of the strip 53 and the suspended metal block 52 is processed to achieve electrical conduction between the pixel electrode 42 and the suspended metal block 52, and the electrical conduction between the electrode strip 53 and the suspended metal block 52 makes two adjacent pixel electrodes 42 The brightness is kept the same, thereby eliminating defects, so that the abnormally displayed pixel unit 40 can display normally.
  • the spare element 50 is disposed at an end of two adjacent pixel electrodes 42 away from the switching element 41.
  • the pixel unit 40 further includes a common electrode 80 which is disposed to be insulated from the corresponding pixel electrode 42.
  • the display panel generally includes an array substrate 100, a color filter substrate (not shown), and a liquid crystal layer (not shown) provided between the array substrate 100 and the color filter substrate.
  • the common electrode 80 is a common electrode on the color filter substrate ( (Not shown) provides a common voltage and forms a storage capacitor with the pixel electrode 42 on the array substrate 100.
  • There are various installation positions of the common electrode 80 such as the parallel scan lines 20 or the parallel data lines. Depending on the installation positions, the functions are different.
  • the specific steps for repairing the array substrate 100 include:
  • the spare element 50 is electrically connected to two adjacent pixel electrodes 42.
  • a laser is used to cut off the switching element 41 from the scanning line 20, the data line 30, or the pixel electrode 42.
  • the switching element 41 is insulated from the scanning line 20, the data line 30, or the pixel electrode 42.
  • at least one of the connection between the switching element 41 and the scanning line 20, the connection between the switching element 41 and the data line 30, or the connection between the switching element 41 and the pixel electrode 42 is cut off.
  • the connection between the switching element 41 and the pixel electrode 42 may be cut off, so that the switching element 41 and the pixel electrode 42 are electrically insulated. As shown by the arrow in FIG. 2, the direction of the laser cutting is shown.
  • the spare element 50 is then electrically connected to two adjacent pixel electrodes 42 by laser melting or chemical vapor deposition, so that the abnormally displayed pixel unit 40 can be displayed normally.
  • the step of electrically connecting the spare element 50 to two adjacent pixel electrodes 42 includes:
  • a laser is used to fuse the insulation connection between the spare element 50 and the pixel electrode 42 so that the spare element 50 is electrically connected to two adjacent pixel electrodes 42.
  • the laser energy used for laser melting is 0.5J ⁇ 1J
  • the laser energy used for laser cutting is 1 J ⁇ 5J, as shown by the arrows in Figure 4 and Figure 7, the direction of laser melting.
  • the present application also proposes a display panel including an array substrate 100.
  • a display panel including an array substrate 100.
  • the display panel adopts all the technical solutions of all the above embodiments, it has at least the above embodiments. All the beneficial effects brought by the technical solution are not repeated here.
  • the present application also proposes a display device including a display panel.
  • a display panel For a specific structure of the display panel, refer to the foregoing embodiments. Since the display device adopts all the technical solutions of all the above embodiments, it has at least the technologies of the above embodiments. All the beneficial effects brought by the scheme are not repeated here one by one.

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Abstract

一种阵列基板（100）、显示面板及显示装置，阵列基板（100）的相邻两像素电极（42）之间通过一数据线（30）隔开，备用元件（50）跨过数据线（30），并至少与一像素电极（42）绝缘连接。

Description

阵列基板、显示面板及显示装置
技术领域
本申请涉及显示技术领域，特别涉及一种阵列基板、显示面板及显示装置。
背景技术
液晶显示器在生产过程中，由于异物颗粒或者制造工序中产生的问题，会对阵列基板上的结构产生影响，形成亮点、亮线之类的不良。其中部分不良是可以维修的，例如由薄膜残留和异物颗粒引起的，有一些可以通过修补工序修成正常点，另外一些比较严重或者无法维修的则被修成暗点。但是暗点对于阵列基板的整体良率以及液晶显示模组成品的品质仍然存在很大影响，显著降低产品的性能和品质。
发明内容
本申请的主要目的是提供一种阵列基板，旨在提高产品性能。
为实现上述目的，本申请提出的阵列基板，包括底板，形成于所述底板上的多条扫描线和多条数据线，所述多条扫描线和多条数据线绝缘交叉限定多个像素单元；
每一像素单元包括开关元件和与所述开关元件电连接的像素电极，所述像素电极通过开关元件与对应的扫描线和数据线电连接，相邻两像素电极之间设有至少一备用元件，相邻两所述像素电极之间通过一数据线隔开，所述备用元件跨过所述数据线，并至少与一像素电极绝缘连接。
可选的，所述备用元件与所述数据线异层设置，并至少部分设于所述底板，所述备用元件设于所述底板的部分与所述数据线之间设有第一绝缘层。
可选的，相邻两所述像素电极与所述数据线之间设有第二绝缘层，且每一像素电极通过对应的开关元件与所述数据线电连接。
可选的，所述备用元件包括设于所述底板的悬置金属件，每一所述像素电极于所述底板上的投影面积与所述悬置金属件于所述底板上的投影面积至少部分重叠。
可选的，所述备用元件包括隔开设置的悬浮金属块和电极条，所述悬浮金属块设于所述底板，所述电极条与一所述像素电极电连接并跨过所述数据线与相邻的像素电极间隔设置；
所述悬浮金属块于所述底板上的投影面积与未连接有电极条的像素电极于所述底板上的投影面积至少部分重叠，且所述电极条于所述底板上的投影面积与所述悬浮金属块于所述底板上的投影面积至少部分重叠。
可选的，所述备用元件设于相邻两个像素电极远离所述开关元件的一端。
可选的，所述像素单元还包括与对应的像素电极绝缘设置的公共电极。
可选的，所述开关元件包括控制端、输入端和输出端，所述控制端与对应的扫描线电连接，所述输入端与对应的数据线电连接，所述输出端与对应的像素电极电连接。
本申请还提出一种显示面板，所述显示面板包括阵列基板，所述阵列基板，包括底板，形成于所述底板上的多条扫描线和多条数据线，所述多条扫描线和多条数据线绝缘交叉限定多个像素单元；
每一像素单元包括薄膜晶体管和与所述薄膜晶体管电连接的像素电极，所述像素电极通过薄膜晶体管与对应的扫描线和数据线电连接，相邻两像素电极之间设有至少一备用元件，相邻两所述像素电极之间通过一数据线隔开，所述备用元件跨过所述数据线，并至少与一像素电极绝缘连接。
本申请还提出一种显示装置，所述显示装置包括显示面板，所述显示面板包括阵列基板，所述阵列基板，包括底板，形成于所述底板上的多条扫描线和多条数据线，所述多条扫描线和多条数据线绝缘交叉限定多个像素单元；
每一像素单元包括薄膜晶体管和与所述薄膜晶体管电连接的像素电极，所述像素电极通过薄膜晶体管与对应的扫描线和数据线电连接，相邻两像素电极之间设有至少一备用元件，相邻两所述像素电极之间通过一数据线隔开，所述备用元件跨过所述数据线，并至少与一像素电极绝缘连接。
本申请阵列基板通过在相邻两列像素单元之间设有至少一备用元件，备用元件跨过数据线，并至少与一像素单元绝缘连接，当阵列基板正常工作时，通过开关元件给对应的像素电极充电，此时相邻两个像素电极的亮度保持一致；当其中一个像素单元出现缺陷时，通过备用元件将相邻两个像素电极进行电连接，两个像素电极的亮度相同，实现缺陷修补，不仅可以修复亮点，也可以修复暗点，因而提高了产品性能，且备用元件所占空间小，设置方便，大大提高修复效率。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请阵列基板一实施例的平面结构示意图；
图2为图1中A-A处进行激光切断前的部分剖示图；
图3为图1中A-A处进行激光切断后的部分剖示图；
图4为图1中B-B处进行激光熔融前的部分剖示图；
图5为图1中B-B处进行激光熔融后的部分剖示图；
图6为本申请阵列基板另一实施例的平面结构示意图；
图7为图6中C-C处进行激光熔融前的部分剖示图；
图8为图6中C-C处进行激光熔融后的部分剖示图。
附图标号说明：
标号 名称 标号 名称
100 阵列基板 50 备用元件
10 底板 51 悬置金属件
20 扫描线 52 悬浮金属块
30 数据线 53 电极条
40 像素单元 60 第一绝缘层
41 开关元件 70 第二绝缘层
42 像素电极 80 公共电极
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，本申请实施例中所有方向性指示（诸如上、下、左、右、前、后……）仅设置为解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
在本申请中，除非另有明确的规定和限定，术语“连接”、“固定”等应做广义理解，例如，“固定”可以是固定连接，也可以是可拆卸连接，或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系，除非另有明确的限定。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
另外，在本申请中如涉及“第一”、“第二”等的描述仅设置为描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出一种阵列基板100。
参照图1和图6，在本申请实施例中，该阵列基板100，包括底板10，形成于所述底板10上的多条扫描线20和多条数据线30，所述多条扫描线20和多条数据线30绝缘交叉限定多个像素单元40；
每一像素单元40包括开关元件41和与所述开关元件41电连接的像素电极42，所述像素电极42通过开关元件41与对应的扫描线20和数据线30电连接，相邻两像素电极42之间设有至少一备用元件50，相邻两所述像素电极42之间通过一数据线30隔开，所述备用元件50跨过所述数据线30，并至少与一像素电极42绝缘连接。
具体的，底板10为透明基板，如玻璃基板、石英基板等。扫描线20和数据线30均为导体材料形成，如铝合金、铬金属等。其中，阵列基板100包括多个呈阵列排布的像素单元40，扫描线20与数据线30绝缘交叉限定多个像素单元40，扫描线20与数据线30相互垂直设置，多条扫描线20平行间隔设置，多条数据线30平行间隔设置，相邻两条数据线30和相邻两条扫描线20围合限定一个像素单元40。
每一像素单元40包括开关元件41和像素电极42，像素电极42通过开关元件41与对应的扫描线20和数据线30电连接。本实施例中，开关元件41包括控制端（未图示）、输入端（未图示）和输出端（未图示），所述控制端与对应的扫描线20电连接，所述输入端与对应的数据线30电连接，所述输出端与对应的像素电极42电连接。可选开关元件41为薄膜晶体管，薄膜晶体管包括栅极、源极和漏极，栅极与对应的扫描线20电连接，栅极一般与扫描线20采用相同材质同时形成；源极与对应的数据线30电连接，漏极与对应的像素电极42电连接。通常源极和漏极与数据线30采用相同材质同时形成。薄膜晶体管还包括有源层（未图示），有源层可以包括半导体层和掺杂半导体层，位于源极和漏极的下方，且位于栅极的上方，源电极和漏电极之间的全部掺杂半导体层 和部分半导体层被刻蚀掉，形成TFT沟道。当栅极通入高电平时，源极和漏极通过有源层导通，将数据线30中的图像信号电压通入像素电极42。为保持各导电结构之间的绝缘，在扫描线20和栅极上覆盖的绝缘层为栅极绝缘层，在数据线30、有源层、源极和漏 极上覆盖的绝缘层为钝化层。像素电极42形成在钝化层上，像素电极42通过钝化层上的过孔与漏极相连。像素电极42可以是半透明电极或反射电极。当像素电极42是半透明电极时，像素电极42可包括透明导电层。透明导电层可包括例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟(In2O3)、氧化铟镓(IGO)和氧化铝锌(AZO)中的至少一种。
除了透明导电层之外，像素电极42可包括设置为提高发光效率的半透反射层。半透反射层可以是薄层(例如几纳米至几十纳米厚)，并且可包括Ag、Mg、Al、Pt、Pd、Au、Ni、Nd、Ir、Cr、Li、Ca和Yb中的至少一种。
相邻两像素电极42之间设有至少一备用元件50，相邻两像素电极42之间通过一数据线30隔开，备用元件50跨过数据线30，并至少与一像素电极42绝缘连接。备用元件50为导电材料，可选为电阻低的金属。 由于像素电极42不能直接跨过数据线30，通过设置备用元件50进行连接，相较于跨过扫描线20，所占用空间小，设置方便。当备用元件50为一体设置时，备用元件50与两个像素电极42均绝缘连接，当备用元件50为分体设置时，备用元件50的其中一部分与一像素电极42绝缘连接，其另一部分与另一像素电极42电连接。
在对像素单元40进行检测后，如果各个像素单元40都能正常显示，由于备用元件50与至少一像素电极42绝缘连接，使得相邻两个像素电极42之间信号互不干扰，备用元件50也未与其他导电结构连接，此时备用元件50对生产工艺和阵列基板100的显示特性没有任何影响。当检测出现了非正常显示的像素单元40后，将开关元件41与扫描线20的连接处、开关元件41与数据线30的连接处或开关元件41与像素电极42的连接处至少其中之一切断。本实施例中可选将开关元件41与像素电极42的连接处进行切断，使得开关元件41与像素电极42之间电绝缘。
本申请阵列基板100通过在相邻两列像素单元40之间设有至少一备用元件50，备用元件50跨过数据线30，并至少与一像素单元40绝缘连接，当阵列基板100正常工作时，通过开关元件41给对应的像素电极42充电，此时相邻两个像素电极42的亮度保持一致；当其中一个像素单元40出现缺陷时，通过备用元件50将相邻两个像素电极42进行电连接，两个像素电极42的亮度相同，实现缺陷修补，不仅可以修复亮点，也可以修复暗点，因而提高了产品性能，且备用元件50所占空间小，设置方便，大大提高修复效率。
参照图4、图5、图7和图8，所述备用元件50与所述数据线30异层设置，并至少部分设于所述底板10，所述备用元件50设于所述底板10的部分与所述数据线30之间设有第一绝缘层60。
本实施例中，备用元件50与数据线30异层设置，可以理解的，备用元件50与数据线30之间层叠设置或者夹设有绝缘材料，使得备用元件50能跨过数据线30，异层设置能实现不同金属层之间跨线，避免信号短接。当备用元件50为一体设置时，备用元件50全部设于底板10，此时备用元件50与数据线30之间设有第一绝缘层60，第一绝缘层60设置为对备用元件50和数据线30进行电绝缘。当备用元件50为分体设置时，备用元件50的其中一部分设于底板10，另一部分与另一像素电极42电连接，设于底板10的部分与数据线30之间通过第一绝缘层60绝缘设置，该第一绝缘层60为栅极绝缘层。
进一步的，相邻两所述像素电极42与所述数据线30之间设有第二绝缘层70，且每一像素电极42通过对应的开关元件41与所述数据线30电连接。
本实施例中，相邻两像素电极42与数据线30之间设有第二绝缘层70，第二绝缘层70设置为对像素电极42和数据线30进行电绝缘，像素电极42通过对应的开关元件41与数据线30电连接，其中，第二绝缘层70为聚氯乙烯绝缘层，其具有抗日照和低温挠性、较厚的绝缘层和耐燃级别。
参照图1至图5，一实施例中，所述备用元件50包括设于所述底板10的悬置金属件51，每一所述像素电极42于所述底板10上的投影面积与所述悬置金属件51于所述底板10上的投影面积至少部分重叠。
本实施例中，备用元件50为一体设置，此时备用元件50为设于底板10的悬置金属件51，每一像素电极42于底板10上的投影面积与悬置金属件51于底板10上的投影面积至少部分重叠，如此设置，当某一像素单元40出现非正常显示时，可通过激光熔融或化学气相沉积对像素电极42和悬置金属件51的重叠部分进行处理，实现像素电极42和悬置金属件51的电性导通，使得相邻两个像素电极42之间的亮度保持一致，进而消除缺陷，使得非正常显示的像素单元40能够正常显示。
参照图6至图8，另一实施例中，所述备用元件50包括隔开设置的悬浮金属块52和电极条53，所述悬浮金属块52设于所述底板10，所述电极条53与一所述像素电极42电连接并跨过所述数据线30与相邻的像素电极42间隔设置；
所述悬浮金属块52于所述底板10上的投影面积与未连接有电极条53的像素电极42于所述底板10上的投影面积至少部分重叠，且所述电极条53于所述底板10上的投影面积与所述悬浮金属块52于所述底板10上的投影面积至少部分重叠。
本实施例中，备用元件50为分体设置，此时备用元件50包括悬浮金属块52和电极条53，两者分开设置，其中，悬浮金属块52设于底板10，且与数据线30之间通过第一绝缘层60绝缘设置。电极条53与像素电极42电连接并跨过数据线30与相邻的像素电极42间隔设置，电极条53可选设于一像素电极42的边缘，为了实现较好的电性连接，电极条53的材质与像素电极42为相同材质的导电材料，例如氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)、氧化铟(In2O3 )、氧化铟镓(IGO)和氧化铝锌(AZO)中的至少一种。除了透明导电层之外，还包括设置为提高发光效率的半透反射层。半透反射层可以是薄层(例如几纳米至几十纳米厚)，并且可包括Ag、Mg、Al、Pt、Pd、Au、Ni、Nd、Ir、Cr、Li、Ca和Yb中的至少一种。
悬浮金属块52于底板10上的投影面积与未连接有电极条53的像素电极42于底板10上的投影面积至少部分重叠，且电极条53于底板10上的投影面积与悬浮金属块52于底板10上的投影面积至少部分重叠，如此设置，当某一像素单元40出现非正常显示时，可通过激光熔融或化学气相沉积对像素电极42和悬浮金属块52的重叠部分进行处理，以及电极条53与悬浮金属块52的重叠部分进行处理，实现像素电极42和悬浮金属块52的电性导通，电极条53和悬浮金属块52的电性导通，使得相邻两个像素电极42之间的亮度保持一致，进而消除缺陷，使得非正常显示的像素单元40能够正常显示。
进一步的，为了方便备用元件50的设置，所述备用元件50设于相邻两个像素电极42远离所述开关元件41的一端。
进一步的，所述像素单元40还包括与对应的像素电极42绝缘设置的公共电极80。显示面板一般包括阵列基板100、彩膜基板（未图示）、和设于阵列基板100和彩膜基板之间的液晶层（未图示），公共电极80为彩膜基板上的公共电极（未图示）提供公共电压，并与阵列基板100上的像素电极42形成存储电容。公共电极80的设置位置有多种，如平行扫描线20设置、或平行数据线设置，根据其设置位置，作用也不一样。
参照图1至图8，其中，阵列基板100修补的具体步骤包括：
采用激光切断所述开关元件41与所述扫描线20、数据线30或像素电极42的连接处，将开关元件41与扫描线20、数据线30或像素电极42绝缘连接；
将所述备用元件50与相邻两个像素电极42进行电连接。
本实施例中，在对像素单元40进行检测后，当检测出现了非正常显示的像素单元40后，采用激光切断所述开关元件41与所述扫描线20、数据线30或像素电极42的连接处，将开关元件41与扫描线20、数据线30或像素电极42绝缘连接。具体的，将开关元件41与扫描线20的连接处、开关元件41与数据线30的连接处或开关元件41与像素电极42的连接处至少其中之一切断。本实施例中可选将开关元件41与像素电极42的连接处进行切断，使得开关元件41与像素电极42之间电绝缘，如图2中箭头所示为激光切断的方向。
然后通过激光熔融或化学气相沉积将备用元件50与相邻两个像素电极42进行电连接，使得非正常显示的像素单元40能够正常显示。
本实施例中，可选将所述备用元件50与相邻两个像素电极42进行电连接的步骤包括：
采用激光熔融所述备用元件50与所述像素电极42的绝缘连接处，以使所述备用元件50与相邻两个像素电极42电连接。
其中，激光熔融所采用的激光能量为0.5J ~1J，激光切断所采用的激光能量为1 J ~5J，如图4和图7中箭头所示为激光熔融的方向。
本申请还提出一种显示面板，该显示面板包括阵列基板100，该阵列基板100的具体结构参照上述实施例，由于本显示面板采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有有益效果，在此不再一一赘述。
本申请还提出一种显示装置，该显示装置包括显示面板，该显示面板的具体结构参照上述实施例，由于本显示装置采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有有益效果，在此不再一一赘述。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的发明构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (20)

  1. 一种阵列基板，其中，包括底板，形成于所述底板上的多条扫描线和多条数据线，所述多条扫描线和多条数据线绝缘交叉限定多个像素单元；
    每一像素单元包括开关元件和与所述开关元件电连接的像素电极，所述像素电极通过开关元件与对应的扫描线和数据线电连接，相邻两像素电极之间设有至少一备用元件，相邻两所述像素电极之间通过一数据线隔开，所述备用元件跨过所述数据线，并至少与一像素电极绝缘连接。
  2. 如权利要求1所示的阵列基板，其中，所述备用元件与所述数据线异层设置，并至少部分设于所述底板，所述备用元件设于所述底板的部分与所述数据线之间设有第一绝缘层。
  3. 如权利要求2所示的阵列基板，其中，相邻两所述像素电极与所述数据线之间设有第二绝缘层，且每一像素电极通过对应的开关元件与所述数据线电连接。
  4. 如权利要求1所示的阵列基板，其中，所述备用元件包括设于所述底板的悬置金属件，每一所述像素电极于所述底板上的投影面积与所述悬置金属件于所述底板上的投影面积至少部分重叠。
  5. 如权利要求1所示的阵列基板，其中，所述备用元件包括隔开设置的悬浮金属块和电极条，所述悬浮金属块设于所述底板，所述电极条与一所述像素电极电连接并跨过所述数据线与相邻的像素电极间隔设置；
    所述悬浮金属块于所述底板上的投影面积与未连接有电极条的像素电极于所述底板上的投影面积至少部分重叠，且所述电极条于所述底板上的投影面积与所述悬浮金属块于所述底板上的投影面积至少部分重叠。
  6. 如权利要求1所示的阵列基板，其中，所述备用元件设于相邻两个像素电极远离所述开关元件的一端。
  7. 如权利要求1所示的阵列基板，其中，所述像素单元还包括与对应的像素电极绝缘设置的公共电极。
  8. 如权利要求1所示的阵列基板，其中，所述开关元件包括控制端、输入端和输出端，所述控制端与对应的扫描线电连接，所述输入端与对应的数据线电连接，所述输出端与对应的像素电极电连接。
  9. 一种显示面板，其中，所述显示面板包括所述的阵列基板，所述阵列基板包括底板，形成于所述底板上的多条扫描线和多条数据线，所述多条扫描线和多条数据线绝缘交叉限定多个像素单元；
    每一像素单元包括开关元件和与所述开关元件电连接的像素电极，所述像素电极通过开关元件与对应的扫描线和数据线电连接，相邻两像素电极之间设有至少一备用元件，相邻两所述像素电极之间通过一数据线隔开，所述备用元件跨过所述数据线，并至少与一像素电极绝缘连接。
  10. 如权利要求9所示的显示面板，其中，所述备用元件与所述数据线异层设置，并至少部分设于所述底板，所述备用元件设于所述底板的部分与所述数据线之间设有第一绝缘层。
  11. 如权利要求10所示的显示面板，其中，相邻两所述像素电极与所述数据线之间设有第二绝缘层，且每一像素电极通过对应的开关元件与所述数据线电连接。
  12. 如权利要求9所示的显示面板，其中，所述备用元件包括设于所述底板的悬置金属件，每一所述像素电极于所述底板上的投影面积与所述悬置金属件于所述底板上的投影面积至少部分重叠。
  13. 如权利要求9所示的显示面板，其中，所述备用元件包括隔开设置的悬浮金属块和电极条，所述悬浮金属块设于所述底板，所述电极条与一所述像素电极电连接并跨过所述数据线与相邻的像素电极间隔设置；
    所述悬浮金属块于所述底板上的投影面积与未连接有电极条的像素电极于所述底板上的投影面积至少部分重叠，且所述电极条于所述底板上的投影面积与所述悬浮金属块于所述底板上的投影面积至少部分重叠。
  14. 如权利要求9所示的显示面板，其中，所述备用元件设于相邻两个像素电极远离所述开关元件的一端。
  15. 如权利要求9所示的显示面板，其中，所述像素单元还包括与对应的像素电极绝缘设置的公共电极。
  16. 如权利要求9所示的显示面板，其中，所述开关元件包括控制端、输入端和输出端，所述控制端与对应的扫描线电连接，所述输入端与对应的数据线电连接，所述输出端与对应的像素电极电连接。
  17. 一种显示装置，其中，所述显示装置包括所述的显示面板，所述显示面板包括所述的阵列基板，所述阵列基板包括底板，形成于所述底板上的多条扫描线和多条数据线，所述多条扫描线和多条数据线绝缘交叉限定多个像素单元；
    每一像素单元包括开关元件和与所述开关元件电连接的像素电极，所述像素电极通过开关元件与对应的扫描线和数据线电连接，相邻两像素电极之间设有至少一备用元件，相邻两所述像素电极之间通过一数据线隔开，所述备用元件跨过所述数据线，并至少与一像素电极绝缘连接。
  18. 如权利要求17所示的显示装置，其中，所述备用元件与所述数据线异层设置，并至少部分设于所述底板，所述备用元件设于所述底板的部分与所述数据线之间设有第一绝缘层。
  19. 如权利要求18所示的显示装置，其中，相邻两所述像素电极与所述数据线之间设有第二绝缘层，且每一像素电极通过对应的开关元件与所述数据线电连接。
  20. 如权利要求17所示的显示装置，其中，所述备用元件包括设于所述底板的悬置金属件，每一所述像素电极于所述底板上的投影面积与所述悬置金属件于所述底板上的投影面积至少部分重叠。
PCT/CN2018/114456 2018-09-30 2018-11-08 阵列基板、显示面板及显示装置 WO2020062460A1 (zh)

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