WO2020052047A1 - 栅极驱动电路、电位移转器及显示装置 - Google Patents

栅极驱动电路、电位移转器及显示装置 Download PDF

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Publication number
WO2020052047A1
WO2020052047A1 PCT/CN2018/115121 CN2018115121W WO2020052047A1 WO 2020052047 A1 WO2020052047 A1 WO 2020052047A1 CN 2018115121 W CN2018115121 W CN 2018115121W WO 2020052047 A1 WO2020052047 A1 WO 2020052047A1
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WIPO (PCT)
Prior art keywords
unit
sub
output
current
clock signal
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PCT/CN2018/115121
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English (en)
French (fr)
Inventor
王明良
Original Assignee
重庆惠科金渝光电科技有限公司
惠科股份有限公司
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Application filed by 重庆惠科金渝光电科技有限公司, 惠科股份有限公司 filed Critical 重庆惠科金渝光电科技有限公司
Priority to US16/257,083 priority Critical patent/US10878931B2/en
Publication of WO2020052047A1 publication Critical patent/WO2020052047A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present application relates to the technical field of display panels, and in particular, to a gate driving circuit, an electric displacement converter, and a display device.
  • GOA Gate driver on Array. Gate driver integration on an array substrate
  • a general display panel has Gate IC (gate driver IC) bound to the panel, and Gate The size of the IC limits further narrowing of the bezel.
  • the GOA circuit is to split the original Gate IC into an electric displacement converter (level shifter IC) and shift register (shift register) two parts, the electric displacement converter is made on the driver board, the shift register is on the panel, the electric displacement converter sends CLK to the shift register to complete the drive, thereby saving Gate
  • the IC structure further compresses the frame length.
  • the GOA process will make shift registers on the left and right sides of the panel to achieve bilateral driving.
  • the shift register on one side may be damaged and the display may be abnormal. Damaged, so it is impossible to fix a driving method.
  • Driver boards are costly and time consuming.
  • the main purpose of this application is to provide a gate driving circuit, which aims to improve the compatibility of the driving board and reduce the design cost.
  • the gate driving circuit includes:
  • the potential boosting unit is configured to divide the clock signal output by the timing controller into two clock signal groups and output the two corresponding shift registers to the display panel to drive the display panel to work; two clock signal groups Each includes at least one sub-clock signal;
  • a switching unit connected in series between the potential boosting unit and the shift registers at both ends of the display panel and configured to be correspondingly turned on or off according to the received control signal to control the clock signal group output or stop the output;
  • the current detection unit is connected in series between the potential boosting unit and the switching unit, or is connected in series between the switching unit and the shift register at both ends of the display panel, and is configured to detect the two clock signal groups respectively. Output current of each of the sub-clock signals, and feedback multiple current signals to the control unit; and
  • the control unit is configured to receive a plurality of the current signals output by the current detection unit, and compare the current values corresponding to the plurality of current signals with a preset current threshold respectively. When any one of the clock signal groups When the current value of the sub-clock signal is less than the preset current threshold, a control signal is output to the switch unit to control the switch unit to cut off the output of the clock signal group.
  • a signal input terminal of the potential boosting unit is provided for connection with a signal output terminal of the timing controller, a signal output terminal of the potential boosting unit is connected to a signal input terminal of the electric detection unit, and the current
  • the signal output terminal of the detection unit is connected to the signal input terminal of the switch unit, and the first signal output terminal of the switch unit is connected to the signal input terminal of the first group of shift registers of the display panel.
  • the second signal output terminal is connected to the signal input terminal of the second group of shift registers of the display panel, the controlled terminal of the potential boosting unit, the signal output terminal of the current detection unit, and the controlled unit of the switching unit.
  • the terminals are connected to the signal terminal of the control unit.
  • the switching unit includes a first sub-switching unit and a second sub-switching unit, and the potential boosting unit outputs two identical clock signals via the first sub-switching unit and the second sub-switching unit, respectively.
  • the shift registers grouped to both ends of the display panel, the controlled end of the first sub-switching unit and the controlled end of the second sub-switching unit are both connected to the control end of the control unit.
  • the switching unit includes a plurality of sub-switching units, and each of the sub-clock signals is output to the shift register through each of the sub-switching units.
  • the control terminal of the control unit is connected.
  • a plurality of sub-switching units provided between the current detection unit and the first group of shift registers are linked, and a plurality of sub-switching units provided between the current detection unit and the second group of shift registers are linked.
  • each of the sub-switching units is a metal-oxide semiconductor field-effect transistor.
  • each of the sub-switching units is a triode.
  • the current detection unit includes a plurality of sub-current detection units, and each of the sub-current detection units detects a current of each of the sub-clock signals and feeds back a current signal to the control unit, respectively.
  • the present application also proposes an electric displacement converter, which includes the gate driving circuit as described above, and the gate driving circuit includes:
  • the potential boosting unit is configured to divide the clock signal output by the timing controller into two clock signal groups and output the corresponding two sets of shift registers on the display panel to drive the display panel to work; two clock signals The groups each include at least one sub-clock signal;
  • a switching unit connected in series between the potential boosting unit and the shift registers at both ends of the display panel and configured to be correspondingly turned on or off according to the received control signal to control the clock signal group output or stop the output;
  • the current detection unit is connected in series between the potential boosting unit and the switching unit, or is connected in series between the switching unit and the shift register at both ends of the display panel, and is configured to detect the two clock signal groups respectively. Output current of each of the sub-clock signals, and feedback multiple current signals to the control unit; and
  • the control unit is configured to receive a plurality of the current signals output by the current detection unit, and compare the current values corresponding to the plurality of current signals with a preset current threshold respectively. When any one of the clock signal groups When the current value of the sub-clock signal is less than the preset current threshold, a control signal is output to the switch unit to control the switch unit to cut off the output of the clock signal group.
  • a signal input terminal of the potential boosting unit is provided for connection with a signal output terminal of the timing controller, a signal output terminal of the potential boosting unit is connected with a signal input terminal of the current detection unit, and the current detection
  • the signal output terminal of the unit is connected to the signal input terminal of the switch unit, and the first signal output terminal of the switch unit is connected to the signal input terminal of the first group of shift registers of the display panel.
  • the two signal output terminals are connected to the signal input terminals of the second group of shift registers of the display panel, the controlled terminal of the potential boosting unit, the signal output terminal of the current detection unit, and the controlled terminal of the switching unit. Are connected to the signal end of the control unit.
  • the switching unit includes a first sub-switching unit and a second sub-switching unit, and the potential boosting unit outputs two identical clock signals via the first sub-switching unit and the second sub-switching unit, respectively.
  • the shift registers grouped to both ends of the display panel, the controlled end of the first sub-switching unit and the controlled end of the second sub-switching unit are both connected to the control end of the control unit.
  • the switching unit includes a plurality of sub-switching units, and each of the sub-clock signals is output to the shift register via each of the sub-switching units, and the controlled ends of each of the sub-switching units are respectively connected with The control terminal of the control unit is connected.
  • a plurality of sub-switching units provided between the current detection unit and the first group of shift registers are linked, and a plurality of sub-switching units provided between the current detection unit and the second group of shift registers are linked.
  • each of the sub-switching units is a metal-oxide semiconductor field-effect transistor.
  • each of the sub-switching units is a triode.
  • the current detection unit includes a plurality of sub-current detection units, and each of the sub-current detection units detects a current of each of the sub-clock signals and feeds back a current signal to the control unit, respectively.
  • the potential boosting unit, the current detecting unit, the switching unit, and the control unit are integrated in the electric displacement converter.
  • the present application also proposes a display device including the electric displacement converter as described above.
  • the electric displacement converter includes the gate driving circuit.
  • the gate driving circuit includes:
  • the potential boosting unit is configured to divide the clock signal output by the timing controller into two clock signal groups and output the corresponding two sets of shift registers on the display panel to drive the display panel to work; two clock signals The groups each include at least one sub-clock signal;
  • a switching unit connected in series between the potential boosting unit and the shift registers at both ends of the display panel and configured to be correspondingly turned on or off according to the received control signal to control the clock signal group output or stop the output;
  • the current detection unit is connected in series between the potential boosting unit and the switching unit, or is connected in series between the switching unit and the shift register at both ends of the display panel, and is configured to detect the two clock signal groups respectively. Output current of each of the sub-clock signals, and feedback multiple current signals to the control unit; and
  • the control unit is configured to receive a plurality of the current signals output by the current detection unit, and compare the current values corresponding to the plurality of current signals with a preset current threshold respectively. When any one of the clock signal groups When the current value of the sub-clock signal is less than the preset current threshold, a control signal is output to the switch unit to control the switch unit to cut off the output of the clock signal group.
  • the technical solution of the present application uses a potential boosting unit, a current detection unit, a switching unit and a control unit to form a gate driving circuit.
  • the potential boosting unit performs potential boosting of the low-voltage logic signal input by the timing controller, and is divided into two channels including at least one sub-circuit.
  • the clock signal group of the clock signal is output to two shift registers on the display panel, so that the display panel is driven bilaterally.
  • the current detection unit detects the current of the clock signal current of each channel, and then feeds it back to the control unit. When one of the display panels moves When the bit register is damaged, the current of the clock signal output to the shift register is abnormal.
  • the control unit outputs a control signal to the switch unit corresponding to the current signal fed back by the current detection unit, thereby turning off the clock signal output to the shift register. Achieve unilateral driving. Therefore, different abnormal states of the shift registers at both ends of the display panel are dynamically matched, and the compatibility of the driver board is improved.
  • FIG. 1 is a functional module schematic diagram of an embodiment of a gate driving circuit of the present application
  • FIG. 2 is a schematic diagram of a functional module of another embodiment of a gate driving circuit of the present application.
  • FIG. 3 is a schematic diagram of a functional module of another embodiment of a gate driving circuit of the present application.
  • FIG. 4 is a schematic diagram of a functional module of an embodiment of the electric displacement converter of the present application.
  • the gate driving circuit 100 of the present application is configured to drive a small-sized display panel.
  • the load of the gate line is small. Therefore, a bilateral driving or a unilateral driving can be adopted, as shown in FIG.
  • FIG. A functional module schematic diagram of an embodiment of applying a gate driving circuit.
  • the gate driving circuit 100 includes:
  • the potential boosting unit 110 is configured to divide the clock signals output by the timing controller 200 into two clock signal groups and output the corresponding two sets of shift registers to the display panel to drive the display panel to work.
  • the signal groups each include at least one sub-clock signal;
  • the switching unit 140 is connected in series between the potential boosting unit 110 and the shift registers at both ends of the display panel, and is configured to be correspondingly turned on or off according to the received switch control signal to control the clock signal group output or stop Output
  • the current detection unit 130 is connected in series between the potential boosting unit 110 and the switching unit 140, or is connected in series between the switching unit 140 and a shift register at both ends of the display panel, and is configured to detect two channels respectively. Describing the output current of each sub-clock signal of the clock signal group, and feeding back multiple current signals to the control unit 120; and
  • the control unit 120 is configured to receive a plurality of the current signals output by the current detection unit 130, and compare the current values corresponding to the plurality of current signals with a preset current threshold, respectively. When the current value of any sub-clock signal is less than the preset current threshold, a control signal is output to the switching unit 140 to control the switching unit 140 to cut off the output of the clock signal group.
  • the display panel includes, but is not limited to, a liquid crystal display panel, an organic light emitting diode display panel, a field emission display panel, a plasma display panel, and a curved panel.
  • the liquid crystal panel includes a thin film transistor liquid crystal display panel, TN (Twisted Nematic (Twisted Nematic) panels, VA (Vertical Alignment) panels, IPS (In-Plane Switching, plane switching) panel.
  • the shift registers provided at the two ends of the display panel receive multiple clock signals output by the gate driving circuit 100 and drive the pixels inside the display panel to work.
  • the two sets of shift registers respectively receive the same clock signals, and each clock signal is better than the previous one.
  • the clock signal advances a certain period.
  • the clock signals output by the gate drive circuit 100 to the two sets of shift registers are CLK1 ⁇ CLK4, CLK2 is 1/4 cycle ahead of CLK1, and CLK3 is 1/4 cycle ahead of CLK2.
  • the driving circuit 100 can also output 6 sub-clock signals or 8 sub-clock signals according to requirements. Using more CLK signals can reduce the load of each signal line and reduce power consumption, but it will also increase the circuit pins. In actual design, the number of clock signals to be output can be selected according to the conditions of the frame width, product size, integrated circuit design, and resolution of the specific product.
  • the potential boosting unit 110 receives the low-level clock signal output from the timing controller 200, and performs level conversion on the clock signal under the modulation of the control unit 120. After the low-level clock signal is boosted, it outputs two identical clock signals Each clock signal group includes at least one sub-clock signal. The number of sub-clock signals can be set according to requirements, such as 4, 6, or 8.
  • the clock signal group output by the potential boosting unit 110 flows through the current detection unit 130.
  • the switch unit 140 outputs two sets of shift registers at both ends of the display panel.
  • the current detection unit 130 detects the current of each sub-clock signal.
  • the current detection circuit can select circuits such as sampling resistors or transformers for current detection.
  • the switch unit 140 You can select multiple switching components or switching circuits with switching capabilities, such as relays, field-effect transistors, and triodes. You can choose one switch to control the signal output of a clock signal group, or one switch to control the output of a sub-clock signal. The controlled end of the switch is connected to the control end of the control unit 120, according to The control signal output by the control unit 120 is turned on or off.
  • the control unit 120 can select a microprocessor, a programmable single-chip microcomputer, etc., and a comparator circuit can be set up on the periphery for voltage comparison. It can be specifically set according to the actual situation. Here, there are no specific restrictions.
  • the signal input terminal of the potential boosting unit 110 is provided for connection with the signal output terminal of the timing controller 200, and the signal output terminal of the potential boosting unit 110 flows with the signal of the electrical detection unit.
  • the input terminal is connected.
  • the signal output terminal of the current detection unit 130 is connected to the signal input terminal of the switch unit 140.
  • the first signal output terminal of the switch unit 140 is connected to the first group of shift registers 310 of the display panel.
  • the signal input terminal of the switch unit 140 is connected to the signal input terminal of the second group of shift registers 320 of the display panel.
  • the controlled terminal of the potential boosting unit 110 and the current are connected.
  • the signal output terminal of the detection unit 130 and the controlled terminal of the switch unit 140 are both connected to the signal terminal of the control unit 120.
  • the current detection unit 130 may be disposed at the front end or the rear end of the switch unit 140, and may be specifically set according to the position of the driving board, which is not specifically limited here.
  • the current detection unit 130 is disposed at the switch unit.
  • the signal output end of the switch unit 140 is connected to the signal input ends of the two sets of shift registers respectively.
  • bilateral driving is realized.
  • the current detection unit 130 detects the size of the clock signal and feeds back the current value of each sub-clock signal to the control unit 120.
  • the control unit 120 judges that the group of shift registers is abnormal according to the magnitude of the current value and a preset current threshold, and outputs a control signal to the switching unit 140.
  • the sub-switching unit 140 inside the switching unit 140 correspondingly turns on or off. , Cut off the clock signal group output to this group of shift registers to realize unilateral driving If the two shift registers are damaged, then the two clock signals are cut off and the repair or replacement of the shift register.
  • the gate driving circuit 100 can be set to drive a small-sized display panel.
  • the driving is bilateral, and when an abnormality occurs in one of the shift registers, the driving is automatically switched to the unilateral driving and the gate driving
  • the circuit 100 is installed on the driving board, and can drive the left, right, and left and right sides normally. There is no need to design three kinds of driving boards, thereby improving the compatibility of the driving boards and reducing the design cost.
  • the technical solution of the present application adopts a potential boosting unit 110, a current detection unit 130, a switching unit 140, and a control unit 120 to form a gate driving circuit 100.
  • the potential boosting unit 110 performs potential boosting on a low-voltage logic signal input from the timing controller 200, and divides The two clock signal groups including at least one sub-clock signal are output to two sets of shift registers on the display panel, thereby driving the display panel bilaterally.
  • the current detection unit 130 detects the current of the clock signal current of each channel and then feeds it back to the control unit 120. When a group of shift registers on the display panel is damaged, the current of the clock signal output to the group of shift registers is abnormal.
  • the control unit 120 outputs a control signal to the switch unit 140 according to the current signal fed back by the current detection unit 130. , So as to turn off the clock signal output to the group of shift registers, and realize unilateral driving. Therefore, different abnormal states of the shift registers at both ends of the display panel are dynamically matched, and the compatibility of the driver board is improved.
  • the switching unit 140 includes a first sub-switching unit 141 and a second sub-switching unit. 142.
  • the potential boosting unit 110 outputs two identical clock signal groups to the shift registers at both ends of the display panel via the first sub-switching unit 141 and the second sub-switching unit 142, respectively.
  • the first sub-switch The controlled terminal of the unit 141 and the controlled terminal of the second sub-switching unit 142 are both connected to the control terminal of the control unit 120.
  • two sets of clock signals are output to the corresponding shift register via the first sub-switch unit 141 and the second sub-switch unit 142, respectively, to realize bilateral driving.
  • the first sub-switch unit 141 and the second sub-switch The unit 142 controls the output of multiple sub-clock signals at the same time.
  • the first sub-switching unit 141 and the second sub-switching unit 142 initially remain on.
  • one of the two sets of shift registers is damaged, such as the first group of shifts, Register 310.
  • the current of the clock signal group output to the first group of shift registers 310 is abnormal.
  • One of the sub-clock signal currents is too small, or one of the multiple sub-clock signal currents is too small.
  • control unit 120 When the current value is less than the preset current threshold, the control unit 120 outputs a control signal to the first sub-switching unit 141, and the first sub-switching unit 141 is turned off, thereby cutting off at least one sub-clock output to the first group of shift registers 310 Signal, thereby forming a single-sided drive. Similarly, when the second group of shift registers 320 is damaged, the second sub-switching unit 142 is turned off.
  • the first sub-switching unit 141 and the second sub-switching unit 142 may adopt multiple-input multiple-output relays or other switching components, and may be specifically designed according to actual conditions, and are not specifically limited herein.
  • FIG. 3 is a functional module schematic diagram of another embodiment of a gate driving circuit of the present application.
  • the switching unit 140 includes a plurality of sub-switching units 140, and each sub-clock The signal is output to the shift register through each sub-switching unit 140, and the controlled end of each of the sub-switching units 140 is respectively connected to the control end of the control unit 120.
  • the switching unit 140 includes a plurality of sub-switching units 140, such as K1 to K8.
  • the sub-switching units 140 correspond to the clock signals output by the potential boosting unit 110 one by one.
  • Each sub-switching unit 140 is connected in series to the current detection unit. 130 and the shift register are set to control the output of each sub-clock signal, and a plurality of sub-switch units 140 provided between the current detection unit 130 and the first group of shift registers 310 are linked, for example, K1 in FIG. 3 ⁇ K4 is turned on or off at the same time, and a plurality of sub-switching units 140 provided between the current detection unit 130 and the second group of shift registers 320 are linked.
  • K5 to K8 in FIG. 3 are turned on or off at the same time, thereby achieving A plurality of sub-clock signals of the clock signal group are controlled synchronously, and the automatic switching between the bilateral driving and the unilateral driving is realized under the control of the control unit 120.
  • each of the sub-switching units is a metal-oxide semiconductor field effect transistor.
  • each sub-switching unit may use a metal-oxide semiconductor field-effect transistor, and the gate of the metal-oxide semiconductor field-effect transistor is a sub-switching unit.
  • the controlled end of the metal-oxide semiconductor field-effect transistor is connected to the control terminal of the control unit 120.
  • the source or drain of the metal-oxide semiconductor field-effect transistor is connected to the signal output terminal of the current detection unit 130.
  • the source or source is connected to the first group of shift registers 310 or the second group of shift registers 320.
  • the metal-oxide semiconductor field-effect transistor can be an N-channel metal-oxide semiconductor field-effect transistor or a P-channel metal-oxide.
  • the control unit 120 When using an N-channel metal-oxide semiconductor field-effect transistor, the control unit 120 outputs a high level to the metal-oxide semiconductor field-effect transistor to make it conductive, and outputs a low level to the metal-oxide To turn off the semiconductor field effect transistor. When a P-channel metal-oxide semiconductor field effect transistor is selected, the control unit 120 outputs a low level to the metal-oxide semiconductor field. The MOSFET is turned on, and a high level is output to the MOSFET to turn it off. The type of the MOSFET can be flexibly selected without specific restrictions.
  • each of the sub-switch units is a triode.
  • each sub-switching unit may also use a triode, and the base of the triode is the controlled end of the sub-switching unit and connected to the control end of the control unit 120.
  • the collector or emitter of the transistor is connected to the signal output terminal of the current detection unit 130.
  • the emitter or collector of the transistor is connected to the signal input terminal of the corresponding shift register.
  • the transistor can be an NPN transistor or a PNP transistor. When an NPN transistor is selected The control unit 120 outputs a high level to the NPN transistor to control its conduction and outputs a low level to turn it off. Correspondingly, when a PNP transistor is selected, the control unit 120 outputs a low level to a PNP transistor to control its conduction. Turn on and output high level to turn it off.
  • the type of triode can be flexibly selected without specific restrictions.
  • the current detection unit 130 includes a plurality of sub-current detection units, and each of the sub-current detection units separately detects a current of each of the sub-clock signals, and respectively feeds back the current signals to the sub-clock signals. Control unit 120.
  • multiple sub-current detection units are set to detect the sub-clock signals output by the potential boosting unit 110, and the number of sub-current detection units is equal to the number of sub-clock signals and corresponds one-to-one, and each sub-current detection unit detects a correspondence
  • the sub-clock signal is fed back to the control unit 120.
  • the sub-current detection unit may use a current transformer or a sampling resistor to perform current detection, and may be set according to specific conditions.
  • FIG. 4 is a functional block diagram of an embodiment of the electric displacement converter of the present application.
  • the present application also proposes an electric displacement converter 400 including the gate driving circuit 100 as described above.
  • the GOA circuit is to split the original Gate IC into an electric shift converter 400 (level shifter IC) and shift register (shift register) two parts, the electrical shift converter 400 is on the driver board, the shift register is on the panel, the electrical shift converter 400 sends CLK to the shift register to complete the drive, thereby saving Gate
  • the IC structure further reduces the length of the frame. Therefore, the potential boosting unit 110 in the gate driving circuit 100 can be used as the electric displacement converter 400 alone, or the potential boosting unit 110, the current detection unit 130, the switching unit 140, and the control unit 120 can be integrated. In the electric displacement converter 400, the length of the frame is further compressed.
  • the second method is adopted, that is, the potential increase unit 110, the current detection unit 130, the switching unit 140, and the control unit 120 are integrated in the electric displacement converter 400. .
  • the present application also proposes a display device, which includes an electric displacement converter 400.
  • a display device which includes an electric displacement converter 400.
  • the electric displacement converter 400 For a specific structure of the electric displacement converter 400, refer to the foregoing embodiments. Since the display device adopts all the technical solutions of all the embodiments described above, at least All the technical effects brought by the technical solutions of the foregoing embodiments are not repeated here one by one.

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Abstract

一种栅极驱动电路（100）、电位移转器（400）和显示装置，其中，栅极驱动电路（100）包括电位提升单元（110）、电开关元（140）、电流检测单元（130）及控制单元（120），电位提升单元（110），设置为将时序控制器（200）输出的时钟信号进行电位提升后分为两路时钟信号组，并对应输出至显示面板的两组移位寄存器（310、320），电开关元（140），设置为控制时钟信号组输出或停止输出；电流检测单元（130），设置为分别检测两路时钟信号组的每一子时钟信号的输出电流；控制单元（120），设置为将多个电流信号对应的电流值与预设电流阈值分别比较，当其中一路时钟信号组中的任一子时钟信号的电流值小于预设电流阈值时，输出控制信号至电开关元（140）以控制电开关元（140）切断该路时钟信号组的输出。

Description

栅极驱动电路、电位移转器及显示装置
技术领域
本申请涉及显示面板技术领域，特别涉及一种栅极驱动电路、电位移转器及显示装置。
背景技术
随着大众对电视窄边框的需求越来越强烈，一种新型的GOA（Gate driver on Array.阵列基板上栅驱动集成）驱动架构正越来越受到欢迎。一般的显示面板要将Gate IC（门驱动IC）绑定在面板上，而Gate IC的尺寸限制了边框的进一步缩窄。但近些年随着新型GOA技术的问世，逐渐代替了传统的驱动方式，GOA电路是将原本的Gate IC拆分成电位移转器（level shifter IC）和移位寄存器（shift register）两部分，电位移转器做在驱动板上，移位寄存器在了面板上，电位移转器输送CLK给移位寄存器完成驱动，从而节省Gate IC结构，进一步压缩边框长度。
GOA制程会在面板的左右两侧都制作移位寄存器，实现双边驱动，但是由于制程的稳定性及使用过程中可能会造成某一侧的移位寄存器损坏造成显示异常，由于左右侧均有可能受到损伤，所以无法固定一种驱动方式，那么目前只能开发单独驱动左侧，单独驱动右侧，以及左右侧都正常驱动的三个驱动板，然后再根据实际损伤状况去被动地选择对应的驱动板，成本高昂且费时费力。
发明内容
本申请的主要目的是提供一种栅极驱动电路，旨在提高驱动板的兼容性，降低设计成本。
为实现上述目的，本申请提出的一种栅极驱动电路，该栅极驱动电路包括：
电位提升单元，设置为将时序控制器输出的时钟信号进行电位提升后分为两路时钟信号组，并对应输出至显示面板的两组移位寄存器，以驱动显示面板工作；两路时钟信号组分别包括至少一个子时钟信号；
开关单元，串接在所述电位提升单元与显示面板两端的移位寄存器之间，设置为根据接收到的控制信号对应导通或者关断，以控制所述时钟信号组输出或者停止输出；
电流检测单元，串接在所述电位提升单元与所述开关单元之间，或者串接在所述开关单元与显示面板两端的移位寄存器之间，设置为分别检测两路所述时钟信号组的每一子时钟信号的输出电流，并将多个电流信号反馈至控制单元；以及
控制单元，设置为接收所述电流检测单元输出的多个所述电流信号，并将多个所述电流信号对应的电流值与预设电流阈值分别比较，当其中一路时钟信号组中的任一子时钟信号的电流值小于所述预设电流阈值时，输出控制信号至所述开关单元以控制所述开关单元切断该路时钟信号组的输出。
可选地，所述电位提升单元的信号输入端供与所述时序控制器的信号输出端连接，所述电位提升单元的信号输出端流与所述电检测单元的信号输入端连接，所述电流检测单元的信号输出端与所述开关单元的信号输入端连接，所述开关单元的第一信号输出端与所述显示面板的第一组移位寄存器的信号输入端连接，所述开关单元的第二信号输出端与所述显示面板的第二组移位寄存器的信号输入端连接，所述电位提升单元的受控端、所述电流检测单元的信号输出端及所述开关单元的受控端均与所述控制单元的信号端连接。
可选地，所述开关单元包括第一子开关单元及第二子开关单元，所述电位提升单元分别经所述第一子开关单元及所述第二子开关单元输出两路相同的时钟信号组至显示面板两端的移位寄存器，所述第一子开关单元的受控端及所述第二子开关单元的受控端均与所述控制单元的控制端连接。
可选地，所述开关单元包括多个子开关单元，所述每一子时钟信号经每一子开关单元输出至所述移位寄存器，每一所述子开关单元的受控端分别与所述控制单元的控制端连接。
可选地，设置在电流检测单元与第一组移位寄存器之间的多个子开关单元联动，设置在电流检测单元与第二组移位寄存器之间的多个子开关单元联动。
可选地，每一所述子开关单元为金属-氧化物半导体场效应管。
可选地，每一所述子开关单元为三极管。
可选地，所述电流检测单元包括多个子电流检测单元，每一所述子电流检测单元分别检测每一所述子时钟信号的电流，并将电流信号分别反馈至所述控制单元。
本申请还提出一种电位移转器，包括如上所述的栅极驱动电路，所述栅极驱动电路包括：
电位提升单元，设置为将时序控制器输出的时钟信号进行电位提升后分为两路时钟信号组，并对应输出至显示面板上的两组移位寄存器，以驱动显示面板工作；两路时钟信号组分别包括至少一个子时钟信号；
开关单元，串接在所述电位提升单元与显示面板两端的移位寄存器之间，设置为根据接收到的控制信号对应导通或者关断，以控制所述时钟信号组输出或者停止输出；
电流检测单元，串接在所述电位提升单元与所述开关单元之间，或者串接在所述开关单元与显示面板两端的移位寄存器之间，设置为分别检测两路所述时钟信号组的每一子时钟信号的输出电流，并将多个电流信号反馈至控制单元；以及
控制单元，设置为接收所述电流检测单元输出的多个所述电流信号，并将多个所述电流信号对应的电流值与预设电流阈值分别比较，当其中一路时钟信号组中的任一子时钟信号的电流值小于所述预设电流阈值时，输出控制信号至所述开关单元以控制所述开关单元切断该路时钟信号组的输出。
可选地，所述电位提升单元的信号输入端供与所述时序控制器的信号输出端连接，所述电位提升单元的信号输出端与所述电流检测单元的信号输入端连接，所述电流检测单元的信号输出端与所述开关单元的信号输入端连接，所述开关单元的第一信号输出端与所述显示面板的第一组移位寄存器的信号输入端连接，所述开关单元的第二信号输出端与所述显示面板的第二组移位寄存器的信号输入端连接，所述电位提升单元的受控端、所述电流检测单元的信号输出端及所述开关单元的受控端均与所述控制单元的信号端连接。
可选地，所述开关单元包括第一子开关单元及第二子开关单元，所述电位提升单元分别经所述第一子开关单元及所述第二子开关单元输出两路相同的时钟信号组至显示面板两端的移位寄存器，所述第一子开关单元的受控端及所述第二子开关单元的受控端均与所述控制单元的控制端连接。
可选地，所述开关单元包括多个子开关单元，所述每一子时钟信号经每一所述子开关单元输出至所述移位寄存器，每一所述子开关单元的受控端分别与所述控制单元的控制端连接。
可选地，设置在电流检测单元与第一组移位寄存器之间的多个子开关单元联动，设置在电流检测单元与第二组移位寄存器之间的多个子开关单元联动。
可选地，每一所述子开关单元为金属-氧化物半导体场效应管。
可选地，每一所述子开关单元为三极管。
可选地，所述电流检测单元包括多个子电流检测单元，每一所述子电流检测单元分别检测每一所述子时钟信号的电流，并将电流信号分别反馈至所述控制单元。
可选地，所述电位提升单元、所述电流检测单元、所述开关单元及所述控制单元集成在所述电位移转器内。
本申请还提出一种显示装置，包括如上所述的电位移转器，所述电位移转器，包括所述栅极驱动电路，所述栅极驱动电路包括：
电位提升单元，设置为将时序控制器输出的时钟信号进行电位提升后分为两路时钟信号组，并对应输出至显示面板上的两组移位寄存器，以驱动显示面板工作；两路时钟信号组分别包括至少一个子时钟信号；
开关单元，串接在所述电位提升单元与显示面板两端的移位寄存器之间，设置为根据接收到的控制信号对应导通或者关断，以控制所述时钟信号组输出或者停止输出；
电流检测单元，串接在所述电位提升单元与所述开关单元之间，或者串接在所述开关单元与显示面板两端的移位寄存器之间，设置为分别检测两路所述时钟信号组的每一子时钟信号的输出电流，并将多个电流信号反馈至控制单元；以及
控制单元，设置为接收所述电流检测单元输出的多个所述电流信号，并将多个所述电流信号对应的电流值与预设电流阈值分别比较，当其中一路时钟信号组中的任一子时钟信号的电流值小于所述预设电流阈值时，输出控制信号至所述开关单元以控制所述开关单元切断该路时钟信号组的输出。
本申请技术方案通过采用电位提升单元、电流检测单元、开关单元及控制单元组成栅极驱动电路，电位提升单元将时序控制器输入的低压逻辑信号进行电位提升，并分为两路包括至少一个子时钟信号的时钟信号组输出至显示面板上的两个移位寄存器，从而双边驱动显示面板，电流检测单元检测每一路的时钟信号电流大小，然后反馈给控制单元，当显示面板上的其中一个移位寄存器出现损坏时，输出至该移位寄存器的时钟信号的电流异常，控制单元根据电流检测单元反馈的电流信号对应输出控制信号至开关单元，从而关断输出至该移位寄存器的时钟信号，实现单边驱动。从而动态匹配显示面板的两端移位寄存器的不同异常状态，提高了驱动板的兼容性。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请栅极驱动电路一实施例的功能模块示意图；
图2为本申请栅极驱动电路另一实施例的功能模块示意图；
图3为本申请栅极驱动电路又一实施例的功能模块示意图；
图4为本申请电位移转器一实施例的功能模块示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，在本申请中涉及“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，全文中出现的“和/或”的含义为：包括三个并列的方案，以“A/B”为例，包括A方案，或B方案，或A和B同时满足的方案，另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请栅极驱动电路100设置为驱动小尺寸显示面板，对于小尺寸显示面板，栅极线的负载较小，因此，可采用双边驱动或者单边驱动，如图1所示，图1为本申请栅极驱动电路一实施例的功能模块示意图，该栅极驱动电路100包括：
电位提升单元110，设置为将时序控制器200输出的时钟信号进行电位提升后分为两路时钟信号组，并对应输出至显示面板的两组移位寄存器，以驱动显示面板工作；两路时钟信号组分别包括至少一个子时钟信号；
开关单元140，串接在所述电位提升单元110与显示面板两端的移位寄存器之间，设置为根据接收到的开关控制信号对应导通或者关断，以控制所述时钟信号组输出或者停止输出；
电流检测单元130，串接在所述电位提升单元110与所述开关单元140之间，或者串接在所述开关单元140与显示面板两端的移位寄存器之间，设置为分别检测两路所述时钟信号组的每一子时钟信号的输出电流，并将多个电流信号反馈至控制单元120；以及
控制单元120，设置为接收所述电流检测单元130输出的多个所述电流信号，并将多个所述电流信号对应的电流值与预设电流阈值分别比较，当其中一路时钟信号组中的任一子时钟信号的电流值小于所述预设电流阈值时，输出控制信号至所述开关单元140以控制所述开关单元140切断该路时钟信号组的输出。
本实施例中，所述显示面板包括但不限于液晶显示面板、有机发光二极管显示面板、场发射显示面板、等离子显示面板、曲面型面板，所述液晶面板包括薄膜晶体管液晶显示面板、TN(Twisted Nematic，扭曲向列型)面板、VA(Vertical Alignment，垂直配向技术)类面板、IPS(In-Plane Switching，平面转换)面板等。设置在显示面板两端的移位寄存器接收栅极驱动电路100输出的多个时钟信号并驱动显示面板内部的像素工作，两组移位寄存器分别接收的时钟信号相同，并且每一时钟信号比前一时钟信号提前一定周期，假设栅极驱动电路100输出至两组移位寄存器的时钟信号分别均有CLK1~CLK4，则CLK2比CLK1提前1/4周期，CLK3比CLK2提前1/4周期，栅极驱动电路100还可根据需求分别输出6个子时钟信号或者8个子时钟信号，采用更多的CLK信号可以减小每一条信号线的负载，同时可以降低功耗，但同时也会增加电路的管脚数，在实际设计中，可以根据具体产品的边框宽度、产品尺寸、集成电路设计和分辨率等条件选择输出的时钟信号的数量。
电位提升单元110接收时序控制器200输出的低电平时钟信号，并在控制单元120的调制下对时钟信号进行电平转换，将低电平时钟信号进行电位提升后输出两路相同的时钟信号组，每一时钟信号组包括至少一个子时钟信号，子时钟信号数量可根据需求对应设置，例如4个、6个或者8个等，电位提升单元110输出的时钟信号组流经电流检测单元130、开关单元140输出至显示面板两端的两组移位寄存器，电流检测单元130分别检测每一子时钟信号的电流大小，电流检测电路可选择采样电阻或者互感器等电路进行电流检测，开关单元140可选择多个具有开关能力的开关元器件或者开关电路，例如继电器、场效应管以及三极管等等，可选择一个开关控制一路时钟信号组的信号输出，或者一个开关控制一个子时钟信号的输出，开关的受控端与控制单元120的控制端连接，根据控制单元120输出的控制信号进行导通或者关断，控制单元120可选择微处理器、可编程控制的单片机等，还可在外围搭建比较器电路进行电压比较，具体可根据实际情况进行具体设置，在此，不做具体限制。
在一可选实施例中，所述电位提升单元110的信号输入端供与所述时序控制器200的信号输出端连接，所述电位提升单元110的信号输出端流与所述电检测单元的信号输入端连接，所述电流检测单元130的信号输出端与所述开关单元140的信号输入端连接，所述开关单元140的第一信号输出端与所述显示面板的第一组移位寄存器310的信号输入端连接，所述开关单元140的第二信号输出端与所述显示面板的第二组移位寄存器320的信号输入端连接，所述电位提升单元110的受控端、所述电流检测单元130的信号输出端及所述开关单元140的受控端均与所述控制单元120的信号端连接。
需要说明的是，电流检测单元130可设置在开关单元140的前端或者后端，可根据驱动板的位置具体设置，在此不做具体限制，本实施例中，电流检测单元130设置在开关单元140的前端，开关单元140的信号输出端分别与两组移位寄存器的信号输入端连接，在显示面板两端的移位寄存器均正常时，实现双边驱动，在其中一组移位寄存器出现损坏时，对应输出至该组移位寄存器的子时钟信号存在全部或者单个无法正常输入，进而造成驱动异常，电流检测单元130检测时钟信号的大小，并将各个子时钟信号的电流值反馈至控制单元120，控制单元120根据电流值的大小与预设电流阈值比较，判断该组移位寄存器处于异常，并输出控制信号至开关单元140，开关单元140内部的子开关单元140对应导通或者关断动作，将输出至该组移位寄存器的时钟信号组切断，实现单边驱动，如果两组移位寄存器均出现损坏，则将两路时钟信号组均切断，并对移位寄存器进行修复或者替换。
栅极驱动电路100可设置为驱动小尺寸显示面板，在显示面板两端的移位寄存器均正常时，双边驱动，在其中一组移位寄存器出现异常时，自动切换至单边驱动，栅极驱动电路100安装在驱动板上，可驱动左侧、右侧以及左右侧都正常驱动，无需设计三种驱动板，从而提高驱动板的兼容性，降低设计成本。
本申请技术方案通过采用电位提升单元110、电流检测单元130、开关单元140及控制单元120组成栅极驱动电路100，电位提升单元110将时序控制器200输入的低压逻辑信号进行电位提升，并分为两路包括至少一个子时钟信号的时钟信号组输出至显示面板上的两组移位寄存器，从而双边驱动显示面板，电流检测单元130检测每一路的时钟信号电流大小，然后反馈给控制单元120，当显示面板上的其中一组移位寄存器出现损坏时，输出至该组移位寄存器的时钟信号的电流异常，控制单元120根据电流检测单元130反馈的电流信号对应输出控制信号至开关单元140，从而关断输出至该组移位寄存器的时钟信号，实现单边驱动。从而动态匹配显示面板的两端移位寄存器的不同异常状态，提高驱动板的兼容性。
在一可选实施例中，如图2所示，图2为本申请栅极驱动电路另一实施例的功能模块示意图，所述开关单元140包括第一子开关单元141及第二子开关单元142，所述电位提升单元110分别经所述第一子开关单元141及所述第二子开关单元142输出两路相同的时钟信号组至显示面板两端的移位寄存器，所述第一子开关单元141的受控端及所述第二子开关单元142的受控端均与所述控制单元120的控制端连接。
在本实施例中，两路时钟信号组分别经第一子开关单元141及第二子开关单元142输出至对应的移位寄存器中，实现双边驱动，第一子开关单元141和第二子开关单元142同时控制多个子时钟信号的输出，第一子开关单元141及第二子开关单元142初始时保持导通状态，当两组移位寄存器其中一组出现损坏时，例如第一组移位寄存器310，输出至第一组移位寄存器310的时钟信号组的电流出现异常，可能是其中一个子时钟信号电流过小，或者其中多个子时钟信号电流过小，当其中任一子时钟信号的电流值小于预设电流阈值时，控制单元120则输出控制信号至第一子开关单元141，第一子开关单元141关断，从而切断了输出至第一组移位寄存器310的至少一个子时钟信号，从而形成单边驱动，同理，当第二组移位寄存器320出现损坏时，则关断第二子开关单元142。
第一子开关单元141及第二子开关单元142可采用多输入多输出的继电器或者其它开关元器件，具体可根据实际情况进行设计，在此不做具体限制。
在一可选实施例中，如图3所示，图3为本申请栅极驱动电路又一实施例的功能模块示意图，所述开关单元140包括多个子开关单元140，所述每一子时钟信号经每一子开关单元140输出至移位寄存器，每一所述子开关单元140的受控端分别与所述控制单元120的控制端连接。
在本实施例中，开关单元140包括多个子开关单元140，例如K1~K8，子开关单元140与电位提升单元110输出的时钟信号一一对应，每一子开关单元140串接在电流检测单元130与移位寄存器之间，设置为控制每一子时钟信号的输出，并且设置在电流检测单元130与第一组移位寄存器310之间的多个子开关单元140联动，例如图3中的K1~K4同时导通或者关断，设置在电流检测单元130与第二组移位寄存器320之间的多个子开关单元140联动，例如图3中的K5~K8同时导通或者关断，从而实现时钟信号组的多个子时钟信号的同步控制，并在控制单元120的控制下实现双边驱动与单边驱动的自动切换。
进一步地，每一所述子开关单元为金属-氧化物半导体场效应管。
在开关单元140包括数量与对应的子时钟信号数量相同的子开关单元时，每一子开关单元可采用金属-氧化物半导体场效应管，金属-氧化物半导体场效应管的栅极为子开关单元的受控端，并与控制单元120的控制端连接，金属-氧化物半导体场效应管的源极或者漏极与电流检测单元130的信号输出端连接，金属-氧化物半导体场效应管的漏极或者源极与第一组移位寄存器310或者第二组移位寄存器320连接，金属-氧化物半导体场效应管可选用N沟道金属-氧化物半导体场效应管或者P沟道金属-氧化物半导体场效应管，当选用N沟道金属-氧化物半导体场效应管，控制单元120输出高电平至金属-氧化物半导体场效应管以使其导通，输出低电平至金属-氧化物半导体场效应管以使其关断，当选用P沟道金属-氧化物半导体场效应管，控制单元120输出低电平至金属-氧化物半导体场效应管以使其导通，输出高电平至金属-氧化物半导体场效应管以使其关断，金属-氧化物半导体场效应管的类型可灵活选择，不做具体限制。
进一步地，每一所述子开关单元为三极管。
在开关单元140包括数量与子时钟信号数量相同的子开关单元时，每一子开关单元还可采用三极管，三极管的基极为子开关单元的受控端并与控制单元120的控制端连接，三极管的集电极或者发射极与电流检测单元130的信号输出端连接，三极管的发射极或者集电极与对应的移位寄存器的信号输入端连接，三极管可选择NPN三极管或者PNP三极管，当选择NPN三极管时，控制单元120输出高电平至NPN三极管以控制其导通以及输出低电平以使其关断，对应地，当选择PNP三极管时，控制单元120输出低电平至PNP三极管以控制其导通以及输出高电平以使其关断，三极管的类型可灵活选择，不做具体限制。
在一可选实施例中，所述电流检测单元130包括多个子电流检测单元，每一所述子电流检测单元分别检测每一所述子时钟信号的电流，并将电流信号分别反馈至所述控制单元120。
需要说明的是，多个子电流检测单元设置为检测电位提升单元110输出的子时钟信号，并且子电流检测单元的数量与子时钟信号的数量相等且一一对应，每一子电流检测单元检测对应的子时钟信号并将电流信号反馈至控制单元120，子电流检测单元可采用电流互感器或者采样电阻等电路进行电流检测，可根据具体情况进行设置。
进一步地，如图4所示，图4为本申请电位移转器一实施例的功能模块示意图，本申请还提出一种电位移转器400，包括如上所述的栅极驱动电路100。
需要说明的是，GOA电路是将原本的Gate IC拆分成电位移转器400（level shifter IC）和移位寄存器（shift register）两部分，电位移转器400做在驱动板上，移位寄存器在了面板上，电位移转器400输送CLK给移位寄存器完成驱动，从而节省Gate IC结构，进一步压缩边框长度，因此，栅极驱动电路100中的电位提升单元110单独可作为电位移转器400，或者将电位提升单元110、电流检测单元130、开关单元140以及控制单元120集成在电位移转器400内，进一步压缩边框长度，本实施例中，采用第二种方式，即电位提升单元110、电流检测单元130、开关单元140以及控制单元120集成在电位移转器400内。
本申请还提出一种显示装置，该显示装置包括电位移转器400，该电位移转器400的具体结构参照上述实施例，由于本显示装置采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有技术效果，在此不再一一赘述。
以上所述仅为本申请的优选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (18)

  1. 一种栅极驱动电路，包括：
    电位提升单元，设置为将时序控制器输出的时钟信号进行电位提升后分为两路时钟信号组，并对应输出至显示面板上的两组移位寄存器，以驱动显示面板工作；两路时钟信号组分别包括至少一个子时钟信号；
    开关单元，串接在所述电位提升单元与显示面板两端的移位寄存器之间，设置为根据接收到的控制信号对应导通或者关断，以控制所述时钟信号组输出或者停止输出；
    电流检测单元，串接在所述电位提升单元与所述开关单元之间，或者串接在所述开关单元与显示面板两端的移位寄存器之间，设置为分别检测两路所述时钟信号组的每一子时钟信号的输出电流，并将多个电流信号反馈至控制单元；以及
    控制单元，设置为接收所述电流检测单元输出的多个所述电流信号，并将多个所述电流信号对应的电流值与预设电流阈值分别比较，当其中一路时钟信号组中的任一子时钟信号的电流值小于所述预设电流阈值时，输出控制信号至所述开关单元以控制所述开关单元切断该路时钟信号组的输出。
  2. 如权利要求1所述的栅极驱动电路，其中，所述电位提升单元的信号输入端供与所述时序控制器的信号输出端连接，所述电位提升单元的信号输出端与所述电流检测单元的信号输入端连接，所述电流检测单元的信号输出端与所述开关单元的信号输入端连接，所述开关单元的第一信号输出端与所述显示面板的第一组移位寄存器的信号输入端连接，所述开关单元的第二信号输出端与所述显示面板的第二组移位寄存器的信号输入端连接，所述电位提升单元的受控端、所述电流检测单元的信号输出端及所述开关单元的受控端均与所述控制单元的信号端连接。
  3. 如权利要求1所述的栅极驱动电路，其中，所述开关单元包括第一子开关单元及第二子开关单元，所述电位提升单元分别经所述第一子开关单元及所述第二子开关单元输出两路相同的时钟信号组至显示面板两端的移位寄存器，所述第一子开关单元的受控端及所述第二子开关单元的受控端均与所述控制单元的控制端连接。
  4. 如权利要求1所述的栅极驱动电路，其中，所述开关单元包括多个子开关单元，所述每一子时钟信号经每一所述子开关单元输出至所述移位寄存器，每一所述子开关单元的受控端分别与所述控制单元的控制端连接。
  5. 如权利要求4所述的栅极驱动电路，其中，设置在电流检测单元与第一组移位寄存器之间的多个子开关单元联动，设置在电流检测单元与第二组移位寄存器之间的多个子开关单元联动。
  6. 如权利要求4所述的栅极驱动电路，其中，每一所述子开关单元为金属-氧化物半导体场效应管。
  7. 如权利要求4所述的栅极驱动电路，其中，每一所述子开关单元为三极管。
  8. 如权利要求1所述的栅极驱动电路，其中，所述电流检测单元包括多个子电流检测单元，每一所述子电流检测单元分别检测每一所述子时钟信号的电流，并将电流信号分别反馈至所述控制单元。
  9. 一种电位移转器，其中，包括所述栅极驱动电路，所述栅极驱动电路包括：
    电位提升单元，设置为将时序控制器输出的时钟信号进行电位提升后分为两路时钟信号组，并对应输出至显示面板上的两组移位寄存器，以驱动显示面板工作；两路时钟信号组分别包括至少一个子时钟信号；
    开关单元，串接在所述电位提升单元与显示面板两端的移位寄存器之间，设置为根据接收到的控制信号对应导通或者关断，以控制所述时钟信号组输出或者停止输出；
    电流检测单元，串接在所述电位提升单元与所述开关单元之间，或者串接在所述开关单元与显示面板两端的移位寄存器之间，设置为分别检测两路所述时钟信号组的每一子时钟信号的输出电流，并将多个电流信号反馈至控制单元；以及
    控制单元，设置为接收所述电流检测单元输出的多个所述电流信号，并将多个所述电流信号对应的电流值与预设电流阈值分别比较，当其中一路时钟信号组中的任一子时钟信号的电流值小于所述预设电流阈值时，输出控制信号至所述开关单元以控制所述开关单元切断该路时钟信号组的输出。
  10. 如权利要求9所述的电位移转器，其中，所述电位提升单元的信号输入端供与所述时序控制器的信号输出端连接，所述电位提升单元的信号输出端与所述电流检测单元的信号输入端连接，所述电流检测单元的信号输出端与所述开关单元的信号输入端连接，所述开关单元的第一信号输出端与所述显示面板的第一组移位寄存器的信号输入端连接，所述开关单元的第二信号输出端与所述显示面板的第二组移位寄存器的信号输入端连接，所述电位提升单元的受控端、所述电流检测单元的信号输出端及所述开关单元的受控端均与所述控制单元的信号端连接。
  11. 如权利要求9所述的电位移转器，其中，所述开关单元包括第一子开关单元及第二子开关单元，所述电位提升单元分别经所述第一子开关单元及所述第二子开关单元输出两路相同的时钟信号组至显示面板两端的移位寄存器，所述第一子开关单元的受控端及所述第二子开关单元的受控端均与所述控制单元的控制端连接。
  12. 如权利要求9所述的电位移转器，其中，所述开关单元包括多个子开关单元，所述每一子时钟信号经每一所述子开关单元输出至所述移位寄存器，每一所述子开关单元的受控端分别与所述控制单元的控制端连接。
  13. 如权利要求12所述的电位移转器，其中，设置在电流检测单元与第一组移位寄存器之间的多个子开关单元联动，设置在电流检测单元与第二组移位寄存器之间的多个子开关单元联动。
  14. 如权利要求12所述的电位移转器，其中，每一所述子开关单元为金属-氧化物半导体场效应管。
  15. 如权利要求12所述的电位移转器，其中，每一所述子开关单元为三极管。
  16. 如权利要求9所述的电位移转器，其中，所述电流检测单元包括多个子电流检测单元，每一所述子电流检测单元分别检测每一所述子时钟信号的电流，并将电流信号分别反馈至所述控制单元。
  17. 如权利要求9所述的电位移转器，其中，所述电位提升单元、所述电流检测单元、所述开关单元及所述控制单元集成在所述电位移转器内。
  18. 一种显示装置，其中，包括所述电位移转器，所述电位移转器，包括所述栅极驱动电路，所述栅极驱动电路包括：
    电位提升单元，设置为将时序控制器输出的时钟信号进行电位提升后分为两路时钟信号组，并对应输出至显示面板上的两组移位寄存器，以驱动显示面板工作；两路时钟信号组分别包括至少一个子时钟信号；
    开关单元，串接在所述电位提升单元与显示面板两端的移位寄存器之间，设置为根据接收到的控制信号对应导通或者关断，以控制所述时钟信号组输出或者停止输出；
    电流检测单元，串接在所述电位提升单元与所述开关单元之间，或者串接在所述开关单元与显示面板两端的移位寄存器之间，设置为分别检测两路所述时钟信号组的每一子时钟信号的输出电流，并将多个电流信号反馈至控制单元；以及
    控制单元，设置为接收所述电流检测单元输出的多个所述电流信号，并将多个所述电流信号对应的电流值与预设电流阈值分别比较，当其中一路时钟信号组中的任一子时钟信号的电流值小于所述预设电流阈值时，输出控制信号至所述开关单元以控制所述开关单元切断该路时钟信号组的输出。
PCT/CN2018/115121 2018-09-13 2018-11-13 栅极驱动电路、电位移转器及显示装置 WO2020052047A1 (zh)

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