WO2020051832A1

WO2020051832A1 - Electrostatic discharge protection circuit and integrated circuit chip

Info

Publication number: WO2020051832A1
Application number: PCT/CN2018/105486
Authority: WO
Inventors: 张�浩
Original assignee: 深圳市汇顶科技股份有限公司
Priority date: 2018-09-13
Filing date: 2018-09-13
Publication date: 2020-03-19
Also published as: CN109314388A; CN109314388B

Abstract

The present application relates to the technical field of electronics, and provided thereby are an electrostatic discharge protection circuit and an integrated circuit chip. The electrostatic discharge protection circuit comprises: a field-effect transistor trigger module, a voltage-dividing module and a discharge module (103) that are connected in parallel between a power supply pin and a ground pin; the voltage-dividing module comprises a first voltage-dividing unit (1021) and a second voltage-dividing unit (1022); the first voltage-dividing unit and the second voltage-dividing unit are connected in series, and the connection point serves as an output end of the voltage-dividing module; an output end of the field-effect transistor trigger module is connected to the output end of the voltage-dividing module; the output end of the voltage-dividing module is connected to an input end of the discharge module; when the power supply pin experiences an electrostatic attack, the field-effect transistor trigger module is turned on, the first voltage-dividing unit is short circuited, the voltage at the output end of the voltage-dividing module is pulled up to a high level, and the discharge module is turned on and discharges static electricity at the power supply pin. The present application may reduce the layout area of an electrostatic discharge circuit and attain stronger electrostatic discharge capabilities.

Description

Electrostatic discharge protection circuit and integrated circuit chip

Technical field

The present application relates to the field of electronic technology, and in particular, to an electrostatic discharge protection circuit and an integrated circuit chip.

Background technique

During the production, packaging, testing, and transportation of integrated circuit chips, static discharge events of varying degrees will occur. Electrostatic discharge is a transient process in which a large amount of electric charge is poured into an integrated circuit from the outside to the inside of the integrated circuit when it is floating. In this process, it is easy to cause the failure of the integrated circuit chip.

The inventor of the present patent application has found that a typical electrostatic discharge protection circuit in the prior art is shown in FIG. 1 and includes a capacitor C1, a capacitor C3, a resistor R1, and field effect transistors M1, M2, M3, M4, M5, M6, and M7. , M8, and M9. During normal operation, VDDH at the power supply pins is slowly powered on, GND is at 0 potential, M5, M6, M7, M8, and M9 provide the VDDH to GND voltage division, and VM is the intermediate potential obtained after VDDH voltage division (VM equals 0.5VDDH) ), VG_ND is low, M2 is on, M1 is off, there is no leakage from VDDH to GND, and the potential between VM and VDDH is not too high to break through M2. During the VDDH electrostatic attack at the power pin, VDDH increases sharply, the power pin is at a high potential, the VM potential is pulled up under the coupling of C3, and the capacitor C1 is slowly charged through the resistor R1, and VG_ND is pulled to VM , M1 and M2 are turned on at the same time to achieve electrostatic discharge at VDDH. Among them, before the upper plate of C1 is charged to a high potential, VG_ND is always at the same high potential as VM, and static electricity is discharged from VDDH to GND through M1 and M2. When the upper plate of C1 is charged to a high potential, VG_ND is pulled to GND, at this time M1 is turned off, and the static discharge path is disconnected.

It is not difficult to see that the VM in the above circuit is coupled by C3 to a high level as close to VDDH as possible. In order to achieve the highest discharge capacity of M1 and M2, it is necessary to make VM equal to VDDH, but under this condition, the size of M2 is larger, the required capacitance of capacitor C3 is larger, and the size of C3 is larger, so that the layout area of the entire circuit It is very large, and it is easy to cause waste of chip area.

Summary of the Invention

The purpose of some embodiments of the present application is to provide an electrostatic discharge protection circuit and an integrated circuit chip, which aim to reduce the layout area of the electrostatic discharge circuit and obtain a stronger electrostatic discharge capability.

An embodiment of the present application provides an electrostatic discharge protection circuit, including a field effect tube triggering module, a voltage dividing module, and a bleeding module connected in parallel between a power pin and a ground pin; wherein the voltage dividing module includes a first A voltage dividing unit and a second voltage dividing unit, the first voltage dividing unit and the second voltage dividing unit are connected in series, and the connection point of the first voltage dividing unit and the second voltage dividing unit is used as an output terminal of the voltage dividing module;

The output of the FET trigger module is connected to the output of the voltage divider module;

The output of the voltage divider module is connected to the input of the bleeder module;

The FET trigger module is turned on when the power pin is subjected to electrostatic attack, the first voltage dividing unit is shorted, the voltage of the output terminal of the voltage dividing module is pulled up to a high level, the bleeder module is turned on and the power pin is discharged. Of static electricity.

An embodiment of the present application further provides an integrated circuit chip including the above-mentioned electrostatic discharge protection circuit.

Compared with the prior art, the embodiment of the present application provides a field effect tube triggering module in the electrostatic discharge protection circuit to replace the capacitor C3 in the prior art. The field effect tube triggering module is directly guided when the power pin is subjected to electrostatic attack. The output terminal voltage of the voltage-dividing module is pulled up to a high level. At this time, the bleeder module is turned on, and a point of static electricity at the power pin is discharged to the ground through the bleeder module. Among them, because the field-effect transistor trigger module is directly turned on, the voltage at the output end of the voltage-dividing module can be pulled up to be equal to the voltage at the power supply pin, without the need for coupling through capacitors. Capacity, and reduce the overall layout area of the electrostatic discharge circuit.

In addition, the FET trigger module specifically includes: a detection unit and a FET; the detection unit is connected between the power pin and the ground pin, and the output end of the detection unit is connected to the gate of the FET; The source is connected to the power pin, and the drain is used as the output terminal of the FET trigger module. Among them, when the power pin is electrostatically attacked, the output of the detection unit is low. This embodiment provides a specific implementation form of the FET trigger module, which increases the flexibility of the embodiments of the present application. In addition, the detection unit is used to ensure that the FET has no risk of overvoltage during static operation, and the FET trigger module is more reliable.

In addition, the detection unit specifically includes: a resistor and a capacitor; the resistor and the capacitor are connected in series between the power pin and the ground pin in sequence; wherein the connection end of the resistor and the capacitor serves as the output end of the detection unit. The structure of the detection unit provided in this embodiment is relatively simple.

In addition, the field-effect tube triggering module specifically includes a third voltage-dividing unit, a fourth voltage-dividing unit, a detection unit, a driving unit, and a field-effect tube; a first end of the third voltage-dividing unit is connected to a power pin, and a second end Connected to the first end of the fourth voltage division unit; the second end of the fourth voltage division unit is connected to the ground pin; the detection unit and the drive unit are connected in parallel between the power pin and the ground pin; the third voltage division unit The second end of the MOSFET is connected to the first input of the drive unit; the output of the detection unit is connected to the second input of the drive unit; the gate of the FET is connected to the output of the drive unit, and the source is connected to the power pin The drain is used as the output terminal of the FET trigger module. When the power pin is subjected to electrostatic attack, the second terminal of the third voltage dividing unit is low, and the output of the detection unit is high. The output is low. This embodiment provides a specific implementation form of the FET trigger module, which increases the flexibility of the embodiments of the present application. In addition, the detection unit and the driving unit are used to ensure that the FET has no risk of overvoltage during static operation, and the FET trigger module is more reliable.

In addition, the detection unit specifically includes: a capacitor and a resistor; the capacitor and the resistor are connected in series between the power pin and the ground pin in sequence; wherein the connection end of the capacitor and the resistance is used as the output terminal of the detection unit. The structure of the detection unit provided in this embodiment is relatively simple.

In addition, the driving unit specifically includes: a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, and a fourth field-effect transistor; the gate of the first field-effect transistor is connected to the output terminal of the detection unit, and the source and The ground pin is connected, the drain is connected to the source of the second FET; the gate of the second FET is connected to the second end of the third voltage division unit, and the drain is connected to the drain of the third FET ; The source of the third FET is connected to the power pin, the gate is connected to the source of the fourth FET; the gate of the fourth FET is connected to the second end of the third voltage-dividing unit, and the drain Connected to the output of the detection unit. This embodiment provides a specific implementation form of the driving unit, which increases the flexibility of the embodiments of the present application. In addition, the driving unit is composed of a plurality of field effect transistors, and the layout area of the driving unit is small.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments are exemplified by the pictures in the accompanying drawings. These exemplary descriptions do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the drawings in the drawings do not constitute a limitation on scale.

1 is a circuit diagram of an electrostatic discharge protection circuit in the prior art;

2 is a schematic diagram of an electrostatic discharge protection circuit in the first embodiment of the present application;

FIG. 3 is a schematic diagram of an electrostatic discharge protection circuit in a second embodiment of the present application.

detailed description

In order to make the purpose, technical solution, and advantages of the present application clearer, some embodiments of the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application, and are not used to limit the application.

The first embodiment of the present application relates to an electrostatic discharge protection circuit, as shown in FIG. 2, including a field effect tube trigger module, a voltage division module, and a bleeder module connected in parallel between a power pin VDDH and a ground pin GND. 103. The voltage dividing module includes a first voltage dividing unit 1021 and a second voltage dividing unit 1022. The first voltage dividing unit 1021 and the second voltage dividing unit 1022 are connected in series, and the first voltage dividing unit 1021 and the second voltage dividing unit 1022. The connection point is used as the output of the voltage divider module.

Specifically, the output terminal of the field effect tube triggering module is connected to the output terminal of the voltage dividing module, and the output terminal of the voltage dividing module is connected to the input terminal of the bleeder module 103. Among them, the FET trigger module is turned on when the power pin VDDH is subjected to an electrostatic attack, the first voltage dividing unit 1021 is shorted, the output terminal voltage of the voltage dividing module is pulled up to a high level, and the bleeder module 103 is turned on and discharged. Discharge the static electricity at the pin VDDH. The specific structure of each functional module of the electrostatic discharge protection circuit in this embodiment is described below:

The field-effect transistor triggering module includes a detection unit 1011 and a field-effect transistor M10. The detection unit 1011 is connected between the power pin VDDH and the ground pin GND, and the output terminal of the detection unit 1011 is connected to the gate of the field effect transistor M10. The source of the MOSFET M10 is connected to the power pin VDDH, and the drain is used as the output terminal of the MOSFET trigger module.

The detection unit 1011 includes a resistor R2 and a capacitor C2. The resistor R2 and the capacitor C2 are connected in series between the power pin VDDH and the ground pin GND in order. The connection terminal of the resistor R2 and the capacitor C2 is used as the output terminal of the detection unit, that is, RC2_OUT is used as the output terminal.

The first voltage dividing unit 1021 may include field effect transistors M7, M8, and M9. The specific connection relationship may be as shown in FIG. 2: The source of M9 is connected to VDDH. The gate of M9 is connected to the drain and connected to the source of M8. The gate of M8 is connected to the drain and connected to the source of M7. The gate of M7 is connected to the drain, and is connected to the second voltage dividing unit 1022. The second voltage dividing unit 1022 may include field effect transistors M5 and M6. The specific connection relationship may be as shown in FIG. 2, that is, the gate of M7 is connected to the drain, and the gate and drain of M6 are connected, and the source of M6 The electrode is connected to the gate and drain of M5, and the source of M5 is connected to the ground pin GND.

The bleed module 103 includes a buffer unit, an inverter, a fifth field-effect transistor M1 and a sixth field-effect transistor M2. The buffer unit and the inverter are connected in parallel between the output terminal of the voltage dividing module and the ground pin GND. The output of the buffer unit is connected to the input of the inverter, the output of the inverter is connected to the gate of M1, the source of M1 is connected to the ground pin GND, and the drain is connected to the source of M2. The drain of M2 is connected to the power pin VDDH, and the gate is used as the input terminal of the bleeder module 103.

Among them, the buffer unit is an RC oscillation circuit, which is composed of a resistor R1 and a capacitor C1. One end of the resistor R1 is connected to the output end of the voltage dividing module, and the other end is connected to C1, and C1 is also connected to the ground pin GND. The inverter consists of field-effect transistors M3 and M4. The specific connection is shown in Figure 2.

The working principle of the electrostatic discharge circuit in this embodiment is explained below:

(1) VDDH has not been attacked by static electricity:

VDDH is slowly powered on. M5, M6, M7, M8, and M9 provide the voltage division from VDDH to GND. VM is the intermediate potential obtained after VDDH division. VM is equal to 0.5VDDH, and M2 is turned on. RC1_OUT is high, RC1_OUT is VG_ND via the inverter, VG_ND is low, M1 is off, there is no static current, and the bleeder module 103 is not turned on. At this time, RC2_OUT is high-level VDDH, M10 is in the off state, there is no quiescent current, and because the drain voltage of M10 is VM, there is no risk of overvoltage in M10.

(2) VDDH is subject to electrostatic attack:

The VDDH voltage increases sharply, and R2 and C2 in the detection unit 1011 are too late to respond, so RC2_OUT is low relative to VDDH, M10 is turned on, the first voltage dividing unit 1021 is shorted, and VM is pulled up to VDDH, M2 Continuity. At the same time, R1 and C1 in the buffer unit are too late to respond, so RC1_OUT is low level relative to VM, RC1_OUT gets VG_ND through the inverter, VG_ND is high level, and M1 is turned on. Since M1 and M2 are both on, that is, the bleeder module 103 is on, the static electricity at VDDH is discharged to GND through M1 and M2. When the plate on the capacitor C1 in the buffer unit is charged to a high level, M1 is turned off, and the bleed module 103 is not turned on again.

Compared with the prior art, in this embodiment, a field-effect transistor triggering module is provided in the electrostatic discharge protection circuit to replace the capacitor C3 in the prior art. The field-effect transistor triggering module directly conducts electricity when the power pin VDDH is subjected to an electrostatic attack. The output terminal voltage of the voltage dividing module is pulled up to a high level. At this time, the bleeder module 103 is turned on, and a point of static electricity at the power pin VDDH is discharged to the ground through the bleeder module 103. Among them, because the field-effect transistor trigger module is directly turned on, the voltage of the output terminal of the voltage-dividing module can be pulled up to be equal to the voltage at the power pin VDDH, and no coupling is required through the capacitor. Discharge capacity, and reduce the overall layout area of the electrostatic discharge circuit.

The second embodiment of the present application relates to an electrostatic discharge protection circuit, as shown in FIG. 3. The second embodiment is substantially the same as the first embodiment, and the main difference is that the implementation form of the field effect tube trigger module is different, which will be described in detail below:

In this embodiment, the field-effect transistor triggering module specifically includes a third voltage-dividing unit 1012, a fourth voltage-dividing unit 1013, a detection unit 1011, a driving unit 1014, and a field-effect tube M10. The first terminal of the third voltage dividing unit 1012 is connected to the power pin VDDH, the second terminal is connected to the first terminal of the fourth voltage dividing unit 1013, and the second terminal of the fourth voltage dividing unit 1013 is connected to the ground pin GND. The detection unit 1011 and the driving unit 1014 are both connected in parallel between the power pin VDDH and the ground pin GND. The second terminal of the third voltage dividing unit 1012 is connected to the first input terminal of the driving unit 1014, the output terminal of the detecting unit 1011 is connected to the second input terminal of the driving unit 1014, and the gate of the field effect tube M10 is connected to the driving unit 1014. The output terminal is connected, the source is connected to the power pin VDDH, and the drain is used as the output terminal of the FET trigger module. When the power pin VDDH is subjected to an electrostatic attack, the second terminal of the third voltage dividing unit 1012 is at a low level, the output terminal of the detection unit 1011 is at a high level, and the output terminal of the driving unit 1013 is at a low level. The specific structure of each functional module of the FET trigger module in this embodiment is described below:

The detection unit 1011 includes a capacitor C3 and a resistor R3. The capacitor C3 and the resistor R3 are connected in series between the power pin VDDH and the ground pin GND. The connection terminal of the capacitor C3 and the resistor R3 serves as an output terminal of the detection unit 1011.

The third voltage-dividing unit 1012 includes field-effect transistors M17, M18, and M19. The specific connection is shown in FIG. That is, the source of M19 is connected to VDDH. The gate of M19 is connected to the drain and is connected to the source of M18. The gate of M18 is connected to the drain and is connected to the source of M17. The gate of M17 is connected to the drain, and is connected to the second voltage dividing unit 1013. The second voltage dividing unit 1013 includes field effect tubes M15 and M16, and the specific connection is shown in FIG. 3. That is, the gate of M17 is connected to the gate and drain of M6, the source of M16 is connected to the gate and drain of M15, and the source of M15 is connected to the ground pin GND.

The driving unit 1014 includes a first field effect tube M11, a second field effect tube M12, a third field effect tube M13, and a fourth field effect tube M14. The gate of M11 is connected to the output terminal of detection unit 1011, the source is connected to the ground pin, and the drain is connected to the source of M12. The gate of M12 is connected to the second end of the third voltage dividing unit 1012, and the drain is connected to the drain of M13. The source of M13 is connected to the power pin VDDH, and the gate is connected to the source of M14. The gate of M14 is connected to the second terminal of the third voltage division unit 1012, and the drain is connected to the output terminal of the detection unit 1011.

(1) VDDH has not been attacked by static electricity.

VDDH powers up slowly. M5, M6, M7, M8, and M9 provide the voltage division from VDDH to GND. VM is the intermediate potential obtained after VDDH division. VM is equal to 0.5VDDH, VM is high, M2 is on, and RC2_OUT is low Level, M11 is off. Similarly, M15, M16, M17, M18, and M19 provide the voltage division from VDDH to GND, and VX is the intermediate potential obtained after VDDH division. VX is equal to 0.5VDDH, VX is high, and M14 and M12 are turned off. The gate of M13 is low level, M13 is turned on, the gate voltage of M10 is pulled to a high potential VDDH by M13, M10 is in the off state, and no leakage will occur in M10 and M11. Since VM is equal to 0.5VDDH and VM is high level, RC1_OUT is high level, RC1_OUT is VG_ND via the inverter, VG_ND is low level, M1 is turned off, there is no static current, and the bleeder module 103 is not turned on.

(2) VDDH is attacked by static electricity.

VDDH voltage increases sharply, RC2_OUT is high level, VX is equal to 0.5VDDH, VX is high level, M11, M12, M14 are turned on at the same time, so that the gate voltage of M10 is pulled to low level GND, and M10 is turned on, so that VM is pulled to VDDH and M2 is turned on. At the same time, R1 and C1 in the buffer unit are too late to respond, so RC1_OUT is low level relative to VM, RC1_OUT gets VG_ND through the inverter, VG_ND is high level, and M1 is turned on. Since M1 and M2 are both on, that is, the bleeder module 103 is on, the static electricity at VDDH is discharged to GND through M1 and M2. When the plate on the capacitor C1 in the buffer unit is charged to a high level, M1 is turned off, and the bleeder module 103 is not turned on again.

Compared with the prior art, in this embodiment, a field-effect transistor triggering module is provided in the electrostatic discharge protection circuit to replace the capacitor C3 in the prior art. The field-effect transistor triggering module directly conducts electricity when the power pin VDDH is subjected to an electrostatic attack. The output terminal voltage of the voltage dividing module is pulled up to a high level. At this time, the bleeder module 103 is turned on, and a point of static electricity at the power pin VDDH is discharged to the ground through the bleeder module 103. Among them, because the field-effect transistor trigger module is directly turned on, the voltage of the output terminal of the voltage-dividing module can be pulled up to be equal to the voltage at the power pin VDDH, without the need for coupling through the capacitor, so that the strong discharge of the electrostatic discharge circuit can be achieved. Discharge capacity, and reduce the overall layout area of the electrostatic discharge circuit.

The third embodiment of the present application relates to an integrated circuit chip, and the integrated circuit chip is provided with the electrostatic discharge protection circuit mentioned in the above embodiment.

Those of ordinary skill in the art can understand that the foregoing embodiments are specific embodiments for implementing the present application, and in practical applications, various changes can be made in form and details without departing from the spirit and range.

Claims

An electrostatic discharge protection circuit, comprising: a field effect tube triggering module, a voltage dividing module, and a bleeding module connected in parallel between a power pin and a ground pin; wherein the voltage dividing module includes a first A voltage division unit and a second voltage division unit, the first voltage division unit and the second voltage division unit are connected in series, and a connection point between the first voltage division unit and the second voltage division unit is taken as the Output of voltage dividing module;

An output terminal of the field effect tube triggering module is connected to an output terminal of the voltage dividing module;

An output terminal of the voltage dividing module is connected to an input terminal of the bleed module;

The field effect tube triggering module is turned on when the power pin is subjected to an electrostatic attack, the first voltage dividing unit is short-circuited, the output terminal voltage of the voltage dividing module is pulled up to a high level, and the bleed The module conducts and discharges static electricity at the power pins.
The electrostatic discharge protection circuit according to claim 1, wherein the field effect tube triggering module comprises: a detection unit and a field effect tube;

The detection unit is connected between the power pin and the ground pin, and the output terminal of the detection unit is connected to the gate of the field effect transistor;

A source of the field effect tube is connected to the power pin, and a drain is used as an output terminal of the field effect tube trigger module;

When the power pin is electrostatically attacked, the output terminal of the detection unit is at a low level.
The electrostatic discharge protection circuit according to claim 2, wherein the detection unit comprises: a resistor and a capacitor;

The resistor and the capacitor are connected in series between the power pin and the ground pin in sequence;

Wherein, a connection terminal of the resistor and the capacitor is used as an output terminal of the detection unit.
The electrostatic discharge protection circuit according to claim 1, wherein the field effect tube triggering module comprises: a third voltage division unit, a fourth voltage division unit, a detection unit, a driving unit, and a field effect tube;

A first end of the third voltage dividing unit is connected to the power pin, and a second end of the third voltage dividing unit is connected to the first end of the fourth voltage dividing unit;

A second end of the fourth voltage dividing unit is connected to the ground pin;

The detection unit and the driving unit are both connected in parallel between the power pin and the ground pin;

A second end of the third voltage dividing unit is connected to a first input end of the driving unit;

An output terminal of the detection unit is connected to a second input terminal of the driving unit;

A gate of the field effect transistor is connected to an output terminal of the driving unit, a source is connected to the power pin, and a drain is used as an output terminal of the field effect transistor trigger module;

When the power pin is subjected to electrostatic attack, the second terminal of the third voltage dividing unit is at a low level, the output terminal of the detection unit is at a high level, and the output terminal of the driving unit is at a low voltage. level.
The electrostatic discharge protection circuit according to claim 4, wherein the detection unit comprises: a capacitor and a resistor;

The capacitor and the resistor are connected in series between the power pin and the ground pin in sequence;

Wherein, the connection end of the capacitor and the resistance is used as the output end of the detection unit.
The electrostatic discharge protection circuit according to claim 4, wherein the driving unit comprises: a first field effect tube, a second field effect tube, a third field effect tube, and a fourth field effect tube;

A gate of the first field effect transistor is connected to an output end of the detection unit, a source is connected to the ground pin, and a drain is connected to a source of the second field effect transistor;

A gate of the second FET is connected to a second end of the third voltage dividing unit, and a drain is connected to a drain of the third FET;

A source of the third FET is connected to the power pin, and a gate is connected to the source of the fourth FET;

A gate of the fourth field effect transistor is connected to a second end of the third voltage dividing unit, and a drain is connected to an output end of the detection unit.
The electrostatic discharge protection circuit according to claim 1, wherein the bleed module comprises: a buffer unit, an inverter, a fifth field-effect transistor and a sixth field-effect transistor;

The buffer unit and the inverter are connected in parallel between the output terminal of the voltage dividing module and the ground pin;

An output terminal of the buffer unit is connected to an input terminal of the inverter, and an output terminal of the inverter is connected to a gate of the fifth field effect transistor;

A source of the fifth FET is connected to the ground pin, and a drain is connected to the source of the sixth FET;

The drain of the sixth FET is connected to the power pin, and the gate is used as an input terminal of the bleed module.
The electrostatic discharge protection circuit according to claim 4, wherein the third voltage dividing unit comprises: a seventh field-effect tube, an eighth field-effect tube, and a ninth field-effect tube;

The source of the seventh FET is used as the first end of the third voltage dividing unit, and is connected to the power pin;

A gate and a drain of the seventh field effect transistor are connected to a source of the eighth field effect transistor;

The gate of the eighth field effect transistor is connected to the drain, and is connected to the source of the ninth field effect transistor;

The gate of the ninth field-effect transistor is connected to the drain, and the second end of the third voltage-dividing unit is connected to the first end of the fourth voltage-dividing unit.
The electrostatic discharge protection circuit according to claim 4, wherein the fourth voltage dividing unit comprises: a tenth field effect transistor and an eleventh field effect transistor;

The gate of the tenth field-effect transistor is connected to the drain, and serves as a first end of the fourth voltage dividing unit;

A source of the tenth field effect transistor is connected to a gate and a drain of the eleventh field effect transistor;

The source of the eleventh field effect transistor is connected to the ground pin as the second end of the fourth voltage dividing unit.
The electrostatic discharge protection circuit according to any one of claims 1 to 9, wherein the first voltage dividing unit comprises: a twelfth field effect tube, a thirteenth field effect tube, and a fourteenth field effect tube;

The source of the twelfth field effect transistor is connected to the power pin;

The gate of the twelfth field effect transistor is connected to the drain, and is connected to the source of the thirteenth field effect transistor;

A gate and a drain of the thirteenth field effect transistor are connected to a source of the fourteenth field effect transistor;

A gate and a drain of the fourteenth field-effect transistor are connected to the second voltage dividing unit.
The electrostatic discharge protection circuit according to any one of claims 1 to 10, wherein the second voltage dividing unit comprises: a fifteenth field-effect tube and a sixteenth field-effect tube;

The gate of the fifteenth field-effect transistor is connected to the drain, and the source is connected to the gate of the sixteenth field-effect transistor;

The source of the sixteenth FET is connected to the ground pin.
An integrated circuit chip, comprising the electrostatic discharge protection circuit according to any one of claims 1 to 7.