CN114189136B - Discharge circuit - Google Patents
Discharge circuit Download PDFInfo
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- CN114189136B CN114189136B CN202111408096.1A CN202111408096A CN114189136B CN 114189136 B CN114189136 B CN 114189136B CN 202111408096 A CN202111408096 A CN 202111408096A CN 114189136 B CN114189136 B CN 114189136B
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- 208000028659 discharge Diseases 0.000 claims abstract description 54
- 239000003990 capacitor Substances 0.000 claims abstract description 27
- 208000035795 Hypocalcemic vitamin D-dependent rickets Diseases 0.000 claims abstract description 23
- 208000033584 type 1 vitamin D-dependent rickets Diseases 0.000 claims abstract description 23
- 238000010168 coupling process Methods 0.000 claims abstract description 12
- 238000005859 coupling reaction Methods 0.000 claims abstract description 12
- 238000007599 discharging Methods 0.000 claims description 39
- 238000004146 energy storage Methods 0.000 claims description 28
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
Abstract
The present invention provides a discharge circuit comprising: a discharge cell, an anti-coupling cell, and a power supply VDDI, the discharge cell comprising: the first PMOS tube, the second PMOS tube, the first NMOS tube, the second NMOS tube and the third NMOS tube; the decoupling unit includes: the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the capacitor and the current source. According to the anti-coupling unit, the potential of the ground end in the discharge loop of the discharge unit can be quickly pulled up in the second discharge stage, the situation that the potential of the ground end and positive high voltage VPOS in other circuits exceed BV is avoided, and the voltage breakdown problem is eliminated.
Description
Technical Field
The application relates to the technical field of low-current discharge circuits, in particular to a discharge circuit.
Background
Referring to fig. 1, fig. 1 is a schematic diagram of a VNEG high voltage discharge circuit in the prior art, and the VNEG high voltage discharge circuit is generally divided into three stages: a high voltage phase, a first discharge phase and a second discharge phase.
In the high voltage stage, disenneng (gate of N2 tube) is set at low level, disennengb (gates of P1 tube and N1 tube) is set at high level, P1 tube and N2 tube are turned off, N1 tube is turned on, and gate charge of N3 tube is transferred to VNEG terminal (negative high voltage terminal) through N1 tube.
In the first discharging stage, DISENEG is set at a high level, DISENEGB is set at a low level, the P1 tube and the N2 tube are turned on, the N1 tube is turned off, and the second discharging stage is started when the VNEG negative high voltage end discharges to a trigger voltage value (GND voltage value-N2 tube conduction voltage drop VT).
In the second discharging stage, disnenneg is set high, disnenneg is set low, the N1 tube is turned off, and the NN1 node is pulled to GND a50 potential, so that the negative high voltage terminal of VNEG is discharged to the potential of GNDA50 (ground terminal potential).
The circuit has the following defects: in the second discharging stage, the negative high voltage terminal of VNEG is conducted with GND, and the negative high voltage terminal of VNEG pulls down the potential of GND a50, even to-0.9V or below, resulting in the risk of extra BV (high voltage breakdown) between the ground terminal of GND a50 and the positive high voltage VPOS in other circuits.
Disclosure of Invention
The application provides a discharge circuit, which can solve the problem that the potential of the ground terminal in a discharge circuit is interfered to fluctuate, so that the potential of the ground terminal and positive high voltage VPOS in other circuits have the risk of exceeding BV.
In one aspect, embodiments of the present application provide a discharging circuit that discharges electric charges to a negative high voltage terminal of an external energy storage unit in a high voltage stage and receives electric charges stored in the high voltage stage from the negative high voltage terminal of the energy storage unit in a discharging stage, the discharging circuit including: discharge cell, anti-coupling cell and power supply VDDI, wherein,
the discharge unit includes: the power supply comprises a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube, wherein the first PMOS tube, the second PMOS tube and the first NMOS tube are sequentially connected in series, the second NMOS tube and the third NMOS tube are connected in series, a grid electrode of the third NMOS tube is connected with a serial node between the second PMOS tube and the first NMOS tube, a source electrode of the first PMOS tube is connected with the power supply VDDI, a grid electrode of the second PMOS tube is grounded, and a source electrode of the first NMOS tube and a source electrode of the third NMOS tube are both connected with a negative high-voltage end of an external energy storage unit;
the decoupling unit includes: the power supply comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a capacitor and a current source, wherein the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are all connected with the power supply VDDI, the drain electrode of the fourth PMOS tube is connected with one end of the capacitor, the other end of the capacitor and the drain electrode of the third PMOS tube are connected to the source electrode of the second NMOS tube and the ground terminal, the grid electrode of the third PMOS tube is connected with a connecting node between the fourth PMOS tube and the capacitor, the drain electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the fourth PMOS tube are all connected with one end of the current source, and the other end of the current source is grounded.
Optionally, in the discharge circuit, the high voltage stage is configured to: the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are at a high level, and the grid electrode of the second NMOS tube is at a low level, wherein the first PMOS tube and the second NMOS tube are turned off, the first NMOS tube is turned on, at the moment, the potential of the grid electrode of the third NMOS tube is equal to the potential of the negative high-voltage end of the external energy storage unit, and the third NMOS tube is turned off.
Optionally, in the discharging circuit, a discharging phase of the discharging circuit includes: a first discharge phase and a second discharge phase, each configured to: the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are set at a low level, and the grid electrode of the second NMOS tube is set at a high level;
in the first discharging stage, the first PMOS transistor, the second NMOS transistor and the first NMOS transistor are turned on, and the power supply VDDI, the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and a negative high voltage end of an external energy storage unit form a path;
when the negative high voltage output by the negative high voltage end of the external energy storage unit discharges to a trigger voltage value, the first NMOS tube is turned off, and at the moment, the discharge unit enters the second discharge stage.
Optionally, in the discharging circuit, the trigger voltage value is equal to a ground voltage value minus a turn-on threshold voltage of the first NMOS transistor.
Optionally, in the discharging circuit, in the second discharging stage, the third NMOS tube is turned on, the negative high voltage end of the external energy storage unit, the third NMOS tube, the second NMOS tube and the ground end form a discharging loop, when the negative high voltage output by the negative high voltage end of the external energy storage unit discharges to the ground voltage value, the gate potential of the third PMOS tube is pulled down to the potential of the ground end through the capacitor, and at this time, the third PMOS tube is turned on to pull up the potential of the ground end in the discharging loop through the power supply VDDI; and when the potential of the ground end in the discharge loop is pulled up, the grid potential of the third PMOS tube is pulled up through the capacitor, and at the moment, the third PMOS tube is turned off.
Optionally, in the discharging circuit, the gate potential and the drain potential of the fifth PMOS transistor and the gate potential of the fourth PMOS transistor are adjusted by using the current source, so that a connection node between the fourth PMOS transistor and the capacitor has an initial potential, and the third PMOS transistor is kept turned off in the high voltage stage and the first discharging stage by the initial potential.
Optionally, in the discharging circuit, a voltage value of the initial potential is equal to a voltage value of the power supply VDDI minus a conduction voltage drop of the fourth PMOS transistor.
The technical scheme of the application at least comprises the following advantages:
according to the anti-coupling unit, the potential of the ground end in the discharge loop of the discharge unit can be quickly raised in the second discharge stage, the situation that the potential of the ground end and the positive high voltage VPOS in other circuits exceed BV is avoided, and the high-voltage breakdown problem is solved.
Further, in the second discharging stage, when the potential of the gate of the third PMOS transistor is pulled down to the potential of the ground end by the capacitor coupling, the third PMOS transistor may be opened quickly, so that the potential of the ground end is lifted quickly, and the lifted potential of the ground end is coupled to the gate node of the third PMOS transistor by the capacitor, so that the potential of the gate of the third PMOS transistor is lifted quickly, and reliability and stability of the anti-coupling unit are improved, so that reliability and stability of the discharging circuit are improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art VNEG high voltage discharge circuit;
FIG. 2 is a schematic diagram of a discharge circuit according to an embodiment of the present invention;
wherein reference numerals are as follows:
10-discharge unit, 20-anti-coupling unit.
Detailed Description
The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.
In one aspect, referring to fig. 2, fig. 2 is a schematic diagram of a discharging circuit according to an embodiment of the present invention, in which charges are discharged to a negative high voltage terminal VNEG of an external energy storage unit S in a high voltage stage, and charges stored in the high voltage stage are received from the negative high voltage terminal VNEG of the energy storage unit in a discharging stage, the discharging circuit includes: a discharge cell 10, an anti-coupling cell 20 and a power supply VDDI, wherein the discharge cell comprises: the PMOS transistor comprises a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2 and a third NMOS transistor N3, wherein the first PMOS transistor P1, the second PMOS transistor P2 and the first NMOS transistor N1 are sequentially connected in series, specifically, the drain electrode of the first PMOS transistor P1 is connected with the source electrode of the second PMOS transistor P2, and the drain electrode of the second PMOS transistor P2 is connected with the drain electrode of the first NMOS transistor N1. The second NMOS transistor N2 and the third NMOS transistor N3 are connected in series, and specifically, a drain electrode of the second NMOS transistor N2 is connected to a drain electrode of the third NMOS transistor N3. The grid electrode of the third NMOS tube is connected with a series node NN1 between the second PMOS tube P2 and the first NMOS tube N1, the source electrode of the first PMOS tube P1 is connected with the power supply VDDI, and the grid electrode of the second PMOS tube P2 is grounded, so that the second PMOS tube P2 is always in a normally open state and plays a role in isolating the first PMOS tube P1 and the first NMOS tube N1. The source electrode of the first NMOS transistor N1 and the source electrode of the third NMOS transistor N3 are both connected to the negative high voltage terminal VNEG of the external energy storage unit.
Further, the decoupling unit 20 includes: the three-phase current source comprises a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a capacitor C0 and a current source I0, wherein the source electrode of the third PMOS tube P3, the source electrode of the fourth PMOS tube P4 and the source electrode of the fifth PMOS tube P5 are all connected with a power supply VDDI, the drain electrode of the fourth PMOS tube P4 is connected with one end of the capacitor C0, the other end of the capacitor C0 and the drain electrode of the third PMOS tube P3 are connected to the source electrode of the second NMOS tube N2 and the ground end GND A50, the grid electrode of the third PMOS tube P3 is connected with a connecting node NG between the fourth PMOS tube P4 and the capacitor C0, the drain electrode of the fifth PMOS tube P5, the grid electrode of the fifth PMOS tube P5 and the grid electrode of the fourth PMOS tube P4 are all connected with the positive end of the current source I0, and the negative end of the current source I0 is grounded at the GND A50.
Wherein the high voltage phase of the discharge circuit is configured to: the gate of the first PMOS transistor P1 and the gate of the first NMOS transistor N1 are set at a high level (e.g., the voltage value of the power supply VDDI), i.e., the disnengb is set at a high level, and the gate of the second NMOS transistor is set at a low level (e.g., 0V), i.e., the disneng is set at a low level, where the first PMOS transistor P1 and the second NMOS transistor N2 are turned off, and the first NMOS transistor N1 is turned on, at this time, the potential of the gate of the third NMOS transistor N3 may be regarded as the potential equal to the potential of the negative high voltage end VNEG of the external energy storage unit S, and the potential of the gate and the source of the third NMOS transistor N3 are the same, i.e., the gate and the source of the third NMOS transistor N3 are shorted, so that the third NMOS transistor N3 is turned off.
Further, the discharging stage of the discharging circuit includes: a first discharge phase and a second discharge phase, each configured to: the gate of the first PMOS transistor P1 and the gate of the first NMOS transistor N1 are set at a low level, i.e., a disable is set at a low level, and the gate of the second NMOS transistor is set at a high level, i.e., a disable is set at a high level.
In the first discharging stage, the first PMOS transistor P1 and the second NMOS transistor N2 are turned on, the discharging of the negative high voltage terminal VNEG of the external energy storage unit S is a dynamic process, the gate of the first NMOS transistor N1 is connected to a low level, but the source of the first NMOS transistor N1 is connected to a negative high voltage, so that the first NMOS transistor N1 is turned on, and the power supply VDDI, the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, and the negative high voltage terminal of the external energy storage unit S form a path. When the negative high voltage output by the negative high voltage end VNEG of the external energy storage unit S discharges to a trigger voltage value, the first NMOS transistor N1 is turned off, and at this time, the discharge unit enters the second discharge stage. In this embodiment, the trigger voltage value is equal to the ground GND a50 minus the on threshold voltage VT (N1) of the first NMOS transistor N1, i.e., the trigger voltage value=gnd-VT (N1). That is, when the potential of the series node NN1 between the second PMOS transistor P2 and the first NMOS transistor N1 is dynamically adjusted to be greater than a negative VT according to the negative high voltage terminal VNEG of the external energy storage unit S (the absolute value of the voltage of the negative high voltage terminal VNEG of the external energy storage unit S is smaller than VT at this time), the gate-source voltage of the first NMOS transistor N1 is equal to 0-VNEG, that is, smaller than VT (turn-on threshold voltage), and the first NMOS transistor N1 is turned off.
When the second discharging stage is entered, since the first NMOS transistor N1 is turned off, the gate potential of the third NMOS transistor N3 is pulled up by the power supply VDDI, so that the third NMOS transistor N3 is turned on, and at this time, the negative high voltage terminal VNEG of the external energy storage unit S, the third NMOS transistor N3, the second NMOS transistor N2, and the ground terminal GND a50 (i.e., vneg→n2→n1→gnda 50) form a discharging loop. When the negative high voltage output by the negative high voltage terminal VNEG of the external energy storage unit S is discharged to the voltage value of the ground terminal GND a50, the ground terminal GND a50 is coupled to the ground terminal GND a50 through the capacitor C0 because the voltage difference between the two ends of the capacitor C0 cannot be suddenly changed, the gate potential (NG node) of the third PMOS transistor P3 is pulled down to the potential of the ground terminal GND a50, that is, the gate of the third PMOS transistor P3 is set to a low level, at this time, the gate-source of the third PMOS transistor P3 is subjected to a negative voltage, the third PMOS transistor P3 is turned on, a path is formed between the power supply VDDI, the third PMOS transistor P3 and the ground terminal GND a50, and the power supply VDDI can rapidly pull up the potential of the ground terminal GND a50 in the discharge loop. In this application, ground end GND a50 in the return circuit of discharging can be through condenser C0 coupling, will pull down the potential of NG node, will third PMOS pipe P3 switches on form the route between power VDDI third PMOS pipe P3 and ground end GND a50, can be pulled up fast by the potential of the ground end GND a50 that the negative high voltage end (VNEG) discharge of outside energy storage unit pulled down, avoids taking place the condition of super high voltage breakdown between the potential of ground end GND a50 and the positive high voltage VPOS in other circuits to the high voltage breakdown risk of the circuit that positive high voltage VPOS is located has been eliminated.
Further, after the potential of the ground end GND a50 in the discharging loop is pulled up, the potential of the gate of the third PMOS transistor P3 is pulled up through the coupling of the capacitor C0, that is, the gate of the third PMOS transistor P3 is set to a high level, and at this time, the third PMOS transistor P3 is turned off. In this embodiment, the gate potential and the drain potential of the fifth PMOS transistor P5 and the gate potential of the fourth PMOS transistor P4 are adjusted by using the current source I0, so that the connection node NG between the fourth PMOS transistor P4 and the capacitor C0 has an initial potential, and the third PMOS transistor P3 is always turned off in the high voltage stage and the first discharging stage by the initial potential. In this embodiment, the voltage value of the initial potential is equal to the voltage value of the power supply VDDI minus the conduction voltage drop of the fourth PMOS transistor P4. In this application, through the fifth PMOS transistor P5, the fourth PMOS transistor P4 may be mirrored to obtain a current, so as to ensure that the initial potential of the NG node will not turn on the third PMOS transistor P3. In the second discharging stage, when the potential of the NG node is pulled down to the potential of the ground GND a50 by the coupling of the capacitor C0, the third PMOS transistor P3 is opened quickly, so that the potential of the ground GND a50 is raised, and then the raised potential of the ground GND a50 is coupled to the NG node by the capacitor C0, so that the potential of the NG node (the potential of the gate of the third PMOS transistor P3) is raised quickly, thereby improving the reliability and stability of the decoupling unit 20, and further improving the reliability and stability of the discharging circuit.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.
Claims (4)
1. A discharge circuit that discharges electric charge to a negative high voltage terminal of an external energy storage unit in a high voltage stage and receives electric charge stored in the high voltage stage from the negative high voltage terminal of the energy storage unit in a discharge stage, the discharge circuit comprising: discharge cell, anti-coupling cell and power supply VDDI, wherein,
the discharge unit includes: the power supply comprises a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube, wherein the first PMOS tube, the second PMOS tube and the first NMOS tube are sequentially connected in series, the second NMOS tube and the third NMOS tube are connected in series, a grid electrode of the third NMOS tube is connected with a serial node between the second PMOS tube and the first NMOS tube, a source electrode of the first PMOS tube is connected with the power supply VDDI, a grid electrode of the second PMOS tube is grounded, and a source electrode of the first NMOS tube and a source electrode of the third NMOS tube are both connected with a negative high-voltage end of an external energy storage unit;
the decoupling unit includes: the power supply comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a capacitor and a current source, wherein the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are all connected with the power supply VDDI, the drain electrode of the fourth PMOS tube is connected with one end of the capacitor, the other end of the capacitor and the drain electrode of the third PMOS tube are connected to the source electrode of the second NMOS tube and the ground terminal, the grid electrode of the third PMOS tube is connected with a connecting node between the fourth PMOS tube and the capacitor, the drain electrode of the fifth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the fourth PMOS tube are all connected with one end of the current source, and the other end of the current source is grounded;
wherein the high pressure stage is configured to: the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are at a high level, and the grid electrode of the second NMOS tube is at a low level, wherein the first PMOS tube and the second NMOS tube are turned off, the first NMOS tube is turned on, at the moment, the potential of the grid electrode of the third NMOS tube is equal to the potential of the negative high-voltage end of the external energy storage unit, and the third NMOS tube is turned off;
the discharge phase of the discharge circuit comprises: a first discharge phase and a second discharge phase, each configured to: the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are set at a low level, and the grid electrode of the second NMOS tube is set at a high level;
in the first discharging stage, the first PMOS transistor, the second NMOS transistor and the first NMOS transistor are turned on, and the power supply VDDI, the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and a negative high voltage end of an external energy storage unit form a path;
when the negative high voltage output by the negative high voltage end of the external energy storage unit discharges to a trigger voltage value, the first NMOS tube is turned off, and at the moment, the discharge unit enters the second discharge stage;
in the second discharging stage, the third NMOS tube is turned on, the negative high voltage end of the external energy storage unit, the third NMOS tube, the second NMOS tube and the ground end form a discharging loop, when the negative high voltage output by the negative high voltage end of the external energy storage unit discharges to the ground end voltage value, the gate potential of the third PMOS tube is pulled down to the potential of the ground end through the capacitor, and at this time, the third PMOS tube is turned on to pull up the potential of the ground end in the discharging loop through the power supply VDDI; and when the potential of the ground end in the discharge loop is pulled up, the grid potential of the third PMOS tube is pulled up through the capacitor, and at the moment, the third PMOS tube is turned off.
2. The discharge circuit of claim 1, wherein the trigger voltage value is equal to a ground voltage value minus a turn-on threshold voltage of the first NMOS transistor.
3. The discharge circuit of claim 1, wherein the gate and drain potentials of the fifth PMOS transistor and the gate potential of the fourth PMOS transistor are adjusted by the current source such that a connection node between the fourth PMOS transistor and the capacitor has an initial potential by which the third PMOS transistor remains turned off during the high voltage phase and the first discharge phase.
4. A discharge circuit according to claim 3, wherein the voltage value of the initial potential is equal to the voltage value of power supply VDDI minus the conduction voltage drop of the fourth PMOS transistor.
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| CN202111408096.1A CN114189136B (en) | 2021-11-25 | 2021-11-25 | Discharge circuit |
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| Publication number | Publication date |
|---|---|
| CN114189136A (en) | 2022-03-15 |
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