CN101997304A - Electrostatic protection circuit - Google Patents
Electrostatic protection circuit Download PDFInfo
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- CN101997304A CN101997304A CN2009101675747A CN200910167574A CN101997304A CN 101997304 A CN101997304 A CN 101997304A CN 2009101675747 A CN2009101675747 A CN 2009101675747A CN 200910167574 A CN200910167574 A CN 200910167574A CN 101997304 A CN101997304 A CN 101997304A
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Abstract
The invention provides an electrostatic protection circuit which is suitable for an integrated circuit system, wherein the integrated circuit system comprises a first power end, a second power end, an internal circuit and a resetting signal wire. The electrostatic protection circuit comprises a first transistor and a second transistor, wherein the first transistor is provided with a first grid, a first electrode and a second electrode, wherein the first grid is coupled to the first power end, and the first electrode is connected to the second power end; and the second transistor is provided with a second grid, a third electrode and a fourth electrode, wherein the second grid, the third electrode and the fourth electrode are respectively connected to the second electrode, the first power end and the resetting signal wire. When the integrated circuit system is in an electrostatic discharge state, the first transistor and the second transistor are conducted, so that the potential of the resetting signal wire corresponds to the potential of the first power end. The electrostatic protection circuit of the invention can be used for detecting the occurrence of the electrostatic discharge, and can maintain the potential of the resetting signal wire after the electrostatic discharge occurs to avoid the situation of false triggering.
Description
Technical field
The present invention relates to a kind of electrostatic discharge protection circuit, particularly a kind of electrostatic discharge protection circuit that is used for corresponding reset signal line.
Background technology
Along with development of semiconductor, more advanced technology is constantly introduced in the making of integrated circuit.Therefore the consumer also enjoys more frivolous, more high-effect and the high-tech product of low power consumption more.With hand-held electronic product such as mobile phone, digital camera, personal digital assistant (personal digital assistant, PDA) be example, more and more Duo circuit is integrated into the system-on-a-chip (System-on-Chip of very small dimensions, SoC) in, make various digital products take under the minimum space usefulness that performance is maximum.
Microelectronic circuit now, its element size is constantly dwindled with the speed of multiple.The electronic system that present stage is highly integrated need be carried out judgment processing with high frequency stabilization ground under small and accurate signal drive, carry out various application functions in order to correspondence.Yet, the noise effect that electronic system is produced by extraneous input or inner member also may down in working order, static discharge (electrostatic discharge for example, ESD) be and cause one of microelectronics system factors of instability, may not cause part internal circuit element in the system to be subjected to the influence of these transient noise and then generation systems fault (mal-function) at static discharge current in expectancy.
In general, the static discharge effect mainly is divided into two aspects to the influence of internal circuit.One of them is for when static discharge, produces excessive discharging current and directly enters and in the internal circuit electron channel is caused damage; Another then is when static discharge, the control signal wire or the specific input end of electronic chip is caused interference, and then make the unusual condition on active electronic chip generation function.
In general, has the control signal wire of several particular importances in the electronic chip usually, for example clock cable (clock), enabling signal line (enable) and reset signal line (reset) etc.For instance, if having not, the static discharge effect in expection takes place, then possible errors triggers the reset signal line of (mis-trigger) some electronic chip or element, make the operating electronic component of part or some important parameter be compelled to reset (reset) suddenly, whole system is absorbed in stops or the partial function inefficacy, finally may needing starts shooting whole system again (or restarts, reboot), even reinstall firmware and could recover, will cause the loss of a large amount of time and human cost like this.
In the prior art, electronic installation to damage or fault that inner operating circuit may cause, is provided with systems for providing electrostatic discharge protection for fear of static discharge current usually.Systems for providing electrostatic discharge protection can be when static discharge, and the signal level of specific control signal wire is maintained certain voltage level, takes place with the situation of avoiding erroneous trigger.Yet systems for providing electrostatic discharge protection of the prior art is except being provided with specific circuit structure, and the specific firmware of still need arranging in pairs or groups carries out computing to be judged, its control method is comparatively complicated.That is to say, cooperate the effect that just can reach the antistatic capacity of raising system when needing hardware (or hardware) with firmware.
The invention provides a kind of electrostatic discharge protection circuit, it can be in order to detecting the generation of static discharge, and after static discharge takes place, can keep the current potential of reset signal line, avoids the situation of erroneous trigger, to address the above problem.
Summary of the invention
One aspect of the present invention is to provide a kind of electrostatic discharge protection circuit that is used for integrated circuit (IC) system, this integrated circuit (IC) system comprises first power end, second source end, internal circuit and the reset signal line that is connected with this internal circuit, and internal circuit is coupled between this first power end and this second source end.
According to a specific embodiment, electrostatic discharge protection circuit comprises the first transistor and transistor seconds.The first transistor has first grid, first electrode and second electrode, and wherein first grid directly connects or is coupled to this first power end indirectly, and first electrode is connected to the second source end.And transistor seconds has second grid, third electrode and the 4th electrode, and second grid is connected to second electrode, and third electrode is connected to first power end, and the 4th electrode is connected to the reset signal line.
In this embodiment, when integrated circuit (IC) system is in the static discharge state, the first transistor and transistor seconds conducting, the current potential that causes the reset signal line is by the current potential of transistor seconds corresponding to first power end.
According to electrostatic discharge protection circuit of the present invention, in one embodiment, this first power end is the working power end of this internal circuit, and this second source end is the system earth end.
According to electrostatic discharge protection circuit of the present invention, in one embodiment, the first transistor is a nmos pass transistor, and this transistor seconds is the PMOS transistor.
According to electrostatic discharge protection circuit of the present invention, in another embodiment, first power end is the system earth end, and this second source end working power end that is this internal circuit.
According to electrostatic discharge protection circuit of the present invention, in another embodiment, the first transistor is the PMOS transistor, and this transistor seconds is a nmos pass transistor.
According to electrostatic discharge protection circuit of the present invention, wherein, first grid further connects a RC circuit, and this second grid further connects the 2nd RC circuit.
According to electrostatic discharge protection circuit of the present invention, wherein, a RC circuit has very first time constant, and the 2nd RC circuit has second time constant, and should very first time constant and this second time constant all greater than the static discharge time.
Another aspect of the present invention is to provide a kind of electrostatic discharge protection circuit that is used for integrated circuit (IC) system, this integrated circuit (IC) system comprises working power end, system earth end, internal circuit and the reset signal line that is connected with this internal circuit, and this internal circuit is coupled between this working power end and this system earth end.
According to a specific embodiment, this electrostatic discharge protection circuit comprises a RC circuit, the 2nd RC circuit, PMOS transistor and nmos pass transistor.The one RC circuit is serially connected between working power end and the system earth end, and a RC circuit comprises first resistance that is connected in series this working power end and first electric capacity that is connected in series this system earth end.The 2nd RC circuit is serially connected between this working power end and this system earth end, and the 2nd RC circuit comprises second resistance that is connected in series this system earth end and second electric capacity that is connected in series this working power end.The PMOS transistor is coupled between this working power end and this reset signal line, and this PMOS transistor has the first grid that is coupled between this first resistance and this first electric capacity.Nmos pass transistor is coupled between this PMOS transistor first grid and this system earth end, and this nmos pass transistor has the second grid that is coupled between this second resistance and this second electric capacity.
In this embodiment, when this integrated circuit (IC) system is in the static discharge state, the conducting that is triggered of PMOS transistor AND gate nmos pass transistor, the current potential that causes the reset signal line is by the current potential of PMOS transistor corresponding to this working power end.
According to electrostatic discharge protection circuit of the present invention, wherein, the product of first resistance value and this first capacitance is a very first time constant, and the product of this second resistance value and this second capacitance is second time constant, and should very first time constant and this second time constant all greater than the static discharge time.
According to electrostatic discharge protection circuit of the present invention, wherein, after this second time constant of static discharge state process, this nmos pass transistor enters closed condition.
According to electrostatic discharge protection circuit of the present invention, wherein, when this nmos pass transistor enters closed condition, to this first electric capacity charging, and through behind this very first time constant, this PMOS transistor enters closed condition to this working power end by this first resistance.
Another aspect of the present invention is to provide a kind of electrostatic discharge protection circuit that is used for integrated circuit (IC) system, this integrated circuit (IC) system comprises working power end, system earth end, internal circuit and the reset signal line that is connected with this internal circuit, and this internal circuit is coupled between this working power end and this system earth end.
According to a specific embodiment, this electrostatic discharge protection circuit comprises a RC circuit, the 2nd RC circuit, PMOS transistor and nmos pass transistor.The one RC circuit is serially connected between this working power end and this system earth end, and a RC circuit comprises first electric capacity of serial connection to first resistance of this working power end and serial connection to this system earth end.The 2nd RC circuit is serially connected between this working power end and this system earth end, and the 2nd RC circuit comprises second electric capacity of serial connection to second resistance of this system earth end and serial connection to this working power end.Nmos pass transistor is coupled between this reset signal line and this system earth end, and this nmos pass transistor has the first grid that is coupled between this second resistance and this second electric capacity.The PMOS transistor is coupled between the first grid and this working power end of this nmos pass transistor, and this PMOS transistor has the second grid that is coupled between this first electric capacity and this first resistance.
In this embodiment, when this integrated circuit (IC) system is in the static discharge state, the conducting that is triggered of this this nmos pass transistor of PMOS transistor AND gate, the current potential that causes this reset signal line is by the current potential of this nmos pass transistor corresponding to this system earth end.
According to electrostatic discharge protection circuit of the present invention, wherein, the product of first resistance value and this first capacitance is a very first time constant, and the product of this second resistance value and this second capacitance is second time constant, and should very first time constant and this second time constant all greater than the static discharge time.
According to electrostatic discharge protection circuit of the present invention, wherein, behind this very first time constant of static discharge state process, this PMOS transistor enters closed condition.
According to electrostatic discharge protection circuit of the present invention, wherein, when this PMOS transistor enters closed condition, to this second electric capacity charging, through after this second time constant, this nmos pass transistor enters closed condition to this system earth end by this second resistance.
Electrostatic discharge protection circuit needs firmware and hardware (or hardware) to cooperatively interact to improve the static tolerance of system in the prior art, electrostatic discharge protection circuit of the present invention is by being provided with simple circuit configuration, utilize the charge-discharge characteristic of transistor switch and RC circuit, can judge the generation of static discharge, and and then in the regular hour, the current potential of reset signal line is maintained on certain voltage level, avoid the phenomenon of static discharge to cause internal circuit to break down, like this, can improve the stability of electronic system integral body by simple electrostatic discharge protection circuit.
Can be further understood by following embodiment and accompanying drawing about the advantages and spirit of the present invention.
Description of drawings
Fig. 1 shows according to the electrostatic discharge protection circuit in first specific embodiment of the present invention and the schematic diagram of integrated circuit (IC) system.
Fig. 2 shows the internal circuit schematic diagram of electrostatic discharge protection circuit among Fig. 1.
Fig. 3 shows according to the electrostatic discharge protection circuit in second specific embodiment of the present invention and the schematic diagram of integrated circuit (IC) system.
Fig. 4 shows the internal circuit schematic diagram of electrostatic discharge protection circuit among Fig. 3.
Embodiment
With reference to Fig. 1.Fig. 1 shows the schematic diagram according to electrostatic discharge protection circuit 1 and integrated circuit (IC) system 2 in first specific embodiment of the present invention.As shown in Figure 1, integrated circuit (IC) system 2 can comprise two power ends, internal circuit 20 and the reset signal line 22 that is connected with this internal circuit 20.In this embodiment, two power ends can be respectively the working power end Vdd and the system earth end Vss of integrated circuit (IC) system 2, but the present invention is not limited to this.This internal circuit 20 is coupled between these two power ends (working power end Vdd and system earth end Vss), and internal circuit 20 can obtain the necessary power supply supply of operation from working power end Vdd and system earth end Vss.
In addition, as shown in Figure 1, integrated circuit (IC) system 2 can comprise input pad (input pad) IN in addition, and reset signal line 22 is connected electrically between input pad IN and the internal circuit 20, and reset signal line 22 is responsible for being sent to this internal circuit 20 in order to the control signal of replacement internal circuit 20.In this embodiment, the control signal that reset signal line 22 transmits be reverse logic (or negative logic) reverse reset signal (negative logic reset signal, RSTN).So-called reverse reset signal refers to that when reverse reset signal was low-voltage position standard or ground connection, internal circuit 20 was promptly reset; Otherwise, when reverse reset signal is high voltage level, the promptly normal operation of internal circuit 20.Refer to that just in this embodiment, reset signal line 22 should maintain high voltage level in the ordinary course of things, make internal circuit 20 can keep normal operation.
Yet when static discharge took place, change temporary and that can not expect may take place in the current potential of working power end Vdd in the integrated circuit (IC) system 2 and system earth end Vss.In the present invention, electrostatic discharge protection circuit 1 can produce abnormal influence to the reset signal line 22 that is coupled between input pad IN and the internal circuit 20 in order to avoid the static discharge phenomenon.
With reference to Fig. 2, Fig. 2 shows the internal circuit schematic diagram of the electrostatic discharge protection circuit 1 among Fig. 1 in the lump.In this embodiment, electrostatic discharge protection circuit 1 comprises a RC circuit 10, the 2nd RC circuit 12 and two transistor switch elements.In this embodiment, these two transistor switch elements are respectively PMOS transistor SW1 and nmos pass transistor SW2, but the present invention is not limited to this.
As shown in Figure 2, the one RC circuit 10 is serially connected between working power end Vdd and the system earth end Vss, the one RC circuit 10 comprises that first resistance R 1 and first capacitor C, 1, the first resistance R 1 are connected in series to working power end Vdd, and first capacitor C 1 is connected in series to system earth end Vss.Wherein, the resistance value of first resistance R 1 is the very first time constant of a corresponding RC circuit 10 with the product of the capacitance of first capacitor C 1, speed speed and cycle length that on behalf of a RC circuit 10, the big I of this very first time constant discharge and recharge.
The 2nd RC circuit 12 is serially connected between working power end Vdd and the system earth end Vss, and the 2nd RC circuit 12 comprises that second resistance R 2 and second capacitor C, 2, the second resistance R 2 are connected in series to system earth end Vss, and second capacitor C 2 is connected in series to working power end Vdd.Wherein, the resistance value of second resistance R 2 is second time constant of corresponding the 2nd RC circuit 12 with the product of the capacitance of second capacitor C 2, speed speed and cycle length that on behalf of the 2nd RC circuit 12, the big I of this second time constant discharge and recharge.
PMOS transistor SW1 is coupled between working power end Vdd and the reset signal line 22, and the grid of PMOS transistor SW1 is coupled in (as the first node N1 place among Fig. 2) between first resistance R 1 and first capacitor C 1.The on off state of PMOS transistor SW1 is controlled by the charging and discharging state of a RC circuit 10, and exactly, it is according to the node potential of first node N1 and the diverter switch state.
Nmos pass transistor SW2 is coupled between the grid and system earth end Vss of PMOS transistor SW1, and the grid of nmos pass transistor SW2 is coupled to (as the Section Point N2 place among Fig. 2) between this second resistance and this second electric capacity.The on off state of nmos pass transistor SW2 is controlled by the charging and discharging state of the 2nd RC circuit 12, and exactly, it is according to the node potential of Section Point N2 and the diverter switch state.
Wherein, when this integrated circuit (IC) system 2 is in the static discharge state, this moment, working power end Vdd and system earth end Vss were influenced by the transient voltage of static discharge or transient current, potential difference between working power end Vdd and the system earth end Vss is amplified, and may be that working power end Vdd rises suddenly or system earth end Vss descends suddenly in the practical application.When static discharge took place, the grid-source voltage poor (Vgs) of the grid-source voltage of PMOS transistor SW1 poor (Vgs) and nmos pass transistor SW2 will thereby amplify, and then made PMOS transistor SW1 and the nmos pass transistor SW2 conducting that is triggered.Thus, reset signal line 22 will be electrically connected with working power end Vdd by the PMOS transistor SW1 that opens, and causes the current potential of the current potential of reset signal line 22 corresponding to working power end Vdd.
That is to say that when static discharge took place, PMOS transistor SW1 and nmos pass transistor SW2 were switched on simultaneously, and reset signal line 22 is temporarily maintained high voltage level (corresponding to the current potential of working power end Vdd).Like this, reset signal line 22 just is unlikely flip-flop to low-voltage position standard, can avoid forming the function of reset of reverse reset signal and then erroneous trigger internal circuit 20.
In addition, after above-mentioned generation of static discharge state and second time constant through corresponding the 2nd RC circuit 12, because of the node potential of Section Point N2 in the 2nd RC circuit 12 descends by 2 discharges of second resistance R gradually, final descend make the grid-source voltage of nmos pass transistor SW2 poor (Vgs) goes forward side by side into the state of closing less than the threshold voltage (threshold voltage) of itself.
Then, after nmos pass transistor SW2 enters closed condition, working power end Vdd is by 1 charging of 1 pair first capacitor C of first resistance R, the node potential of first node N1 is risen gradually, and through behind this very first time constant, the grid-source voltage of PMOS transistor SW1 poor (Vgs) is gone forward side by side into the state of closing less than the threshold voltage (threshold voltage) of itself.
What need pay special attention to is, start at since when static discharge takes place, making PMOS transistor SW1 and the nmos pass transistor SW2 conducting that is triggered, SW1 gets back to closed condition once more up to the PMOS transistor, the current potential of reset signal line 22 all is maintained at a fixed value in this section period, just corresponding to the current potential of working power end Vdd.
In this embodiment, can be further the very first time constant and second time constant by design the one RC circuit 10 and the 2nd RC circuit 12, make in the very first time constant and second time constant at least one greater than or both are all greater than the possible static discharge time of integrated circuit (IC) system 2.Like this, just, can guarantee the stability of the signal condition of reset signal line 22 under the state of static discharge.
In the first above-mentioned specific embodiment, the reset signal line 22 that electrostatic discharge protection circuit 1 of the present invention can corresponding reverse logic carries out the electrostatic discharge protective operation, yet the present invention is not limited to this.With reference to Fig. 3 and Fig. 4.Fig. 3 shows the schematic diagram according to electrostatic discharge protection circuit 3 and integrated circuit (IC) system 4 in second specific embodiment of the present invention.Fig. 4 shows the internal circuit schematic diagram of electrostatic discharge protection circuit 3 among Fig. 3.
Compare with the first previous specific embodiment, the maximum difference of second specific embodiment is, reset signal line 42 herein in order to the control signal that transmits be the forward logic reset signal (reset signal, RST).So-called forward reset signal is meant that when the forward reset signal was high voltage level, internal circuit 40 was promptly reset; Otherwise, when the forward reset signal is low-voltage position standard or ground connection, the promptly normal operation of internal circuit 40.Refer to just that in this embodiment reset signal line 42 should maintain low-voltage position standard in the ordinary course of things, make internal circuit 40 can keep normal operation.
For when the static discharge phenomenon takes place, still can keep reset signal line 42 to stablize and be positioned at low-voltage position standard, in integrated circuit (IC) system 4, be provided with electrostatic discharge protection circuit 3 provided by the present invention.
As shown in Figure 4, electrostatic discharge protection circuit 3 comprises a RC circuit 30, the 2nd RC circuit 32 and two transistor switch elements.In this embodiment, these two transistor switch elements can be respectively nmos pass transistor SW3 and PMOS transistor SW4.
The one RC circuit 30 is serially connected between working power end Vdd and the system earth end Vss, and a RC circuit 30 comprises first resistance R 1 and first capacitor C 1.First resistance R 1 is connected in series to working power end Vdd, and first capacitor C, 1 serial connection is to this system earth end Vss.
The 2nd RC circuit 32 is serially connected between working power end Vdd and the system earth end Vss, and the 2nd RC circuit 32 comprises second resistance R 2 and second capacitor C 2.Second resistance R 2 is connected in series to system earth end Vss, and second capacitor C 2 is connected in series to working power end Vdd.
Nmos pass transistor SW3 is coupled between reset signal line 42 and the system earth end Vss, and the grid of nmos pass transistor SW3 is coupled to (as the Section Point N2 among Fig. 4) between second resistance R 2 and second capacitor C 2.
PMOS transistor SW4 is coupled between the grid and working power end Vdd of nmos pass transistor SW3, and the grid of PMOS transistor SW4 is coupled to (as the first node N1 among Fig. 4) between first capacitor C 1 and first resistance R 1.
When integrated circuit (IC) system 4 is in the static discharge state, nmos pass transistor SW3 and the PMOS transistor SW4 conducting that is triggered, the current potential that causes reset signal line 42 is by the current potential of nmos pass transistor SW3 corresponding to system earth end Vss.
Then, charging along with a RC circuit 30, the voltage level of first node N1 improves gradually, after through the very first time constant of a corresponding RC circuit 30 or the grid-source voltage poor (Vgs) of PMOS transistor SW4 during less than threshold voltage itself, PMOS transistor SW4 just gets back to closed condition.
Then, discharge along with the 2nd RC circuit 32, the voltage level of Section Point N2 descends gradually, after through second time constant of corresponding the 2nd RC circuit 32 or the grid-source voltage poor (Vgs) of nmos pass transistor SW3 during less than threshold voltage itself, nmos pass transistor SW3 just gets back to closed condition, makes integrated circuit (IC) system 4 get back to operating state.Wherein the operational mode of electrostatic discharge protection circuit 3 is similar substantially with first specific embodiment or corresponding relation arranged, and therefore the part that has described in detail at first specific embodiment just repeats no more, can be with reference to the detailed description of previous first specific embodiment.
That is to say,, can guarantee just that at static discharge reset signal line 42 can be stable at low-voltage position standard in the time, avoid the situation of erroneous trigger to take place by the time constant of suitable adjustment the one RC circuit 30 and the 2nd RC circuit 32.
In sum, electrostatic discharge protection circuit of the present invention is by being provided with simple circuit configuration, utilize the charge-discharge characteristic of transistor switch and RC circuit, can judge the generation of static discharge, and and then in the regular hour, the current potential of reset signal line is maintained on certain voltage level, avoid the phenomenon of static discharge to cause internal circuit to break down, like this, can improve the stability of electronic system integral body by simple electrostatic discharge protection circuit.
By the detailed description of above preferred specific embodiment, hope can be known description feature of the present invention and spirit more, and is not to come scope of the present invention is limited with above-mentioned disclosed preferred specific embodiment.On the contrary, its objective is that hope can be contained various changes and identity property is replaced in the scope of claim of the present invention.
The main element symbol description
1,3: electrostatic discharge protection circuit 2,4: IC system
20,40: internal circuit 22,42: the reset signal line
10,30: the RC circuit 12,32: the two RC circuit
R1: the first resistance C1: first electric capacity
R2: the second resistance C2: second electric capacity
N1: first node N2: Section Point
SW1, SW4:PMOS transistor
SW2, SW3:NMOS transistor
Vdd: working power end Vss: system earth end.
Claims (10)
1. electrostatic discharge protection circuit, be used for integrated circuit (IC) system, described integrated circuit (IC) system comprises first power end, second source end, internal circuit and the reset signal line that is connected with described internal circuit, described internal circuit is coupled between described first power end and the described second source end, and described electrostatic discharge protection circuit comprises:
The first transistor has first grid, first electrode and second electrode, and described first grid is coupled to described first power end, and described first electrode is connected to described second source end; And
Transistor seconds has second grid, third electrode and the 4th electrode, and described second grid is connected to described second electrode, and described third electrode is connected to described first power end, and described the 4th electrode is connected to described reset signal line;
Wherein, when described integrated circuit (IC) system is in the static discharge state, described the first transistor and described transistor seconds conducting, the current potential that causes described reset signal line is by the current potential of described transistor seconds corresponding to described first power end.
2. electrostatic discharge protection circuit according to claim 1, wherein, described first power end is the working power end of described internal circuit, and described second source end is the system earth end.
3. electrostatic discharge protection circuit according to claim 2, wherein, described the first transistor is a nmos pass transistor, and described transistor seconds is the PMOS transistor.
4. electrostatic discharge protection circuit according to claim 1, wherein, described first power end is the system earth end, and the described second source end working power end that is described internal circuit.
5. electrostatic discharge protection circuit according to claim 4, wherein, described the first transistor is the PMOS transistor, and described transistor seconds is a nmos pass transistor.
6. electrostatic discharge protection circuit according to claim 1, wherein, described first grid further is connected to a RC circuit, and described second grid further is connected to the 2nd RC circuit.
7. electrostatic discharge protection circuit according to claim 1, wherein, a described RC circuit has very first time constant, and described the 2nd RC circuit has second time constant, and described very first time constant and described second time constant are all greater than the static discharge time.
8. electrostatic discharge protection circuit, be used for integrated circuit (IC) system, described integrated circuit (IC) system comprises working power end, system earth end, internal circuit and the reset signal line that is connected with described internal circuit, described internal circuit is coupled between described working power end and the described system earth end, and described electrostatic discharge protection circuit comprises:
The one RC circuit is serially connected between described working power end and the described system earth end, and a described RC circuit comprises first electric capacity of serial connection to first resistance of described working power end and serial connection to described system earth end;
The 2nd RC circuit is serially connected between described working power end and the described system earth end, and described the 2nd RC circuit comprises second electric capacity of serial connection to second resistance of described system earth end and serial connection to described working power end;
The PMOS transistor is coupled between described working power end and the described reset signal line, and described PMOS transistor has the first grid that is coupled between described first resistance and described first electric capacity; And
Nmos pass transistor is coupled between described first grid and the described system earth end, and described nmos pass transistor has the second grid that is coupled between described second resistance and described second electric capacity;
Wherein, when described integrated circuit (IC) system is in the static discharge state, the conducting that is triggered of the described nmos pass transistor of described PMOS transistor AND gate, the current potential that causes described reset signal line is by the current potential of described PMOS transistor corresponding to described working power end.
9. electrostatic discharge protection circuit according to claim 8, wherein, the product of described first resistance value and described first capacitance is a very first time constant, the product of described second resistance value and described second capacitance is second time constant, and described very first time constant and described second time constant are all greater than the static discharge time.
10. electrostatic discharge protection circuit, be used for integrated circuit (IC) system, described integrated circuit (IC) system comprises working power end, system earth end, internal circuit and the reset signal line that is connected with described internal circuit, described internal circuit is coupled between described working power end and the described system earth end, and described electrostatic discharge protection circuit comprises:
The one RC circuit is serially connected between described working power end and the described system earth end, and a described RC circuit comprises first electric capacity of serial connection to first resistance of described working power end and serial connection to described system earth end;
The 2nd RC circuit is serially connected between described working power end and the described system earth end, and described the 2nd RC circuit comprises second electric capacity of serial connection to second resistance of described system earth end and serial connection to described working power end;
Nmos pass transistor is coupled between described reset signal line and the described system earth end, and described nmos pass transistor has the first grid that is coupled between described second resistance and described second electric capacity; And
The PMOS transistor is coupled between described first grid and the described working power end, and described PMOS transistor has the second grid that is coupled between described first electric capacity and described first resistance;
Wherein, when described integrated circuit (IC) system is in the static discharge state, the conducting that is triggered of the described nmos pass transistor of described PMOS transistor AND gate, the current potential that causes described reset signal line is by the current potential of described nmos pass transistor corresponding to described system earth end.
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| CN2009101675747A CN101997304A (en) | 2009-08-26 | 2009-08-26 | Electrostatic protection circuit |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102904236A (en) * | 2011-07-28 | 2013-01-30 | 瑞鼎科技股份有限公司 | Electronic device with electrostatic discharge protection effect |
| CN104377670A (en) * | 2013-08-15 | 2015-02-25 | 恩智浦有限公司 | Electrostatic discharge protection device used for integrated circuit device |
| CN105529693A (en) * | 2015-09-01 | 2016-04-27 | 北京中电华大电子设计有限责任公司 | Internal ESD protection circuit for integrated circuit |
| CN106786455A (en) * | 2015-12-16 | 2017-05-31 | 成都芯源系统有限公司 | Esd protection circuit |
| CN110739302A (en) * | 2019-10-28 | 2020-01-31 | 长江存储科技有限责任公司 | Power supply electrostatic protection circuit, power supply module and semiconductor device |
| CN110967568A (en) * | 2018-09-30 | 2020-04-07 | 奇景光电股份有限公司 | Electrostatic discharge detection device |
| CN112272812A (en) * | 2019-11-25 | 2021-01-26 | 深圳市大疆创新科技有限公司 | Power management device, electronic equipment and movable platform assembly |
| CN112930014A (en) * | 2021-01-28 | 2021-06-08 | 青岛信芯微电子科技股份有限公司 | Electrostatic discharge protection circuit and protection method |
| CN114172137A (en) * | 2020-11-03 | 2022-03-11 | 台湾积体电路制造股份有限公司 | Circuit and method for electrostatic discharge protection |
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Cited By (14)
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|---|---|---|---|---|
| CN102904236A (en) * | 2011-07-28 | 2013-01-30 | 瑞鼎科技股份有限公司 | Electronic device with electrostatic discharge protection effect |
| CN104377670A (en) * | 2013-08-15 | 2015-02-25 | 恩智浦有限公司 | Electrostatic discharge protection device used for integrated circuit device |
| CN104377670B (en) * | 2013-08-15 | 2018-02-13 | 恩智浦有限公司 | Electrostatic discharge protector for IC-components |
| CN105529693A (en) * | 2015-09-01 | 2016-04-27 | 北京中电华大电子设计有限责任公司 | Internal ESD protection circuit for integrated circuit |
| CN106786455A (en) * | 2015-12-16 | 2017-05-31 | 成都芯源系统有限公司 | Esd protection circuit |
| CN106786455B (en) * | 2015-12-16 | 2019-01-15 | 成都芯源系统有限公司 | ESD protection circuit |
| CN110967568B (en) * | 2018-09-30 | 2022-07-26 | 奇景光电股份有限公司 | Electrostatic discharge detection device |
| CN110967568A (en) * | 2018-09-30 | 2020-04-07 | 奇景光电股份有限公司 | Electrostatic discharge detection device |
| CN110739302A (en) * | 2019-10-28 | 2020-01-31 | 长江存储科技有限责任公司 | Power supply electrostatic protection circuit, power supply module and semiconductor device |
| WO2021102629A1 (en) * | 2019-11-25 | 2021-06-03 | 深圳市大疆创新科技有限公司 | Power supply management apparatus, electronic device and movable platform assembly |
| CN112272812A (en) * | 2019-11-25 | 2021-01-26 | 深圳市大疆创新科技有限公司 | Power management device, electronic equipment and movable platform assembly |
| CN114172137A (en) * | 2020-11-03 | 2022-03-11 | 台湾积体电路制造股份有限公司 | Circuit and method for electrostatic discharge protection |
| CN112930014A (en) * | 2021-01-28 | 2021-06-08 | 青岛信芯微电子科技股份有限公司 | Electrostatic discharge protection circuit and protection method |
| CN112930014B (en) * | 2021-01-28 | 2022-04-01 | 青岛信芯微电子科技股份有限公司 | Electrostatic discharge protection circuit and protection method |
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Application publication date: 20110330 |