CN114189136A

CN114189136A - Discharge circuit

Info

Publication number: CN114189136A
Application number: CN202111408096.1A
Authority: CN
Inventors: 马媛; 邵博闻
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2021-11-25
Filing date: 2021-11-25
Publication date: 2022-03-15
Anticipated expiration: 2041-11-25
Also published as: CN114189136B

Abstract

The present invention provides a discharge circuit, including: a discharge unit, an anti-coupling unit and a power supply VDDI, the discharge unit including: the NMOS transistor comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor and a third NMOS transistor; the anti-coupling unit includes: the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, the capacitor and the current source. This application passes through anti coupling unit can be in the second discharge phase with the discharge unit discharge the electric potential of the ground terminal in the return circuit and pull up fast, avoids the electric potential of ground terminal and the positive high voltage VPOS in other circuits to take place the condition of exceeding BV, eliminates the voltage breakdown problem.

Description

Discharge circuit

Technical Field

The application relates to the technical field of low-current discharge circuits, in particular to a discharge circuit.

Background

Referring to fig. 1, fig. 1 is a schematic diagram of a VNEG high-voltage discharge circuit in the prior art, which is generally divided into three stages: a high voltage phase, a first discharge phase and a second discharge phase.

In the high-voltage stage, the DISENNEG (grid of the N2 tube) is set to be low, the DISENNEGB (grid of the P1 tube and the N1 tube) is set to be high, the P1 tube and the N2 tube are turned off, the N1 tube is turned on, and grid charges of the N3 tube are transmitted to a VNEG terminal (negative high-voltage terminal) through the N1 tube.

In the first discharge stage, the DISENNEG is set to be at a high level, the DISENNEGB is set to be at a low level, the P1 tube and the N2 tube are switched on, the N1 tube is switched off, and when the VNEG negative high-voltage end discharges to a trigger voltage value (the voltage value of GND-the conduction voltage drop VT of the N2 tube), the second discharge stage is started.

In the second discharge phase, the DISENNEG is set to high level, the DISENNEGB is set to low level, the N1 tube is cut off, and the NN1 node is pulled to GND A50 potential, thereby discharging the VNEG negative high-voltage end to GNDA50 potential (ground potential).

The circuit has the following defects: in the second discharge phase, the negative high-voltage terminal of VNEG is conducted to GND, and the negative high-voltage terminal of VNEG will pull down the potential of GND a50, even to-0.9V or below, resulting in a risk of exceeding BV (high voltage breakdown) between the ground terminal of GND a50 and the positive high-voltage VPOS in other circuits.

Disclosure of Invention

The application provides a discharge circuit, can solve the problem that the electric potential of ground terminal receives the interference fluctuation and leads to having the super BV risk with the positive high voltage VPOS in other circuits in the return circuit that discharges.

In one aspect, an embodiment of the present application provides a discharge circuit that discharges charges to a negative high-voltage terminal of an external energy storage unit in a high-voltage stage and receives charges stored in the high-voltage stage from the negative high-voltage terminal of the energy storage unit in a discharge stage, where the discharge circuit includes: a discharge unit, an anti-coupling unit, and a power supply VDDI, wherein,

the discharge unit includes: the power supply comprises a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube, wherein the first PMOS tube, the second PMOS tube and the first NMOS tube are sequentially connected in series, the second NMOS tube and the third NMOS tube are connected in series, a grid electrode of the third NMOS tube is connected with a series node between the second PMOS tube and the first NMOS tube, a source electrode of the first PMOS tube is connected with the power supply VDDI, a grid grounding end of the second PMOS tube, a source electrode of the first NMOS tube and a source electrode of the third NMOS tube are both connected with a negative high-voltage end of an external energy storage unit;

the anti-coupling unit includes: the power supply device comprises a third PMOS (P-channel metal oxide semiconductor) tube, a fourth PMOS tube, a fifth PMOS tube, a capacitor and a current source, wherein a source electrode of the third PMOS tube, a source electrode of the fourth PMOS tube and a source electrode of the fifth PMOS tube are all connected with the power supply VDDI (high voltage differential amplifier), a drain electrode of the fourth PMOS tube is connected with one end of the capacitor, the other end of the capacitor and a drain electrode of the third PMOS tube are connected to a source electrode of a second NMOS (N-channel metal oxide semiconductor) tube and a grounding end, a grid electrode of the third PMOS tube is connected with a connecting node between the fourth PMOS tube and the capacitor, a drain electrode of the fifth PMOS tube, a grid electrode of the fifth PMOS tube and a grid electrode of the fourth PMOS tube are all connected with one end of the current source, and the other end of the current source is grounded.

Optionally, in the discharge circuit, the high voltage stage is configured to: the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are set to be at high level, the grid electrode of the second NMOS tube is set to be at low level, the first PMOS tube and the second NMOS tube are turned off, the first NMOS tube is turned on, at the moment, the potential of the grid electrode of the third NMOS tube is equal to the potential of the negative high-voltage end of the external energy storage unit, and the third NMOS tube is turned off.

Optionally, in the discharge circuit, the discharge phase of the discharge circuit includes: a first discharge phase and a second discharge phase, each configured to: the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are set to be at a low level, and the grid electrode of the second NMOS tube is set to be at a high level;

in the first discharging stage, the first PMOS transistor, the second NMOS transistor and the first NMOS transistor are turned on, and the power supply VDDI, the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and a negative high-voltage end of an external energy storage unit form a path;

when the negative high voltage output by the negative high voltage end of the external energy storage unit discharges to a trigger voltage value, the first NMOS tube is turned off, and at the moment, the discharge unit enters the second discharge stage.

Optionally, in the discharge circuit, the trigger voltage value is equal to a ground voltage value minus a turn-on threshold voltage of the first NMOS transistor.

Optionally, in the discharge circuit, in the second discharge stage, the third NMOS transistor is turned on, the negative high voltage terminal of the external energy storage unit, the third NMOS transistor, the second NMOS transistor, and the ground terminal form a discharge loop, when the negative high voltage output by the negative high voltage terminal of the external energy storage unit discharges to a voltage value of the ground terminal, the gate potential of the third PMOS transistor is pulled down to the potential of the ground terminal through the capacitor, and at this time, the third PMOS transistor is turned on to pull up the potential of the ground terminal in the discharge loop through the VDDI power supply; when the potential of the ground end in the discharge loop is pulled high, the grid potential of the third PMOS tube is pulled high through the capacitor, and at the moment, the third PMOS tube is turned off.

Optionally, in the discharge circuit, the gate potential and the drain potential of the fifth PMOS transistor and the gate potential of the fourth PMOS transistor are adjusted by using the current source, so that a connection node between the fourth PMOS transistor and the capacitor has an initial potential, and the third PMOS transistor is kept turned off in the high-voltage stage and the first discharge stage by the initial potential.

Optionally, in the discharge circuit, a voltage value of the initial potential is equal to a voltage value of the power supply VDDI minus a conduction voltage drop of the fourth PMOS transistor.

The technical scheme at least comprises the following advantages:

this application passes through anti coupling unit can be in the second discharge phase with the discharge unit discharge the electric potential of the ground terminal in the return circuit high speed, avoids the electric potential of ground terminal and the positive high voltage VPOS in other circuits to take place the condition of super BV, eliminates high-voltage breakdown problem.

Further, in a second discharging stage, in the anti-coupling unit, when the potential of the gate of the third PMOS transistor is coupled and pulled down to the potential of the ground by the capacitor, the third PMOS transistor may be quickly turned on, so that the potential of the ground is quickly raised, and then the raised potential of the ground is coupled to the gate node of the third PMOS transistor by the capacitor, so that the potential of the gate of the third PMOS transistor is quickly raised, the reliability and stability of the anti-coupling unit are improved, and the reliability and stability of the discharging circuit are improved.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic diagram of a VNEG high-voltage discharge circuit of the prior art;

FIG. 2 is a schematic diagram of a discharge circuit of an embodiment of the present invention;

wherein the reference numerals are as follows:

10-discharge unit, 20-anti-coupling unit.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

In one aspect, an embodiment of the present invention provides a discharge circuit, and referring to fig. 2, fig. 2 is a schematic diagram of a discharge circuit according to an embodiment of the present invention, which discharges charges to a negative high-voltage end VNEG of an external energy storage unit S in a high-voltage phase and receives charges stored in the high-voltage phase from the negative high-voltage end VNEG of the energy storage unit in the discharge phase, and the discharge circuit includes: a discharge cell 10, an anti-coupling cell 20, and a power supply VDDI, wherein the discharge cell includes: the transistor comprises a first PMOS tube P1, a second PMOS tube P2, a first NMOS tube N1, a second NMOS tube N2 and a third NMOS tube N3, wherein the first PMOS tube P1, the second PMOS tube P2 and the first NMOS tube N1 are sequentially connected in series, specifically, the drain electrode of the first PMOS tube P1 is connected with the source electrode of the second PMOS tube P2, and the drain electrode of the second PMOS tube P2 is connected with the drain electrode of the first NMOS tube N1. The second NMOS transistor N2 and the third NMOS transistor N3 are connected in series, and specifically, the drain of the second NMOS transistor N2 is connected to the drain of the third NMOS transistor N3. The gate of the third NMOS transistor is connected to the series node NN1 between the second PMOS transistor P2 and the first NMOS transistor N1, the source of the first PMOS transistor P1 is connected to the power supply VDDI, and the gate of the second PMOS transistor P2 is grounded, so that the second PMOS transistor P2 is always in a normally open state, and functions to isolate the first PMOS transistor P1 from the first NMOS transistor N1. The source electrode of the first NMOS transistor N1 and the source electrode of the third NMOS transistor N3 are both connected to the negative high-voltage terminal VNEG of the external energy storage unit.

Further, the anti-coupling unit 20 includes: a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a capacitor C0, and a current source I0, wherein a source of the third PMOS transistor P3, a source of the fourth PMOS transistor P4, and a source of the fifth PMOS transistor P5 are all connected to the power supply VDDI, a drain of the fourth PMOS transistor P4 is connected to one end of the capacitor C0, the other end of the capacitor C0 and a drain of the third PMOS transistor P3 are connected to a source of the second NMOS transistor N2 and a ground terminal GND a50, a gate of the third PMOS transistor P3 is connected to a connection node NG between the fourth PMOS transistor P4 and the capacitor C0, a drain of the fifth PMOS transistor P5, a gate of the fifth PMOS transistor P5, and a gate of the fourth PMOS transistor P4 are all connected to a positive terminal of the current source I0, and a negative terminal GND of the ground terminal 50 of the current source I0.

Wherein the high voltage phase of the discharge circuit is configured to: the gate of the first PMOS transistor P1 and the gate of the first NMOS transistor N1 are set to a high level (e.g., a voltage value of a power supply VDDI), i.e., a high level, discennegb, and the gate of the second NMOS transistor N1 is set to a low level (e.g., 0V), i.e., discenneg, wherein the first PMOS transistor P1 and the second NMOS transistor N2 are turned off, and the first NMOS transistor N1 is turned on, at this time, the gate of the third NMOS transistor N3 may be considered to be equal to the potential of the negative high-voltage terminal VNEG of the external energy storage unit S, and the gate and the source of the third NMOS transistor N3 are equal in potential, i.e., the gate and the source of the third NMOS transistor N3 are shorted, so that the third NMOS transistor N3 is turned off.

Further, the discharging phase of the discharging circuit comprises: a first discharge phase and a second discharge phase, each configured to: the grid electrode of the first PMOS pipe P1 and the grid electrode of the first NMOS pipe N1 are set to be low level, namely, DISENNEGB is set to be low level, and the grid electrode of the second NMOS pipe is set to be high level, namely, DISENNEG is set to be high level.

In the first discharging stage, the first PMOS transistor P1 and the second NMOS transistor N2 are turned on, the negative high voltage VNEG of the external energy storage unit S is discharged dynamically, the gate of the first NMOS transistor N1 is connected to a low level, but the source of the first NMOS transistor N1 is connected to a negative high voltage, so that the first NMOS transistor N1 is turned on, and the power supply VDDI, the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1 and the negative high voltage of the external energy storage unit S form a path. When the negative high voltage output by the negative high voltage end VNEG of the external energy storage unit S is discharged to a trigger voltage value, the first NMOS transistor N1 is turned off, and at this time, the discharge unit enters the second discharge phase. In this embodiment, the trigger voltage is equal to the voltage value of the ground GND a50 minus the turn-on threshold voltage VT (N1) of the first NMOS transistor N1, i.e., the trigger voltage is equal to GND-VT (N1). That is, when the potential of the series node NN1 between the second PMOS transistor P2 and the first NMOS transistor N1 is dynamically adjusted to be greater than a negative VT according to the negative high-voltage terminal VNEG of the external energy storage unit S (at this time, the absolute value of the voltage of the negative high-voltage terminal VNEG of the external energy storage unit S is smaller than VT), then for the first NMOS transistor N1, the gate-source voltage thereof is equal to 0-VNEG, that is, smaller than VT (turn-on threshold voltage), and then the first NMOS transistor N1 is turned off.

When the second discharge phase is entered, since the first NMOS transistor N1 is turned off, the gate potential of the third NMOS transistor N3 is pulled high by the power supply VDDI, so that the third NMOS transistor N3 is turned on, and at this time, the negative high-voltage terminal VNEG of the external energy storage unit S, the third NMOS transistor N3, the second NMOS transistor N2, and the ground terminal GND a50 (i.e., VNEG → N2 → N1 → GNDA50) form a discharge loop. When the negative high voltage output by the negative high voltage terminal VNEG of the external energy storage unit S is discharged to the voltage value of the ground terminal GND a50, because the voltage difference between the two ends of the capacitor C0 cannot suddenly change, the ground terminal GND a50 is coupled through the capacitor C0, the gate potential (NG node) of the third PMOS transistor P3 is pulled down to the potential of the ground terminal GND a50, that is, the gate of the third PMOS transistor P3 is set to a low level, at this time, the gate-source of the third PMOS transistor P3 receives a negative voltage, the third PMOS transistor P3 is turned on, a path is formed between the power supply VDDI, the third PMOS transistor P3 and the ground terminal GND a50, and the power supply VDDI can quickly pull up the potential of the ground terminal GND a50 in the discharge circuit. In this application, ground terminal GND a50 in the return circuit that discharges can pass through condenser C0 coupling, pulls down the potential of NG node, will third PMOS pipe P3 switches on power VDDI form the route between third PMOS pipe P3 and ground terminal GND a50, can pull up the potential of the ground terminal GND a50 that is pulled down by the negative high voltage terminal (VNEG) of the energy storage unit of outside discharges fast, avoids taking place the condition of superhigh pressure breakdown between the potential of ground terminal GND a50 and the positive high voltage VPOS in other circuits to the high voltage breakdown risk of the circuit that positive high voltage VPOS belongs to has been eliminated.

Further, after the potential of the ground GND a50 in the discharge loop is pulled high, the gate potential of the third PMOS transistor P3 is pulled high by the coupling of the capacitor C0, that is, the gate of the third PMOS transistor P3 is set to a high level, and at this time, the third PMOS transistor P3 is turned off. In this embodiment, the gate potential and the drain potential of the fifth PMOS transistor P5 and the gate potential of the fourth PMOS transistor P4 are adjusted by the current source I0, so that the connection node NG between the fourth PMOS transistor P4 and the capacitor C0 has an initial potential, and the third PMOS transistor P3 is kept off at all times during the high voltage phase and the first discharge phase by the initial potential. In this embodiment, the voltage value of the initial potential is equal to the voltage value of the power supply VDDI minus the conduction voltage drop of the fourth PMOS transistor P4. In the present application, through the fifth PMOS transistor P5, the fourth PMOS transistor P4 can be mirrored with a current, so as to ensure that the initial potential of the NG node will not turn on the third PMOS transistor P3. In the second discharging phase, when the potential of the NG node is coupled and pulled down to the potential of the ground terminal GND a50 by the capacitor C0, the third PMOS transistor P3 is quickly turned on, so that the potential of the ground terminal GND a50 is raised, and the raised potential of the ground terminal GND a50 is coupled to the NG node by the capacitor C0, so that the potential of the NG node (the potential of the gate of the third PMOS transistor P3) is quickly raised, thereby improving the reliability and stability of the anti-coupling unit 20, and thus improving the reliability and stability of the discharging circuit.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims

1. A discharge circuit that discharges electric charges to a negative high-voltage terminal of an external energy storage unit in a high-voltage stage and receives the electric charges stored in the high-voltage stage from the negative high-voltage terminal of the energy storage unit in a discharge stage, the discharge circuit comprising: a discharge unit, an anti-coupling unit, and a power supply VDDI, wherein,

2. The discharge circuit of claim 1, wherein the high voltage phase is configured to: the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are set to be at high level, the grid electrode of the second NMOS tube is set to be at low level, the first PMOS tube and the second NMOS tube are turned off, the first NMOS tube is turned on, at the moment, the potential of the grid electrode of the third NMOS tube is equal to the potential of the negative high-voltage end of the external energy storage unit, and the third NMOS tube is turned off.

3. The discharge circuit of claim 2, wherein the discharge phase of the discharge circuit comprises: a first discharge phase and a second discharge phase, each configured to: the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are set to be at a low level, and the grid electrode of the second NMOS tube is set to be at a high level;

4. The discharge circuit of claim 3, wherein the trigger voltage is equal to a ground voltage minus a turn-on threshold voltage of the first NMOS transistor.

5. The discharge circuit of claim 3, wherein in the second discharge phase, the third NMOS transistor is turned on, the negative high voltage terminal of the external energy storage unit, the third NMOS transistor, the second NMOS transistor, and the ground terminal form a discharge loop, when the negative high voltage output from the negative high voltage terminal of the external energy storage unit is discharged to the voltage value of the ground terminal, the gate voltage of the third PMOS transistor is pulled down to the voltage level of the ground terminal through the capacitor, and at this time, the third PMOS transistor is turned on to pull up the voltage level of the ground terminal in the discharge loop through the power supply VDDI; when the potential of the ground end in the discharge loop is pulled high, the grid potential of the third PMOS tube is pulled high through the capacitor, and at the moment, the third PMOS tube is turned off.

6. The discharge circuit of claim 3, wherein the gate potential and the drain potential of the fifth PMOS transistor and the gate potential of the fourth PMOS transistor are adjusted by the current source to make a connection node between the fourth PMOS transistor and the capacitor have an initial potential by which the third PMOS transistor is kept off in the high-voltage phase and the first discharge phase.

7. The discharge circuit of claim 6, wherein the voltage value of the initial potential is equal to the voltage value of the power supply VDDI minus the conduction voltage drop of the fourth PMOS transistor.