CN112928736B - Delay adjustable circuit and lithium battery protection circuit thereof - Google Patents
Delay adjustable circuit and lithium battery protection circuit thereof Download PDFInfo
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- CN112928736B CN112928736B CN202110141855.6A CN202110141855A CN112928736B CN 112928736 B CN112928736 B CN 112928736B CN 202110141855 A CN202110141855 A CN 202110141855A CN 112928736 B CN112928736 B CN 112928736B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/18—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for batteries; for accumulators
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
- H02J7/00304—Overcurrent protection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/007—Regulation of charging or discharging current or voltage
- H02J7/00712—Regulation of charging or discharging current or voltage the cycle being controlled or terminated in response to electric parameters
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- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The invention discloses a delay adjustable circuit and a lithium battery protection circuit thereof, wherein the delay adjustable circuit comprises a voltage-controlled oscillator circuit, a reference circuit, a short-circuit detection circuit, a delay circuit and a switch tube, wherein: the reference circuit is used for generating a reference voltage source and a current source which are not changed along with the voltage inside the chip; the short-circuit detection circuit is used for detecting whether the current at the two ends of the switching tube exceeds a set current value or not; the delay circuit is used for setting the delay of the short circuit detection circuit; the switch tube is used for controlling the on or off of the charge and discharge path; the voltage-controlled oscillator circuit is used for controlling the time delay of the oscillator through the voltage at the VM end. According to the invention, by controlling the charging and discharging speed and time of the second capacitor or the third capacitor, the protection delay is reduced when the short-circuit current is large, the damage of energy accumulation to the switching tube is reduced, and the protection delay is increased when the short-circuit current is small, so that the switching tube is prevented from being triggered and turned off by mistake, and the stability and the reliability of the lithium battery protection circuit are protected.
Description
Technical Field
The invention relates to the technical field of lithium battery protection, in particular to a delay adjustable circuit and a lithium battery protection circuit thereof.
Background
Due to the increasing capacity of lithium batteries and the generation of high-rate lithium batteries, particularly in applications such as smart phones and mobile power supplies, the capacity of the batteries is as high as several thousands of mAH, even tens of thousands of mAH.
In the prior art, when a lithium battery is short-circuited, the short-circuited current can reach dozens of A or even hundreds of A, and the current lithium battery protection chip turns off a discharge path for protection after detecting that the short-circuited current of the lithium battery reaches or exceeds a set value and is delayed by a corresponding delay circuit. Because the fixed time delay is adopted, different short-circuit current protection time is the same after the short-circuit current is exceeded, if the short protection time delay is selected, the short-circuit protection function is easily triggered during the system working, the switching tube is turned off by mistake, and if the long protection time delay is selected, the energy is easily accumulated during the large short-circuit current, the switching tube is burnt out, the function of a lithium battery protection chip is invalid, and the battery is damaged in serious cases.
Disclosure of Invention
In order to solve the problems, the invention provides a delay adjustable circuit and a lithium battery protection circuit thereof, which reduce protection delay during large short-circuit current by controlling the charging and discharging speed and time of a second capacitor or a third capacitor, reduce the damage of energy accumulation to a switching tube, increase protection delay during small short-circuit current, prevent the switching tube from being triggered and turned off by mistake, and protect the stability and reliability of the lithium battery protection circuit.
The technical scheme adopted by the invention is as follows:
the application provides a time delay adjustable circuit, including voltage controlled oscillator circuit, reference circuit, short circuit detection circuitry, delay circuit and switch tube, wherein:
the reference circuit is used for generating a reference voltage source and a current source which are not changed along with the voltage in the chip;
the short-circuit detection circuit is used for detecting whether the current at the two ends of the switching tube exceeds a set current value;
the delay circuit is used for setting the delay of the short circuit detection circuit;
the switch tube is used for controlling the on or off of the charge and discharge passage;
the voltage-controlled oscillator circuit is used for controlling the time delay of the oscillator through the voltage of the VM end.
Preferably, a first input end of the reference circuit is connected to the VDD terminal, a second input end of the reference circuit is connected to the second end of the switch tube, an output end of the reference circuit is connected to the second input end of the short-circuit detection circuit, an output end of the short-circuit detection circuit is connected to the first input end of the delay circuit, and an output end of the delay circuit is connected to the first end of the switch tube;
the voltage-controlled oscillator circuit comprises a voltage-controlled current source circuit and an oscillating circuit, wherein:
the voltage-controlled current source circuit comprises a first MOS tube, a second MOS tube, a third MOS tube and a first current source, wherein the grid electrode of the first MOS tube is connected with a bias voltage end, the source electrode of the first MOS tube is connected with the first input end of the short-circuit detection circuit and the third end of the switch tube, the drain electrode of the first MOS tube is connected with the output end of the first current source, the drain electrode of the second MOS tube, the grid electrode of the second MOS tube and the grid electrode of the third MOS tube, and the source electrode of the second MOS tube is connected with the source electrode of the third MOS tube and then is connected with the grounding end;
The oscillation circuit comprises a fourth MOS tube, a fifth MOS tube, a second capacitor, a second current source, a comparator and a voltage selection circuit, wherein one end of the second capacitor is connected with a source electrode of the fourth MOS tube, a source electrode of the second MOS tube and a source electrode of the third MOS tube, the other end of the second capacitor is connected with a drain electrode of the third MOS tube, a drain electrode of the fifth MOS tube, a same-phase end of the comparator and an input end of the second current source, the source electrode of the fifth MOS tube is connected with an input end of the first current source, a grid electrode of the fifth MOS tube is connected with an output end of the comparator, a grid electrode of the fourth MOS tube and a second end of the voltage selection circuit, the first end of the voltage selection circuit is connected with an inverting end of the comparator, and the third end of the comparator is connected with an enabling end.
Preferably, the voltage selection circuit is further connected with a reference high voltage terminal and a reference low voltage terminal.
The application also provides an improvement scheme, voltage-controlled current source circuit still includes eighth MOS pipe and ninth MOS pipe, the drain electrode of eighth MOS pipe is connected the drain electrode of third MOS pipe, the grid of eighth MOS pipe and the grid of ninth MOS pipe, the input of first current source and the source electrode of ninth MOS pipe are connected to the source electrode of eighth MOS pipe.
Preferably, the oscillation circuit includes a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a third capacitor, a third current source, a fourth current source, a second not gate, a third or gate, and a fourth not gate, where:
the source electrode of the tenth MOS tube is connected with the source electrode of the ninth MOS tube, the source electrode of the eighth MOS tube, the input end of the first current source and the input end of the fourth current source, the grid electrode of the tenth MOS tube is connected with the grid electrode of the eleventh MOS tube and the output end of the third OR gate, and the drain electrode of the tenth MOS tube is connected with the input end of the third current source;
the output end of the third current source is connected with a drain electrode of the ninth MOS tube, one end of a third capacitor, a drain electrode of the eleventh MOS tube and a grid electrode of the twelfth MOS tube, and the other end of the third capacitor is connected with a source electrode of the eleventh MOS tube, a source electrode of the twelfth MOS tube, a source electrode of the third MOS tube and a source electrode of the second MOS tube;
the output end of the fourth current source is connected with the drain electrode of the twelfth MOS transistor and the input end of the second NOT gate, the output end of the second NOT gate is connected with the first input end of the third OR gate and the second input end of the delay circuit, the second input end of the third OR gate is connected with the output end of the fourth NOT gate, and the input end of the fourth NOT gate is connected with the enabling end.
Preferentially, the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the eleventh MOS transistor and the twelfth MOS transistor all adopt N-channel MOS transistors, and the fifth MOS transistor, the eighth MOS transistor, the ninth MOS transistor and the tenth MOS transistor all adopt P-channel MOS transistors.
Based on foretell adjustable circuit of time delay, this application still provides a lithium cell protection circuit, including foretell adjustable circuit of time delay, still include battery, filter circuit and load or charger, wherein:
the positive electrode of the battery is connected with one end of the filter circuit and the positive electrode of the load or the charger, the negative electrode of the battery is connected with the other end of the filter circuit, the second input end of the reference circuit and the second end of the switch tube, and the negative electrode of the load or the charger is connected with the third end of the switch tube, the source electrode of the first MOS tube and the first input end of the short-circuit detection circuit; the filter circuit is used for absorbing peak voltage, reducing interference and providing signals with high signal-to-noise ratio for the delay adjustable circuit.
Preferably, the filter circuit includes a first resistor and a first capacitor, one end of the first resistor is connected to the positive electrode of the battery and the positive electrode of the load or the charger, the other end of the first resistor is connected to the VDD terminal, the first input terminal of the reference circuit and one end of the first capacitor, and the other end of the first capacitor is connected to the negative electrode of the battery, the second input terminal of the reference circuit and the second terminal of the switch tube.
Based on the lithium battery protection circuit, the application also provides a lithium battery protection chip which comprises the lithium battery protection circuit.
The invention has the beneficial effects that:
1. the current of the third MOS tube is influenced by the source voltage of the first MOS tube, and the on-off of the fourth MOS tube and the fifth MOS tube is controlled by the output end voltage of the comparator, so that the charging or discharging speed of the second capacitor is controlled, the change of the oscillation period time is realized, the time delay protection of a longer time is generated when the current is small, and the time delay protection of a shorter time is generated when the current is large;
2. the improved voltage-controlled current source circuit is provided with an eighth MOS transistor and a ninth MOS transistor which form a mirror current source, the slow charging time and the charging and discharging speed of the third capacitor are mainly controlled through the third current source, when the ninth MOS transistor has current, the charging speed of the third capacitor is accelerated, and the corresponding charging time is reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a circuit diagram of a voltage controlled oscillator circuit of the present invention;
Fig. 2 is a circuit diagram of another voltage controlled oscillator circuit of the present invention;
fig. 3 is a circuit diagram of a lithium battery protection circuit of the present invention.
Labeled in the figure as: 1. the circuit comprises a delay adjustable circuit, 11 a reference circuit, 12 a short-circuit detection circuit, 13 a delay circuit, 14 a voltage-controlled oscillator circuit, 141 a voltage-controlled current source circuit, 142 an oscillating circuit, 15 a switch tube, 2 a battery, 3 a filter circuit and 4 a load or a charger.
Detailed Description
Example one
As shown in fig. 3, the present application provides a delay adjustable circuit, which includes a voltage-controlled oscillator circuit 14, a reference circuit 11, a short circuit detection circuit 12, a delay circuit 13, and a switch tube 15, wherein:
the reference circuit 11 is used for generating a reference voltage source and a current source which do not change with the voltage inside the chip, a first input end of the reference circuit 11 is connected with a VDD end, a second input end of the reference circuit 11 is connected with a second end of the switch tube 15, and an output end of the reference circuit 11 is connected with a second input end of the short-circuit detection circuit 12.
The short-circuit detection circuit 12 is used for detecting whether the current at the two ends of the switching tube 15 exceeds a set current value, and the output end of the short-circuit detection circuit 12 is connected with the first input end of the delay circuit 13.
The delay circuit 13 is used for setting the delay of the short circuit detection circuit 12, and the output end of the delay circuit 13 is connected with the first end of the switch tube 15.
The switch tube 15 is used for controlling the on/off of the charge/discharge path.
As shown in fig. 1, the voltage-controlled oscillator circuit 14 is used for controlling the delay of the oscillator by the voltage at the VM end, and the voltage-controlled oscillator circuit 14 includes a voltage-controlled current source circuit 141 and an oscillation circuit 142, where:
as shown in fig. 1, the voltage-controlled current source circuit 141 includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, and a first current source Idc1, a gate of the first MOS transistor M1 is connected to the bias voltage terminal VBIAS, a source of the first MOS transistor M1 is connected to the first input terminal of the short-circuit detection circuit 12 and the third terminal of the switch tube 15, a drain of the first MOS transistor M1 is connected to the output terminal of the first current source Idc1, the drain of the second MOS transistor M2, the gate of the second MOS transistor M2, and the gate of the third MOS transistor M3, and a source of the second MOS transistor M2 is connected to the ground after being connected to the source of the third MOS transistor M3.
As shown in fig. 1, when the current flowing through the switching transistor 15 is small, the voltage at the VM terminal is approximately equal to the voltage at the ground terminal, at this time, the gate-source voltage Vgs of the first MOS transistor M1 is large, the current capability of the first MOS transistor M1 is large, since the current capability of the first current source Idc1 remains unchanged, the current flowing through the second MOS transistor M2 is small or zero, and the current flowing through the third MOS transistor M3 is small or zero, the frequency of the oscillation circuit 142 is less affected or zero;
As shown in fig. 1, when the current flowing through the switching transistor 15 is large, the voltage at the VM terminal is greater than the voltage at the ground terminal, the gate-source voltage Vgs of the first MOS transistor M1 is small, and the current capability of the first MOS transistor M1 is small, then the current flowing through the second MOS transistor M2 is greater than or equal to the first current source Idc1, and the current flowing through the third MOS transistor M3 is greater than or equal to N times the first current source Idc1, where the multiple depends on the width-to-length ratio of the third MOS transistor M3 to the second MOS transistor M2.
As shown in fig. 1, the oscillation circuit 142 includes a fourth MOS transistor M4, a fifth MOS transistor M5, a second capacitor C2, a second current source Idc2, a comparator COMP, and a voltage selection circuit MUX, one end of the second capacitor C2 is connected to the source of the fourth MOS transistor M4, the source of the second MOS transistor M2, and the source of the third MOS transistor M3, the other end of the second capacitor C2 is connected to the drain of the third MOS transistor M3, the drain of the fifth MOS transistor M5, the non-inverting terminal of the comparator COMP, and the input end of the second current source Idc2, the source of the fifth MOS transistor M5 is connected to the input end of the first current source Idc1, the gate of the fifth MOS transistor M5 is connected to the output end of the comparator COMP, the gate of the fourth MOS transistor M4, and the second end of the voltage selection circuit MUX, the first end of the voltage selection circuit MUX is connected to the inverting terminal of the comparator COMP, the voltage selection circuit VrefH and the reference terminal of the low-side of the comparator COMP, the first MOS transistor M1 to the fourth MOS transistor M4 adopt N-channel MOS transistors, and the fifth MOS transistor M5 adopts P-channel MOS transistors.
As shown in fig. 1, when the enable terminal EN is low, the comparator COMP does not operate, the output terminal OUT of the comparator COMP is at a low level, and the fifth MOS transistor M5 is controlled to be turned on, and the fourth MOS transistor M4 is controlled to be turned off. When the enable end EN is high, the comparator COMP starts to operate normally, because the voltage of the non-inverting end of the comparator COMP is higher than the voltage of the inverting end, the output end OUT of the comparator COMP is high, the fifth MOS transistor M5 is turned off, the fourth MOS transistor M4 is turned on, the voltage selection circuit MUX selects the reference low voltage end VrefL to output to the inverting end of the comparator COMP, the second capacitor C2 starts to discharge slowly, and when the voltage of the second capacitor C2 is lower than the reference low voltage end VrefL, the output end OUT of the comparator COMP is low; when the output end OUT of the comparator COMP is low, the fifth MOS transistor M5 is turned on, the fourth MOS transistor M4 is turned off, the voltage selection circuit MUX selects the reference high voltage end VrefH to output to the non-inverting end of the comparator COMP, the second capacitor C2 starts to charge, and when the voltage of the second capacitor C2 is higher than the reference high voltage end VrefH, the output end of the comparator COMP is high; as described above, the output terminal OUT of the comparator COMP cyclically outputs a high level and a low level.
As shown in fig. 3, based on the above delay adjustable circuit 1, the present application further provides a lithium battery protection circuit, which includes the above delay adjustable circuit 1, and further includes a battery 2, a filter circuit 3, and a load or charger 4, where:
The positive pole of the battery 2 is connected with one end of the filter circuit 3 and the positive pole P + of the load or charger 4, the negative pole of the battery 2 is connected with the other end of the filter circuit 3, the second input end of the reference circuit 11 and the second end of the switch tube 15, and the negative pole P-of the load or charger 4 is connected with the third end of the switch tube 15, the source electrode of the first MOS tube M1 and the first input end of the short-circuit detection circuit 12.
As shown in fig. 3, the filter circuit 3 is configured to absorb a peak voltage, reduce interference, and provide a signal with a high signal-to-noise ratio for the delay adjustable circuit 1, the filter circuit 3 includes a first resistor R1 and a first capacitor C1, one end of the first resistor R1 is connected to the positive electrode of the battery 2 and the positive electrode P + of the load or charger 4, the other end of the first resistor R1 is connected to the VDD terminal, the first input terminal of the reference circuit 11 and one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the negative electrode of the battery 2, the second input terminal of the reference circuit 11 and the second terminal of the switching tube 15.
Based on the lithium battery protection circuit, the application also provides a lithium battery protection chip which comprises the lithium battery protection circuit.
The lithium battery protection circuit shown in fig. 3 can also be applied to a positive lithium battery protection circuit and a protection system thereof, a multi-section lithium battery protection circuit and a protection system thereof, and a circuit in which a switching tube 15 is connected with a sampling resistor in series, wherein the sampling resistor is used for detecting current, and the lithium battery protection circuit has a short-circuit protection function, and also has a charging overcurrent protection function and a discharging overcurrent protection function.
Example two
As shown in fig. 2, the present embodiment is different from the first embodiment in that: the present application also provides an improvement to voltage controlled oscillator circuit 14, wherein: the voltage-controlled current source circuit 141 further includes an eighth MOS transistor M8 and a ninth MOS transistor M9, a drain of the eighth MOS transistor M8 is connected to a drain of the third MOS transistor M3, a gate of the eighth MOS transistor M8 and a gate of the ninth MOS transistor M9, and a source of the eighth MOS transistor M8 is connected to an input terminal of the first current source Idc1 and a source of the ninth MOS transistor M9.
As shown in fig. 2, when the current flowing through the switching transistor 15 is small, the voltage at the VM terminal is approximately equal to the voltage at the ground terminal, at this time, the gate-source voltage Vgs of the first MOS transistor M1 is large, the current capability of the first MOS transistor M1 is large, and since the current capability of the first current source Idc1 is maintained, the current flowing through the second MOS transistor M2 is small or zero, the current flowing through the third MOS transistor M3, the eighth MOS transistor M8, and the ninth MOS transistor M9 is small or zero, and the influence on the frequency of the oscillation circuit 142 is small or zero.
As shown in fig. 2, when the current flowing through the switching tube 15 is large, the voltage at the VM terminal is greater than the voltage at the ground terminal, the gate-source voltage Vgs of the first MOS transistor M1 is small, the current capability of the first MOS transistor M1 is small, the current flowing through the second MOS transistor M2 is greater than or equal to the first current source Idc1, the current flowing through the third MOS transistor M3, the eighth MOS transistor M8, and the ninth MOS transistor M9 is greater than or equal to N times the first current source Idc1, and the current times depend on the width-length ratio of the third MOS transistor M3 to the second MOS transistor M2 and the width-length ratio of the ninth MOS transistor M9 to the eighth MOS transistor M8.
As shown in fig. 2, the oscillation circuit 142 includes a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a third capacitor C3, a third current source Idc3, a fourth current source Idc4, a second not gate I2, a third or gate I3, and a fourth not gate I4, where:
a source of the tenth MOS transistor M10 is connected to a source of the ninth MOS transistor M9, a source of the eighth MOS transistor M8, an input end of the first current source Idc1, and an input end of the fourth current source Idc4, a gate of the tenth MOS transistor M10 is connected to a gate of the eleventh MOS transistor M11 and an output end of the third or gate I3, and a drain of the tenth MOS transistor M10 is connected to an input end of the third current source Idc 3; the output end of the third current source Idc3 is connected with the drain of the ninth MOS transistor M9, one end of a third capacitor C3, the drain of the eleventh MOS transistor M11 and the gate of the twelfth MOS transistor M12, and the other end of the third capacitor C3 is connected with the source of the eleventh MOS transistor M11, the source of the twelfth MOS transistor M12, the source of the third MOS transistor M3 and the source of the second MOS transistor M2; an output end of the fourth current source Idc4 is connected to the drain of the twelfth MOS transistor M12 and an input end of the second not gate I2, an output end of the second not gate I2 is connected to a first input end of the third or gate I3 and a second input end of the delay circuit 13, a second input end of the third or gate I3 is connected to an output end of the fourth not gate I4, and an input end of the fourth not gate I4 is connected to the enable end EN. As shown in fig. 2, the eleventh MOS transistor M11 and the twelfth MOS transistor M12 both employ N-channel MOS transistors, and the eighth MOS transistor M8, the ninth MOS transistor M9 and the tenth MOS transistor M10 all employ P-channel MOS transistors.
As shown in fig. 2, when the enable terminal EN is at a low level, the output of the fourth not gate I4 is high, the eleventh MOS transistor M11 is turned on, the tenth MOS transistor M10 is turned off, the gate of the twelfth MOS transistor M12 is at a low level, and the oscillation circuit 142 does not operate; when the enable terminal EN is at a high level, the output of the fourth not gate I4 is low, and the gate of the twelfth MOS transistor M12 is low, the drain voltage of the twelfth MOS transistor M12 is high, the output terminal OUT of the oscillation circuit 142 is low, the eleventh MOS transistor M11 is turned off, the tenth MOS transistor M10 is turned on, and the gate voltage of the twelfth MOS transistor M12 is pulled high; when the gate voltage of the twelfth MOS transistor M12 is high, the drain voltage of the twelfth MOS transistor M12 is low, the output terminal voltage of the second not gate I2 is high, the eleventh MOS transistor M11 is turned on, and the gate voltage of the twelfth MOS transistor M12 is pulled low, so that the oscillation is performed cyclically.
As shown in fig. 2, in this embodiment, mainly the third current source Idc3 charges the third capacitor C3 slowly, and when the ninth MOS transistor M9 has a current, the charging speed of the third capacitor C3 is increased, and the corresponding charging time is reduced. When the voltage of the third capacitor C3 is higher than the threshold voltage Vth of the twelfth MOS transistor M12, the drain voltage output of the twelfth MOS transistor M12 is low, the output terminal OUT of the oscillator circuit 142 is high, the tenth MOS transistor M10 is turned off, the charging path of the third capacitor C3 is turned off, the eleventh MOS transistor M11 is turned on, and the voltage of the third capacitor C3 is pulled to 0V quickly. When the voltage of the third capacitor C3 is 0V, it is lower than the threshold voltage Vth of the twelfth MOS transistor M12, the drain voltage output of the twelfth MOS transistor M12 is high, the output of the output terminal OUT of the oscillation circuit 142 is low, the eleventh MOS transistor M11 is turned off, the tenth MOS transistor M10 is turned on, and the third capacitor C3 starts to be charged slowly again.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A delay adjustable circuit, characterized in that: including voltage controlled oscillator circuit, reference circuit, short-circuit detection circuit, delay circuit and switch tube, wherein:
the reference circuit is used for generating a reference voltage source and a current source which are not changed along with the voltage in the chip;
the short-circuit detection circuit is used for detecting whether the current at the two ends of the switching tube exceeds a set current value;
the delay circuit is used for setting the delay of the short circuit detection circuit;
the switch tube is used for controlling the on or off of the charge and discharge passage;
the voltage-controlled oscillator circuit is used for controlling the time delay of the oscillator through the voltage of the VM end; the first input end of the reference circuit is connected with a VDD end, the second input end of the reference circuit is connected with the second end of the switch tube, the output end of the reference circuit is connected with the second input end of the short-circuit detection circuit, the output end of the short-circuit detection circuit is connected with the first input end of the delay circuit, and the output end of the delay circuit is connected with the first end of the switch tube;
The voltage-controlled oscillator circuit comprises a voltage-controlled current source circuit and an oscillating circuit, wherein:
the voltage-controlled current source circuit comprises a first MOS tube, a second MOS tube, a third MOS tube and a first current source, wherein the grid electrode of the first MOS tube is connected with a bias voltage end, the source electrode of the first MOS tube is connected with the first input end of the short-circuit detection circuit and the third end of the switch tube, the drain electrode of the first MOS tube is connected with the output end of the first current source, the drain electrode of the second MOS tube, the grid electrode of the second MOS tube and the grid electrode of the third MOS tube, and the source electrode of the second MOS tube is connected with the ground end after being connected with the source electrode of the third MOS tube;
the oscillation circuit comprises a fourth MOS tube, a fifth MOS tube, a second capacitor, a second current source, a comparator and a voltage selection circuit, wherein one end of the second capacitor is connected with a source electrode of the fourth MOS tube, a source electrode of the second MOS tube and a source electrode of the third MOS tube, the other end of the second capacitor is connected with a drain electrode of the third MOS tube, a drain electrode of the fifth MOS tube, a same-phase end of the comparator and an input end of the second current source, the source electrode of the fifth MOS tube is connected with an input end of the first current source, a grid electrode of the fifth MOS tube is connected with an output end of the comparator, a grid electrode of the fourth MOS tube and a second end of the voltage selection circuit, the first end of the voltage selection circuit is connected with an inverting end of the comparator, and the third end of the comparator is connected with an enabling end.
2. A delay adjustable circuit, characterized in that: including voltage controlled oscillator circuit, reference circuit, short-circuit detection circuit, delay circuit and switch tube, wherein:
the reference circuit is used for generating a reference voltage source and a current source which are not changed along with the voltage in the chip;
the short-circuit detection circuit is used for detecting whether the current at the two ends of the switching tube exceeds a set current value or not;
the delay circuit is used for setting the delay of the short circuit detection circuit;
the switch tube is used for controlling the on or off of the charge and discharge passage;
the voltage-controlled oscillator circuit is used for controlling the time delay of the oscillator through the voltage of the VM end; the first input end of the reference circuit is connected with a VDD end, the second input end of the reference circuit is connected with the second end of the switch tube, the output end of the reference circuit is connected with the second input end of the short-circuit detection circuit, the output end of the short-circuit detection circuit is connected with the first input end of the delay circuit, and the output end of the delay circuit is connected with the first end of the switch tube;
the voltage-controlled oscillator circuit comprises a voltage-controlled current source circuit and an oscillating circuit, wherein:
the voltage-controlled current source circuit comprises a first MOS tube, a second MOS tube, a third MOS tube and a first current source, wherein the grid electrode of the first MOS tube is connected with a bias voltage end, the source electrode of the first MOS tube is connected with the first input end of the short-circuit detection circuit and the third end of the switch tube, the drain electrode of the first MOS tube is connected with the output end of the first current source, the drain electrode of the second MOS tube, the grid electrode of the second MOS tube and the grid electrode of the third MOS tube, and the source electrode of the second MOS tube is connected with the ground end after being connected with the source electrode of the third MOS tube;
The oscillation circuit comprises a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a third capacitor, a third current source, a fourth current source, a second NOT gate, a third OR gate and a fourth NOT gate, wherein:
the source electrode of the tenth MOS tube is connected with the source electrode of the ninth MOS tube, the source electrode of the eighth MOS tube, the input end of the first current source and the input end of the fourth current source, the grid electrode of the tenth MOS tube is connected with the grid electrode of the eleventh MOS tube and the output end of the third OR gate, and the drain electrode of the tenth MOS tube is connected with the input end of the third current source;
the output end of the third current source is connected with the drain electrode of the ninth MOS tube, one end of a third capacitor, the drain electrode of the eleventh MOS tube and the grid electrode of the twelfth MOS tube, and the other end of the third capacitor is connected with the source electrode of the eleventh MOS tube, the source electrode of the twelfth MOS tube, the source electrode of the third MOS tube and the source electrode of the second MOS tube;
the output end of the fourth current source is connected with the drain electrode of the twelfth MOS tube and the input end of the second NOT gate, the output end of the second NOT gate is connected with the first input end of the third OR gate and the second input end of the delay circuit, the second input end of the third OR gate is connected with the output end of the fourth NOT gate, and the input end of the fourth NOT gate is connected with the enabling end; the voltage-controlled current source circuit further comprises an eighth MOS tube and a ninth MOS tube, wherein the drain electrode of the eighth MOS tube is connected with the drain electrode of the third MOS tube, the grid electrode of the eighth MOS tube and the grid electrode of the ninth MOS tube, and the source electrode of the eighth MOS tube is connected with the input end of the first current source and the source electrode of the ninth MOS tube.
3. The delay adjustable circuit of claim 1 or 2, wherein: the voltage selection circuit is also connected with a reference high-voltage end and a reference low-voltage end.
4. The delay tunable circuit of claim 1, wherein: the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are all N-channel MOS tubes.
5. The delay tunable circuit of claim 2, wherein: and the eleventh MOS tube and the twelfth MOS tube both adopt N-channel MOS tubes, and the fifth MOS tube, the eighth MOS tube, the ninth MOS tube and the tenth MOS tube all adopt P-channel MOS tubes.
6. A lithium battery protection circuit is characterized in that: the delay tunable circuit of any one of claims 1 to 5, further comprising a battery, a filter circuit, and a load or charger, wherein:
the positive electrode of the battery is connected with one end of the filter circuit and the positive electrode of the load or the charger, the negative electrode of the battery is connected with the other end of the filter circuit, the second input end of the reference circuit and the second end of the switch tube, and the negative electrode of the load or the charger is connected with the third end of the switch tube, the source electrode of the first MOS tube and the first input end of the short-circuit detection circuit; the filter circuit is used for absorbing peak voltage, reducing interference and providing signals with high signal-to-noise ratio for the delay adjustable circuit.
7. The lithium battery protection circuit according to claim 6, wherein: the filter circuit comprises a first resistor and a first capacitor, one end of the first resistor is connected with the positive pole of the battery and the positive pole of the load or the charger, the other end of the first resistor is connected with the VDD end, the first input end of the reference circuit and one end of the first capacitor, and the other end of the first capacitor is connected with the negative pole of the battery, the second input end of the reference circuit and the second end of the switch tube.
8. A lithium battery protection chip is characterized in that: a lithium battery protection circuit comprising a lithium battery according to any one of claims 6-7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110141855.6A CN112928736B (en) | 2021-02-02 | 2021-02-02 | Delay adjustable circuit and lithium battery protection circuit thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110141855.6A CN112928736B (en) | 2021-02-02 | 2021-02-02 | Delay adjustable circuit and lithium battery protection circuit thereof |
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| CN112928736B true CN112928736B (en) | 2022-06-28 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113241940B (en) * | 2021-07-12 | 2021-09-10 | 上海芯龙半导体技术股份有限公司 | Overcurrent protection circuit and switching power supply chip |
| CN114237079B (en) * | 2021-09-30 | 2024-04-30 | 宁波三星智能电气有限公司 | Circuit capable of utilizing serial port to turn off power supply |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101282036A (en) * | 2008-05-29 | 2008-10-08 | 北京中星微电子有限公司 | Overcurrent protection circuit for discharging electricity |
| CN209805407U (en) * | 2019-03-19 | 2019-12-17 | 浙江大华技术股份有限公司 | Short-circuit protection circuit |
| CN111463847A (en) * | 2020-03-09 | 2020-07-28 | 深圳市创芯微微电子有限公司 | Battery protection chip and battery protection board |
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2021
- 2021-02-02 CN CN202110141855.6A patent/CN112928736B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101282036A (en) * | 2008-05-29 | 2008-10-08 | 北京中星微电子有限公司 | Overcurrent protection circuit for discharging electricity |
| CN209805407U (en) * | 2019-03-19 | 2019-12-17 | 浙江大华技术股份有限公司 | Short-circuit protection circuit |
| CN111463847A (en) * | 2020-03-09 | 2020-07-28 | 深圳市创芯微微电子有限公司 | Battery protection chip and battery protection board |
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