CN112398096B - Lithium battery protection circuit with ultra-low power consumption - Google Patents

Lithium battery protection circuit with ultra-low power consumption Download PDF

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Publication number
CN112398096B
CN112398096B CN202110079344.6A CN202110079344A CN112398096B CN 112398096 B CN112398096 B CN 112398096B CN 202110079344 A CN202110079344 A CN 202110079344A CN 112398096 B CN112398096 B CN 112398096B
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circuit
gate
trigger
lithium battery
voltage
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CN112398096A (en
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蒋锦茂
崔国庆
龚坤林
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Suzhou Saixin Electronic Technology Co ltd
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Suzhou Saixin Electronic Technology Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/18—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for batteries; for accumulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/00302—Overcharge protection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/00304—Overcurrent protection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/00306—Overdischarge protection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/0031—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using battery or load disconnect circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0068—Battery or charger load switching, e.g. concurrent charging and load supply

Abstract

The invention discloses a lithium battery protection circuit with ultra-low power consumption, which comprises a battery, a filter circuit, a lithium battery protection chip and a charger or a load, wherein: lithium cell protection chip includes square wave generating circuit, first OR gate, reference circuit, detection circuitry, drive circuit, switch tube, wherein: the square wave generating circuit is used for generating square wave signals and controlling the working time of the reference circuit and the detection circuit; the reference circuit is used for generating voltage and current which are not changed along with the voltage in the lithium battery protection chip; the detection circuit is used for judging the working state of the lithium battery protection chip, wherein the working state comprises a normal state, an overcharging voltage state, an overdischarging voltage state, a discharging overcurrent state and a charging overcurrent state; the driving circuit is used for controlling the switching tube to be switched on or switched off according to a switching signal generated in the lithium battery protection chip. When the lithium battery protection circuit works normally, at least part of circuits are started at intervals to reduce the average current consumed by the lithium battery protection circuit.

Description

Lithium battery protection circuit with ultra-low power consumption
Technical Field
The invention relates to the technical field of lithium battery protection, in particular to a lithium battery protection circuit with ultra-low power consumption.
Background
With the development of the electronic technology in the twentieth century, the lithium battery enters a large-scale practical stage, the number of miniaturized devices is increasing, and the capacity of the lithium battery is required to be smaller and smaller, and especially in applications such as TWS (two way switching) and smart bracelet watches, the capacity of the lithium battery may be only dozens of mAH (small area antenna impedance), even as low as a few mAH (small area antenna impedance).
In the prior art, the lithium battery protection circuit can be divided into 4 modules: reference circuit, detection circuitry, drive circuit, switch tube. The driving circuit is a logic control circuit and does not consume current when in normal work; the switch tube is an MOS tube, and does not consume current when being stably switched on or switched off. The modules consuming current are therefore the reference circuit and the detection circuit. After lithium cell and lithium battery protection chip are connected, the current of lithium cell is just being consumed always to lithium battery protection chip, because the capacity of lithium cell is more and more littleer, then requires that the operating current of lithium battery protection chip is more and more littleer, otherwise leads to the voltage drop of lithium cell too fast easily, leads to the capacity of battery to descend, influences customer's experience, influences the performance and the life-span of battery when serious.
Disclosure of Invention
In order to solve the problems, the invention provides a lithium battery protection circuit with ultra-low power consumption, and the current consumed by lithium battery protection is reduced by starting the circuit at intervals during normal operation.
The technical scheme adopted by the invention is as follows:
the application provides lithium battery protection circuit of ultra-low power consumption, including battery, filter circuit, lithium battery protection chip and charger or load, wherein:
lithium cell protection chip includes square wave generating circuit, first OR gate, reference circuit, detection circuitry, drive circuit and switch tube, wherein:
the square wave generating circuit is used for generating a square wave signal and controlling the working time of at least one module in the reference circuit or the detection circuit;
the reference circuit is used for generating voltage or current which does not change along with the voltage;
the detection circuit is used for judging the working state of the lithium battery protection chip, and the working state comprises a normal state, an overcharging voltage state, an overdischarging voltage state, a discharging overcurrent state, a charging overcurrent state and other working states;
the drive circuit is used for controlling the switching tube to be switched on or switched off according to a switching signal generated in the lithium battery protection chip;
the switch tube is used for controlling the charging or discharging of the battery.
Preferably, the output end of the square wave generating circuit is connected with the first input end of the first or gate;
the reference circuit comprises a plurality of output ends, wherein the output ends comprise a VOC1 end, a VCHOC end, a VOCV end and a VODV end;
the detection circuit comprises a discharge overcurrent judgment circuit, a charge overcurrent judgment circuit, an over-discharge voltage judgment circuit, an over-charge voltage judgment circuit, a first delay circuit, a second delay circuit, a third delay circuit, a fourth delay circuit, a second resistor, a third resistor, a fourth resistor, a second NOT gate, a third NAND gate, a fourth AND gate and a PMOS (P-channel metal oxide semiconductor) tube, wherein:
the source electrode of the PMOS tube is connected with a VDD end, the drain electrode of the PMOS tube is connected with one end of a second resistor, the grid electrode of the PMOS tube is connected with the output end of a second NOT gate, and the input end of the second NOT gate is connected with an enabling end and then connected with a discharging overcurrent judging circuit, a charging overcurrent judging circuit, a discharging voltage judging circuit and an overcharging voltage judging circuit;
the other end of the second resistor is connected with one end of a third resistor and the in-phase end of the over-charging voltage judging circuit, the other end of the third resistor is connected with one end of a fourth resistor and the reverse-phase end of the over-charging voltage judging circuit, and the other end of the fourth resistor is connected with a grounding end;
the in-phase end of the discharge overcurrent judging circuit is connected with the VOC1 end of the reference circuit, the inverting end of the discharge overcurrent judging circuit is connected with the in-phase end of the charge overcurrent judging circuit, the negative electrode of the charger or the load and the third end of the switch tube, the inverting end of the charge overcurrent judging circuit is connected with the VCHOC end of the reference circuit, the inverting end of the over-discharge voltage judging circuit is connected with the VODV end of the reference circuit, the in-phase end of the over-charge voltage judging circuit is connected with the VOCV end of the reference circuit, the output end of the discharge overcurrent judging circuit is connected with the input end of the fourth delay circuit and the first input end of the third NAND gate, the output end of the charge overcurrent judging circuit is connected with the input end of the third delay circuit and the second input end of the third NAND gate, and the output end of the over-discharge voltage judging circuit is connected with the input end of the second delay circuit and the third input end of the third, the output end of the overcharge voltage judgment circuit is connected with the input end of the first delay circuit and the fourth input end of the third NAND gate;
the output end of the fourth delay circuit, the output end of the third delay circuit, the output end of the second delay circuit and the output end of the first delay circuit are all connected with the input end of a fourth AND gate;
the output end of the third NAND gate is connected with the second input end of the first OR gate, the output end of the fourth AND gate is connected with the input end of the driving circuit, the output end of the driving circuit is connected with the first end of the switch tube, the output end of the first OR gate is connected with the enabling end of the detection circuit and the first input end of the reference circuit, and the reference circuit and the detection circuit are controlled by the square wave generation circuit.
The invention also provides an improved scheme that the connection between the enabling end of the detection circuit and the first input end of the reference circuit is disconnected, namely only the detection circuit is controlled by the square wave generation circuit.
Preferably, the discharge overcurrent determination circuit, the charge overcurrent determination circuit, the over-discharge voltage determination circuit, and the overcharge voltage determination circuit all employ comparators.
Preferably, the filter circuit includes a first resistor and a first capacitor, the positive electrode of the battery is connected with one end of the first resistor and the positive electrode of the charger or the load, the other end of the first resistor is connected with one end of the first capacitor, the VDD terminal and the second input terminal of the reference circuit, and the other end of the first capacitor is connected with the third input terminal of the reference circuit, the ground terminal of the detection circuit and the second terminal of the switching tube.
Preferably, the square wave generating circuit includes an eighth flip-flop, a ninth flip-flop, a tenth flip-flop, an eleventh flip-flop, a thirteenth and gate, a twelfth nand gate, a fifth not gate, a sixth not gate, a seventh not gate, a second capacitor, and a third capacitor, wherein:
the D end of the eighth trigger is connected with the Q-not end of the eighth trigger, the clock end of the eighth trigger is connected with the input end of the fifth not gate and the output end of the seventh not gate, and the Q end of the eighth trigger is connected with the clock end of the ninth trigger and the first input end of the thirteenth and gate; the D end of the ninth flip-flop is connected with the Q-not end of the ninth flip-flop, and the Q end of the ninth flip-flop is connected with the clock end of the tenth flip-flop and the first input end of the twelfth NAND gate; the D end of the tenth trigger is connected with the Q-not end of the tenth trigger, and the Q end of the tenth trigger is connected with the clock end of the eleventh trigger; the D end of the eleventh trigger is connected with the Q-not end of the eleventh trigger, the Q end of the eleventh trigger is connected with the second input end of the thirteenth AND gate and the second input end of the twelfth NAND gate, and the reset end of the eighth trigger, the reset end of the ninth trigger, the reset end of the tenth trigger and the reset end of the eleventh trigger are connected with the output end of the twelfth NAND gate after being connected.
Preferably, the output end of the fifth not gate is connected to the input end of the sixth not gate and one end of the second capacitor, the output end of the sixth not gate is connected to the input end of the seventh not gate and one end of the third capacitor, and the other end of the second capacitor is connected to the ground after being connected to the other end of the third capacitor.
Preferably, the eighth flip-flop, the ninth flip-flop, the tenth flip-flop and the eleventh flip-flop are all triggered at a high level.
The invention has the beneficial effects that: the square wave generating circuit is additionally arranged, the square wave circuit is used for generating a square wave signal, when the square wave signal is high, the reference circuit and the detection circuit are controlled to work and consume current, when the square wave signal is low, the reference circuit and the detection circuit do not work and do not consume current, and therefore the purpose of ultralow average power consumption is achieved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a circuit diagram of a lithium battery protection circuit of the present invention;
FIG. 2 is a circuit diagram of another lithium battery protection circuit of the present invention;
FIG. 3 is a circuit diagram of the detection circuit of the present invention;
fig. 4 is a circuit diagram of a square wave generating circuit of the present invention.
Labeled as: 1. the lithium battery charging circuit comprises a battery, 2, a filter circuit, 3, a square wave generating circuit, 4, a reference circuit, 5, a detection circuit, 51, a discharging overcurrent judging circuit, 52, a charging overcurrent judging circuit, 53, an overdischarging voltage judging circuit, 54, an overcharging voltage judging circuit, 55, a first delay circuit, 56, a second delay circuit, 57, a third delay circuit, 58, a fourth delay circuit, 6, a driving circuit, 7, a switching tube, 8, a charger or a load and 9, and a lithium battery protecting chip.
Detailed Description
Example one
As shown in fig. 1, the present application provides an ultra-low power consumption lithium battery protection circuit, which includes a battery 1, a filter circuit 2, a lithium battery protection chip 9, and a charger or load 8, wherein:
the filter circuit 2 comprises a first resistor R1 and a first capacitor C1, the positive pole of the battery 1 is connected with one end of the first resistor R1 and the positive pole P + of the charger or the load 8, the other end of the first resistor R1 is connected with one end of the first capacitor C1, the VDD end and the second input end of the reference circuit 4, and the other end of the first capacitor C1 is connected with the third input end of the reference circuit 4, the grounding end of the detection circuit 5 and the second end of the switch tube 7.
The lithium battery protection chip 9 comprises a square wave generating circuit 3, a first or gate I1, a reference circuit 4, a detection circuit 5, a driving circuit 6 and a switch tube 7, wherein:
the square wave generating circuit 3 is used for generating a square wave signal and controlling the working time of the reference circuit 4 or the detection circuit 5, and the output end of the square wave generating circuit 3 is connected with the first input end of the first or gate I1.
The reference circuit 4 is used for generating voltage and current which are not changed along with the voltage, and the reference circuit 4 comprises a plurality of output ends, wherein the output ends comprise a VOC1 end, a VCHOC end, a VOCV end and a VODV end.
The detection circuit 5 is used for judging the working state of the lithium battery protection chip 9, wherein the working state comprises a normal state, an overcharging voltage state, an overdischarging voltage state, a discharging overcurrent state, a charging overcurrent state and other working states; the detection circuit 5 includes a discharging overcurrent determination circuit 51, a charging overcurrent determination circuit 52, an overdischarging voltage determination circuit 53, an overcharging voltage determination circuit 54, a first delay circuit 55, a second delay circuit 56, a third delay circuit 57, a fourth delay circuit 58, a second resistor R2, a third resistor R3, a fourth resistor R4, a second not gate I2, a third nand gate I3, a fourth and gate I4, and a PMOS transistor M1, the discharging overcurrent determination circuit 51, the charging overcurrent determination circuit 52, the overdischarging voltage determination circuit 53, and the overcharging voltage determination circuit 54 all employ comparators, wherein:
the source of the PMOS transistor M1 is connected to the VDD terminal, the drain of the PMOS transistor M1 is connected to one end of the second resistor R2, the gate of the PMOS transistor M1 is connected to the output terminal of the second not gate I2, and the input terminal of the second not gate I2 is connected to the enable terminal EN and then connected to the discharging overcurrent determination circuit 51, the charging overcurrent determination circuit 52, the over-discharging voltage determination circuit 53, and the over-charging voltage determination circuit 54.
The other end of the second resistor R2 is connected to one end of the third resistor R3 and the non-inverting end of the over-charge voltage determining circuit 53, the other end of the third resistor R3 is connected to one end of the fourth resistor R4 and the inverting end of the over-charge voltage determining circuit, and the other end of the fourth resistor R4 is connected to the ground terminal.
The in-phase end of the discharging overcurrent judging circuit 51 is connected with the VOC1 end of the reference circuit 4, the inverting end of the discharging overcurrent judging circuit 51 is connected with the in-phase end of the charging overcurrent judging circuit 52, the cathode P-of the charger or load 8 and the third end of the switch tube 7, the inverting end of the charging overcurrent judging circuit 52 is connected with the VCHOC end of the reference circuit 4, the inverting end of the over-discharge voltage judging circuit 53 is connected with the VODV end of the reference circuit 4, the in-phase end of the over-charge voltage judging circuit 54 is connected with the VOCV end of the reference circuit 4, the output end of the discharging overcurrent judging circuit 51 is connected with the input end of the fourth delay circuit 58 and the first input end of the third NAND gate I3, the output end of the charging overcurrent judging circuit 52 is connected with the input end of the third delay circuit 57 and the second input end of the third NAND gate I3, the output end of the over-discharge voltage judging circuit 53 is connected with the input end of the second delay circuit 56 and the third input, the output end of the overcharge voltage judging circuit 54 is connected to the input end of the first delay circuit 55 and the fourth input end of the third nand gate I3, and the output end of the fourth delay circuit 58, the output end of the third delay circuit 57, the output end of the second delay circuit 56 and the output end of the first delay circuit 55 are connected to the input end of the fourth and gate I4.
The output end of the third nand gate I3 is connected to the second input end of the first or gate I1, the output end of the fourth and gate I4 is connected to the input end of the driving circuit 6, the output end of the driving circuit 6 is connected to the first end of the switch tube 7, the output end of the first or gate I1 is connected to the enable end EN of the detection circuit 5 and the first input end of the reference circuit 4, that is, the reference circuit 4 and the detection circuit 5 are both controlled by the square wave generating circuit 3, the driving circuit 6 is used for controlling the switch tube 7 according to a switching signal generated inside the lithium battery protection chip 9, and the switch tube 7 is used for controlling whether the battery 1 can be charged or discharged.
As shown in fig. 1, the principle of implementing low power consumption in the present invention is: the average operating current is reduced by controlling the reference circuit 4 and the detection circuit 5 to operate only for a part of the time by the square wave generating circuit 3, for example: when the working current of the conventional lithium battery protection circuit is 1uA, that is, the current consumed by the reference circuit 4 and the detection circuit 5 is 1 uA. In the application, if the average current of the square wave generating circuit 3 is 0.1uA, a square wave with 10% time being high level and 90% time being low level is generated, so that the reference circuit 4 and the detection circuit 5 only consume current for 10% of time, no current is consumed for 90% of time, and the average current consumed by the reference circuit 4 and the detection circuit 5 is 0.1 uA. The total current consumed is 0.1uA of the current generated by the square-wave generating circuit 3 plus 0.1uA of the current generated by the reference circuit 4 and the detection circuit 5, and the total current is 0.2uA, which is much smaller than 1uA in the conventional scheme.
As shown in fig. 1 and 3, when the discharging overcurrent judging circuit 51, the charging overcurrent judging circuit 52, the over-discharging voltage judging circuit 53, and the over-charging voltage judging circuit 54 are in the normal state, and the input voltage of the non-inverting terminal is higher than the input voltage of the inverting terminal, the output is all high level, when the input voltage of the in-phase end is lower than the input voltage of the inversion end, the low level is output after the delay of the delay circuit, wherein the delay of the fourth delay circuit 58 is generally set to 10ms, the delay of the third delay circuit 57 is generally set to 10ms, the delay of the second delay circuit 56 is generally set to 40ms to 100ms, the delay of the first delay circuit 55 is generally set to 1s, the duration time can be set according to experience, the square wave generating circuit 3 generates a high pulse every 1ms to work for the detection circuit 5, and the detection circuit 5 can normally judge without influencing the working performance of the chip.
As shown in fig. 4, the square wave generating circuit 3 includes an eighth flip-flop I8, a ninth flip-flop I9, a tenth flip-flop I10, an eleventh flip-flop I11, a thirteenth and gate I13, a twelfth nand gate I12, a fifth not gate I5, a sixth not gate I6, a seventh not gate I7, a second capacitor C2 and a third capacitor C3, wherein the eighth flip-flop I8, the ninth flip-flop I9, the tenth flip-flop I10 and the eleventh flip-flop I11 are all high level flip-flops, and:
the D end of the eighth flip-flop I8 is connected with the Q-not end of the eighth flip-flop I8, the clock end of the eighth flip-flop I8 is connected with the input end of the fifth not gate I5 and the output end of the seventh not gate I7, and the Q end of the eighth flip-flop I8 is connected with the clock end of the ninth flip-flop I9 and the first input end of the thirteenth and gate I13; the D end of the ninth flip-flop I9 is connected with the Q-not end of the ninth flip-flop I9, and the Q end of the ninth flip-flop I9 is connected with the clock end of the tenth flip-flop I10 and the first input end of the twelfth NAND gate I12; the D end of the tenth flip-flop I10 is connected with the Q-not end of the tenth flip-flop I10, and the Q end of the tenth flip-flop I10 is connected with the clock end of the eleventh flip-flop I11; the D end of the eleventh flip-flop I11 is connected to the Q-not end of the eleventh flip-flop I11, the Q end of the eleventh flip-flop I11 is connected to the second input end of the thirteenth and gate I13 and the second input end of the twelfth nand gate I12, the Reset end Reset of the eighth flip-flop I8, the Reset end Reset of the ninth flip-flop I9, the Reset end Reset of the tenth flip-flop I10 and the Reset end Reset of the eleventh flip-flop I11 are connected to the output end of the twelfth nand gate I12, the output end of the fifth not gate I5 is connected to the input end of the sixth not gate I6 and one end of the second capacitor C2, the output end of the sixth not gate I6 is connected to the input end of the seventh not gate I7 and one end of the third capacitor C3, and the other end of the second capacitor C2 is connected to the other end of the third capacitor C3 and then grounded.
As shown in fig. 4, when initially powering up, the input terminal NET1 of the fifth not gate I5 is at a low level, the input terminal NET1 of the fifth not gate I5 charges the second capacitor C2 after passing through the fifth not gate I5 until the output terminal NET2 of the fifth not gate I5 is at a high level, the sixth not gate I6 discharges the third capacitor C3 until the output terminal NET3 of the sixth not gate I6 is at a low level, the output terminal NET1 of the fifth not gate I5 is pulled high after passing through the seventh not gate I7, the input terminal NET2 of the fifth not gate I5 is pulled high after the input terminal NET1 of the fifth not gate I5 is pulled high, the output terminal NET2 of the sixth not gate I2 is pulled high, the input terminal NET2 of the fifth not gate I2 is pulled low after passing through the seventh not gate I7, and therefore the cycle generates a clock signal CLK, wherein the cycle of the clock signal is as shown in the eleventh to eleventh clock signal table, wherein the eleventh flip-flop CLK, the ninth not gate I2, the ninth flip-flop is the ninth flip-flop I2, the ninth flip-flop, VSQ terminal, Reset terminal Reset level voltage.
Figure 170873DEST_PATH_IMAGE001
As can be seen from the above table, the output of the eleventh CLK is the same as the output of the first CLK, i.e., the period is 10 CLKs, the VSQ terminal outputs a high level only in one CLK clock, and the other clocks all output a low level, so that only 10% of the time is output as a high level.
Example two
As shown in fig. 2, the present embodiment is different from the embodiment in that: the connection between the enable terminal EN of the detection circuit 5 and the first input terminal of the reference circuit 4 is disconnected, that is, only the detection circuit 5 is controlled by the square wave generation circuit 3, and the working current of the lithium battery protection chip 9 in this embodiment is higher than that in the first embodiment, but is lower than that of the conventional lithium battery protection circuit.
The first embodiment and the second embodiment are single-cell negative lithium battery protection systems, and meanwhile, the present application is also applicable to a single-cell positive lithium battery protection system and a multi-cell lithium battery protection system.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (6)

1. The utility model provides a lithium cell protection circuit of ultra-low power consumption which characterized in that: including battery, filter circuit, lithium cell protection chip and charger or load, wherein:
lithium cell protection chip includes square wave generating circuit, first OR gate, reference circuit, detection circuitry, drive circuit and switch tube, wherein:
the square wave generating circuit is used for generating a square wave signal and controlling the working time of at least one module in the reference circuit or the detection circuit;
the reference circuit is used for generating voltage or current which does not change along with the voltage;
the detection circuit is used for judging the working state of the lithium battery protection chip, and the working state comprises a normal state, an overcharging voltage state, an overdischarging voltage state, a discharging overcurrent state and a charging overcurrent state;
the drive circuit is used for controlling the switching tube to be switched on or switched off according to a switching signal generated in the lithium battery protection chip;
the switching tube is used for controlling the charging or discharging of the battery;
the output end of the square wave generating circuit is connected with the first input end of the first OR gate;
the reference circuit comprises a plurality of output ends, wherein the output ends comprise a VOC1 end, a VCHOC end, a VOCV end and a VODV end;
the detection circuit comprises a discharge overcurrent judgment circuit, a charge overcurrent judgment circuit, an over-discharge voltage judgment circuit, an over-charge voltage judgment circuit, a first delay circuit, a second delay circuit, a third delay circuit, a fourth delay circuit, a second resistor, a third resistor, a fourth resistor, a second NOT gate, a third NAND gate, a fourth AND gate and a PMOS (P-channel metal oxide semiconductor) tube, wherein:
the source electrode of the PMOS tube is connected with a VDD end, the drain electrode of the PMOS tube is connected with one end of a second resistor, the grid electrode of the PMOS tube is connected with the output end of a second NOT gate, and the input end of the second NOT gate is connected with an enabling end and then connected with a discharging overcurrent judging circuit, a charging overcurrent judging circuit, a discharging voltage judging circuit and an overcharging voltage judging circuit;
the other end of the second resistor is connected with one end of a third resistor and the in-phase end of the over-charging voltage judging circuit, the other end of the third resistor is connected with one end of a fourth resistor and the reverse-phase end of the over-charging voltage judging circuit, and the other end of the fourth resistor is connected with a grounding end;
the in-phase end of the discharge overcurrent judging circuit is connected with the VOC1 end of the reference circuit, the inverting end of the discharge overcurrent judging circuit is connected with the in-phase end of the charge overcurrent judging circuit, the negative electrode of the charger or the load and the third end of the switch tube, the inverting end of the charge overcurrent judging circuit is connected with the VCHOC end of the reference circuit, the inverting end of the over-discharge voltage judging circuit is connected with the VODV end of the reference circuit, the in-phase end of the over-charge voltage judging circuit is connected with the VOCV end of the reference circuit, the output end of the discharge overcurrent judging circuit is connected with the input end of the fourth delay circuit and the first input end of the third NAND gate, the output end of the charge overcurrent judging circuit is connected with the input end of the third delay circuit and the second input end of the third NAND gate, and the output end of the over-discharge voltage judging circuit is connected with the input end of the second delay circuit and the third input end of the third, the output end of the overcharge voltage judgment circuit is connected with the input end of the first delay circuit and the fourth input end of the third NAND gate;
the output end of the fourth delay circuit, the output end of the third delay circuit, the output end of the second delay circuit and the output end of the first delay circuit are all connected with the input end of a fourth AND gate;
the output end of the third NAND gate is connected with the second input end of the first OR gate, the output end of the fourth AND gate is connected with the input end of the driving circuit, the output end of the driving circuit is connected with the first end of the switch tube, the output end of the first OR gate is connected with the enabling end of the detection circuit and the first input end of the reference circuit, namely, the reference circuit and the detection circuit are controlled by the square wave generation circuit;
the square wave generating circuit comprises an eighth trigger, a ninth trigger, a tenth trigger, an eleventh trigger, a thirteenth AND gate, a twelfth NAND gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, a second capacitor and a third capacitor, wherein:
the D end of the eighth trigger is connected with the Q-not end of the eighth trigger, the clock end of the eighth trigger is connected with the input end of the fifth not gate and the output end of the seventh not gate, and the Q end of the eighth trigger is connected with the clock end of the ninth trigger and the first input end of the thirteenth and gate; the D end of the ninth flip-flop is connected with the Q-not end of the ninth flip-flop, and the Q end of the ninth flip-flop is connected with the clock end of the tenth flip-flop and the first input end of the twelfth NAND gate; the D end of the tenth trigger is connected with the Q-not end of the tenth trigger, and the Q end of the tenth trigger is connected with the clock end of the eleventh trigger; the D end of the eleventh trigger is connected with the Q-not end of the eleventh trigger, the Q end of the eleventh trigger is connected with the second input end of the thirteenth AND gate and the second input end of the twelfth NAND gate, and the reset end of the eighth trigger, the reset end of the ninth trigger, the reset end of the tenth trigger and the reset end of the eleventh trigger are connected with the output end of the twelfth NAND gate after being connected.
2. The ultra-low power lithium battery protection circuit of claim 1, wherein: the connection between the enabling end of the detection circuit and the first input end of the reference circuit is disconnected, namely, only the detection circuit is controlled by the square wave generation circuit.
3. The ultra-low power lithium battery protection circuit of claim 1, wherein: the discharging overcurrent judging circuit, the charging overcurrent judging circuit, the over-discharging voltage judging circuit and the over-charging voltage judging circuit all adopt comparators.
4. The ultra-low power lithium battery protection circuit of claim 1, wherein: the filter circuit comprises a first resistor and a first capacitor, the positive pole of the battery is connected with one end of the first resistor and the positive pole of the charger or the load, the other end of the first resistor is connected with one end of the first capacitor, the VDD end and the second input end of the reference circuit, and the other end of the first capacitor is connected with the third input end of the reference circuit, the grounding end of the detection circuit and the second end of the switch tube.
5. The ultra-low power lithium battery protection circuit of claim 1, wherein: the output end of the fifth NOT gate is connected with the input end of a sixth NOT gate and one end of a second capacitor, the output end of the sixth NOT gate is connected with the input end of a seventh NOT gate and one end of a third capacitor, and the other end of the second capacitor is connected with the other end of the third capacitor and then grounded.
6. The ultra-low power lithium battery protection circuit of claim 1, wherein: and the eighth trigger, the ninth trigger, the tenth trigger and the eleventh trigger are all triggered by high level.
CN202110079344.6A 2021-01-21 2021-01-21 Lithium battery protection circuit with ultra-low power consumption Active CN112398096B (en)

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