CN214480523U - Pulse width modulation signal generating circuit - Google Patents
Pulse width modulation signal generating circuit Download PDFInfo
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- CN214480523U CN214480523U CN202022997123.0U CN202022997123U CN214480523U CN 214480523 U CN214480523 U CN 214480523U CN 202022997123 U CN202022997123 U CN 202022997123U CN 214480523 U CN214480523 U CN 214480523U
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Abstract
The embodiment of the utility model discloses a pulse width modulation signal produces circuit, switch the module including switch module and charge-discharge. And under the condition that the first PWM signal is at a low level, the connection between the third end of the switch module and the second end of the switch module is conducted so as to output a positive voltage signal, and the connection between the third end of the switch module and the fourth end of the switch module is conducted so as to charge the charge and discharge switching module. And under the condition that the first PWM signal is a high-level signal, the connection between the third end of the discharge switch branch and the fourth end of the discharge switch branch is conducted, and the connection between the third end of the discharge switch branch and the second end of the discharge switch branch is conducted so as to output a negative voltage signal. Thereby obtaining a PWM signal whose low level is a negative voltage. The utility model provides a pulse width modulation signal produces circuit can not cause electromagnetic interference to other devices of system inside, and the cost is lower.
Description
Technical Field
The utility model relates to a signal processing technology field especially relates to a pulse width modulation signal produces circuit.
Background
Pulse Width Modulation (PWM) is a very efficient technique for controlling analog circuits using the digital output of a microprocessor, and is widely used in many fields ranging from measurement, communications to power control and conversion.
Present singlechip power supply all is +5V or +3.3V, is the positive voltage when needs use the high level, and the low level is the PWM signal of negative voltage, often needs to use level conversion chip, converts the positive voltage into negative voltage, but the inside operating frequency of level conversion chip is higher, and is great to singlechip system's electromagnetic interference, in addition, level conversion chip's cost is high.
SUMMERY OF THE UTILITY MODEL
In view of the above, it is necessary to provide a pwm signal generating circuit in order to solve the above problems.
The utility model discloses a technical means do: the pulse width modulation signal generating circuit comprises a switch module and a charge-discharge switching module, wherein:
the first end of the switch module is used for receiving an input first PWM signal, the second end of the switch module is used for outputting a second PWM signal, the third end of the switch module is connected with a power supply end, and the fourth end of the switch module is connected with the charge-discharge switching module; the switch module is used for conducting connection between a third end of the switch module and a second end of the switch module to output a positive voltage signal and conducting connection between the third end of the switch module and a fourth end of the switch module to charge the charge-discharge switching module under the condition that the first PWM signal is at a low level;
the charging and discharging switching module comprises a charging switch branch and a discharging switch branch which share an energy storage capacitor;
the first end of the charging switch branch circuit is the anode of the energy storage capacitor and is connected with the fourth end of the switch module, and the second end of the charging switch is grounded; the charging switch branch circuit is used for being conducted when receiving the voltage output by the power supply end so as to charge the energy storage capacitor;
the first end of the discharge switch branch circuit is connected with the first end of the switch module, the second end of the discharge switch branch circuit is connected with the second end of the switch module, the third end of the discharge switch branch circuit is the anode of the energy storage capacitor, and the fourth end of the discharge switch branch circuit is grounded; the discharge switch branch circuit is used for conducting connection between a third end of the discharge switch branch circuit and a fourth end of the discharge switch branch circuit under the condition that the first PWM signal is a high-level signal, and conducting connection between the third end of the discharge switch branch circuit and a second end of the discharge switch branch circuit so as to output a negative voltage signal.
Adopt the embodiment of the utility model provides a, following beneficial effect has:
the embodiment of the utility model provides a pair of pulse width modulation signal produces circuit, under the condition that first PWM signal is the low level, switches on switch module's third end with be connected between switch module's the second end to output positive voltage signal, and switch on switch module's third end with be connected between switch module's the fourth end, in order to give charge-discharge switching module fills. And under the condition that the first PWM signal is a high-level signal, the connection between the third end of the discharge switch branch and the fourth end of the discharge switch branch is conducted, and the connection between the third end of the discharge switch branch and the second end of the discharge switch branch is conducted so as to output a negative voltage signal. Adopt the utility model provides a pulse width modulation signal produces circuit, through the switch branch road and the discharge switch branch road that charge who sets up switch module, sharing energy storage capacitor, just can convert first PWM signal into the second PWM signal output that the low level is the negative voltage, need not to use the level conversion chip, saves the circuit cost.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Wherein:
FIG. 1 is a block diagram of a PWM signal generating circuit according to an embodiment;
FIG. 2 is a block diagram of a PWM signal generating circuit according to an embodiment;
fig. 3 is a schematic circuit diagram of a pwm signal generating circuit according to an embodiment.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
The terms first, second and the like in the description and in the claims, and in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be practiced otherwise than as specifically illustrated.
The embodiment of the utility model discloses pulse width modulation signal generating circuit, as shown in fig. 1, a pulse width modulation signal generating circuit, a serial communication port, switch module 20 including switch module 10 and charge-discharge, wherein:
a first end of the switch module 10 is configured to receive an input first PWM signal, a second end of the switch module 10 is configured to output a second PWM signal, a third end of the switch module 10 is connected to the power supply terminal 1, and a fourth end of the switch module 10 is connected to the charge-discharge switching module 20; the switch module 10 is configured to, when the first PWM signal is at a low level, turn on a connection between the third terminal of the switch module 10 and the second terminal of the switch module 10 to output a positive voltage signal, and turn on a connection between the third terminal of the switch module 10 and the fourth terminal of the switch module 10 to charge the charge/discharge switching module 20, and, when the first PWM signal is at a high level, turn off a connection between the third terminal of the switch module 10 and the second terminal of the switch module 10 to stop outputting the positive voltage signal, and turn off a connection between the third terminal of the switch module 10 and the fourth terminal of the switch module 10 to stop charging the charge/discharge switching module 20.
The charge-discharge switching module 20 includes a charge switch branch 21 and a discharge switch branch 22 sharing an energy storage capacitor 23.
The first end of the charging switch branch 21 is the anode of the energy storage capacitor 23 and is connected with the fourth end of the switch module 10, and the second end of the charging switch branch 21 is grounded; the charging switch branch 21 is configured to be turned on when receiving the voltage output by the power source terminal 1 to charge the energy storage capacitor 23, and to be turned off when not receiving the voltage output by the power source terminal 1 to stop charging the energy storage capacitor 23.
A first end of the discharge switch branch 22 is connected with a first end of the switch module 10, a second end of the discharge switch branch 22 is connected with a second end of the switch module 10, a third end of the discharge switch branch 22 is an anode of the energy storage capacitor 23, and a fourth end of the discharge switch branch 22 is grounded; the discharge switch branch 22 is configured to, when the first PWM signal is a low-level signal, turn off a connection between the third end of the discharge switch branch 22 and the fourth end of the discharge switch branch 22, turn off a connection between the third end of the discharge switch branch 22 and the second end of the discharge switch branch 22, and, when the first PWM signal is a high-level signal, turn on a connection between the third end of the discharge switch branch 22 and the fourth end of the discharge switch branch 22, and turn on a connection between the third end of the discharge switch branch 22 and the second end of the discharge switch branch 22, so as to output a negative voltage signal.
The embodiment of the utility model provides a pulse width modulation signal generating circuit, under the condition that first PWM signal is the low level, switch-on is connected between the third end of switch module 10 and the second end of switch module 10, the connection of the third end of discharge switch branch road 22 and the fourth end of discharge switch branch road 22 is cut off, the connection between the third end of turn-off discharge switch branch road 22 and the second end of discharge switch branch road 22 is cut off, the second end of discharge switch branch road 22 does not have the output, the positive voltage signal of power end is exported to the second end of switch module 10, so second PWM is the positive voltage signal; the third terminal of the switch module 10 is connected to the fourth terminal of the switch module 10, and the charging switch branch 21 is connected to receive the voltage output by the power supply terminal 1 to charge the energy storage capacitor 23. Under the condition that the first PWM signal is a high level signal, the connection between the third terminal of the switch module 10 and the fourth terminal of the switch module 10 is turned off, and the charging switch branch 21 does not receive the voltage output by the power supply terminal 1, and stops charging the energy storage capacitor; the connection between the third end of the switch module 10 and the second end of the switch module 10 is turned off, the second end of the switch module 10 has no output, the connection between the third end of the discharge switch branch 22 and the fourth end of the discharge switch branch 22 is turned on, so that the energy storage capacitor is grounded, the connection between the third end of the discharge switch branch 22 and the second end of the discharge switch branch 22 is turned on, the second end of the discharge switch branch outputs a negative voltage signal, and therefore the second PWM signal is a negative voltage signal. Therefore, the conversion of the PWM signals is realized through a simple circuit module, and the cost is low.
Further, as shown in fig. 2, the pulse width modulation signal generating circuit includes: a first controllable switch 100, a second controllable switch 200, a third controllable switch 300, a fourth controllable switch 400, a fifth controllable switch 500. The first controllable switch 100 and the second controllable switch 200 form a switch module 10, the third controllable switch 300 and the energy storage capacitor 23 form a charging switch branch 21, and the fourth controllable switch 400, the fifth controllable switch 500 and the energy storage capacitor 23 form a discharging switch branch 22.
The first controllable switch 100 is configured to receive the first PWM signal, and is in an on state when the first PWM signal is at a low level, and is in an off state when the first PWM signal is at a high level; the first switch terminal of the first controllable switch 100 is connected to a supply terminal 1.
The fourth controllable switch 400 is configured to receive the first PWM signal, and is in an off state when the first PWM signal is at a low level, and is in an on state when the first PWM signal is at a high level; the first switch end of the fourth controllable switch 400 is connected to the ground terminal 2; the second switch terminal of the fourth controllable switch 400 is connected to the second switch terminal of the first controllable switch 100 and forms a first common terminal 3.
The second controllable switch 200 is configured to receive the first PWM signal, and is in an on state when the first PWM signal is at a low level, and is in an off state when the first PWM signal is at a high level; the first switch terminal of the second controllable switch 200 is connected to the first common terminal 3.
The third controllable switch 300 is configured to receive a signal transmitted by the first common node 3, and is in an on state when the signal transmitted by the first common node 3 is at a high level, and is in an off state when the signal transmitted by the first common node 3 is at a low level; the first switch terminal of the third controllable switch 300 is connected to the ground terminal 2.
The fifth controllable switch 500 is used for receiving the signal transmitted by the ground terminal 2; the first switch terminal of the fifth controllable switch 500 is connected to the second switch terminal of the third controllable switch 300 and forms a second common terminal 4; the fifth controllable switch 500 is in an on state when the voltage transmitted by the second common terminal 4 is less than 0V, and is in an off state when the voltage transmitted by the second common terminal 4 is greater than or equal to 0V; a second switch end of the fifth controllable switch 500 is connected with a second switch end of the second controllable switch 200 and forms a third common end 5; the third common terminal 5 outputs a second PWM signal. The energy storage capacitor 23 is used for storing energy under the condition that the first PWM signal is at a low level; releasing energy under the condition that the PWM signal is at a high level; the energy storage capacitor 23 is connected in series between the first common terminal 3 and the second common terminal 4.
It is understood that the control terminal of the first controllable switch 100, the control terminal of the fourth controllable switch 400 and the control terminal of the second controllable switch 200 all receive the first PWM signal. The first switch terminal of the first controllable switch 100 is connected to a supply terminal 1. The first switch terminal of the fourth controllable switch 400, the first switch terminal of the fourth controllable switch 40 and the control terminal of the fifth controllable switch 500 are all connected to the ground terminal 2. The first switch terminal of the second controllable switch 200 and the control terminal of the fourth controllable switch 40 are both connected to the first common terminal 3. The positive pole of the energy storage capacitor 23 is connected with the first common terminal 3, and the negative pole of the energy storage capacitor 23 is connected with the second common terminal 4.
The embodiment of the utility model provides a pair of pulse width modulation signal generating circuit, under the condition that first PWM signal is the low level, first controllable switch 100, second controllable switch 200 and third controllable switch 300 all switch on, and fourth controllable switch 400 and fifth controllable switch 500 break off, and energy storage capacitor 23 charges, and at this moment, the third is total to hold 5 output positive voltages, and the high level of the second PWM signal of the 5 output of third is the positive voltage promptly. Under the condition that the first PWM signal is at a high level, the first controllable switch 100, the second controllable switch 200, and the third controllable switch 300 are all turned off, the fourth controllable switch 400 and the fifth controllable switch 500 are turned on, the anode of the energy storage capacitor 23 is connected to the ground terminal 2 through the fourth controllable switch 400, the cathode of the energy storage capacitor 23 is connected to the third common terminal 5 through the fifth controllable switch 500, and the energy storage capacitor 23 plays a role of clamping in the circuit due to the storage of the electric energy, so that the cathode of the energy storage capacitor 23 is at a negative voltage, at this time, the third common terminal 5 is clamped at a negative voltage, that is, the low level of the second PWM signal output by the third common terminal 5 is at a negative voltage. The utility model provides a pulse width modulation signal generating circuit converts first PWM signal into second PWM signal output through first controllable switch 100, fourth controllable switch 400, second controllable switch 200, fourth controllable switch 40, fifth controllable switch 500 and energy storage electric capacity 23 wherein, and the high level of second PWM signal is the positive voltage, and the low level of second PWM signal is the negative voltage. Thereby obtaining a PWM signal whose low level is a negative voltage. Additionally, the utility model provides a pulse width modulation signal produces circuit can not cause electromagnetic interference to other devices of system inside, and the cost is lower.
In one embodiment, as shown in fig. 3, the switch module 10 includes a first transistor Q1 and a second transistor Q2, and the first transistor Q1 and the second transistor Q2 are PNP transistors. The base of the first triode Q1 and the base of the second triode Q2 are both connected to the first end of the switch module 10; the collector of the second transistor Q2 is the second terminal of the switch module 10; the emitter of the first transistor Q1 is the third terminal of the switch module 10; the collector of the first transistor Q1 is connected to the emitter of the second transistor Q2, which is the fourth terminal of the switch module 10.
Further, the switch module 10 further includes a first resistor R1 and a second resistor R2, a base of the first transistor Q1 is connected to the first end of the switch module 10 through the first resistor R1, and a base of the second transistor Q2 is connected to the second end of the switch module 10 through the second resistor R2. Under the condition that the first PWM signal is at a low level, the first transistor Q1, the second transistor Q2 and the third transistor Q3 are all turned on, and a positive voltage signal is output from the collector of the second transistor Q2, at this time, the first transistor Q1 is turned on, and the voltage of the power supply terminal 1 charges the charge and discharge switching module 20 through the first transistor Q1.
In an embodiment, the switch module 10 includes a first MOS transistor and a second MOS transistor, and both the first MOS transistor and the second MOS transistor are PMOS transistors. The grid electrode of the first MOS tube and the grid electrode of the second MOS tube are both connected to the first end of the switch module 10; the drain of the second MOS transistor is the second end of the switch module 10; the source of the first MOS transistor is the third terminal of the switch module 10; the drain of the first MOS transistor is connected to the source of the second MOS transistor and is the fourth terminal of the switch module 10.
In one embodiment, as shown in fig. 3, the charging switch branch 21 includes an energy storage capacitor 23 and a third transistor Q3, and the third transistor Q3 is an NPN-type transistor. The base of the third transistor Q3 is connected to the positive electrode of the energy storage capacitor 23, the negative electrode of the energy storage capacitor 23 is connected to the collector of the third transistor Q3, and the emitter of the third transistor Q3 is the second end of the charging switch branch 21.
Further, the charging switch branch 21 further includes a third resistor R3, and a base of the third transistor Q3 is connected to the anode of the energy storage capacitor 23 through the third resistor R3.
In one embodiment, the charging switch branch 21 includes an energy storage capacitor 23 and a third MOS transistor, and the third transistor Q3 is an NMOS transistor; the gate of the third MOS transistor is connected to the energy storage capacitor 23, the cathode of the energy storage capacitor 23 is connected to the drain of the third MOS transistor, and the source of the third MOS transistor is the second end of the charging switch branch 21.
In one embodiment, as shown in fig. 3, the discharge switch branch 22 includes an energy storage capacitor 23, a fourth transistor Q4, and a fifth transistor Q5, where the fourth transistor Q4 and the fifth transistor Q5 are both NPN transistors; the base of the fourth transistor Q4 is connected to the first end of the discharge switch branch 22; the collector of the fifth triode Q5 is the second end of the discharging switch branch 22; the collector of the fourth triode Q4 is connected with the positive electrode of the energy storage capacitor 23; the emitter of the fourth transistor Q4 is the fourth terminal of the discharging switch branch 22, and the base of the fifth transistor Q5 is connected to the emitter of the fourth transistor Q4; the cathode of the energy storage capacitor 23 is connected to the emitter of the fifth transistor Q5.
Further, the discharge switch branch 22 further includes a fourth resistor R4 and a fifth resistor R5; the base of the fourth transistor Q4 is connected to the first terminal of the discharge switch branch 22 through a fourth resistor R4, and the base of the fifth transistor Q5 is connected to the emitter of the fourth transistor Q4 through a fifth resistor R5. Under the condition that the first PWM signal is a high level signal, the fourth transistor Q4 and the fifth transistor Q5 are turned on, the positive electrode of the conductive energy-storage capacitor 23 is grounded through the fourth transistor, and the negative electrode of the energy-storage capacitor 23 passes through the fifth transistor Q5, so as to output a negative voltage signal.
In one implementation, the discharge switch branch 22 includes an energy storage capacitor 23, a fourth MOS transistor and a fifth MOS transistor, where the fourth MOS transistor and the fifth MOS transistor are both NMOS transistors; the gate of the fourth MOS transistor is connected to the first end of the discharge switch branch 22; the drain of the fifth MOS transistor is the second end of the discharge switch branch 22; the drain electrode of the fourth MOS tube is connected with the positive electrode of the energy storage capacitor 23; the source electrode of the fourth MOS transistor is the fourth end of the discharge switch branch 22, and the gate electrode of the fifth MOS transistor is connected to the source electrode of the fourth MOS transistor; and the cathode of the energy storage capacitor 23 is connected with the source of the fifth MOS tube.
In one embodiment, as shown in fig. 3, the first controllable switch 100 is a first transistor Q1, and the second controllable switch 200 is a second transistor Q2; the third controllable switch 300 is a third transistor Q3; the fourth controllable switch 400 is a fourth transistor Q4; the fifth controllable switches 500 are all fifth transistors Q5. The first triode Q1 and the second triode Q2 are PNP type triodes; the third transistor Q3, the fourth transistor Q4, and the fifth transistor Q5 are NPN transistors.
It is understood that the control terminal of the first controllable switch 100 is the base of the first transistor Q1, the input terminal of the first controllable switch 100 is the emitter of the first transistor Q1, and the output terminal of the first controllable switch 100 is the collector of the first transistor Q1. The control terminal of the second controllable switch 200 is the base of a second transistor Q2, the input terminal of the second controllable switch 300 is the emitter of a second transistor Q2, and the output terminal of the second controllable switch 200 is the collector of a second transistor Q2. The control terminal of the third controllable switch 300 is the base of the third transistor Q3, the input terminal of the third controllable switch 300 is the emitter of the third transistor Q3, and the output terminal of the third controllable switch 300 is the collector of the third transistor Q3. The control terminal of the fourth controllable switch 400 is the base of a fourth transistor Q4, the input terminal of the fourth controllable switch 400 is the emitter of a fourth transistor Q4, and the output terminal of the fourth controllable switch 400 is the collector of a fourth transistor Q4. The control terminal of the fifth controllable switch 500 is the base of the fifth transistor Q5, the input terminal of the fifth controllable switch 500 is the emitter of the fifth transistor Q5, and the output terminal of the fifth controllable switch 500 is the collector of the fifth transistor Q5.
Further, the base of the first transistor Q1 inputs the first PWM signal, the emitter of the first transistor Q1 is connected to the power source terminal 1, and the collector of the first transistor Q1 is connected to the first common terminal 3. The base of the second triode Q2 inputs the first PWM signal, the emitter of the second triode Q2 is connected to the first common terminal 3, and the collector of the second triode Q2 is connected to the third common terminal 5. The base of the third transistor Q3 is connected to the first common terminal 3, the emitter of the third transistor Q3 is connected to the ground terminal 2, and the collector of the third transistor Q3 is connected to the second common terminal 4. The base of the fourth transistor Q4 inputs the first PWM signal, the emitter of the fourth transistor Q4 is connected to the ground terminal 2, and the collector of the fourth transistor Q4 is connected to the first common terminal 3. The base electrode of the fifth triode Q5 is connected with the grounding end 2, and the emitter electrode of the fifth triode Q5 is connected with the second common end 4; the collector of the fifth transistor Q5 is connected to the third common terminal 5.
Further, the pulse width modulation signal generating circuit further comprises a first resistor R1, a second resistor R2, a first resistor R3, a first resistor R4 and a fifth resistor R5. The first PWM signal is input to the base of the first transistor Q1 through a first resistor R1. The first PWM signal is input to the base of the second transistor Q2 through the second resistor R2. The first PWM signal is input to the base of the fourth transistor Q4 through the fourth resistor R4. The base of the third transistor Q3 is connected to the first common node 3 through a third resistor R3. The base of the fifth transistor Q4 is connected to the ground terminal 2 through a fifth resistor R5. The first resistor R1, the second resistor R2, the first resistor R3, the first resistor R4 and the fifth resistor R5 are all 1k Ω.
Further, when the first PWM signal is at a low level, the first transistor Q1, the second transistor Q2 and the third transistor Q3 are all turned on, the fourth transistor Q4 and the fifth transistor Q5 are turned off, the energy storage capacitor 23 is charged, and at this time, the input voltage of the power supply terminal 1 is output to the third common terminal 5 through the first transistor Q1 and the second transistor Q2, so that the third common terminal outputs a positive voltage, that is, the high level of the second PWM signal output by the third common terminal 5 is a positive voltage. Under the condition that the first PWM signal is at a high level, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are all turned off, the fourth transistor Q4 and the fifth transistor Q5 are turned on, the positive electrode of the energy storage capacitor 23 is connected to the ground terminal 2 through the fourth transistor Q4, the negative electrode of the energy storage capacitor 23 is connected to the third common terminal 5 through the fifth transistor Q5, and at this time, the third common terminal 5 is clamped to a negative voltage. Thereby obtaining a PWM signal whose low level is a negative voltage, i.e., a second PWM signal. It can be understood that the energy storage capacitor 23 plays a role of clamping in the circuit due to the stored electric energy, so that when the anode of the energy storage capacitor 23 is grounded, the cathode of the energy storage capacitor 23 is a negative voltage, and at this time, the third common terminal 5 is clamped to be a negative voltage, that is, the low level of the second PWM signal output by the third common terminal 5 is a negative voltage. The utility model provides a pulse width modulation signal produces circuit can not cause electromagnetic interference to other devices of system inside, and the cost is lower.
In an embodiment, the first controllable switch 100, the second controllable switch 200, the third controllable switch 300, the fourth controllable switch 40, and the fifth controllable switch 500 are MOS transistors. Specifically, the first controllable switch 100 is a first MOS transistor; the second controllable switch 200 is a second MOS transistor; the third controllable switch 300 is a third MOS transistor; the fourth controllable switch 400 is a fourth MOS transistor; the fifth controllable switches 500 are all fifth MOS transistors. The first MOS tube and the second MOS tube are PMOS tubes; the third MOS tube, the fourth MOS tube and the fifth MOS tube are NMOS tubes.
It can be understood that the control terminal of the first controllable switch 100 is a gate of the first MOS transistor, the input terminal of the first controllable switch 100 is a source of the first MOS transistor, and the output terminal of the first controllable switch 100 is a drain of the first MOS transistor. The control end of the second controllable switch 200 is a gate of a second MOS transistor, the input end of the second controllable switch 200 is a source of the second MOS transistor, and the output end of the second controllable switch 200 is a drain of the second MOS transistor. The control terminal of the third controllable switch 300 is the gate of the third MOS transistor, the input terminal of the third controllable switch 300 is the source of the third MOS transistor, and the output terminal of the third controllable switch 300 is the drain of the third MOS transistor. The control terminal of the fourth controllable switch 400 is the gate of the fourth MOS transistor, the input terminal of the fourth controllable switch 400 is the source of the first tetrode, and the output terminal of the fourth controllable switch 400 is the drain of the fourth MOS transistor. The control end of the fifth controllable switch 500 is a gate of a fifth MOS transistor, the input end of the fifth controllable switch 500 is a source of the fifth MOS transistor, and the output end of the fifth controllable switch 500 is a drain of the fifth MOS transistor.
Furthermore, a first PWM signal is input to the gate of the first MOS transistor, the source of the first MOS transistor is connected to the power supply terminal 1, and the drain of the first MOS transistor is connected to the first common terminal 3. The grid electrode of the second MOS tube inputs a first PWM signal, the source electrode of the second MOS tube is respectively connected with the first common end 3, and the drain electrode of the second MOS tube is connected with the third common end 5. The grid electrode of the third MOS tube is connected with the first common end 3, the source electrode of the third MOS tube is connected with the grounding end 2, and the drain electrode of the third MOS tube is respectively connected with the second common end 4. The grid electrode of the fourth MOS tube inputs a first PWM signal, the source electrode of the fourth MOS tube is connected with the grounding end 2, and the drain electrode of the fourth MOS tube is connected with the first common end 3. The grid electrode of the fifth MOS tube is connected with the grounding end 2, and the source electrode of the fifth MOS tube is connected with the second common end 4; the drain of the fifth MOS transistor is connected to the third common terminal 5.
In one embodiment, the energy storage capacitor 23 is an electrolytic capacitor. The electrolytic capacitor is one kind of capacitor, the metal foil is positive electrode (aluminum or tantalum), the oxide film (aluminum oxide or tantalum pentoxide) close to the metal and the positive electrode is dielectric, and the negative electrode is composed of conductive material, electrolyte (the electrolyte can be liquid or solid) and other materials. Meanwhile, the anode and the cathode of the electrolytic capacitor can not be connected in a wrong way. In this embodiment, the electrolytic capacitor plays a role of charging and storing energy, and when the input first PWM signal is at a high level, the electrolytic capacitor charges and stores energy. When the input first PWM signal is at low level, the electrolytic capacitor plays a role of clamping in the circuit because of storing electric energy, and the cathode of the electrolytic capacitor is at negative voltage because the anode of the electrolytic capacitor is grounded.
Of course, in some other embodiments, the energy storage capacitor 23 may also be a non-polar capacitor, such as a patch capacitor, a film capacitor, or the like.
In one embodiment, the energy storage capacitor 23 is a capacitor with an adjustable capacitance. It will be appreciated that the capacitance of the energy storage capacitor 23 may be adjusted according to the magnitude of the load connected to the third common terminal 5. The larger the load value, the larger the capacitance value of the required energy storage capacitor 23. Preferably, in the case that third common terminal 5 is not loaded, the capacitance of energy storage capacitor 23 is 470 μ f.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. The utility model provides a pulse width modulation signal generation circuit which characterized in that, includes switch module and charge-discharge switching module, wherein:
the first end of the switch module is used for receiving an input first PWM signal, the second end of the switch module is used for outputting a second PWM signal, the third end of the switch module is connected with a power supply end, and the fourth end of the switch module is connected with the charge-discharge switching module; the switch module is used for conducting connection between a third end of the switch module and a second end of the switch module to output a positive voltage signal and conducting connection between the third end of the switch module and a fourth end of the switch module to charge the charge-discharge switching module under the condition that the first PWM signal is at a low level;
the charging and discharging switching module comprises a charging switch branch and a discharging switch branch which share an energy storage capacitor;
the first end of the charging switch branch circuit is the anode of the energy storage capacitor and is connected with the fourth end of the switch module, and the second end of the charging switch is grounded; the charging switch branch circuit is used for being conducted when receiving the voltage output by the power supply end so as to charge the energy storage capacitor;
the first end of the discharge switch branch circuit is connected with the first end of the switch module, the second end of the discharge switch branch circuit is connected with the second end of the switch module, the third end of the discharge switch branch circuit is the anode of the energy storage capacitor, and the fourth end of the discharge switch branch circuit is grounded; the discharge switch branch circuit is used for conducting connection between a third end of the discharge switch branch circuit and a fourth end of the discharge switch branch circuit under the condition that the first PWM signal is a high-level signal, and conducting connection between the third end of the discharge switch branch circuit and a second end of the discharge switch branch circuit so as to output a negative voltage signal.
2. The circuit of claim 1, wherein the switching module comprises a first transistor and a second transistor, and wherein the first transistor and the second transistor are both PNP transistors;
the base electrode of the first triode and the base electrode of the second triode are both connected to the first end of the switch module; the collector of the second triode is the second end of the switch module; the emitter of the first triode is the third end of the switch module; and the collector electrode of the first triode is connected with the emitter electrode of the second triode and is the fourth end of the switch module.
3. The circuit of claim 2, wherein the switch module further comprises a first resistor and a second resistor, wherein the base of the first transistor is connected to the first terminal of the switch module through the first resistor, and the base of the second transistor is connected to the second terminal of the switch module through the second resistor.
4. The circuit of claim 1, wherein the switch module comprises a first MOS transistor and a second MOS transistor, and the first MOS transistor and the second MOS transistor are both PMOS transistors;
the grid electrode of the first MOS tube and the grid electrode of the second MOS tube are both connected to the first end of the switch module; the drain electrode of the second MOS tube is the second end of the switch module; the source electrode of the first MOS tube is the third end of the switch module; and the drain electrode of the first MOS tube is connected with the source electrode of the second MOS tube and is the fourth end of the switch module.
5. The circuit of claim 1, wherein the charge switch branch comprises the energy storage capacitor and a third transistor, and the third transistor is an NPN transistor;
the base electrode of the third triode is connected to the positive electrode of the energy storage capacitor, the negative electrode of the energy storage capacitor is connected with the collector electrode of the third triode, and the emitter electrode of the third triode is the second end of the charging switch branch circuit.
6. The circuit of claim 5, wherein the charging switch branch further comprises a third resistor, and a base of the third transistor is connected to the anode of the energy storage capacitor through the third resistor.
7. The circuit of claim 1, wherein the charging switch branch comprises the energy storage capacitor and a third MOS transistor, and the third MOS transistor is an NMOS transistor;
the grid of the third MOS tube is connected to the energy storage capacitor, the negative electrode of the energy storage capacitor is connected with the drain electrode of the third MOS tube, and the source electrode of the third MOS tube is the second end of the charging switch branch circuit.
8. The circuit of claim 1, wherein the discharge switch branch comprises the energy storage capacitor, a fourth transistor and a fifth transistor, and the fourth transistor and the fifth transistor are both NPN transistors;
the base electrode of the fourth triode is connected to the first end of the discharge switch branch circuit; the collector of the fifth triode is the second end of the discharge switch branch circuit; the collector of the fourth triode is connected with the anode of the energy storage capacitor; an emitter of the fourth triode is a fourth end of the discharge switch branch circuit, and a base of the fifth triode is connected to an emitter of the fourth triode; and the negative electrode of the energy storage capacitor is connected with the emitting electrode of the fifth triode.
9. The circuit of claim 8, wherein the discharge switch leg further comprises a fourth resistor and a fifth resistor;
the base electrode of the fourth triode is connected to the first end of the discharge switch branch circuit through the fourth resistor, and the base electrode of the fifth triode is connected to the emitting electrode of the fourth triode through the fifth resistor.
10. The circuit of claim 1, wherein the discharge switch branch comprises the energy storage capacitor, a fourth MOS transistor and a fifth MOS transistor, and the fourth MOS transistor and the fifth MOS transistor are both NMOS transistors;
the grid electrode of the fourth MOS tube is connected to the first end of the discharge switch branch; the drain electrode of the fifth MOS tube is the second end of the discharge switch branch; the drain electrode of the fourth MOS tube is connected with the anode of the energy storage capacitor; the source electrode of the fourth MOS tube is the fourth end of the discharge switch branch, and the grid electrode of the fifth MOS tube is connected to the source electrode of the fourth MOS tube; and the negative electrode of the energy storage capacitor is connected with the source electrode of the fifth MOS tube.
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| CN202022997123.0U CN214480523U (en) | 2020-12-14 | 2020-12-14 | Pulse width modulation signal generating circuit |
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| CN202022997123.0U CN214480523U (en) | 2020-12-14 | 2020-12-14 | Pulse width modulation signal generating circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115833331A (en) * | 2023-01-09 | 2023-03-21 | 中天宽带技术有限公司 | Charging and discharging switching circuit for energy storage system, and implementation method and device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115833331A (en) * | 2023-01-09 | 2023-03-21 | 中天宽带技术有限公司 | Charging and discharging switching circuit for energy storage system, and implementation method and device |
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