CN218161803U - Starting impact current suppression circuit of power supply - Google Patents
Starting impact current suppression circuit of power supply Download PDFInfo
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- CN218161803U CN218161803U CN202222285068.1U CN202222285068U CN218161803U CN 218161803 U CN218161803 U CN 218161803U CN 202222285068 U CN202222285068 U CN 202222285068U CN 218161803 U CN218161803 U CN 218161803U
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Abstract
The utility model relates to a starting impulse current suppression circuit of power sets up parts such as field effect transistor, parallel capacitor group, a plurality of energy storage electric capacity, divider resistance, power resistance and two stabilivolt through the increase to make corresponding connection to these parts, realized utilizing the discharge process of resistance to an energy storage electric capacity, prevent that the power from making the field effect transistor produce the malfunction because of the residual voltage on this energy storage electric capacity when the interval time of twice start-up is short, cause the condition that starts this impulse current suppression circuit and become invalid even. Therefore, the starting impact current suppression circuit can suppress the instantaneous surge current of the power supply, avoids the condition of misoperation of the field effect transistor caused by overlarge surge current, and ensures the normal work of the power supply.
Description
Technical Field
The utility model relates to a power supply unit field especially relates to a start-up impulse current suppression circuit of power.
Background
The power supply, as an energy supply device, is essential to ensure the proper operation of the equipment. The conventional power supply can easily generate surge current (namely, impact current) at the moment of starting operation, so that the power supply is damaged, and the normal operation of equipment controlled by the power supply is seriously influenced.
Therefore, how to improve the power supply is to inhibit the surge current at the moment of starting the power supply and avoid the adverse effect of the surge current on the power supply, and is important for ensuring the normal power supply work of the power supply.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem that the starting impulse current suppression circuit of a power is provided to above-mentioned prior art.
The utility model provides a technical scheme that above-mentioned technical problem adopted does: a start-up inrush current suppression circuit for a power supply, comprising:
a voltage input terminal J1;
a voltage output terminal VOUT;
the parallel capacitor bank is provided with a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4 which are mutually connected in parallel, the anode of the first capacitor C1, the anode of the second capacitor C2, the anode of the third capacitor C3 and the anode of the fourth capacitor C4 are respectively connected with a voltage output end VOUT, and the cathode of the first capacitor C1, the cathode of the second capacitor C2, the cathode of the third capacitor C3 and the cathode of the fourth capacitor C4 are respectively connected with a ground terminal GND;
a source S of the field effect transistor Q is connected with the negative electrode of the third capacitor C3, a drain D of the field effect transistor Q is connected with a grounding terminal GND, and a resistor R1 is connected in series between the source S and the drain D;
a fifth capacitor C5, the negative electrode of which is connected to the negative electrode of the third capacitor C3, and the positive electrode of the fifth capacitor C5 is connected to the gate G of the field effect transistor Q;
a first end of the resistor R2 is connected with the negative electrode of the third capacitor C3, and a second end of the resistor R2 is connected with the grid G of the field effect transistor Q;
the anode of the first voltage-stabilizing tube Z1 is connected with the second end of the resistor R2, the cathode of the first voltage-stabilizing tube Z1 is connected with the first end of the resistor R3, and the second end of the resistor R3 is connected with the voltage output end VOUT;
a sixth capacitor C6, a positive electrode of which is connected to the first end of the resistor R3, and a negative electrode of the sixth capacitor C6 is connected to the negative electrode of the third capacitor C3;
a first end of the resistor R4 is connected with the negative electrode of the third capacitor C3, and a second end of the resistor R4 is connected with a first end of the resistor R3;
and the anode of the second voltage-stabilizing tube Z2 is connected with the cathode of the third capacitor C3, and the cathode of the second voltage-stabilizing tube Z2 is connected with the first end of the resistor R3.
In the starting impact current suppression circuit of the power supply, the field effect transistor Q is a MOS field effect transistor.
Further, in the start-up inrush current suppression circuit of the power supply, the capacitances of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are all 1 μ F, the capacitance of the fourth capacitor C4 is 820 μ F, the capacitance of the fifth capacitor C5 is 0.1 μ F, and the capacitance of the sixth capacitor C6 is 4.7 μ F.
Still further, in the start-up inrush current suppression circuit of the power supply, the resistance value of the resistor R1 is 22K Ω, the resistance value of the resistor R2 is 100K Ω, the resistance value of the resistor R3 is 82K Ω, and the resistance value of the resistor R4 is 200K Ω.
In a further improvement, in the start-up inrush current suppression circuit of the power supply, the regulated voltage of the first voltage-regulator tube Z1 is 6.2V, and the regulated voltage of the second voltage-regulator tube Z2 is 18V.
Compared with the prior art, the utility model has the advantages of: the utility model discloses a start-up impulse current suppression circuit of well power sets up field effect transistor through increasing, parallelly connected electric capacity group, a plurality of energy storage electric capacity, divider resistance, power resistance and parts such as two stabilivolt, and make corresponding connection to these parts, realized utilizing the voltage input end through the slow charging process of resistance to an energy storage electric capacity, also realized preventing that the power is when the interval time of twice start is short, because of the residual voltage on this energy storage electric capacity makes field effect transistor produce the malfunction, cause the condition of starting this impulse current suppression circuit inefficacy even. Therefore, the starting impact current suppression circuit can suppress the instantaneous surge current of the power supply, avoids the condition of misoperation of the field effect transistor caused by overlarge surge current, and ensures the normal work of the power supply.
Drawings
Fig. 1 is a schematic diagram of a start-up inrush current suppression circuit of a power supply according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the following embodiments.
The embodiment provides a starting impact current suppression circuit of a power supply. Referring to fig. 1, the start-up inrush current suppression circuit of the power supply of the embodiment includes:
a voltage input terminal J1 for inputting an external voltage to the start-up rush current suppressing circuit,
a voltage output terminal VOUT for outputting the suppressed voltage to a back-end circuit of the power supply circuit;
the parallel capacitor bank is provided with a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4 which are mutually connected in parallel, the anode of the first capacitor C1, the anode of the second capacitor C2, the anode of the third capacitor C3 and the anode of the fourth capacitor C4 are respectively connected with a voltage output end VOUT, and the cathode of the first capacitor C1, the cathode of the second capacitor C2, the cathode of the third capacitor C3 and the cathode of the fourth capacitor C4 are respectively connected with a ground terminal GND; wherein, four capacitors in the parallel capacitor group are all energy storage capacitors, the capacitance of the first capacitor C1, the capacitance of the second capacitor C2 and the capacitance of the third capacitor C3 are all 1 muF, and the capacitance of the fourth capacitor C4 is 820 muF;
a source S of the field effect transistor Q is connected with the negative electrode of the third capacitor C3, a drain D of the field effect transistor Q is connected with a ground end GND, and a resistor R1 is connected in series between the source S and the drain D; the field effect transistor Q is an MOS field effect transistor, the resistor R1 is a voltage dividing resistor, and the resistance value of the resistor R1 is 22K omega;
a negative electrode of the fifth capacitor C5 is connected with a negative electrode of the third capacitor C3, and a positive electrode of the fifth capacitor C5 is connected with the gate G of the field effect transistor Q; the fifth capacitor C5 is an energy storage capacitor, and the capacitance of the fifth capacitor C5 is 0.1 muF;
a first end of the resistor R2 is connected with the negative electrode of the third capacitor C3, and a second end of the resistor R2 is connected with the grid G of the field effect transistor Q; wherein, the resistor R2 is a divider resistor, and the resistance value of the resistor R2 is 100K omega;
the anode of the first voltage-regulator tube Z1 is connected with the second end of the resistor R2, the cathode of the first voltage-regulator tube Z1 is connected with the first end of the resistor R3, and the second end of the resistor R3 is connected with the voltage output end VOUT; wherein, the stable voltage of the first voltage-regulator tube Z1 is 6.2V, the resistor R3 is a power resistor and the resistance value of the resistor R3 is 82K omega;
a sixth capacitor C6, a positive electrode of which is connected to the first end of the resistor R3, and a negative electrode of the sixth capacitor C6 is connected to the negative electrode of the third capacitor C3; wherein, the sixth capacitor C6 is an energy storage capacitor, and the capacitance of the sixth capacitor C6 is 4.7 μ F;
a first end of the resistor R4 is connected with the negative electrode of the third capacitor C3, and a second end of the resistor R4 is connected with a first end of the resistor R3; wherein, the resistor R4 is a voltage dividing resistor, and the resistance value of the resistor R4 is 200K omega;
and the anode of the second voltage-stabilizing tube Z2 is connected with the cathode of the third capacitor C3, and the cathode of the second voltage-stabilizing tube Z2 is connected with the first end of the resistor R3. Wherein the stabilized voltage of the second regulator tube Z2 is 18V.
The starting impact current suppression circuit of the power supply in the embodiment works according to the following principle:
at the starting moment of the power supply, as the voltage input end J1 charges the sixth capacitor C6 through the resistor R3, the grid G of the field effect transistor Q is at a low level, and the field effect transistor Q1 is in a turn-off state;
the positive voltage of the voltage input end J1 passes through the fourth capacitor C4 and the resistor R1 until the negative voltage of the voltage input end J1; wherein the maximum starting current is I IMAX ，I IMAX = VIN/R1, and the input current flowing to the fourth capacitor C4 decreases exponentially until the fourth capacitor C4 is charged, and the charging time period of the fourth capacitor C4 is the capacitance of the fourth capacitor and the resistance of the resistor R12.3 times of the product;
when the voltage charged by the voltage input end J1 to the sixth capacitor C6 through the resistor R3 reaches the sum of the grid threshold voltage of the field effect transistor Q and the voltage of the first voltage-stabilizing tube Z1, the field effect transistor Q starts to be conducted, and at the moment, the fourth capacitor C4 is already charged; then, the field effect transistor Q1 is completely conducted, the resistor R1 is short-circuited, the first voltage regulator tube Z1 and the second voltage regulator tube Z2 clamp the voltage between the grid source (G-S) of the field effect transistor Q to 11.8V, and the highest voltage between the grid source (G-S) of the field effect transistor Q is 20V, so that the field effect transistor Q is protected from being damaged;
by utilizing the discharging process of the sixth capacitor C6 through the resistor R4, the situation that the residual voltage on the sixth capacitor C6 causes the field effect transistor Q1 to generate false operation even causes the failure of starting the impulse current suppression circuit when the interval time of two starts of the power supply is short can be prevented. Therefore, the starting impact current suppression circuit can suppress the surge current in the moment of starting the power supply, avoids the condition that the front-end air switch is operated by mistake due to overlarge surge current, and ensures the normal work of the power supply.
Although the preferred embodiments of the present invention have been described in detail hereinabove, it should be clearly understood that modifications and variations of the present invention are possible to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. A start-up inrush current suppression circuit for a power supply, comprising:
a voltage input terminal J1;
a voltage output terminal VOUT;
the parallel capacitor bank is provided with a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4 which are mutually connected in parallel, the anode of the first capacitor C1, the anode of the second capacitor C2, the anode of the third capacitor C3 and the anode of the fourth capacitor C4 are respectively connected with a voltage output end VOUT, and the cathode of the first capacitor C1, the cathode of the second capacitor C2, the cathode of the third capacitor C3 and the cathode of the fourth capacitor C4 are respectively connected with a ground terminal GND;
a source S of the field effect transistor Q is connected with the negative electrode of the third capacitor C3, a drain D of the field effect transistor Q is connected with a ground end GND, and a resistor R1 is connected in series between the source S and the drain D;
a negative electrode of the fifth capacitor C5 is connected with a negative electrode of the third capacitor C3, and a positive electrode of the fifth capacitor C5 is connected with the gate G of the field effect transistor Q;
a first end of the resistor R2 is connected with the negative electrode of the third capacitor C3, and a second end of the resistor R2 is connected with the grid G of the field effect transistor Q;
the anode of the first voltage-stabilizing tube Z1 is connected with the second end of the resistor R2, the cathode of the first voltage-stabilizing tube Z1 is connected with the first end of the resistor R3, and the second end of the resistor R3 is connected with the voltage output end VOUT;
a sixth capacitor C6, a positive electrode of which is connected to the first end of the resistor R3, and a negative electrode of the sixth capacitor C6 is connected to the negative electrode of the third capacitor C3;
a first end of the resistor R4 is connected with the negative electrode of the third capacitor C3, and a second end of the resistor R4 is connected with a first end of the resistor R3;
and the anode of the second voltage-stabilizing tube Z2 is connected with the cathode of the third capacitor C3, and the cathode of the second voltage-stabilizing tube Z2 is connected with the first end of the resistor R3.
2. The start-up inrush current suppression circuit of claim 1, wherein the fet Q is a MOS fet.
3. The inrush current suppression circuit of claim 1, wherein the first capacitor C1, the second capacitor C2 and the third capacitor C3 each have a capacitance of 1 μ F, the fourth capacitor C4 has a capacitance of 820 μ F, the fifth capacitor C5 has a capacitance of 0.1 μ F, and the sixth capacitor C6 has a capacitance of 4.7 μ F.
4. The inrush current suppression circuit of claim 3, wherein the resistor R1 has a resistance of 22K Ω, the resistor R2 has a resistance of 100K Ω, the resistor R3 has a resistance of 82K Ω, and the resistor R4 has a resistance of 200K Ω.
5. The start-up inrush current suppression circuit for a power supply as claimed in claim 4, wherein the regulated voltage of the first regulator tube Z1 is 6.2V, and the regulated voltage of the second regulator tube Z2 is 18V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222285068.1U CN218161803U (en) | 2022-08-25 | 2022-08-25 | Starting impact current suppression circuit of power supply |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202222285068.1U CN218161803U (en) | 2022-08-25 | 2022-08-25 | Starting impact current suppression circuit of power supply |
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| CN218161803U true CN218161803U (en) | 2022-12-27 |
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| CN202222285068.1U Active CN218161803U (en) | 2022-08-25 | 2022-08-25 | Starting impact current suppression circuit of power supply |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116667301A (en) * | 2023-07-31 | 2023-08-29 | 成都新欣神风电子科技有限公司 | High-compatibility impact current suppression circuit |
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- 2022-08-25 CN CN202222285068.1U patent/CN218161803U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116667301A (en) * | 2023-07-31 | 2023-08-29 | 成都新欣神风电子科技有限公司 | High-compatibility impact current suppression circuit |
| CN116667301B (en) * | 2023-07-31 | 2023-10-13 | 成都新欣神风电子科技有限公司 | High-compatibility impact current suppression circuit |
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