CN217427663U - Current impact preventing circuit - Google Patents
Current impact preventing circuit Download PDFInfo
- Publication number
- CN217427663U CN217427663U CN202221116839.8U CN202221116839U CN217427663U CN 217427663 U CN217427663 U CN 217427663U CN 202221116839 U CN202221116839 U CN 202221116839U CN 217427663 U CN217427663 U CN 217427663U
- Authority
- CN
- China
- Prior art keywords
- resistor
- diode
- capacitor
- nmos tube
- anode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Direct Current Feeding And Distribution (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
The application discloses prevent current rush circuit belongs to the circuit protection field, has solved present filter circuit and has closed a floodgate transient state electric current too big in the twinkling of an eye, leads to partial device to damage and the unable normal use of switching power supply problem. One end of the first resistor is connected with the anode input end, and the other end of the first resistor is connected with the first capacitor. The second resistor is connected with the first resistor in parallel, the fourth resistor is connected with the second resistor in series, and the other end of the fourth resistor is connected with the grid electrode of the first NMOS tube. The source electrode of the first NMOS tube is connected with the negative electrode input end, the drain electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with the anode of the second diode. The anode of the second diode is connected between the second resistor and the fourth resistor, and the cathode of the second diode is connected between the first resistor and the first capacitor. According to the soft start anti-surge protection circuit, soft start anti-surge can be achieved, and therefore current impact is prevented.
Description
Technical Field
The application relates to the technical field of circuit protection, in particular to a current surge preventing circuit.
Background
At present, in an input circuit of a switching power supply, a rectifying and capacitor filter circuit is generally adopted, and at the moment of switching on, because an initial voltage on a capacitor is zero, a very large transient current can be generated, so that not only can part of devices be damaged, but also the switching power supply can not be normally used.
SUMMERY OF THE UTILITY MODEL
The embodiment of the application provides a current impact preventing circuit, and the problems that a part of devices are damaged and a switching power supply cannot be normally used due to the fact that transient current is too large at the moment of switching on of an existing filter circuit are solved.
The embodiment of the utility model provides a prevent electric current rush circuit, should prevent electric current rush circuit includes power, first diode, second diode, first NMOS pipe, second NMOS pipe, first resistance, second resistance, third resistance, fourth resistance, first electric capacity and second electric capacity; the power supply comprises a positive input end, a positive output end and a negative input end; one end of the first resistor is connected with the positive input end, the other end of the first resistor is connected with the first capacitor, and the other end of the first capacitor is connected with the negative input end; the second resistor is connected with the first resistor in parallel, the fourth resistor is connected with the second resistor in series, and the other end of the fourth resistor is connected with the grid electrode of the first NMOS tube; the source electrode of the first NMOS tube is connected with the negative electrode input end, the drain electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with the anode of the second diode; the anode of the second diode is connected between the second resistor and the fourth resistor, and the cathode of the second diode is connected between the first resistor and the first capacitor; the anode of the first diode is connected with the cathode of the second diode, and the cathode of the first diode is connected with the anode input end; one end of the second capacitor is connected between the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube, the other end of the second capacitor is connected with the third resistor, and the other end of the third resistor is connected between the grid electrode of the second NMOS tube and the anode of the second diode.
In one possible implementation manner, the current surge preventing circuit further comprises an anti-reverse connection circuit; the reverse connection preventing circuit comprises a first voltage regulator tube and a fifth resistor; the anode of the first voltage-stabilizing tube is connected with the source electrode of the second NMOS tube, and the cathode of the first voltage-stabilizing tube is connected with the anode of the second diode; one end of the fifth resistor is connected with the grid electrode of the second NMOS tube, and the other end of the fifth resistor is connected between the cathode of the first voltage-regulator tube and the anode of the second diode.
In a possible implementation manner, the current surge preventing circuit further comprises a third capacitor; one end of the third capacitor is connected with the positive electrode output end, and the other end of the third capacitor is grounded.
In one possible implementation, the third capacitor is a filter capacitor.
The embodiment of the utility model provides an in one or more technical scheme, following technological effect or advantage have at least:
the embodiment of the utility model provides a prevent electric current rush circuit should prevent electric current rush circuit includes power, first diode, second diode, first NMOS pipe, second NMOS pipe, first resistance, second resistance, third resistance, fourth resistance, first electric capacity and second electric capacity. The power supply comprises a positive input end, a positive output end and a negative input end. One end of the first resistor is connected with the positive input end, the other end of the first resistor is connected with the first capacitor, and the other end of the first capacitor is connected with the negative input end. The second resistor is connected with the first resistor in parallel, the fourth resistor is connected with the second resistor in series, and the other end of the fourth resistor is connected with the grid electrode of the first NMOS tube. The source electrode of the first NMOS tube is connected with the negative electrode input end, the drain electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with the anode of the second diode. The anode of the second diode is connected between the second resistor and the fourth resistor, and the cathode of the second diode is connected between the first resistor and the first capacitor. The anode of the first diode is connected with the cathode of the second diode, and the cathode of the first diode is connected with the anode input end. One end of the second capacitor is connected between the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube, the other end of the second capacitor is connected with the third resistor, and the other end of the third resistor is connected between the grid electrode of the second NMOS tube and the anode of the second diode. When the power supply is connected positively, the grid voltage of the first NMOS tube slowly rises, when the grid-source voltage Vgs of the first NMOS tube rises to a certain degree, the second diode is conducted to charge the first capacitor, when the first capacitor is charged, the grid-source voltage Vgs of the first NMOS tube rises at the same speed until the first NMOS tube is conducted, and after the first NMOS tube is conducted, the second NMOS tube is also conducted therewith, so that the soft start surge prevention is realized, the impact of current is prevented, the damage of partial devices is avoided, and the normal use of the switching power supply is ensured.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a circuit diagram of a current surge protection circuit according to an embodiment of the present application.
Icon: vin-positive input terminal; v0 — positive output; vin-negative input; d1 — first diode; d2 — second diode; d4 — first stabilivolt; c1 — first capacitance; c2 — second capacitance; c3 — third capacitance; q1-first NMOS tube; q2-second NMOS tube; r1 — first resistance; r2 — second resistance; r3 — third resistance; r4-fourth resistor; r5-fifth resistor.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In the description of the embodiments of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description of the embodiments of the present invention and for simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. The terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, the terms "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the embodiments of the present invention can be understood by those skilled in the art according to specific situations.
As shown in fig. 1, an embodiment of the present invention provides a current surge protection circuit, which includes a power supply, a first diode D1, a second diode D2, a first NMOS transistor Q1, a second NMOS transistor Q2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, and a second capacitor C2.
In practical applications, the power supply includes a positive input terminal Vin, a positive output terminal V0, and a negative input terminal-Vin. One end of the first resistor R1 is connected to the positive input terminal Vin, the other end of the first resistor R1 is connected to the first capacitor C1, and the other end of the first capacitor C1 is connected to the negative input terminal-Vin. The second resistor R2 is connected in parallel with the first resistor R1, the fourth resistor R4 is connected in series with the second resistor R2, and the other end of the fourth resistor R4 is connected with the gate of the first NMOS transistor Q1. The source electrode of the first NMOS transistor Q1 is connected with the negative electrode input end-Vin, the drain electrode of the first NMOS transistor Q1 is connected with the drain electrode of the second NMOS transistor Q2, the source electrode of the second NMOS transistor Q2 is grounded, and the grid electrode of the second NMOS transistor Q2 is connected with the anode electrode of the second diode D2. An anode of the second diode D2 is connected between the second resistor R2 and the fourth resistor R4, and a cathode of the second diode D2 is connected between the first resistor R1 and the first capacitor C1. The anode of the first diode D1 is connected to the cathode of the second diode D2, and the cathode of the first diode D1 is connected to the positive input terminal Vin. Specifically, a diode is an electronic device made of a semiconductor material (silicon, selenium, germanium, etc.) having unidirectional conductivity, i.e., when a forward voltage is applied to the anode of the diode, the diode is turned on, and when a reverse voltage is applied to the anode and the cathode, the diode is turned off.
With continued reference to fig. 1, one end of the second capacitor C2 is connected between the drain of the first NMOS transistor Q1 and the drain of the second NMOS transistor Q2, the other end of the second capacitor C2 is connected to the third resistor R3, and the other end of the third resistor R3 is connected between the gate of the second NMOS transistor Q2 and the anode of the second diode D2. In practical application, when a power supply is connected positively, the gate voltage of the first NMOS transistor Q1 rises slowly, when the gate-source voltage Vgs of the first NMOS transistor Q1 rises to a certain extent, the second diode D2 is turned on to charge the first capacitor C1, the gate-source voltage Vgs of the first NMOS transistor Q1 rises at the same speed while the first capacitor C1 is charged until the first NMOS transistor Q1 is turned on, at this time, the second NMOS transistor Q2 is turned on in advance due to a body diode, a voltage drop of about 0.7V is generated between the drain and the source of the second NMOS transistor Q2, when the gate-source voltage Vgs of the second NMOS transistor Q2 rises to the point that the second NMOS transistor Q2 is fully turned on, the turn-on voltage is very low, the body diode is turned off, the circuit is turned on, and therefore, soft-start surge prevention is achieved, and current impact is prevented.
The embodiment of the utility model provides a prevent electric current rush circuit, this prevent electric current rush circuit includes power, first diode D1, second diode D2, first NMOS pipe Q1, second NMOS pipe Q2, first resistance R1, second resistance R2, third resistance R3, fourth resistance R4, first electric capacity C1 and second electric capacity C2. The power supply includes a positive input Vin, a positive output V0, and a negative input-Vin. One end of the first resistor R1 is connected to the positive input terminal Vin, the other end of the first resistor R1 is connected to the first capacitor C1, and the other end of the first capacitor C1 is connected to the negative input terminal-Vin. The second resistor R2 is connected in parallel with the first resistor R1, the fourth resistor R4 is connected in series with the second resistor R2, and the other end of the fourth resistor R4 is connected with the gate of the first NMOS transistor Q1. The source electrode of the first NMOS transistor Q1 is connected with the negative electrode input end-Vin, the drain electrode of the first NMOS transistor Q1 is connected with the drain electrode of the second NMOS transistor Q2, the source electrode of the second NMOS transistor Q2 is grounded, and the grid electrode of the second NMOS transistor Q2 is connected with the anode electrode of the second diode D2. An anode of the second diode D2 is connected between the second resistor R2 and the fourth resistor R4, and a cathode of the second diode D2 is connected between the first resistor R1 and the first capacitor C1. The anode of the first diode D1 is connected to the cathode of the second diode D2, and the cathode of the first diode D1 is connected to the positive input terminal Vin. One end of the second capacitor C2 is connected between the drain of the first NMOS transistor Q1 and the drain of the second NMOS transistor Q2, the other end of the second capacitor C2 is connected to the third resistor R3, and the other end of the third resistor R3 is connected between the gate of the second NMOS transistor Q2 and the anode of the second diode D2. When the power supply is connected positively, the gate voltage of the first NMOS tube Q1 rises slowly, when the gate-source voltage Vgs of the first NMOS tube Q1 rises to a certain degree, the second diode D2 is conducted to charge the first capacitor C1, the gate-source voltage Vgs of the first NMOS tube Q1 rises at the same speed while the first capacitor C1 is charged until the first NMOS tube Q1 is conducted, and when the first NMOS tube Q1 is conducted, the second NMOS tube Q2 is also conducted therewith, so that soft start surge prevention is achieved, current impact is prevented, damage of partial devices is avoided, and normal use of the switching power supply is guaranteed.
With continued reference to FIG. 1, the current surge protection circuit also includes an anti-reverse circuit. The reverse connection preventing circuit comprises a first voltage regulator tube D4 and a fifth resistor R5. The anode of the first voltage regulator tube D4 is connected with the source of the second NMOS tube Q2, and the cathode of the first voltage regulator tube D4 is connected with the anode of the second diode D2. One end of the fifth resistor R5 is connected to the gate of the second NMOS transistor Q2, and the other end of the fifth resistor R5 is connected between the cathode of the first regulator D4 and the anode of the second diode D2. Specifically, when the power supply is reversely connected, the body diode of the second NMOS transistor Q2 is not turned on, and there is no current loop in the circuit, thereby playing a role of protecting the back-end load, and avoiding the damage of the circuit caused by the reverse connection of the voltage.
In practical applications, the current surge preventing circuit further comprises a third capacitor C3. One end of the third capacitor C3 is connected to the positive output terminal V0, and the other end of the third capacitor C3 is grounded.
Specifically, the third capacitor C3 is a filter capacitor. The filter capacitor can filter out alternating current components in the circuit, so that direct current output by the circuit is smoother, and the running of equipment is more stable.
The embodiments in the present specification are described in a progressive manner, and the same or similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure.
Claims (4)
1. A current surge preventing circuit is characterized by comprising a power supply, a first diode, a second diode, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor and a second capacitor;
the power supply comprises a positive input end, a positive output end and a negative input end;
one end of the first resistor is connected with the positive input end, the other end of the first resistor is connected with the first capacitor, and the other end of the first capacitor is connected with the negative input end; the second resistor is connected with the first resistor in parallel, the fourth resistor is connected with the second resistor in series, and the other end of the fourth resistor is connected with the grid electrode of the first NMOS tube; the source electrode of the first NMOS tube is connected with the negative electrode input end, the drain electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the grid electrode of the second NMOS tube is connected with the anode of the second diode; the anode of the second diode is connected between the second resistor and the fourth resistor, and the cathode of the second diode is connected between the first resistor and the first capacitor; the anode of the first diode is connected with the cathode of the second diode, and the cathode of the first diode is connected with the anode input end;
one end of the second capacitor is connected between the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube, the other end of the second capacitor is connected with the third resistor, and the other end of the third resistor is connected between the grid electrode of the second NMOS tube and the anode of the second diode.
2. The current surge protection circuit of claim 1, further comprising an anti-reverse circuit;
the reverse connection preventing circuit comprises a first voltage regulator tube and a fifth resistor;
the anode of the first voltage-stabilizing tube is connected with the source electrode of the second NMOS tube, and the cathode of the first voltage-stabilizing tube is connected with the anode of the second diode; one end of the fifth resistor is connected with the grid electrode of the second NMOS tube, and the other end of the fifth resistor is connected between the cathode of the first voltage-regulator tube and the anode of the second diode.
3. The current surge protection circuit of claim 1 or 2, further comprising a third capacitor;
one end of the third capacitor is connected with the positive electrode output end, and the other end of the third capacitor is grounded.
4. The current surge protection circuit of claim 3, wherein the third capacitor is a filter capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221116839.8U CN217427663U (en) | 2022-05-11 | 2022-05-11 | Current impact preventing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221116839.8U CN217427663U (en) | 2022-05-11 | 2022-05-11 | Current impact preventing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217427663U true CN217427663U (en) | 2022-09-13 |
Family
ID=83186396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221116839.8U Active CN217427663U (en) | 2022-05-11 | 2022-05-11 | Current impact preventing circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217427663U (en) |
-
2022
- 2022-05-11 CN CN202221116839.8U patent/CN217427663U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4227124B2 (en) | Fan module hot swap circuit system | |
| CN201256290Y (en) | Protection circuit for suppressing surge current and preventing input voltage reverse connection | |
| CN101753021A (en) | Switching control circuit | |
| CN107947557B (en) | Soft start circuit for resisting overvoltage and undervoltage surges | |
| CN104022634A (en) | Energy-storage capacitor type high-voltage and low-voltage surge suppression circuit and suppression method thereof | |
| CN212163157U (en) | Driving circuit of startup input surge current prevention relay | |
| CN212969451U (en) | Three-level BOOST device | |
| CN213243514U (en) | Protection circuit and electronic equipment | |
| CN217427663U (en) | Current impact preventing circuit | |
| CN214799289U (en) | Power-off discharge circuit of power supply | |
| CN115776103A (en) | Low-power-consumption input reverse connection prevention function control circuit | |
| CN113809730A (en) | High-voltage direct-current input reverse connection protection circuit | |
| CN210724557U (en) | Instantaneous power-down holding circuit with reverse-prevention and power-on impact current suppression | |
| CN209767489U (en) | Circuit for grid voltage clamping driving of PMOS (P-channel metal oxide semiconductor) tube | |
| CN112803526A (en) | Charging control circuit of robot | |
| CN217406186U (en) | Delay conduction circuit for inhibiting startup peak current at negative terminal | |
| CN217240585U (en) | Buffer circuit with load power-on impact current suppression function | |
| CN216215869U (en) | DC power supply reverse connection protection circuit | |
| CN215071629U (en) | Simple and easy DC line surge current suppression circuit | |
| CN204794034U (en) | Input undervoltage protection circuit | |
| CN210167964U (en) | Direct current surge driving circuit | |
| CN218549503U (en) | Reverse connection prevention circuit, power supply device and electronic equipment | |
| CN218733222U (en) | Impulse current suppression circuit and switching power supply | |
| CN115714367A (en) | Low-voltage high-power anti-back-pressure and overvoltage-resistant surge circuit | |
| CN219592120U (en) | Power supply reverse connection preventing circuit and DC electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |