CN104022634A - Energy-storage capacitor type high-voltage and low-voltage surge suppression circuit and suppression method thereof - Google Patents

Energy-storage capacitor type high-voltage and low-voltage surge suppression circuit and suppression method thereof Download PDF

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Publication number
CN104022634A
CN104022634A CN201410300193.2A CN201410300193A CN104022634A CN 104022634 A CN104022634 A CN 104022634A CN 201410300193 A CN201410300193 A CN 201410300193A CN 104022634 A CN104022634 A CN 104022634A
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China
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comparator
connected
sampling resistor
described
voltage
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CN201410300193.2A
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Chinese (zh)
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CN104022634B (en
Inventor
胡海斌
赵隆冬
胡进
徐辉
张石磊
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中国电子科技集团公司第四十三研究所
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Abstract

The invention provides an energy-storage capacitor type high-voltage and low-voltage surge suppression circuit and a suppression method thereof. The circuit comprises a normally closed relay, an anti-backflow diode, a DC/DC (Direct Current/Direct Current) converter, an energy-storage capacitor, a normally opened relay, an MOS (Metal Oxide Semiconductor) tube, a first current limiting resistor, a first sampling circuit composed of a first sampling resistor and a second sampling resistor, a second sampling circuit composed of a third sampling resistor and a fourth sampling resistor, a standard voltage circuit composed of a stable-voltage diode and a second current limiting resistor, and a control circuit composed of a first comparator, a first switching element, a second comparator and a second switching element. The invention further provides the suppression method of the energy-storage capacitor type high-voltage and low-voltage surge suppression circuit. The requirements on suppression of high-voltage surge and low-voltage surge at the same time can be met and the working stability of a power supply circuit is improved.

Description

A kind of storage capacitor formula high and low pressure surge restraint circuit and inhibition method thereof

Technical field

The present invention relates to voltage surge and suppress technical field, specifically a kind of storage capacitor formula high and low pressure surge restraint circuit and inhibition method thereof.

 

Background technology

In the circuit design of field of power supplies, must consider Surge suppression, otherwise in the time of power input input surge voltage, can whole power circuit be produced and be disturbed, circuit is broken down or damage.Traditional storage capacitor formula surge restraint circuit can only suppress separately high voltage surge or low pressure surge, is unfavorable for the stability of whole power circuit.

 

Summary of the invention

The object of the present invention is to provide a kind of storage capacitor formula high and low pressure surge restraint circuit and inhibition method thereof, can meet the demand that suppresses high voltage surge and low pressure surge simultaneously.

Technical scheme of the present invention is:

A kind of storage capacitor formula high and low pressure surge restraint circuit, comprises anti-return diode, DC/DC transducer, storage capacitor and metal-oxide-semiconductor; The input of the anode of described anti-return diode and DC/DC transducer is all connected to power input voltage by normally closed relay, the negative electrode of described anti-return diode is directly connected with power output end, and the output of described DC/DC transducer is connected with power output end by normally opened relay; One end of described storage capacitor is connected to the node between DC/DC transducer and normally opened relay, other end ground connection; The drain electrode of described metal-oxide-semiconductor is connected to power input voltage, and its source electrode is by the first current-limiting resistance ground connection, and the node between metal-oxide-semiconductor and the first current-limiting resistance is connected respectively to the control end of normally closed relay and normally opened relay,

This circuit also comprises the first sample circuit being made up of the first sampling resistor and the second sampling resistor, the second sample circuit being made up of the 3rd sampling resistor and the 4th sampling resistor, the reference voltage circuit being made up of voltage stabilizing didoe and the second current-limiting resistance and the control circuit being made up of the first comparator, the first switch element, the second comparator and second switch element;

Described the first sampling resistor and the second sampling resistor are connected in series, one end of described the first sampling resistor is connected to power input voltage, the other end is by the second sampling resistor ground connection, described the 3rd sampling resistor and the 4th sampling resistor are connected in series, one end of described the 3rd sampling resistor is connected to power input voltage, and the other end is by the 4th sampling resistor ground connection; The plus earth of described voltage stabilizing didoe, its negative electrode is connected to power input voltage by the second current-limiting resistance;

The in-phase input end of the inverting input of described the first comparator and the second comparator is all connected to the node between voltage stabilizing didoe and the second current-limiting resistance, the in-phase input end of described the first comparator is connected to the node between the first sampling resistor and the second sampling resistor, the inverting input of described the second comparator is connected to the node between the 3rd sampling resistor and the 4th sampling resistor, the output of described the first comparator is connected with the grid of metal-oxide-semiconductor by the first switch element, and the output of described the second comparator is connected with the grid of metal-oxide-semiconductor by second switch element.

Described storage capacitor formula high and low pressure surge restraint circuit, described the first switch element is selected the first diode, and the anode of described the first diode is connected with the output of the first comparator, and its negative electrode is connected with the grid of metal-oxide-semiconductor; Described second switch element is selected the second diode, and the anode of described the second diode is connected with the output of the second comparator, and its negative electrode is connected with the grid of MOS pipe.

The inhibition method of described a kind of storage capacitor formula high and low pressure surge restraint circuit, comprises the following steps:

(1) first sample circuit is sampled to power input voltage, deliver to the in-phase input end of the first comparator, the second sample circuit is sampled to power input voltage, deliver to the inverting input of the second comparator, reference voltage circuit output reference voltage, delivers to respectively the inverting input of the first comparator and the in-phase input end of the second comparator;

(2) in the time that power input voltage is stablized, the first comparator and the equal output low level of the second comparator, the first switch element and second switch element all end, metal-oxide-semiconductor cut-off, the closing of contact of normally closed relay, anti-return diode current flow, the contact of normally opened relay disconnects, and DC/DC transducer is storage capacitor charging;

(3) in the time there is high voltage surge in power input voltage, the first comparator output high level, the first switch element conducting, the conducting of driven MOS pipe, the contact of controlling normally closed relay disconnects, the closing of contact of normally opened relay, and storage capacitor is late-class circuit power supply, the cut-off of anti-return diode;

(4) in the time there is low pressure surge in power input voltage, the second comparator output high level, second switch element conductive, the conducting of driven MOS pipe, the contact of controlling normally closed relay disconnects, the closing of contact of normally opened relay, and storage capacitor is late-class circuit power supply, the cut-off of anti-return diode.

As shown from the above technical solution, the present invention can meet the demand that suppresses high voltage surge and low pressure surge simultaneously, has improved the job stability of power circuit.

Brief description of the drawings

Fig. 1 is the electrical block diagram of the specific embodiment of the invention.

 

Embodiment

Further illustrate the present invention below in conjunction with the drawings and specific embodiments.

As shown in Figure 1, a kind of storage capacitor formula is high, low pressure surge restraint circuit, comprise normally closed relay K1, anti-return diode D0, DC/DC transducer 1, storage capacitor C, normally opened relay K2, NMOS manages Q, the first current-limiting resistance R5, the first sample circuit 2, the second sample circuit 3, reference voltage circuit 4 and control circuit 5, the first sample circuit 2 is made up of the first sampling resistor R1 and the second sampling resistor R2, the second sample circuit 3 is made up of the 3rd sampling resistor R4 and the 4th sampling resistor R5, reference voltage circuit 4 is made up of voltage stabilizing didoe Dz and the second current-limiting resistance R6, control circuit 5 is by the first comparator V1, the first diode D1, the second comparator V2 and the second diode D2 form.

The anode of anti-return diode D0 and the input of DC/DC transducer 1 are all connected to power input voltage by normally closed relay K1, the negative electrode of anti-return diode D0 is directly connected with power output end, and the output of DC/DC transducer 1 is connected with power output end by normally opened relay K2.One end of storage capacitor C is connected to the node between DC/DC transducer 1 and normally opened relay K2, other end ground connection.The drain electrode of NMOS pipe Q is connected to power input voltage, and its source electrode is by the first current-limiting resistance R5 ground connection, and the node between NMOS pipe Q and the first current-limiting resistance R5 is connected respectively to the control end of normally closed relay K1 and normally opened relay K2.

The first sampling resistor R1 and the second sampling resistor R2 are connected in series, and one end of the first sampling resistor R1 is connected to power input voltage, and the other end is by the second sampling resistor R2 ground connection.The 3rd sampling resistor R3 and the 4th sampling resistor R4 are connected in series, and one end of the 3rd sampling resistor R3 is connected to power input voltage, and the other end is by the 4th sampling resistor R4 ground connection.The plus earth of voltage stabilizing didoe Dz, its negative electrode is connected to power input voltage by the second current-limiting resistance R6.

The in-phase input end of the inverting input of the first comparator V1 and the second comparator V2 is all connected to the node between voltage stabilizing didoe Dz and the second current-limiting resistance R6, the in-phase input end of the first comparator V1 is connected to the node between the first sampling resistor R1 and the second sampling resistor R2, and the inverting input of the second comparator V2 is connected to the node between the 3rd sampling resistor R3 and the 4th sampling resistor R4.The output of the first comparator V1 connects the anode of the first diode D1, and the negative electrode of the first diode D1 is connected with the grid of NMOS pipe Q.The output of the second comparator V2 connects the anode of the second diode D2, and the negative electrode of the second diode D2 is connected with the grid of NMOS pipe Q.

Operation principle of the present invention:

In the time of power supply steady operation, the contact of normally closed relay K1 is in closure state, anti-return diode D0 conducting, and the contact of normally opened relay K2 is in off-state, and DC/DC transducer 1 is storage capacitor C charging.In the present embodiment, the first sample circuit 2 is sampled to power input voltage, delivers to the in-phase input end of the first comparator V1, compares with the reference voltage of its inverting input of input; The second sample circuit 3 is sampled to power input voltage, delivers to the inverting input of the second comparator V2, compares with the reference voltage of its in-phase input end of input.

In the time there is high voltage surge in power input voltage, the in-phase input end voltage of the first comparator V1 is higher than anti-phase input terminal voltage, the first comparator V1 output high level, the first diode D1 conducting, driving N metal-oxide-semiconductor Q conducting (now, the in-phase input end voltage of the second comparator V2 is lower than anti-phase input terminal voltage, the second comparator V2 output low level, the second diode D2 cut-off), the contact of normally closed relay K1 disconnects suppressing high voltage surge, the closing of contact of normally opened relay K2, storage capacitor C is that late-class circuit powers to prevent its power down, anti-return diode Dz ends to prevent that output voltage from pouring in down a chimney to the input of DC/DC transducer, the steady operation of protective circuit.

In the time there is low pressure surge in power input voltage, the in-phase input end voltage of the second comparator V2 is higher than anti-phase input terminal voltage, the second comparator V2 output high level, the second diode D2 conducting, driving N metal-oxide-semiconductor Q conducting (now, the in-phase input end voltage of the first comparator V1 is lower than anti-phase input terminal voltage, the first comparator V1 output low level, the first diode D1 cut-off), the contact of normally closed relay K1 disconnects suppressing low pressure surge, the closing of contact of normally opened relay K2, storage capacitor C is that late-class circuit powers to prevent its power down, anti-return diode Dz ends to prevent that output voltage from pouring in down a chimney to the input of DC/DC transducer, the steady operation of protective circuit.

The above execution mode is only that the preferred embodiment of the present invention is described; not scope of the present invention is limited; design under the prerequisite of spirit not departing from the present invention; various distortion and improvement that those of ordinary skill in the art make technical scheme of the present invention, all should fall in the definite protection range of claims of the present invention.

Claims (3)

1. a storage capacitor formula high and low pressure surge restraint circuit, comprises anti-return diode, DC/DC transducer, storage capacitor and metal-oxide-semiconductor; The input of the anode of described anti-return diode and DC/DC transducer is all connected to power input voltage by normally closed relay, the negative electrode of described anti-return diode is directly connected with power output end, and the output of described DC/DC transducer is connected with power output end by normally opened relay; One end of described storage capacitor is connected to the node between DC/DC transducer and normally opened relay, other end ground connection; The drain electrode of described metal-oxide-semiconductor is connected to power input voltage, and its source electrode is by the first current-limiting resistance ground connection, and the node between metal-oxide-semiconductor and the first current-limiting resistance is connected respectively to the control end of normally closed relay and normally opened relay,
It is characterized in that: this circuit also comprises the first sample circuit being made up of the first sampling resistor and the second sampling resistor, the second sample circuit being made up of the 3rd sampling resistor and the 4th sampling resistor, the reference voltage circuit being made up of voltage stabilizing didoe and the second current-limiting resistance and the control circuit being made up of the first comparator, the first switch element, the second comparator and second switch element;
Described the first sampling resistor and the second sampling resistor are connected in series, one end of described the first sampling resistor is connected to power input voltage, the other end is by the second sampling resistor ground connection, described the 3rd sampling resistor and the 4th sampling resistor are connected in series, one end of described the 3rd sampling resistor is connected to power input voltage, and the other end is by the 4th sampling resistor ground connection; The plus earth of described voltage stabilizing didoe, its negative electrode is connected to power input voltage by the second current-limiting resistance;
The in-phase input end of the inverting input of described the first comparator and the second comparator is all connected to the node between voltage stabilizing didoe and the second current-limiting resistance, the in-phase input end of described the first comparator is connected to the node between the first sampling resistor and the second sampling resistor, the inverting input of described the second comparator is connected to the node between the 3rd sampling resistor and the 4th sampling resistor, the output of described the first comparator is connected with the grid of metal-oxide-semiconductor by the first switch element, and the output of described the second comparator is connected with the grid of metal-oxide-semiconductor by second switch element.
2. storage capacitor formula high and low pressure surge restraint circuit according to claim 1, it is characterized in that: described the first switch element is selected the first diode, the anode of described the first diode is connected with the output of the first comparator, and its negative electrode is connected with the grid of metal-oxide-semiconductor; Described second switch element is selected the second diode, and the anode of described the second diode is connected with the output of the second comparator, and its negative electrode is connected with the grid of MOS pipe.
3. the inhibition method of a kind of storage capacitor formula high and low pressure surge restraint circuit according to claim 1, is characterized in that, comprises the following steps:
(1) first sample circuit is sampled to power input voltage, deliver to the in-phase input end of the first comparator, the second sample circuit is sampled to power input voltage, deliver to the inverting input of the second comparator, reference voltage circuit output reference voltage, delivers to respectively the inverting input of the first comparator and the in-phase input end of the second comparator;
(2) in the time that power input voltage is stablized, the first comparator and the equal output low level of the second comparator, the first switch element and second switch element all end, metal-oxide-semiconductor cut-off, the closing of contact of normally closed relay, anti-return diode current flow, the contact of normally opened relay disconnects, and DC/DC transducer is storage capacitor charging;
(3) in the time there is high voltage surge in power input voltage, the first comparator output high level, the first switch element conducting, the conducting of driven MOS pipe, the contact of controlling normally closed relay disconnects, the closing of contact of normally opened relay, and storage capacitor is late-class circuit power supply, the cut-off of anti-return diode;
(4) in the time there is low pressure surge in power input voltage, the second comparator output high level, second switch element conductive, the conducting of driven MOS pipe, the contact of controlling normally closed relay disconnects, the closing of contact of normally opened relay, and storage capacitor is late-class circuit power supply, the cut-off of anti-return diode.
CN201410300193.2A 2014-06-30 2014-06-30 A kind of storage capacitor formula high and low pressure surge restraint circuit and suppressing method thereof CN104022634B (en)

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CN201410300193.2A CN104022634B (en) 2014-06-30 2014-06-30 A kind of storage capacitor formula high and low pressure surge restraint circuit and suppressing method thereof

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104362842A (en) * 2014-10-20 2015-02-18 矽力杰半导体技术(杭州)有限公司 Switching power supply and surge protection circuit and method adaptive to same
CN106160158A (en) * 2015-03-31 2016-11-23 丁智博 A kind of power supply device of electric automobile and a kind of motor vehicles
WO2017133391A1 (en) * 2016-02-05 2017-08-10 广东欧珀移动通信有限公司 Charging system, protection method during charging, and power adapter
CN108271428A (en) * 2016-02-05 2018-07-10 广东欧珀移动通信有限公司 Guard method, power supply adaptor when charging system, charging

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58179128A (en) * 1982-04-13 1983-10-20 Mitsubishi Electric Corp Rush-current suppressing circuit
CN102354965A (en) * 2011-10-14 2012-02-15 江苏普明商贸有限公司 Novel surge control circuit
CN103166194A (en) * 2011-12-17 2013-06-19 西安恒飞电子科技有限公司 Input overvoltage and under-voltage protection circuit of communication power supply module
CN203933373U (en) * 2014-06-30 2014-11-05 中国电子科技集团公司第四十三研究所 Energy storage capacitor type high-and-low-voltage surge suppression circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58179128A (en) * 1982-04-13 1983-10-20 Mitsubishi Electric Corp Rush-current suppressing circuit
CN102354965A (en) * 2011-10-14 2012-02-15 江苏普明商贸有限公司 Novel surge control circuit
CN103166194A (en) * 2011-12-17 2013-06-19 西安恒飞电子科技有限公司 Input overvoltage and under-voltage protection circuit of communication power supply module
CN203933373U (en) * 2014-06-30 2014-11-05 中国电子科技集团公司第四十三研究所 Energy storage capacitor type high-and-low-voltage surge suppression circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104362842A (en) * 2014-10-20 2015-02-18 矽力杰半导体技术(杭州)有限公司 Switching power supply and surge protection circuit and method adaptive to same
CN106160158A (en) * 2015-03-31 2016-11-23 丁智博 A kind of power supply device of electric automobile and a kind of motor vehicles
CN106160158B (en) * 2015-03-31 2018-09-18 丁智博 A kind of power supply device of electric automobile and a kind of motor vehicle
WO2017133391A1 (en) * 2016-02-05 2017-08-10 广东欧珀移动通信有限公司 Charging system, protection method during charging, and power adapter
CN108271428A (en) * 2016-02-05 2018-07-10 广东欧珀移动通信有限公司 Guard method, power supply adaptor when charging system, charging

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